369 lines
12 KiB
Verilog
369 lines
12 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first O 327
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// RDY_first O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 327
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// EN_deq -> RDY_enq
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkAluExeToFinFifo(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [326 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [326 : 0] first;
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output RDY_first;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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wire [326 : 0] first;
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wire RDY_deq,
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RDY_enq,
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RDY_first,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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wire [11 : 0] m_m_specBits_0_lat_1$wget;
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wire m_m_valid_0_lat_1$whas;
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// register m_m_row_0
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reg [314 : 0] m_m_row_0;
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wire [314 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// ports of submodule m_m_deqP_ehr_dummy2_0
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wire m_m_deqP_ehr_dummy2_0$D_IN, m_m_deqP_ehr_dummy2_0$EN;
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// ports of submodule m_m_deqP_ehr_dummy2_1
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wire m_m_deqP_ehr_dummy2_1$D_IN, m_m_deqP_ehr_dummy2_1$EN;
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// ports of submodule m_m_specBits_0_dummy2_0
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wire m_m_specBits_0_dummy2_0$D_IN,
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m_m_specBits_0_dummy2_0$EN,
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m_m_specBits_0_dummy2_0$Q_OUT;
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// ports of submodule m_m_specBits_0_dummy2_1
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wire m_m_specBits_0_dummy2_1$D_IN,
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m_m_specBits_0_dummy2_1$EN,
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m_m_specBits_0_dummy2_1$Q_OUT;
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// ports of submodule m_m_valid_0_dummy2_0
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wire m_m_valid_0_dummy2_0$D_IN,
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m_m_valid_0_dummy2_0$EN,
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m_m_valid_0_dummy2_0$Q_OUT;
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// ports of submodule m_m_valid_0_dummy2_1
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wire m_m_valid_0_dummy2_1$D_IN,
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m_m_valid_0_dummy2_1$EN,
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m_m_valid_0_dummy2_1$Q_OUT;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// inputs to muxes for submodule ports
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wire MUX_m_m_valid_0_dummy2_1$write_1__SEL_1;
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// remaining internal signals
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wire [11 : 0] IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60,
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IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13,
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sb__h6795,
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upd__h2322;
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wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6,
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_dand1m_m_valid_0_dummy2_1$EN_write,
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_dand1m_m_valid_0_lat_1$EN_wset;
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// action method enq
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assign RDY_enq = !m_m_valid_0_dummy2_1$Q_OUT || EN_deq || !m_m_valid_0_rl ;
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assign CAN_FIRE_enq =
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!m_m_valid_0_dummy2_1$Q_OUT || EN_deq || !m_m_valid_0_rl ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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assign RDY_deq =
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m_m_valid_0_dummy2_0$Q_OUT && m_m_valid_0_dummy2_1$Q_OUT &&
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m_m_valid_0_rl ;
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assign CAN_FIRE_deq = RDY_deq ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first =
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{ m_m_row_0,
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IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60 } ;
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assign RDY_first = RDY_deq ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// submodule m_m_deqP_ehr_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_deqP_ehr_dummy2_0(.CLK(CLK),
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.D_IN(m_m_deqP_ehr_dummy2_0$D_IN),
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.EN(m_m_deqP_ehr_dummy2_0$EN),
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.Q_OUT());
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// submodule m_m_deqP_ehr_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_deqP_ehr_dummy2_1(.CLK(CLK),
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.D_IN(m_m_deqP_ehr_dummy2_1$D_IN),
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.EN(m_m_deqP_ehr_dummy2_1$EN),
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.Q_OUT());
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// submodule m_m_specBits_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_0(.CLK(CLK),
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.D_IN(m_m_specBits_0_dummy2_0$D_IN),
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.EN(m_m_specBits_0_dummy2_0$EN),
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.Q_OUT(m_m_specBits_0_dummy2_0$Q_OUT));
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// submodule m_m_specBits_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_1(.CLK(CLK),
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.D_IN(m_m_specBits_0_dummy2_1$D_IN),
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.EN(m_m_specBits_0_dummy2_1$EN),
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.Q_OUT(m_m_specBits_0_dummy2_1$Q_OUT));
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// submodule m_m_valid_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_0(.CLK(CLK),
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.D_IN(m_m_valid_0_dummy2_0$D_IN),
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.EN(m_m_valid_0_dummy2_0$EN),
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.Q_OUT(m_m_valid_0_dummy2_0$Q_OUT));
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// submodule m_m_valid_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_1(.CLK(CLK),
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.D_IN(m_m_valid_0_dummy2_1$D_IN),
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.EN(m_m_valid_0_dummy2_1$EN),
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.Q_OUT(m_m_valid_0_dummy2_1$Q_OUT));
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// inputs to muxes for submodule ports
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assign MUX_m_m_valid_0_dummy2_1$write_1__SEL_1 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60[specUpdate_incorrectSpeculation_kill_tag]) ;
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// inlined wires
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assign m_m_valid_0_lat_1$whas = _dand1m_m_valid_0_lat_1$EN_wset || EN_enq ;
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assign m_m_specBits_0_lat_1$wget =
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sb__h6795 & specUpdate_correctSpeculation_mask ;
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// register m_m_row_0
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assign m_m_row_0$D_IN = enq_x[326:12] ;
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assign m_m_row_0$EN = EN_enq ;
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// register m_m_specBits_0_rl
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assign m_m_specBits_0_rl$D_IN =
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EN_specUpdate_correctSpeculation ?
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upd__h2322 :
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IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 ;
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assign m_m_specBits_0_rl$EN = 1'd1 ;
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// register m_m_valid_0_rl
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assign m_m_valid_0_rl$D_IN =
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m_m_valid_0_lat_1$whas ?
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!MUX_m_m_valid_0_dummy2_1$write_1__SEL_1 :
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IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 ;
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assign m_m_valid_0_rl$EN = 1'd1 ;
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// submodule m_m_deqP_ehr_dummy2_0
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assign m_m_deqP_ehr_dummy2_0$D_IN = 1'd1 ;
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assign m_m_deqP_ehr_dummy2_0$EN = EN_deq ;
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// submodule m_m_deqP_ehr_dummy2_1
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assign m_m_deqP_ehr_dummy2_1$D_IN = 1'b0 ;
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assign m_m_deqP_ehr_dummy2_1$EN = 1'b0 ;
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// submodule m_m_specBits_0_dummy2_0
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assign m_m_specBits_0_dummy2_0$D_IN = 1'd1 ;
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assign m_m_specBits_0_dummy2_0$EN = EN_enq ;
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// submodule m_m_specBits_0_dummy2_1
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assign m_m_specBits_0_dummy2_1$D_IN = 1'd1 ;
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assign m_m_specBits_0_dummy2_1$EN = EN_specUpdate_correctSpeculation ;
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// submodule m_m_valid_0_dummy2_0
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assign m_m_valid_0_dummy2_0$D_IN = 1'd1 ;
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assign m_m_valid_0_dummy2_0$EN = EN_deq ;
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// submodule m_m_valid_0_dummy2_1
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assign m_m_valid_0_dummy2_1$D_IN = 1'd1 ;
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assign m_m_valid_0_dummy2_1$EN =
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_dand1m_m_valid_0_dummy2_1$EN_write || EN_enq ;
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// remaining internal signals
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assign IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60 =
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(m_m_specBits_0_dummy2_0$Q_OUT &&
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m_m_specBits_0_dummy2_1$Q_OUT) ?
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m_m_specBits_0_rl :
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12'd0 ;
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assign IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 =
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EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ;
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assign IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 =
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!EN_deq && m_m_valid_0_rl ;
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assign _dand1m_m_valid_0_dummy2_1$EN_write =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60[specUpdate_incorrectSpeculation_kill_tag]) ;
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assign _dand1m_m_valid_0_lat_1$EN_wset =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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IF_m_m_specBits_0_dummy2_0_read__7_AND_m_m_spe_ETC___d60[specUpdate_incorrectSpeculation_kill_tag]) ;
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assign sb__h6795 =
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m_m_specBits_0_dummy2_1$Q_OUT ?
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IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 :
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12'd0 ;
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assign upd__h2322 = m_m_specBits_0_lat_1$wget ;
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// handling of inlined registers
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always@(posedge CLK)
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begin
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if (RST_N == `BSV_RESET_VALUE)
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begin
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m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
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m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
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end
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else
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begin
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if (m_m_specBits_0_rl$EN)
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m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
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if (m_m_valid_0_rl$EN)
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m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
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end
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if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
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end
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// synopsys translate_off
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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initial
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begin
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m_m_row_0 =
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315'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
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m_m_specBits_0_rl = 12'hAAA;
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m_m_valid_0_rl = 1'h0;
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end
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`endif // BSV_NO_INITIAL_BLOCKS
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// synopsys translate_on
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// handling of system tasks
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// synopsys translate_off
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always@(negedge CLK)
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begin
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#0;
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if (RST_N != `BSV_RESET_VALUE)
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if (EN_enq && m_m_valid_0_dummy2_1$Q_OUT &&
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IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6)
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$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
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end
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// synopsys translate_on
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endmodule // mkAluExeToFinFifo
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