530 lines
15 KiB
Verilog
530 lines
15 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first O 422
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// RDY_first O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 422
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// (specUpdate_incorrectSpeculation_kill_all,
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// specUpdate_incorrectSpeculation_kill_tag,
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// EN_deq,
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// EN_specUpdate_incorrectSpeculation) -> RDY_enq
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkAluRegToExeFifo(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [421 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [421 : 0] first;
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output RDY_first;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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wire [421 : 0] first;
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wire RDY_deq,
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RDY_enq,
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RDY_first,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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wire [11 : 0] m_m_specBits_0_lat_1$wget;
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wire m_m_valid_0_lat_0$whas;
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// register m_m_row_0
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reg [409 : 0] m_m_row_0;
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wire [409 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// ports of submodule m_m_deqP_ehr_dummy2_0
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wire m_m_deqP_ehr_dummy2_0$D_IN, m_m_deqP_ehr_dummy2_0$EN;
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// ports of submodule m_m_deqP_ehr_dummy2_1
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wire m_m_deqP_ehr_dummy2_1$D_IN, m_m_deqP_ehr_dummy2_1$EN;
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// ports of submodule m_m_specBits_0_dummy2_0
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wire m_m_specBits_0_dummy2_0$D_IN,
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m_m_specBits_0_dummy2_0$EN,
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m_m_specBits_0_dummy2_0$Q_OUT;
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// ports of submodule m_m_specBits_0_dummy2_1
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wire m_m_specBits_0_dummy2_1$D_IN,
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m_m_specBits_0_dummy2_1$EN,
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m_m_specBits_0_dummy2_1$Q_OUT;
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// ports of submodule m_m_valid_0_dummy2_0
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wire m_m_valid_0_dummy2_0$D_IN,
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m_m_valid_0_dummy2_0$EN,
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m_m_valid_0_dummy2_0$Q_OUT;
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// ports of submodule m_m_valid_0_dummy2_1
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wire m_m_valid_0_dummy2_1$D_IN,
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m_m_valid_0_dummy2_1$EN,
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m_m_valid_0_dummy2_1$Q_OUT;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// inputs to muxes for submodule ports
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wire MUX_m_m_valid_0_dummy2_0$write_1__SEL_1;
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// remaining internal signals
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reg [20 : 0] CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2,
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CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5;
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reg [11 : 0] CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3,
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CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6;
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reg [2 : 0] CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1,
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CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4;
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wire [11 : 0] IF_m_m_specBits_0_dummy2_0_read__78_AND_m_m_sp_ETC___d281,
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IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13,
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sb__h10294,
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upd__h2322;
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wire IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6;
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// action method enq
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assign RDY_enq =
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!m_m_valid_0_dummy2_1$Q_OUT ||
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(m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl) ;
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assign CAN_FIRE_enq =
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!m_m_valid_0_dummy2_1$Q_OUT ||
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(m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl) ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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assign RDY_deq =
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m_m_valid_0_dummy2_0$Q_OUT && m_m_valid_0_dummy2_1$Q_OUT &&
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m_m_valid_0_rl ;
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assign CAN_FIRE_deq = RDY_deq ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first =
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{ m_m_row_0[409:405],
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CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5,
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m_m_row_0[383],
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CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6,
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m_m_row_0[370:0],
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IF_m_m_specBits_0_dummy2_0_read__78_AND_m_m_sp_ETC___d281 } ;
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assign RDY_first = RDY_deq ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// submodule m_m_deqP_ehr_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_deqP_ehr_dummy2_0(.CLK(CLK),
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.D_IN(m_m_deqP_ehr_dummy2_0$D_IN),
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.EN(m_m_deqP_ehr_dummy2_0$EN),
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.Q_OUT());
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// submodule m_m_deqP_ehr_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_deqP_ehr_dummy2_1(.CLK(CLK),
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.D_IN(m_m_deqP_ehr_dummy2_1$D_IN),
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.EN(m_m_deqP_ehr_dummy2_1$EN),
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.Q_OUT());
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// submodule m_m_specBits_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_0(.CLK(CLK),
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.D_IN(m_m_specBits_0_dummy2_0$D_IN),
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.EN(m_m_specBits_0_dummy2_0$EN),
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.Q_OUT(m_m_specBits_0_dummy2_0$Q_OUT));
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// submodule m_m_specBits_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_1(.CLK(CLK),
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.D_IN(m_m_specBits_0_dummy2_1$D_IN),
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.EN(m_m_specBits_0_dummy2_1$EN),
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.Q_OUT(m_m_specBits_0_dummy2_1$Q_OUT));
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// submodule m_m_valid_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_0(.CLK(CLK),
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.D_IN(m_m_valid_0_dummy2_0$D_IN),
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.EN(m_m_valid_0_dummy2_0$EN),
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.Q_OUT(m_m_valid_0_dummy2_0$Q_OUT));
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// submodule m_m_valid_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_1(.CLK(CLK),
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.D_IN(m_m_valid_0_dummy2_1$D_IN),
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.EN(m_m_valid_0_dummy2_1$EN),
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.Q_OUT(m_m_valid_0_dummy2_1$Q_OUT));
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// inputs to muxes for submodule ports
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assign MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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IF_m_m_specBits_0_dummy2_0_read__78_AND_m_m_sp_ETC___d281[specUpdate_incorrectSpeculation_kill_tag]) ;
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// inlined wires
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assign m_m_valid_0_lat_0$whas =
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MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
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assign m_m_specBits_0_lat_1$wget =
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sb__h10294 & specUpdate_correctSpeculation_mask ;
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// register m_m_row_0
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assign m_m_row_0$D_IN =
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{ enq_x[421:417],
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CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2,
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enq_x[395],
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CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3,
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enq_x[382:12] } ;
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assign m_m_row_0$EN = EN_enq ;
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// register m_m_specBits_0_rl
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assign m_m_specBits_0_rl$D_IN =
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EN_specUpdate_correctSpeculation ?
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upd__h2322 :
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IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 ;
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assign m_m_specBits_0_rl$EN = 1'd1 ;
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// register m_m_valid_0_rl
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assign m_m_valid_0_rl$D_IN =
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EN_enq ||
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IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 ;
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assign m_m_valid_0_rl$EN = 1'd1 ;
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// submodule m_m_deqP_ehr_dummy2_0
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assign m_m_deqP_ehr_dummy2_0$D_IN = 1'd1 ;
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assign m_m_deqP_ehr_dummy2_0$EN = EN_deq ;
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// submodule m_m_deqP_ehr_dummy2_1
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assign m_m_deqP_ehr_dummy2_1$D_IN = 1'b0 ;
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assign m_m_deqP_ehr_dummy2_1$EN = 1'b0 ;
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// submodule m_m_specBits_0_dummy2_0
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assign m_m_specBits_0_dummy2_0$D_IN = 1'd1 ;
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assign m_m_specBits_0_dummy2_0$EN = EN_enq ;
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// submodule m_m_specBits_0_dummy2_1
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assign m_m_specBits_0_dummy2_1$D_IN = 1'd1 ;
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assign m_m_specBits_0_dummy2_1$EN = EN_specUpdate_correctSpeculation ;
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// submodule m_m_valid_0_dummy2_0
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assign m_m_valid_0_dummy2_0$D_IN = 1'd1 ;
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assign m_m_valid_0_dummy2_0$EN =
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MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
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// submodule m_m_valid_0_dummy2_1
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assign m_m_valid_0_dummy2_1$D_IN = 1'd1 ;
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assign m_m_valid_0_dummy2_1$EN = EN_enq ;
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// remaining internal signals
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assign IF_m_m_specBits_0_dummy2_0_read__78_AND_m_m_sp_ETC___d281 =
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(m_m_specBits_0_dummy2_0$Q_OUT &&
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m_m_specBits_0_dummy2_1$Q_OUT) ?
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m_m_specBits_0_rl :
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12'd0 ;
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assign IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 =
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EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ;
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assign IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6 =
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m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl ;
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assign sb__h10294 =
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m_m_specBits_0_dummy2_1$Q_OUT ?
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IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 :
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12'd0 ;
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assign upd__h2322 = m_m_specBits_0_lat_1$wget ;
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always@(enq_x)
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begin
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case (enq_x[399:397])
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3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
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CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1 =
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enq_x[399:397];
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default: CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1 = 3'd7;
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endcase
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end
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always@(enq_x or CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1)
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begin
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case (enq_x[416:414])
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3'd0, 3'd1, 3'd2, 3'd3:
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CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
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enq_x[416:396];
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3'd4:
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CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
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{ enq_x[416:414],
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9'h0AA,
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enq_x[404:400],
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CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1,
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enq_x[396] };
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default: CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
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21'd1485482;
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endcase
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end
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always@(enq_x)
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begin
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case (enq_x[394:383])
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12'd1,
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12'd2,
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12'd3,
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12'd256,
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12'd260,
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12'd261,
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12'd262,
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12'd320,
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12'd321,
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12'd322,
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12'd323,
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12'd324,
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12'd384,
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12'd768,
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12'd769,
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12'd770,
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12'd771,
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12'd772,
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12'd773,
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12'd774,
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12'd832,
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12'd833,
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12'd834,
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12'd835,
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12'd836,
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12'd1968,
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12'd1969,
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12'd1970,
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12'd1971,
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12'd2048,
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12'd2049,
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12'd2816,
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12'd2818,
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12'd3072,
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12'd3073,
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12'd3074,
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12'd3857,
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12'd3858,
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12'd3859,
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12'd3860:
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CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3 =
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enq_x[394:383];
|
|
default: CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[387:385])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4 =
|
|
m_m_row_0[387:385];
|
|
default: CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0 or CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4)
|
|
begin
|
|
case (m_m_row_0[404:402])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
|
|
m_m_row_0[404:384];
|
|
3'd4:
|
|
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
|
|
{ m_m_row_0[404:402],
|
|
9'h0AA,
|
|
m_m_row_0[392:388],
|
|
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4,
|
|
m_m_row_0[384] };
|
|
default: CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(m_m_row_0)
|
|
begin
|
|
case (m_m_row_0[382:371])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd1968,
|
|
12'd1969,
|
|
12'd1970,
|
|
12'd1971,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6 =
|
|
m_m_row_0[382:371];
|
|
default: CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_specBits_0_rl$EN)
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
|
|
if (m_m_valid_0_rl$EN)
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
|
|
end
|
|
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_row_0 =
|
|
410'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_specBits_0_rl = 12'hAAA;
|
|
m_m_valid_0_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_enq && m_m_valid_0_dummy2_1$Q_OUT &&
|
|
IF_m_m_valid_0_lat_0_whas_THEN_m_m_valid_0_lat_ETC___d6)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkAluRegToExeFifo
|
|
|