195 lines
4.8 KiB
Verilog
195 lines
4.8 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// pred_0_pred O 1
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// RDY_pred_0_pred O 1 const
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// pred_1_pred O 1
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// RDY_pred_1_pred O 1 const
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// RDY_update O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// CLK I 1 clock
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// RST_N I 1 unused
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// pred_0_pred_pc I 64
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// pred_1_pred_pc I 64
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// update_pc I 64
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// update_taken I 1
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// update_mispred I 1 unused
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// EN_update I 1
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// EN_flush I 1 unused
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// EN_pred_0_pred I 1 unused
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// EN_pred_1_pred I 1 unused
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkBht(CLK,
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RST_N,
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pred_0_pred_pc,
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EN_pred_0_pred,
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pred_0_pred,
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RDY_pred_0_pred,
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pred_1_pred_pc,
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EN_pred_1_pred,
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pred_1_pred,
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RDY_pred_1_pred,
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update_pc,
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update_taken,
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update_mispred,
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EN_update,
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RDY_update,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done);
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input CLK;
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input RST_N;
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// actionvalue method pred_0_pred
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input [63 : 0] pred_0_pred_pc;
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input EN_pred_0_pred;
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output pred_0_pred;
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output RDY_pred_0_pred;
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// actionvalue method pred_1_pred
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input [63 : 0] pred_1_pred_pc;
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input EN_pred_1_pred;
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output pred_1_pred;
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output RDY_pred_1_pred;
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// action method update
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input [63 : 0] update_pc;
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input update_taken;
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input update_mispred;
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input EN_update;
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output RDY_update;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// signals for module outputs
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wire RDY_flush,
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RDY_flush_done,
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RDY_pred_0_pred,
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RDY_pred_1_pred,
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RDY_update,
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flush_done,
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pred_0_pred,
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pred_1_pred;
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// ports of submodule hist
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wire [6 : 0] hist$ADDR_1,
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hist$ADDR_2,
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hist$ADDR_3,
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hist$ADDR_4,
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hist$ADDR_5,
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hist$ADDR_IN;
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wire [1 : 0] hist$D_IN, hist$D_OUT_1, hist$D_OUT_2, hist$D_OUT_3;
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wire hist$WE;
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// rule scheduling signals
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wire CAN_FIRE_flush,
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CAN_FIRE_pred_0_pred,
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CAN_FIRE_pred_1_pred,
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CAN_FIRE_update,
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WILL_FIRE_flush,
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WILL_FIRE_pred_0_pred,
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WILL_FIRE_pred_1_pred,
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WILL_FIRE_update;
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// remaining internal signals
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wire [1 : 0] next_hist__h472, next_hist__h478;
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// actionvalue method pred_0_pred
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assign pred_0_pred = hist$D_OUT_2[1] ;
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assign RDY_pred_0_pred = 1'd1 ;
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assign CAN_FIRE_pred_0_pred = 1'd1 ;
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assign WILL_FIRE_pred_0_pred = EN_pred_0_pred ;
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// actionvalue method pred_1_pred
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assign pred_1_pred = hist$D_OUT_1[1] ;
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assign RDY_pred_1_pred = 1'd1 ;
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assign CAN_FIRE_pred_1_pred = 1'd1 ;
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assign WILL_FIRE_pred_1_pred = EN_pred_1_pred ;
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// action method update
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assign RDY_update = 1'd1 ;
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assign CAN_FIRE_update = 1'd1 ;
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assign WILL_FIRE_update = EN_update ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = 1'd1 ;
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assign RDY_flush_done = 1'd1 ;
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// submodule hist
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RegFile #(.addr_width(32'd7),
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.data_width(32'd2),
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.lo(7'd0),
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.hi(7'd127)) hist(.CLK(CLK),
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.ADDR_1(hist$ADDR_1),
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.ADDR_2(hist$ADDR_2),
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.ADDR_3(hist$ADDR_3),
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.ADDR_4(hist$ADDR_4),
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.ADDR_5(hist$ADDR_5),
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.ADDR_IN(hist$ADDR_IN),
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.D_IN(hist$D_IN),
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.WE(hist$WE),
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.D_OUT_1(hist$D_OUT_1),
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.D_OUT_2(hist$D_OUT_2),
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.D_OUT_3(hist$D_OUT_3),
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.D_OUT_4(),
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.D_OUT_5());
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// submodule hist
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assign hist$ADDR_1 = pred_1_pred_pc[8:2] ;
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assign hist$ADDR_2 = pred_0_pred_pc[8:2] ;
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assign hist$ADDR_3 = update_pc[8:2] ;
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assign hist$ADDR_4 = 7'h0 ;
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assign hist$ADDR_5 = 7'h0 ;
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assign hist$ADDR_IN = update_pc[8:2] ;
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assign hist$D_IN = update_taken ? next_hist__h472 : next_hist__h478 ;
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assign hist$WE = EN_update ;
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// remaining internal signals
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assign next_hist__h472 =
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(hist$D_OUT_3 == 2'b11) ? hist$D_OUT_3 : hist$D_OUT_3 + 2'd1 ;
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assign next_hist__h478 =
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(hist$D_OUT_3 == 2'b0) ? hist$D_OUT_3 : hist$D_OUT_3 - 2'd1 ;
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endmodule // mkBht
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