9010 lines
357 KiB
Verilog
9010 lines
357 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// cRqTransfer_getRq O 153
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// RDY_cRqTransfer_getRq O 1 const
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// cRqTransfer_getEmptyEntryInit O 3 reg
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// RDY_cRqTransfer_getEmptyEntryInit O 1
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// sendRsToP_cRq_getState O 3
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// RDY_sendRsToP_cRq_getState O 1 const
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// sendRsToP_cRq_getRq O 153
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// RDY_sendRsToP_cRq_getRq O 1 const
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// sendRsToP_cRq_getSlot O 58
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// RDY_sendRsToP_cRq_getSlot O 1 const
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// sendRsToP_cRq_getData O 513
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// RDY_sendRsToP_cRq_getData O 1 const
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// RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData O 1 const
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// sendRqToP_getRq O 153
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// RDY_sendRqToP_getRq O 1 const
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// sendRqToP_getSlot O 58
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// RDY_sendRqToP_getSlot O 1 const
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// RDY_pipelineResp_releaseEntry O 1
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// pipelineResp_getState O 3
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// RDY_pipelineResp_getState O 1 const
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// pipelineResp_getRq O 153
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// RDY_pipelineResp_getRq O 1 const
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// pipelineResp_getSlot O 58
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// RDY_pipelineResp_getSlot O 1 const
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// RDY_pipelineResp_setData O 1 const
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// RDY_pipelineResp_setStateSlot O 1 const
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// pipelineResp_getSucc O 4
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// RDY_pipelineResp_getSucc O 1 const
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// RDY_pipelineResp_setSucc O 1 const
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// pipelineResp_searchEndOfChain O 4
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// RDY_pipelineResp_searchEndOfChain O 1 const
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// emptyForFlush O 1
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// RDY_emptyForFlush O 1 const
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// stuck_get O 159 const
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// RDY_stuck_get O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// cRqTransfer_getRq_n I 3
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// cRqTransfer_getEmptyEntryInit_r I 153
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// sendRsToP_cRq_getState_n I 3
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// sendRsToP_cRq_getRq_n I 3
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// sendRsToP_cRq_getSlot_n I 3
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// sendRsToP_cRq_getData_n I 3
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n I 3
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_slot I 58
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// sendRqToP_getRq_n I 3
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// sendRqToP_getSlot_n I 3
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// pipelineResp_releaseEntry_n I 3
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// pipelineResp_getState_n I 3
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// pipelineResp_getRq_n I 3
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// pipelineResp_getSlot_n I 3
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// pipelineResp_setData_n I 3
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// pipelineResp_setData_d I 513
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// pipelineResp_setStateSlot_n I 3
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// pipelineResp_setStateSlot_state I 3
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// pipelineResp_setStateSlot_slot I 58
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// pipelineResp_getSucc_n I 3
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// pipelineResp_setSucc_n I 3
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// pipelineResp_setSucc_succ I 4
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// pipelineResp_searchEndOfChain_addr I 64
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData I 1
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// EN_pipelineResp_releaseEntry I 1
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// EN_pipelineResp_setData I 1
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// EN_pipelineResp_setStateSlot I 1
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// EN_pipelineResp_setSucc I 1
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// EN_cRqTransfer_getEmptyEntryInit I 1
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// EN_stuck_get I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// cRqTransfer_getRq_n -> cRqTransfer_getRq
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// sendRsToP_cRq_getState_n -> sendRsToP_cRq_getState
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// sendRsToP_cRq_getRq_n -> sendRsToP_cRq_getRq
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// sendRsToP_cRq_getSlot_n -> sendRsToP_cRq_getSlot
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// sendRsToP_cRq_getData_n -> sendRsToP_cRq_getData
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// sendRqToP_getRq_n -> sendRqToP_getRq
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// sendRqToP_getSlot_n -> sendRqToP_getSlot
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// (pipelineResp_getState_n,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData) -> pipelineResp_getState
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// pipelineResp_getRq_n -> pipelineResp_getRq
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// (pipelineResp_getSlot_n,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_slot,
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData) -> pipelineResp_getSlot
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// pipelineResp_getSucc_n -> pipelineResp_getSucc
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// (pipelineResp_searchEndOfChain_addr,
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// sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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// EN_sendRsToP_cRq_setWaitSt_setSlot_clearData) -> pipelineResp_searchEndOfChain
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDCRqMshrWrapper(CLK,
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RST_N,
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cRqTransfer_getRq_n,
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cRqTransfer_getRq,
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RDY_cRqTransfer_getRq,
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cRqTransfer_getEmptyEntryInit_r,
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EN_cRqTransfer_getEmptyEntryInit,
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cRqTransfer_getEmptyEntryInit,
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RDY_cRqTransfer_getEmptyEntryInit,
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sendRsToP_cRq_getState_n,
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sendRsToP_cRq_getState,
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RDY_sendRsToP_cRq_getState,
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sendRsToP_cRq_getRq_n,
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sendRsToP_cRq_getRq,
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RDY_sendRsToP_cRq_getRq,
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sendRsToP_cRq_getSlot_n,
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sendRsToP_cRq_getSlot,
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RDY_sendRsToP_cRq_getSlot,
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sendRsToP_cRq_getData_n,
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sendRsToP_cRq_getData,
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RDY_sendRsToP_cRq_getData,
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sendRsToP_cRq_setWaitSt_setSlot_clearData_n,
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sendRsToP_cRq_setWaitSt_setSlot_clearData_slot,
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EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
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RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData,
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sendRqToP_getRq_n,
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sendRqToP_getRq,
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RDY_sendRqToP_getRq,
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sendRqToP_getSlot_n,
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sendRqToP_getSlot,
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RDY_sendRqToP_getSlot,
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pipelineResp_releaseEntry_n,
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EN_pipelineResp_releaseEntry,
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RDY_pipelineResp_releaseEntry,
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pipelineResp_getState_n,
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pipelineResp_getState,
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RDY_pipelineResp_getState,
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pipelineResp_getRq_n,
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pipelineResp_getRq,
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RDY_pipelineResp_getRq,
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pipelineResp_getSlot_n,
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pipelineResp_getSlot,
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RDY_pipelineResp_getSlot,
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pipelineResp_setData_n,
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pipelineResp_setData_d,
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EN_pipelineResp_setData,
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RDY_pipelineResp_setData,
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pipelineResp_setStateSlot_n,
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pipelineResp_setStateSlot_state,
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pipelineResp_setStateSlot_slot,
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EN_pipelineResp_setStateSlot,
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RDY_pipelineResp_setStateSlot,
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pipelineResp_getSucc_n,
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pipelineResp_getSucc,
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RDY_pipelineResp_getSucc,
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pipelineResp_setSucc_n,
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pipelineResp_setSucc_succ,
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EN_pipelineResp_setSucc,
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RDY_pipelineResp_setSucc,
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pipelineResp_searchEndOfChain_addr,
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pipelineResp_searchEndOfChain,
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RDY_pipelineResp_searchEndOfChain,
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emptyForFlush,
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RDY_emptyForFlush,
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EN_stuck_get,
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stuck_get,
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RDY_stuck_get);
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input CLK;
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input RST_N;
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// value method cRqTransfer_getRq
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input [2 : 0] cRqTransfer_getRq_n;
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output [152 : 0] cRqTransfer_getRq;
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output RDY_cRqTransfer_getRq;
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// actionvalue method cRqTransfer_getEmptyEntryInit
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input [152 : 0] cRqTransfer_getEmptyEntryInit_r;
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input EN_cRqTransfer_getEmptyEntryInit;
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output [2 : 0] cRqTransfer_getEmptyEntryInit;
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output RDY_cRqTransfer_getEmptyEntryInit;
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// value method sendRsToP_cRq_getState
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input [2 : 0] sendRsToP_cRq_getState_n;
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output [2 : 0] sendRsToP_cRq_getState;
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output RDY_sendRsToP_cRq_getState;
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// value method sendRsToP_cRq_getRq
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input [2 : 0] sendRsToP_cRq_getRq_n;
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output [152 : 0] sendRsToP_cRq_getRq;
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output RDY_sendRsToP_cRq_getRq;
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// value method sendRsToP_cRq_getSlot
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input [2 : 0] sendRsToP_cRq_getSlot_n;
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output [57 : 0] sendRsToP_cRq_getSlot;
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output RDY_sendRsToP_cRq_getSlot;
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// value method sendRsToP_cRq_getData
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input [2 : 0] sendRsToP_cRq_getData_n;
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output [512 : 0] sendRsToP_cRq_getData;
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output RDY_sendRsToP_cRq_getData;
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// action method sendRsToP_cRq_setWaitSt_setSlot_clearData
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input [2 : 0] sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
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input [57 : 0] sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
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input EN_sendRsToP_cRq_setWaitSt_setSlot_clearData;
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output RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData;
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// value method sendRqToP_getRq
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input [2 : 0] sendRqToP_getRq_n;
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output [152 : 0] sendRqToP_getRq;
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output RDY_sendRqToP_getRq;
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// value method sendRqToP_getSlot
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input [2 : 0] sendRqToP_getSlot_n;
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output [57 : 0] sendRqToP_getSlot;
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output RDY_sendRqToP_getSlot;
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// action method pipelineResp_releaseEntry
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input [2 : 0] pipelineResp_releaseEntry_n;
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input EN_pipelineResp_releaseEntry;
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output RDY_pipelineResp_releaseEntry;
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// value method pipelineResp_getState
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input [2 : 0] pipelineResp_getState_n;
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output [2 : 0] pipelineResp_getState;
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output RDY_pipelineResp_getState;
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// value method pipelineResp_getRq
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input [2 : 0] pipelineResp_getRq_n;
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output [152 : 0] pipelineResp_getRq;
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output RDY_pipelineResp_getRq;
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// value method pipelineResp_getSlot
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input [2 : 0] pipelineResp_getSlot_n;
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output [57 : 0] pipelineResp_getSlot;
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output RDY_pipelineResp_getSlot;
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// action method pipelineResp_setData
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input [2 : 0] pipelineResp_setData_n;
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input [512 : 0] pipelineResp_setData_d;
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input EN_pipelineResp_setData;
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output RDY_pipelineResp_setData;
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// action method pipelineResp_setStateSlot
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input [2 : 0] pipelineResp_setStateSlot_n;
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input [2 : 0] pipelineResp_setStateSlot_state;
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input [57 : 0] pipelineResp_setStateSlot_slot;
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input EN_pipelineResp_setStateSlot;
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output RDY_pipelineResp_setStateSlot;
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// value method pipelineResp_getSucc
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input [2 : 0] pipelineResp_getSucc_n;
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output [3 : 0] pipelineResp_getSucc;
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output RDY_pipelineResp_getSucc;
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// action method pipelineResp_setSucc
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input [2 : 0] pipelineResp_setSucc_n;
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input [3 : 0] pipelineResp_setSucc_succ;
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input EN_pipelineResp_setSucc;
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output RDY_pipelineResp_setSucc;
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// value method pipelineResp_searchEndOfChain
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input [63 : 0] pipelineResp_searchEndOfChain_addr;
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output [3 : 0] pipelineResp_searchEndOfChain;
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output RDY_pipelineResp_searchEndOfChain;
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// value method emptyForFlush
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output emptyForFlush;
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output RDY_emptyForFlush;
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// actionvalue method stuck_get
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input EN_stuck_get;
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output [158 : 0] stuck_get;
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output RDY_stuck_get;
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// signals for module outputs
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reg [2 : 0] pipelineResp_getState, sendRsToP_cRq_getState;
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wire [512 : 0] sendRsToP_cRq_getData;
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wire [158 : 0] stuck_get;
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wire [152 : 0] cRqTransfer_getRq,
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pipelineResp_getRq,
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sendRqToP_getRq,
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sendRsToP_cRq_getRq;
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wire [57 : 0] pipelineResp_getSlot,
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sendRqToP_getSlot,
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sendRsToP_cRq_getSlot;
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wire [3 : 0] pipelineResp_getSucc, pipelineResp_searchEndOfChain;
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wire [2 : 0] cRqTransfer_getEmptyEntryInit;
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wire RDY_cRqTransfer_getEmptyEntryInit,
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RDY_cRqTransfer_getRq,
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RDY_emptyForFlush,
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RDY_pipelineResp_getRq,
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RDY_pipelineResp_getSlot,
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RDY_pipelineResp_getState,
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RDY_pipelineResp_getSucc,
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RDY_pipelineResp_releaseEntry,
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RDY_pipelineResp_searchEndOfChain,
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RDY_pipelineResp_setData,
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RDY_pipelineResp_setStateSlot,
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RDY_pipelineResp_setSucc,
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RDY_sendRqToP_getRq,
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RDY_sendRqToP_getSlot,
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RDY_sendRsToP_cRq_getData,
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RDY_sendRsToP_cRq_getRq,
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RDY_sendRsToP_cRq_getSlot,
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RDY_sendRsToP_cRq_getState,
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RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData,
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RDY_stuck_get,
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emptyForFlush;
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// inlined wires
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wire [2 : 0] m_m_stateVec_0_lat_1$wget,
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m_m_stateVec_1_lat_1$wget,
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m_m_stateVec_2_lat_1$wget,
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m_m_stateVec_3_lat_1$wget,
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m_m_stateVec_4_lat_1$wget,
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m_m_stateVec_5_lat_1$wget,
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m_m_stateVec_6_lat_1$wget,
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m_m_stateVec_7_lat_1$wget;
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wire m_m_dataValidVec_0_lat_1$whas,
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m_m_dataValidVec_1_lat_1$whas,
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m_m_dataValidVec_2_lat_1$whas,
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m_m_dataValidVec_3_lat_1$whas,
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m_m_dataValidVec_4_lat_1$whas,
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m_m_dataValidVec_5_lat_1$whas,
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m_m_dataValidVec_6_lat_1$whas,
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m_m_dataValidVec_7_lat_1$whas,
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m_m_stateVec_0_dummy_1_0$whas,
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m_m_stateVec_0_lat_1$whas,
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m_m_stateVec_0_lat_2$whas,
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m_m_stateVec_1_dummy_1_0$whas,
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m_m_stateVec_1_lat_1$whas,
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m_m_stateVec_1_lat_2$whas,
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m_m_stateVec_2_dummy_1_0$whas,
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m_m_stateVec_2_lat_1$whas,
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m_m_stateVec_2_lat_2$whas,
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m_m_stateVec_3_dummy_1_0$whas,
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m_m_stateVec_3_lat_1$whas,
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m_m_stateVec_3_lat_2$whas,
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m_m_stateVec_4_dummy_1_0$whas,
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m_m_stateVec_4_lat_1$whas,
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m_m_stateVec_4_lat_2$whas,
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m_m_stateVec_5_dummy_1_0$whas,
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m_m_stateVec_5_lat_1$whas,
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m_m_stateVec_5_lat_2$whas,
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m_m_stateVec_6_dummy_1_0$whas,
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m_m_stateVec_6_lat_1$whas,
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m_m_stateVec_6_lat_2$whas,
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m_m_stateVec_7_dummy_1_0$whas,
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m_m_stateVec_7_lat_1$whas,
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m_m_stateVec_7_lat_2$whas,
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m_m_succValidVec_0_lat_1$whas,
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m_m_succValidVec_1_lat_1$whas,
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m_m_succValidVec_2_lat_1$whas,
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m_m_succValidVec_3_lat_1$whas,
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m_m_succValidVec_4_lat_1$whas,
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m_m_succValidVec_5_lat_1$whas,
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m_m_succValidVec_6_lat_1$whas,
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m_m_succValidVec_7_lat_1$whas;
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// register m_m_dataValidVec_0_rl
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reg m_m_dataValidVec_0_rl;
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wire m_m_dataValidVec_0_rl$D_IN, m_m_dataValidVec_0_rl$EN;
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// register m_m_dataValidVec_1_rl
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reg m_m_dataValidVec_1_rl;
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wire m_m_dataValidVec_1_rl$D_IN, m_m_dataValidVec_1_rl$EN;
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// register m_m_dataValidVec_2_rl
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reg m_m_dataValidVec_2_rl;
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wire m_m_dataValidVec_2_rl$D_IN, m_m_dataValidVec_2_rl$EN;
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// register m_m_dataValidVec_3_rl
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reg m_m_dataValidVec_3_rl;
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wire m_m_dataValidVec_3_rl$D_IN, m_m_dataValidVec_3_rl$EN;
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// register m_m_dataValidVec_4_rl
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reg m_m_dataValidVec_4_rl;
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wire m_m_dataValidVec_4_rl$D_IN, m_m_dataValidVec_4_rl$EN;
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// register m_m_dataValidVec_5_rl
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reg m_m_dataValidVec_5_rl;
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wire m_m_dataValidVec_5_rl$D_IN, m_m_dataValidVec_5_rl$EN;
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|
|
// register m_m_dataValidVec_6_rl
|
|
reg m_m_dataValidVec_6_rl;
|
|
wire m_m_dataValidVec_6_rl$D_IN, m_m_dataValidVec_6_rl$EN;
|
|
|
|
// register m_m_dataValidVec_7_rl
|
|
reg m_m_dataValidVec_7_rl;
|
|
wire m_m_dataValidVec_7_rl$D_IN, m_m_dataValidVec_7_rl$EN;
|
|
|
|
// register m_m_initIdx
|
|
reg [2 : 0] m_m_initIdx;
|
|
wire [2 : 0] m_m_initIdx$D_IN;
|
|
wire m_m_initIdx$EN;
|
|
|
|
// register m_m_inited
|
|
reg m_m_inited;
|
|
wire m_m_inited$D_IN, m_m_inited$EN;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
reg [152 : 0] m_m_reqVec_0_rl;
|
|
wire [152 : 0] m_m_reqVec_0_rl$D_IN;
|
|
wire m_m_reqVec_0_rl$EN;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
reg [152 : 0] m_m_reqVec_1_rl;
|
|
wire [152 : 0] m_m_reqVec_1_rl$D_IN;
|
|
wire m_m_reqVec_1_rl$EN;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
reg [152 : 0] m_m_reqVec_2_rl;
|
|
wire [152 : 0] m_m_reqVec_2_rl$D_IN;
|
|
wire m_m_reqVec_2_rl$EN;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
reg [152 : 0] m_m_reqVec_3_rl;
|
|
wire [152 : 0] m_m_reqVec_3_rl$D_IN;
|
|
wire m_m_reqVec_3_rl$EN;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
reg [152 : 0] m_m_reqVec_4_rl;
|
|
wire [152 : 0] m_m_reqVec_4_rl$D_IN;
|
|
wire m_m_reqVec_4_rl$EN;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
reg [152 : 0] m_m_reqVec_5_rl;
|
|
wire [152 : 0] m_m_reqVec_5_rl$D_IN;
|
|
wire m_m_reqVec_5_rl$EN;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
reg [152 : 0] m_m_reqVec_6_rl;
|
|
wire [152 : 0] m_m_reqVec_6_rl$D_IN;
|
|
wire m_m_reqVec_6_rl$EN;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
reg [152 : 0] m_m_reqVec_7_rl;
|
|
wire [152 : 0] m_m_reqVec_7_rl$D_IN;
|
|
wire m_m_reqVec_7_rl$EN;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
reg [57 : 0] m_m_slotVec_0_rl;
|
|
wire [57 : 0] m_m_slotVec_0_rl$D_IN;
|
|
wire m_m_slotVec_0_rl$EN;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
reg [57 : 0] m_m_slotVec_1_rl;
|
|
wire [57 : 0] m_m_slotVec_1_rl$D_IN;
|
|
wire m_m_slotVec_1_rl$EN;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
reg [57 : 0] m_m_slotVec_2_rl;
|
|
wire [57 : 0] m_m_slotVec_2_rl$D_IN;
|
|
wire m_m_slotVec_2_rl$EN;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
reg [57 : 0] m_m_slotVec_3_rl;
|
|
wire [57 : 0] m_m_slotVec_3_rl$D_IN;
|
|
wire m_m_slotVec_3_rl$EN;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
reg [57 : 0] m_m_slotVec_4_rl;
|
|
wire [57 : 0] m_m_slotVec_4_rl$D_IN;
|
|
wire m_m_slotVec_4_rl$EN;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
reg [57 : 0] m_m_slotVec_5_rl;
|
|
wire [57 : 0] m_m_slotVec_5_rl$D_IN;
|
|
wire m_m_slotVec_5_rl$EN;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
reg [57 : 0] m_m_slotVec_6_rl;
|
|
wire [57 : 0] m_m_slotVec_6_rl$D_IN;
|
|
wire m_m_slotVec_6_rl$EN;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
reg [57 : 0] m_m_slotVec_7_rl;
|
|
wire [57 : 0] m_m_slotVec_7_rl$D_IN;
|
|
wire m_m_slotVec_7_rl$EN;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
reg [2 : 0] m_m_stateVec_0_rl;
|
|
wire [2 : 0] m_m_stateVec_0_rl$D_IN;
|
|
wire m_m_stateVec_0_rl$EN;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
reg [2 : 0] m_m_stateVec_1_rl;
|
|
wire [2 : 0] m_m_stateVec_1_rl$D_IN;
|
|
wire m_m_stateVec_1_rl$EN;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
reg [2 : 0] m_m_stateVec_2_rl;
|
|
wire [2 : 0] m_m_stateVec_2_rl$D_IN;
|
|
wire m_m_stateVec_2_rl$EN;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
reg [2 : 0] m_m_stateVec_3_rl;
|
|
wire [2 : 0] m_m_stateVec_3_rl$D_IN;
|
|
wire m_m_stateVec_3_rl$EN;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
reg [2 : 0] m_m_stateVec_4_rl;
|
|
wire [2 : 0] m_m_stateVec_4_rl$D_IN;
|
|
wire m_m_stateVec_4_rl$EN;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
reg [2 : 0] m_m_stateVec_5_rl;
|
|
wire [2 : 0] m_m_stateVec_5_rl$D_IN;
|
|
wire m_m_stateVec_5_rl$EN;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
reg [2 : 0] m_m_stateVec_6_rl;
|
|
wire [2 : 0] m_m_stateVec_6_rl$D_IN;
|
|
wire m_m_stateVec_6_rl$EN;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
reg [2 : 0] m_m_stateVec_7_rl;
|
|
wire [2 : 0] m_m_stateVec_7_rl$D_IN;
|
|
wire m_m_stateVec_7_rl$EN;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
reg m_m_succValidVec_0_rl;
|
|
wire m_m_succValidVec_0_rl$D_IN, m_m_succValidVec_0_rl$EN;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
reg m_m_succValidVec_1_rl;
|
|
wire m_m_succValidVec_1_rl$D_IN, m_m_succValidVec_1_rl$EN;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
reg m_m_succValidVec_2_rl;
|
|
wire m_m_succValidVec_2_rl$D_IN, m_m_succValidVec_2_rl$EN;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
reg m_m_succValidVec_3_rl;
|
|
wire m_m_succValidVec_3_rl$D_IN, m_m_succValidVec_3_rl$EN;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
reg m_m_succValidVec_4_rl;
|
|
wire m_m_succValidVec_4_rl$D_IN, m_m_succValidVec_4_rl$EN;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
reg m_m_succValidVec_5_rl;
|
|
wire m_m_succValidVec_5_rl$D_IN, m_m_succValidVec_5_rl$EN;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
reg m_m_succValidVec_6_rl;
|
|
wire m_m_succValidVec_6_rl$D_IN, m_m_succValidVec_6_rl$EN;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
reg m_m_succValidVec_7_rl;
|
|
wire m_m_succValidVec_7_rl$D_IN, m_m_succValidVec_7_rl$EN;
|
|
|
|
// ports of submodule m_m_dataFile
|
|
wire [511 : 0] m_m_dataFile$D_IN, m_m_dataFile$D_OUT_1;
|
|
wire [2 : 0] m_m_dataFile$ADDR_1,
|
|
m_m_dataFile$ADDR_2,
|
|
m_m_dataFile$ADDR_3,
|
|
m_m_dataFile$ADDR_4,
|
|
m_m_dataFile$ADDR_5,
|
|
m_m_dataFile$ADDR_IN;
|
|
wire m_m_dataFile$WE;
|
|
|
|
// ports of submodule m_m_dataValidVec_0_dummy2_0
|
|
wire m_m_dataValidVec_0_dummy2_0$D_IN,
|
|
m_m_dataValidVec_0_dummy2_0$EN,
|
|
m_m_dataValidVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_0_dummy2_1
|
|
wire m_m_dataValidVec_0_dummy2_1$D_IN,
|
|
m_m_dataValidVec_0_dummy2_1$EN,
|
|
m_m_dataValidVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_0_dummy2_2
|
|
wire m_m_dataValidVec_0_dummy2_2$D_IN,
|
|
m_m_dataValidVec_0_dummy2_2$EN,
|
|
m_m_dataValidVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_1_dummy2_0
|
|
wire m_m_dataValidVec_1_dummy2_0$D_IN,
|
|
m_m_dataValidVec_1_dummy2_0$EN,
|
|
m_m_dataValidVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_1_dummy2_1
|
|
wire m_m_dataValidVec_1_dummy2_1$D_IN,
|
|
m_m_dataValidVec_1_dummy2_1$EN,
|
|
m_m_dataValidVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_1_dummy2_2
|
|
wire m_m_dataValidVec_1_dummy2_2$D_IN,
|
|
m_m_dataValidVec_1_dummy2_2$EN,
|
|
m_m_dataValidVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_2_dummy2_0
|
|
wire m_m_dataValidVec_2_dummy2_0$D_IN,
|
|
m_m_dataValidVec_2_dummy2_0$EN,
|
|
m_m_dataValidVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_2_dummy2_1
|
|
wire m_m_dataValidVec_2_dummy2_1$D_IN,
|
|
m_m_dataValidVec_2_dummy2_1$EN,
|
|
m_m_dataValidVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_2_dummy2_2
|
|
wire m_m_dataValidVec_2_dummy2_2$D_IN,
|
|
m_m_dataValidVec_2_dummy2_2$EN,
|
|
m_m_dataValidVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_3_dummy2_0
|
|
wire m_m_dataValidVec_3_dummy2_0$D_IN,
|
|
m_m_dataValidVec_3_dummy2_0$EN,
|
|
m_m_dataValidVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_3_dummy2_1
|
|
wire m_m_dataValidVec_3_dummy2_1$D_IN,
|
|
m_m_dataValidVec_3_dummy2_1$EN,
|
|
m_m_dataValidVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_3_dummy2_2
|
|
wire m_m_dataValidVec_3_dummy2_2$D_IN,
|
|
m_m_dataValidVec_3_dummy2_2$EN,
|
|
m_m_dataValidVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_4_dummy2_0
|
|
wire m_m_dataValidVec_4_dummy2_0$D_IN,
|
|
m_m_dataValidVec_4_dummy2_0$EN,
|
|
m_m_dataValidVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_4_dummy2_1
|
|
wire m_m_dataValidVec_4_dummy2_1$D_IN,
|
|
m_m_dataValidVec_4_dummy2_1$EN,
|
|
m_m_dataValidVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_4_dummy2_2
|
|
wire m_m_dataValidVec_4_dummy2_2$D_IN,
|
|
m_m_dataValidVec_4_dummy2_2$EN,
|
|
m_m_dataValidVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_5_dummy2_0
|
|
wire m_m_dataValidVec_5_dummy2_0$D_IN,
|
|
m_m_dataValidVec_5_dummy2_0$EN,
|
|
m_m_dataValidVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_5_dummy2_1
|
|
wire m_m_dataValidVec_5_dummy2_1$D_IN,
|
|
m_m_dataValidVec_5_dummy2_1$EN,
|
|
m_m_dataValidVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_5_dummy2_2
|
|
wire m_m_dataValidVec_5_dummy2_2$D_IN,
|
|
m_m_dataValidVec_5_dummy2_2$EN,
|
|
m_m_dataValidVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_6_dummy2_0
|
|
wire m_m_dataValidVec_6_dummy2_0$D_IN,
|
|
m_m_dataValidVec_6_dummy2_0$EN,
|
|
m_m_dataValidVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_6_dummy2_1
|
|
wire m_m_dataValidVec_6_dummy2_1$D_IN,
|
|
m_m_dataValidVec_6_dummy2_1$EN,
|
|
m_m_dataValidVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_6_dummy2_2
|
|
wire m_m_dataValidVec_6_dummy2_2$D_IN,
|
|
m_m_dataValidVec_6_dummy2_2$EN,
|
|
m_m_dataValidVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_7_dummy2_0
|
|
wire m_m_dataValidVec_7_dummy2_0$D_IN,
|
|
m_m_dataValidVec_7_dummy2_0$EN,
|
|
m_m_dataValidVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_7_dummy2_1
|
|
wire m_m_dataValidVec_7_dummy2_1$D_IN,
|
|
m_m_dataValidVec_7_dummy2_1$EN,
|
|
m_m_dataValidVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_dataValidVec_7_dummy2_2
|
|
wire m_m_dataValidVec_7_dummy2_2$D_IN,
|
|
m_m_dataValidVec_7_dummy2_2$EN,
|
|
m_m_dataValidVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_emptyEntryQ
|
|
wire [2 : 0] m_m_emptyEntryQ$D_IN, m_m_emptyEntryQ$D_OUT;
|
|
wire m_m_emptyEntryQ$CLR,
|
|
m_m_emptyEntryQ$DEQ,
|
|
m_m_emptyEntryQ$EMPTY_N,
|
|
m_m_emptyEntryQ$ENQ,
|
|
m_m_emptyEntryQ$FULL_N;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_0
|
|
wire m_m_reqVec_0_dummy2_0$D_IN,
|
|
m_m_reqVec_0_dummy2_0$EN,
|
|
m_m_reqVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_1
|
|
wire m_m_reqVec_0_dummy2_1$D_IN,
|
|
m_m_reqVec_0_dummy2_1$EN,
|
|
m_m_reqVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_2
|
|
wire m_m_reqVec_0_dummy2_2$D_IN,
|
|
m_m_reqVec_0_dummy2_2$EN,
|
|
m_m_reqVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_0
|
|
wire m_m_reqVec_1_dummy2_0$D_IN,
|
|
m_m_reqVec_1_dummy2_0$EN,
|
|
m_m_reqVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_1
|
|
wire m_m_reqVec_1_dummy2_1$D_IN,
|
|
m_m_reqVec_1_dummy2_1$EN,
|
|
m_m_reqVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_2
|
|
wire m_m_reqVec_1_dummy2_2$D_IN,
|
|
m_m_reqVec_1_dummy2_2$EN,
|
|
m_m_reqVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_0
|
|
wire m_m_reqVec_2_dummy2_0$D_IN,
|
|
m_m_reqVec_2_dummy2_0$EN,
|
|
m_m_reqVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_1
|
|
wire m_m_reqVec_2_dummy2_1$D_IN,
|
|
m_m_reqVec_2_dummy2_1$EN,
|
|
m_m_reqVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_2
|
|
wire m_m_reqVec_2_dummy2_2$D_IN,
|
|
m_m_reqVec_2_dummy2_2$EN,
|
|
m_m_reqVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_0
|
|
wire m_m_reqVec_3_dummy2_0$D_IN,
|
|
m_m_reqVec_3_dummy2_0$EN,
|
|
m_m_reqVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_1
|
|
wire m_m_reqVec_3_dummy2_1$D_IN,
|
|
m_m_reqVec_3_dummy2_1$EN,
|
|
m_m_reqVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_2
|
|
wire m_m_reqVec_3_dummy2_2$D_IN,
|
|
m_m_reqVec_3_dummy2_2$EN,
|
|
m_m_reqVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_4_dummy2_0
|
|
wire m_m_reqVec_4_dummy2_0$D_IN,
|
|
m_m_reqVec_4_dummy2_0$EN,
|
|
m_m_reqVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_4_dummy2_1
|
|
wire m_m_reqVec_4_dummy2_1$D_IN,
|
|
m_m_reqVec_4_dummy2_1$EN,
|
|
m_m_reqVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_4_dummy2_2
|
|
wire m_m_reqVec_4_dummy2_2$D_IN,
|
|
m_m_reqVec_4_dummy2_2$EN,
|
|
m_m_reqVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_5_dummy2_0
|
|
wire m_m_reqVec_5_dummy2_0$D_IN,
|
|
m_m_reqVec_5_dummy2_0$EN,
|
|
m_m_reqVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_5_dummy2_1
|
|
wire m_m_reqVec_5_dummy2_1$D_IN,
|
|
m_m_reqVec_5_dummy2_1$EN,
|
|
m_m_reqVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_5_dummy2_2
|
|
wire m_m_reqVec_5_dummy2_2$D_IN,
|
|
m_m_reqVec_5_dummy2_2$EN,
|
|
m_m_reqVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_6_dummy2_0
|
|
wire m_m_reqVec_6_dummy2_0$D_IN,
|
|
m_m_reqVec_6_dummy2_0$EN,
|
|
m_m_reqVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_6_dummy2_1
|
|
wire m_m_reqVec_6_dummy2_1$D_IN,
|
|
m_m_reqVec_6_dummy2_1$EN,
|
|
m_m_reqVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_6_dummy2_2
|
|
wire m_m_reqVec_6_dummy2_2$D_IN,
|
|
m_m_reqVec_6_dummy2_2$EN,
|
|
m_m_reqVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_7_dummy2_0
|
|
wire m_m_reqVec_7_dummy2_0$D_IN,
|
|
m_m_reqVec_7_dummy2_0$EN,
|
|
m_m_reqVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_7_dummy2_1
|
|
wire m_m_reqVec_7_dummy2_1$D_IN,
|
|
m_m_reqVec_7_dummy2_1$EN,
|
|
m_m_reqVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_7_dummy2_2
|
|
wire m_m_reqVec_7_dummy2_2$D_IN,
|
|
m_m_reqVec_7_dummy2_2$EN,
|
|
m_m_reqVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_0_dummy2_0
|
|
wire m_m_slotVec_0_dummy2_0$D_IN,
|
|
m_m_slotVec_0_dummy2_0$EN,
|
|
m_m_slotVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_0_dummy2_1
|
|
wire m_m_slotVec_0_dummy2_1$D_IN,
|
|
m_m_slotVec_0_dummy2_1$EN,
|
|
m_m_slotVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_0_dummy2_2
|
|
wire m_m_slotVec_0_dummy2_2$D_IN,
|
|
m_m_slotVec_0_dummy2_2$EN,
|
|
m_m_slotVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_1_dummy2_0
|
|
wire m_m_slotVec_1_dummy2_0$D_IN,
|
|
m_m_slotVec_1_dummy2_0$EN,
|
|
m_m_slotVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_1_dummy2_1
|
|
wire m_m_slotVec_1_dummy2_1$D_IN,
|
|
m_m_slotVec_1_dummy2_1$EN,
|
|
m_m_slotVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_1_dummy2_2
|
|
wire m_m_slotVec_1_dummy2_2$D_IN,
|
|
m_m_slotVec_1_dummy2_2$EN,
|
|
m_m_slotVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_2_dummy2_0
|
|
wire m_m_slotVec_2_dummy2_0$D_IN,
|
|
m_m_slotVec_2_dummy2_0$EN,
|
|
m_m_slotVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_2_dummy2_1
|
|
wire m_m_slotVec_2_dummy2_1$D_IN,
|
|
m_m_slotVec_2_dummy2_1$EN,
|
|
m_m_slotVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_2_dummy2_2
|
|
wire m_m_slotVec_2_dummy2_2$D_IN,
|
|
m_m_slotVec_2_dummy2_2$EN,
|
|
m_m_slotVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_3_dummy2_0
|
|
wire m_m_slotVec_3_dummy2_0$D_IN,
|
|
m_m_slotVec_3_dummy2_0$EN,
|
|
m_m_slotVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_3_dummy2_1
|
|
wire m_m_slotVec_3_dummy2_1$D_IN,
|
|
m_m_slotVec_3_dummy2_1$EN,
|
|
m_m_slotVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_3_dummy2_2
|
|
wire m_m_slotVec_3_dummy2_2$D_IN,
|
|
m_m_slotVec_3_dummy2_2$EN,
|
|
m_m_slotVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_4_dummy2_0
|
|
wire m_m_slotVec_4_dummy2_0$D_IN,
|
|
m_m_slotVec_4_dummy2_0$EN,
|
|
m_m_slotVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_4_dummy2_1
|
|
wire m_m_slotVec_4_dummy2_1$D_IN,
|
|
m_m_slotVec_4_dummy2_1$EN,
|
|
m_m_slotVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_4_dummy2_2
|
|
wire m_m_slotVec_4_dummy2_2$D_IN,
|
|
m_m_slotVec_4_dummy2_2$EN,
|
|
m_m_slotVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_5_dummy2_0
|
|
wire m_m_slotVec_5_dummy2_0$D_IN,
|
|
m_m_slotVec_5_dummy2_0$EN,
|
|
m_m_slotVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_5_dummy2_1
|
|
wire m_m_slotVec_5_dummy2_1$D_IN,
|
|
m_m_slotVec_5_dummy2_1$EN,
|
|
m_m_slotVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_5_dummy2_2
|
|
wire m_m_slotVec_5_dummy2_2$D_IN,
|
|
m_m_slotVec_5_dummy2_2$EN,
|
|
m_m_slotVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_6_dummy2_0
|
|
wire m_m_slotVec_6_dummy2_0$D_IN,
|
|
m_m_slotVec_6_dummy2_0$EN,
|
|
m_m_slotVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_6_dummy2_1
|
|
wire m_m_slotVec_6_dummy2_1$D_IN,
|
|
m_m_slotVec_6_dummy2_1$EN,
|
|
m_m_slotVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_6_dummy2_2
|
|
wire m_m_slotVec_6_dummy2_2$D_IN,
|
|
m_m_slotVec_6_dummy2_2$EN,
|
|
m_m_slotVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_7_dummy2_0
|
|
wire m_m_slotVec_7_dummy2_0$D_IN,
|
|
m_m_slotVec_7_dummy2_0$EN,
|
|
m_m_slotVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_7_dummy2_1
|
|
wire m_m_slotVec_7_dummy2_1$D_IN,
|
|
m_m_slotVec_7_dummy2_1$EN,
|
|
m_m_slotVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_7_dummy2_2
|
|
wire m_m_slotVec_7_dummy2_2$D_IN,
|
|
m_m_slotVec_7_dummy2_2$EN,
|
|
m_m_slotVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_0
|
|
wire m_m_stateVec_0_dummy2_0$D_IN,
|
|
m_m_stateVec_0_dummy2_0$EN,
|
|
m_m_stateVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_1
|
|
wire m_m_stateVec_0_dummy2_1$D_IN,
|
|
m_m_stateVec_0_dummy2_1$EN,
|
|
m_m_stateVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_2
|
|
wire m_m_stateVec_0_dummy2_2$D_IN,
|
|
m_m_stateVec_0_dummy2_2$EN,
|
|
m_m_stateVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_0
|
|
wire m_m_stateVec_1_dummy2_0$D_IN,
|
|
m_m_stateVec_1_dummy2_0$EN,
|
|
m_m_stateVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_1
|
|
wire m_m_stateVec_1_dummy2_1$D_IN,
|
|
m_m_stateVec_1_dummy2_1$EN,
|
|
m_m_stateVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_2
|
|
wire m_m_stateVec_1_dummy2_2$D_IN,
|
|
m_m_stateVec_1_dummy2_2$EN,
|
|
m_m_stateVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_0
|
|
wire m_m_stateVec_2_dummy2_0$D_IN,
|
|
m_m_stateVec_2_dummy2_0$EN,
|
|
m_m_stateVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_1
|
|
wire m_m_stateVec_2_dummy2_1$D_IN,
|
|
m_m_stateVec_2_dummy2_1$EN,
|
|
m_m_stateVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_2
|
|
wire m_m_stateVec_2_dummy2_2$D_IN,
|
|
m_m_stateVec_2_dummy2_2$EN,
|
|
m_m_stateVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_0
|
|
wire m_m_stateVec_3_dummy2_0$D_IN,
|
|
m_m_stateVec_3_dummy2_0$EN,
|
|
m_m_stateVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_1
|
|
wire m_m_stateVec_3_dummy2_1$D_IN,
|
|
m_m_stateVec_3_dummy2_1$EN,
|
|
m_m_stateVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_2
|
|
wire m_m_stateVec_3_dummy2_2$D_IN,
|
|
m_m_stateVec_3_dummy2_2$EN,
|
|
m_m_stateVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_4_dummy2_0
|
|
wire m_m_stateVec_4_dummy2_0$D_IN,
|
|
m_m_stateVec_4_dummy2_0$EN,
|
|
m_m_stateVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_4_dummy2_1
|
|
wire m_m_stateVec_4_dummy2_1$D_IN,
|
|
m_m_stateVec_4_dummy2_1$EN,
|
|
m_m_stateVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_4_dummy2_2
|
|
wire m_m_stateVec_4_dummy2_2$D_IN,
|
|
m_m_stateVec_4_dummy2_2$EN,
|
|
m_m_stateVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_5_dummy2_0
|
|
wire m_m_stateVec_5_dummy2_0$D_IN,
|
|
m_m_stateVec_5_dummy2_0$EN,
|
|
m_m_stateVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_5_dummy2_1
|
|
wire m_m_stateVec_5_dummy2_1$D_IN,
|
|
m_m_stateVec_5_dummy2_1$EN,
|
|
m_m_stateVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_5_dummy2_2
|
|
wire m_m_stateVec_5_dummy2_2$D_IN,
|
|
m_m_stateVec_5_dummy2_2$EN,
|
|
m_m_stateVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_6_dummy2_0
|
|
wire m_m_stateVec_6_dummy2_0$D_IN,
|
|
m_m_stateVec_6_dummy2_0$EN,
|
|
m_m_stateVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_6_dummy2_1
|
|
wire m_m_stateVec_6_dummy2_1$D_IN,
|
|
m_m_stateVec_6_dummy2_1$EN,
|
|
m_m_stateVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_6_dummy2_2
|
|
wire m_m_stateVec_6_dummy2_2$D_IN,
|
|
m_m_stateVec_6_dummy2_2$EN,
|
|
m_m_stateVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_7_dummy2_0
|
|
wire m_m_stateVec_7_dummy2_0$D_IN,
|
|
m_m_stateVec_7_dummy2_0$EN,
|
|
m_m_stateVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_7_dummy2_1
|
|
wire m_m_stateVec_7_dummy2_1$D_IN,
|
|
m_m_stateVec_7_dummy2_1$EN,
|
|
m_m_stateVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_7_dummy2_2
|
|
wire m_m_stateVec_7_dummy2_2$D_IN,
|
|
m_m_stateVec_7_dummy2_2$EN,
|
|
m_m_stateVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succFile
|
|
wire [2 : 0] m_m_succFile$ADDR_1,
|
|
m_m_succFile$ADDR_2,
|
|
m_m_succFile$ADDR_3,
|
|
m_m_succFile$ADDR_4,
|
|
m_m_succFile$ADDR_5,
|
|
m_m_succFile$ADDR_IN,
|
|
m_m_succFile$D_IN,
|
|
m_m_succFile$D_OUT_1;
|
|
wire m_m_succFile$WE;
|
|
|
|
// ports of submodule m_m_succValidVec_0_dummy2_0
|
|
wire m_m_succValidVec_0_dummy2_0$D_IN, m_m_succValidVec_0_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_0_dummy2_1
|
|
wire m_m_succValidVec_0_dummy2_1$D_IN,
|
|
m_m_succValidVec_0_dummy2_1$EN,
|
|
m_m_succValidVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_0_dummy2_2
|
|
wire m_m_succValidVec_0_dummy2_2$D_IN,
|
|
m_m_succValidVec_0_dummy2_2$EN,
|
|
m_m_succValidVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_1_dummy2_0
|
|
wire m_m_succValidVec_1_dummy2_0$D_IN, m_m_succValidVec_1_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_1_dummy2_1
|
|
wire m_m_succValidVec_1_dummy2_1$D_IN,
|
|
m_m_succValidVec_1_dummy2_1$EN,
|
|
m_m_succValidVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_1_dummy2_2
|
|
wire m_m_succValidVec_1_dummy2_2$D_IN,
|
|
m_m_succValidVec_1_dummy2_2$EN,
|
|
m_m_succValidVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_2_dummy2_0
|
|
wire m_m_succValidVec_2_dummy2_0$D_IN, m_m_succValidVec_2_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_2_dummy2_1
|
|
wire m_m_succValidVec_2_dummy2_1$D_IN,
|
|
m_m_succValidVec_2_dummy2_1$EN,
|
|
m_m_succValidVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_2_dummy2_2
|
|
wire m_m_succValidVec_2_dummy2_2$D_IN,
|
|
m_m_succValidVec_2_dummy2_2$EN,
|
|
m_m_succValidVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_3_dummy2_0
|
|
wire m_m_succValidVec_3_dummy2_0$D_IN, m_m_succValidVec_3_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_3_dummy2_1
|
|
wire m_m_succValidVec_3_dummy2_1$D_IN,
|
|
m_m_succValidVec_3_dummy2_1$EN,
|
|
m_m_succValidVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_3_dummy2_2
|
|
wire m_m_succValidVec_3_dummy2_2$D_IN,
|
|
m_m_succValidVec_3_dummy2_2$EN,
|
|
m_m_succValidVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_4_dummy2_0
|
|
wire m_m_succValidVec_4_dummy2_0$D_IN, m_m_succValidVec_4_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_4_dummy2_1
|
|
wire m_m_succValidVec_4_dummy2_1$D_IN,
|
|
m_m_succValidVec_4_dummy2_1$EN,
|
|
m_m_succValidVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_4_dummy2_2
|
|
wire m_m_succValidVec_4_dummy2_2$D_IN,
|
|
m_m_succValidVec_4_dummy2_2$EN,
|
|
m_m_succValidVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_5_dummy2_0
|
|
wire m_m_succValidVec_5_dummy2_0$D_IN, m_m_succValidVec_5_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_5_dummy2_1
|
|
wire m_m_succValidVec_5_dummy2_1$D_IN,
|
|
m_m_succValidVec_5_dummy2_1$EN,
|
|
m_m_succValidVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_5_dummy2_2
|
|
wire m_m_succValidVec_5_dummy2_2$D_IN,
|
|
m_m_succValidVec_5_dummy2_2$EN,
|
|
m_m_succValidVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_6_dummy2_0
|
|
wire m_m_succValidVec_6_dummy2_0$D_IN, m_m_succValidVec_6_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_6_dummy2_1
|
|
wire m_m_succValidVec_6_dummy2_1$D_IN,
|
|
m_m_succValidVec_6_dummy2_1$EN,
|
|
m_m_succValidVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_6_dummy2_2
|
|
wire m_m_succValidVec_6_dummy2_2$D_IN,
|
|
m_m_succValidVec_6_dummy2_2$EN,
|
|
m_m_succValidVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_7_dummy2_0
|
|
wire m_m_succValidVec_7_dummy2_0$D_IN, m_m_succValidVec_7_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_succValidVec_7_dummy2_1
|
|
wire m_m_succValidVec_7_dummy2_1$D_IN,
|
|
m_m_succValidVec_7_dummy2_1$EN,
|
|
m_m_succValidVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_7_dummy2_2
|
|
wire m_m_succValidVec_7_dummy2_2$D_IN,
|
|
m_m_succValidVec_7_dummy2_2$EN,
|
|
m_m_succValidVec_7_dummy2_2$Q_OUT;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_m_dataValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_4_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_5_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_6_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_7_canon,
|
|
CAN_FIRE_RL_m_m_initEmptyEntry,
|
|
CAN_FIRE_RL_m_m_reqVec_0_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_1_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_2_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_3_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_4_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_5_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_6_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_7_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_0_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_1_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_2_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_3_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_4_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_5_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_6_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_7_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_0_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_1_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_2_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_3_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_4_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_5_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_6_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_7_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_4_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_5_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_6_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_7_canon,
|
|
CAN_FIRE_cRqTransfer_getEmptyEntryInit,
|
|
CAN_FIRE_pipelineResp_releaseEntry,
|
|
CAN_FIRE_pipelineResp_setData,
|
|
CAN_FIRE_pipelineResp_setStateSlot,
|
|
CAN_FIRE_pipelineResp_setSucc,
|
|
CAN_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData,
|
|
CAN_FIRE_stuck_get,
|
|
WILL_FIRE_RL_m_m_dataValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_4_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_5_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_6_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_7_canon,
|
|
WILL_FIRE_RL_m_m_initEmptyEntry,
|
|
WILL_FIRE_RL_m_m_reqVec_0_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_1_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_2_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_3_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_4_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_5_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_6_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_7_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_0_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_1_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_2_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_3_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_4_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_5_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_6_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_7_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_0_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_1_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_2_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_3_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_4_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_5_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_6_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_7_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_4_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_5_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_6_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_7_canon,
|
|
WILL_FIRE_cRqTransfer_getEmptyEntryInit,
|
|
WILL_FIRE_pipelineResp_releaseEntry,
|
|
WILL_FIRE_pipelineResp_setData,
|
|
WILL_FIRE_pipelineResp_setStateSlot,
|
|
WILL_FIRE_pipelineResp_setSucc,
|
|
WILL_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData,
|
|
WILL_FIRE_stuck_get;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_6_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__SEL_2,
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] x__h122834,
|
|
x__h126540,
|
|
x__h131672,
|
|
x__h132330,
|
|
x__h136131,
|
|
x__h139989,
|
|
x__h87830,
|
|
x__h91840;
|
|
reg [51 : 0] x__h127575, x__h132397, x__h141144;
|
|
reg [4 : 0] x__h122029, x__h131633, x__h135238, x__h85367;
|
|
reg [3 : 0] SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118;
|
|
reg [2 : 0] SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615,
|
|
x__h126768,
|
|
x__h132358,
|
|
x__h140281;
|
|
reg [1 : 0] SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565,
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618,
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741,
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014;
|
|
reg SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066,
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121;
|
|
wire [63 : 0] n__read_addr__h122165,
|
|
n__read_addr__h122256,
|
|
n__read_addr__h122347,
|
|
n__read_addr__h122438,
|
|
n__read_addr__h122529,
|
|
n__read_addr__h122620,
|
|
n__read_addr__h122711,
|
|
n__read_addr__h122802,
|
|
n__read_addr__h135385,
|
|
n__read_addr__h135487,
|
|
n__read_addr__h135589,
|
|
n__read_addr__h135691,
|
|
n__read_addr__h135793,
|
|
n__read_addr__h135895,
|
|
n__read_addr__h135997,
|
|
n__read_addr__h136099,
|
|
n__read_addr__h86244,
|
|
n__read_addr__h86466,
|
|
n__read_addr__h86688,
|
|
n__read_addr__h86910,
|
|
n__read_addr__h87132,
|
|
n__read_addr__h87354,
|
|
n__read_addr__h87576,
|
|
n__read_addr__h87798,
|
|
n__read_data__h122169,
|
|
n__read_data__h122260,
|
|
n__read_data__h122351,
|
|
n__read_data__h122442,
|
|
n__read_data__h122533,
|
|
n__read_data__h122624,
|
|
n__read_data__h122715,
|
|
n__read_data__h122806,
|
|
n__read_data__h135389,
|
|
n__read_data__h135491,
|
|
n__read_data__h135593,
|
|
n__read_data__h135695,
|
|
n__read_data__h135797,
|
|
n__read_data__h135899,
|
|
n__read_data__h136001,
|
|
n__read_data__h136103,
|
|
n__read_data__h86248,
|
|
n__read_data__h86470,
|
|
n__read_data__h86692,
|
|
n__read_data__h86914,
|
|
n__read_data__h87136,
|
|
n__read_data__h87358,
|
|
n__read_data__h87580,
|
|
n__read_data__h87802;
|
|
wire [57 : 0] IF_m_m_slotVec_0_lat_1_whas__63_THEN_m_m_slotV_ETC___d169,
|
|
IF_m_m_slotVec_1_lat_1_whas__73_THEN_m_m_slotV_ETC___d179,
|
|
IF_m_m_slotVec_2_lat_1_whas__83_THEN_m_m_slotV_ETC___d189,
|
|
IF_m_m_slotVec_3_lat_1_whas__93_THEN_m_m_slotV_ETC___d199,
|
|
IF_m_m_slotVec_4_lat_1_whas__03_THEN_m_m_slotV_ETC___d209,
|
|
IF_m_m_slotVec_5_lat_1_whas__13_THEN_m_m_slotV_ETC___d219,
|
|
IF_m_m_slotVec_6_lat_1_whas__23_THEN_m_m_slotV_ETC___d229,
|
|
IF_m_m_slotVec_7_lat_1_whas__33_THEN_m_m_slotV_ETC___d239;
|
|
wire [51 : 0] n__read_repTag__h126904,
|
|
n__read_repTag__h126991,
|
|
n__read_repTag__h127078,
|
|
n__read_repTag__h127165,
|
|
n__read_repTag__h127252,
|
|
n__read_repTag__h127339,
|
|
n__read_repTag__h127426,
|
|
n__read_repTag__h127513,
|
|
n__read_repTag__h140423,
|
|
n__read_repTag__h140516,
|
|
n__read_repTag__h140609,
|
|
n__read_repTag__h140702,
|
|
n__read_repTag__h140795,
|
|
n__read_repTag__h140888,
|
|
n__read_repTag__h140981,
|
|
n__read_repTag__h141074;
|
|
wire [4 : 0] n__read_id__h122164,
|
|
n__read_id__h122255,
|
|
n__read_id__h122346,
|
|
n__read_id__h122437,
|
|
n__read_id__h122528,
|
|
n__read_id__h122619,
|
|
n__read_id__h122710,
|
|
n__read_id__h122801,
|
|
n__read_id__h135384,
|
|
n__read_id__h135486,
|
|
n__read_id__h135588,
|
|
n__read_id__h135690,
|
|
n__read_id__h135792,
|
|
n__read_id__h135894,
|
|
n__read_id__h135996,
|
|
n__read_id__h136098,
|
|
n__read_id__h86243,
|
|
n__read_id__h86465,
|
|
n__read_id__h86687,
|
|
n__read_id__h86909,
|
|
n__read_id__h87131,
|
|
n__read_id__h87353,
|
|
n__read_id__h87575,
|
|
n__read_id__h87797;
|
|
wire [3 : 0] IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1499,
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1500,
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1501,
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1502,
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1503,
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1504,
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1505,
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1506;
|
|
wire [2 : 0] IF_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m__ETC___d2347,
|
|
IF_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m__ETC___d2348,
|
|
IF_IF_m_m_stateVec_4_dummy2_1_read__310_AND_m__ETC___d2344,
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1396,
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1397,
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1398,
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1399,
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1400,
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1401,
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1402,
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1403,
|
|
IF_m_m_stateVec_0_dummy2_0_read__285_AND_m_m_s_ETC___d1290,
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754,
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8,
|
|
IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d1296,
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756,
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18,
|
|
IF_m_m_stateVec_2_dummy2_0_read__297_AND_m_m_s_ETC___d1302,
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758,
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28,
|
|
IF_m_m_stateVec_3_dummy2_0_read__303_AND_m_m_s_ETC___d1308,
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760,
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38,
|
|
IF_m_m_stateVec_4_dummy2_0_read__309_AND_m_m_s_ETC___d1314,
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762,
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48,
|
|
IF_m_m_stateVec_5_dummy2_0_read__315_AND_m_m_s_ETC___d1320,
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764,
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58,
|
|
IF_m_m_stateVec_6_dummy2_0_read__321_AND_m_m_s_ETC___d1326,
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766,
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68,
|
|
IF_m_m_stateVec_7_dummy2_0_read__327_AND_m_m_s_ETC___d1332,
|
|
IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768,
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78,
|
|
n__read_way__h126902,
|
|
n__read_way__h126989,
|
|
n__read_way__h127076,
|
|
n__read_way__h127163,
|
|
n__read_way__h127250,
|
|
n__read_way__h127337,
|
|
n__read_way__h127424,
|
|
n__read_way__h127511,
|
|
n__read_way__h140421,
|
|
n__read_way__h140514,
|
|
n__read_way__h140607,
|
|
n__read_way__h140700,
|
|
n__read_way__h140793,
|
|
n__read_way__h140886,
|
|
n__read_way__h140979,
|
|
n__read_way__h141072;
|
|
wire [1 : 0] IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1386,
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1387,
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1388,
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1389,
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1390,
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1391,
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1392,
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1393,
|
|
IF_m_m_slotVec_0_dummy2_0_read__543_AND_m_m_sl_ETC___d1602,
|
|
IF_m_m_slotVec_0_dummy2_1_read__544_AND_m_m_sl_ETC___d1991,
|
|
IF_m_m_slotVec_1_dummy2_0_read__550_AND_m_m_sl_ETC___d1604,
|
|
IF_m_m_slotVec_1_dummy2_1_read__551_AND_m_m_sl_ETC___d1994,
|
|
IF_m_m_slotVec_2_dummy2_0_read__557_AND_m_m_sl_ETC___d1606,
|
|
IF_m_m_slotVec_2_dummy2_1_read__558_AND_m_m_sl_ETC___d1997,
|
|
IF_m_m_slotVec_3_dummy2_0_read__564_AND_m_m_sl_ETC___d1608,
|
|
IF_m_m_slotVec_3_dummy2_1_read__565_AND_m_m_sl_ETC___d2000,
|
|
IF_m_m_slotVec_4_dummy2_0_read__571_AND_m_m_sl_ETC___d1610,
|
|
IF_m_m_slotVec_4_dummy2_1_read__572_AND_m_m_sl_ETC___d2003,
|
|
IF_m_m_slotVec_5_dummy2_0_read__578_AND_m_m_sl_ETC___d1612,
|
|
IF_m_m_slotVec_5_dummy2_1_read__579_AND_m_m_sl_ETC___d2006,
|
|
IF_m_m_slotVec_6_dummy2_0_read__585_AND_m_m_sl_ETC___d1614,
|
|
IF_m_m_slotVec_6_dummy2_1_read__586_AND_m_m_sl_ETC___d2009,
|
|
IF_m_m_slotVec_7_dummy2_0_read__592_AND_m_m_sl_ETC___d1616,
|
|
IF_m_m_slotVec_7_dummy2_1_read__593_AND_m_m_sl_ETC___d2012;
|
|
wire IF_m_m_dataValidVec_0_lat_1_whas__43_THEN_m_m__ETC___d249,
|
|
IF_m_m_dataValidVec_1_lat_1_whas__53_THEN_m_m__ETC___d259,
|
|
IF_m_m_dataValidVec_2_lat_1_whas__63_THEN_m_m__ETC___d269,
|
|
IF_m_m_dataValidVec_3_lat_1_whas__73_THEN_m_m__ETC___d279,
|
|
IF_m_m_dataValidVec_4_lat_1_whas__83_THEN_m_m__ETC___d289,
|
|
IF_m_m_dataValidVec_5_lat_1_whas__93_THEN_m_m__ETC___d299,
|
|
IF_m_m_dataValidVec_6_lat_1_whas__03_THEN_m_m__ETC___d309,
|
|
IF_m_m_dataValidVec_7_lat_1_whas__13_THEN_m_m__ETC___d319,
|
|
IF_m_m_reqVec_0_dummy2_1_read__335_AND_m_m_req_ETC___d2145,
|
|
IF_m_m_reqVec_1_dummy2_1_read__340_AND_m_m_req_ETC___d2164,
|
|
IF_m_m_reqVec_2_dummy2_1_read__345_AND_m_m_req_ETC___d2184,
|
|
IF_m_m_reqVec_3_dummy2_1_read__350_AND_m_m_req_ETC___d2203,
|
|
IF_m_m_reqVec_4_dummy2_1_read__355_AND_m_m_req_ETC___d2224,
|
|
IF_m_m_reqVec_5_dummy2_1_read__360_AND_m_m_req_ETC___d2243,
|
|
IF_m_m_reqVec_6_dummy2_1_read__365_AND_m_m_req_ETC___d2263,
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d2299,
|
|
IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d2363,
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d2304,
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d2310,
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d2315,
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d2322,
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d2327,
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d2333,
|
|
NOT_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_ETC___d2154,
|
|
NOT_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_ETC___d2294,
|
|
NOT_IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_ETC___d2173,
|
|
NOT_IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_ETC___d2193,
|
|
NOT_IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_ETC___d2212,
|
|
NOT_IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_ETC___d2233,
|
|
NOT_IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_ETC___d2252,
|
|
NOT_IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_ETC___d2272,
|
|
NOT_IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_ETC___d2291,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1406,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1416,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1426,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1437,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1447,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1458,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1468,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1479,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1509,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1519,
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1529,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1407,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1417,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1427,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1438,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1448,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1459,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1469,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1480,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1510,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1520,
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1530,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1408,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1418,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1428,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1439,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1449,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1460,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1470,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1481,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1511,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1521,
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1531,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1409,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1419,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1429,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1440,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1450,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1461,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1471,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1482,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1512,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1522,
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1532,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1410,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1420,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1430,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1441,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1451,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1462,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1472,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1483,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1513,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1523,
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1533,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1411,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1421,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1431,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1442,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1452,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1463,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1473,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1484,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1514,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1524,
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1534,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1412,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1422,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1432,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1443,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1453,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1464,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1474,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1485,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1515,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1525,
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1535,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1413,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1423,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1433,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1444,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1454,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1465,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1475,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1486,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1516,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1526,
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1536,
|
|
m_m_slotVec_0_dummy2_0_read__543_AND_m_m_slotV_ETC___d1638,
|
|
m_m_slotVec_0_dummy2_1_read__544_AND_m_m_slotV_ETC___d2043,
|
|
m_m_slotVec_1_dummy2_0_read__550_AND_m_m_slotV_ETC___d1640,
|
|
m_m_slotVec_1_dummy2_1_read__551_AND_m_m_slotV_ETC___d2046,
|
|
m_m_slotVec_2_dummy2_0_read__557_AND_m_m_slotV_ETC___d1642,
|
|
m_m_slotVec_2_dummy2_1_read__558_AND_m_m_slotV_ETC___d2049,
|
|
m_m_slotVec_3_dummy2_0_read__564_AND_m_m_slotV_ETC___d1644,
|
|
m_m_slotVec_3_dummy2_1_read__565_AND_m_m_slotV_ETC___d2052,
|
|
m_m_slotVec_4_dummy2_0_read__571_AND_m_m_slotV_ETC___d1646,
|
|
m_m_slotVec_4_dummy2_1_read__572_AND_m_m_slotV_ETC___d2055,
|
|
m_m_slotVec_5_dummy2_0_read__578_AND_m_m_slotV_ETC___d1648,
|
|
m_m_slotVec_5_dummy2_1_read__579_AND_m_m_slotV_ETC___d2058,
|
|
m_m_slotVec_6_dummy2_0_read__585_AND_m_m_slotV_ETC___d1650,
|
|
m_m_slotVec_6_dummy2_1_read__586_AND_m_m_slotV_ETC___d2061,
|
|
m_m_slotVec_7_dummy2_0_read__592_AND_m_m_slotV_ETC___d1652,
|
|
m_m_slotVec_7_dummy2_1_read__593_AND_m_m_slotV_ETC___d2064;
|
|
|
|
// value method cRqTransfer_getRq
|
|
assign cRqTransfer_getRq =
|
|
{ x__h85367,
|
|
x__h87830,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018,
|
|
x__h91840,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 } ;
|
|
assign RDY_cRqTransfer_getRq = 1'd1 ;
|
|
|
|
// actionvalue method cRqTransfer_getEmptyEntryInit
|
|
assign cRqTransfer_getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
|
|
assign RDY_cRqTransfer_getEmptyEntryInit =
|
|
m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign CAN_FIRE_cRqTransfer_getEmptyEntryInit =
|
|
m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign WILL_FIRE_cRqTransfer_getEmptyEntryInit =
|
|
EN_cRqTransfer_getEmptyEntryInit ;
|
|
|
|
// value method sendRsToP_cRq_getState
|
|
always@(sendRsToP_cRq_getState_n or
|
|
IF_m_m_stateVec_0_dummy2_0_read__285_AND_m_m_s_ETC___d1290 or
|
|
IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d1296 or
|
|
IF_m_m_stateVec_2_dummy2_0_read__297_AND_m_m_s_ETC___d1302 or
|
|
IF_m_m_stateVec_3_dummy2_0_read__303_AND_m_m_s_ETC___d1308 or
|
|
IF_m_m_stateVec_4_dummy2_0_read__309_AND_m_m_s_ETC___d1314 or
|
|
IF_m_m_stateVec_5_dummy2_0_read__315_AND_m_m_s_ETC___d1320 or
|
|
IF_m_m_stateVec_6_dummy2_0_read__321_AND_m_m_s_ETC___d1326 or
|
|
IF_m_m_stateVec_7_dummy2_0_read__327_AND_m_m_s_ETC___d1332)
|
|
begin
|
|
case (sendRsToP_cRq_getState_n)
|
|
3'd0:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_0_dummy2_0_read__285_AND_m_m_s_ETC___d1290;
|
|
3'd1:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d1296;
|
|
3'd2:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_2_dummy2_0_read__297_AND_m_m_s_ETC___d1302;
|
|
3'd3:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_3_dummy2_0_read__303_AND_m_m_s_ETC___d1308;
|
|
3'd4:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_4_dummy2_0_read__309_AND_m_m_s_ETC___d1314;
|
|
3'd5:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_5_dummy2_0_read__315_AND_m_m_s_ETC___d1320;
|
|
3'd6:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_6_dummy2_0_read__321_AND_m_m_s_ETC___d1326;
|
|
3'd7:
|
|
sendRsToP_cRq_getState =
|
|
IF_m_m_stateVec_7_dummy2_0_read__327_AND_m_m_s_ETC___d1332;
|
|
endcase
|
|
end
|
|
assign RDY_sendRsToP_cRq_getState = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getRq
|
|
assign sendRsToP_cRq_getRq =
|
|
{ x__h122029,
|
|
x__h122834,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488,
|
|
x__h126540,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 } ;
|
|
assign RDY_sendRsToP_cRq_getRq = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getSlot
|
|
assign sendRsToP_cRq_getSlot =
|
|
{ x__h126768,
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618,
|
|
x__h127575,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 } ;
|
|
assign RDY_sendRsToP_cRq_getSlot = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getData
|
|
assign sendRsToP_cRq_getData =
|
|
{ SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705,
|
|
m_m_dataFile$D_OUT_1 } ;
|
|
assign RDY_sendRsToP_cRq_getData = 1'd1 ;
|
|
|
|
// action method sendRsToP_cRq_setWaitSt_setSlot_clearData
|
|
assign RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData = 1'd1 ;
|
|
assign CAN_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData = 1'd1 ;
|
|
assign WILL_FIRE_sendRsToP_cRq_setWaitSt_setSlot_clearData =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData ;
|
|
|
|
// value method sendRqToP_getRq
|
|
assign sendRqToP_getRq =
|
|
{ x__h131633,
|
|
x__h131672,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730,
|
|
x__h132330,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 } ;
|
|
assign RDY_sendRqToP_getRq = 1'd1 ;
|
|
|
|
// value method sendRqToP_getSlot
|
|
assign sendRqToP_getSlot =
|
|
{ x__h132358,
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741,
|
|
x__h132397,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 } ;
|
|
assign RDY_sendRqToP_getSlot = 1'd1 ;
|
|
|
|
// action method pipelineResp_releaseEntry
|
|
assign RDY_pipelineResp_releaseEntry =
|
|
m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign CAN_FIRE_pipelineResp_releaseEntry =
|
|
m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign WILL_FIRE_pipelineResp_releaseEntry = EN_pipelineResp_releaseEntry ;
|
|
|
|
// value method pipelineResp_getState
|
|
always@(pipelineResp_getState_n or
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 or
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 or
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 or
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 or
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 or
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 or
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 or
|
|
IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768)
|
|
begin
|
|
case (pipelineResp_getState_n)
|
|
3'd0:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754;
|
|
3'd1:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756;
|
|
3'd2:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758;
|
|
3'd3:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760;
|
|
3'd4:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762;
|
|
3'd5:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764;
|
|
3'd6:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766;
|
|
3'd7:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getState = 1'd1 ;
|
|
|
|
// value method pipelineResp_getRq
|
|
assign pipelineResp_getRq =
|
|
{ x__h135238,
|
|
x__h136131,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900,
|
|
x__h139989,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940,
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 } ;
|
|
assign RDY_pipelineResp_getRq = 1'd1 ;
|
|
|
|
// value method pipelineResp_getSlot
|
|
assign pipelineResp_getSlot =
|
|
{ x__h140281,
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014,
|
|
x__h141144,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 } ;
|
|
assign RDY_pipelineResp_getSlot = 1'd1 ;
|
|
|
|
// action method pipelineResp_setData
|
|
assign RDY_pipelineResp_setData = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setData = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setData = EN_pipelineResp_setData ;
|
|
|
|
// action method pipelineResp_setStateSlot
|
|
assign RDY_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setStateSlot = EN_pipelineResp_setStateSlot ;
|
|
|
|
// value method pipelineResp_getSucc
|
|
assign pipelineResp_getSucc =
|
|
{ SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121,
|
|
m_m_succFile$D_OUT_1 } ;
|
|
assign RDY_pipelineResp_getSucc = 1'd1 ;
|
|
|
|
// action method pipelineResp_setSucc
|
|
assign RDY_pipelineResp_setSucc = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setSucc = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setSucc = EN_pipelineResp_setSucc ;
|
|
|
|
// value method pipelineResp_searchEndOfChain
|
|
assign pipelineResp_searchEndOfChain =
|
|
{ NOT_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_ETC___d2294,
|
|
IF_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m__ETC___d2348 } ;
|
|
assign RDY_pipelineResp_searchEndOfChain = 1'd1 ;
|
|
|
|
// value method emptyForFlush
|
|
assign emptyForFlush =
|
|
IF_m_m_stateVec_0_dummy2_0_read__285_AND_m_m_s_ETC___d1290 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d2363 ;
|
|
assign RDY_emptyForFlush = 1'd1 ;
|
|
|
|
// actionvalue method stuck_get
|
|
assign stuck_get = 159'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_stuck_get = 1'd0 ;
|
|
assign CAN_FIRE_stuck_get = 1'd0 ;
|
|
assign WILL_FIRE_stuck_get = EN_stuck_get ;
|
|
|
|
// submodule m_m_dataFile
|
|
RegFile #(.addr_width(32'd3),
|
|
.data_width(32'd512),
|
|
.lo(3'd0),
|
|
.hi(3'd7)) m_m_dataFile(.CLK(CLK),
|
|
.ADDR_1(m_m_dataFile$ADDR_1),
|
|
.ADDR_2(m_m_dataFile$ADDR_2),
|
|
.ADDR_3(m_m_dataFile$ADDR_3),
|
|
.ADDR_4(m_m_dataFile$ADDR_4),
|
|
.ADDR_5(m_m_dataFile$ADDR_5),
|
|
.ADDR_IN(m_m_dataFile$ADDR_IN),
|
|
.D_IN(m_m_dataFile$D_IN),
|
|
.WE(m_m_dataFile$WE),
|
|
.D_OUT_1(m_m_dataFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_m_emptyEntryQ$D_IN),
|
|
.ENQ(m_m_emptyEntryQ$ENQ),
|
|
.DEQ(m_m_emptyEntryQ$DEQ),
|
|
.CLR(m_m_emptyEntryQ$CLR),
|
|
.D_OUT(m_m_emptyEntryQ$D_OUT),
|
|
.FULL_N(m_m_emptyEntryQ$FULL_N),
|
|
.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succFile
|
|
RegFile #(.addr_width(32'd3),
|
|
.data_width(32'd3),
|
|
.lo(3'd0),
|
|
.hi(3'd7)) m_m_succFile(.CLK(CLK),
|
|
.ADDR_1(m_m_succFile$ADDR_1),
|
|
.ADDR_2(m_m_succFile$ADDR_2),
|
|
.ADDR_3(m_m_succFile$ADDR_3),
|
|
.ADDR_4(m_m_succFile$ADDR_4),
|
|
.ADDR_5(m_m_succFile$ADDR_5),
|
|
.ADDR_IN(m_m_succFile$ADDR_IN),
|
|
.D_IN(m_m_succFile$D_IN),
|
|
.WE(m_m_succFile$WE),
|
|
.D_OUT_1(m_m_succFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_1_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_2_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_3_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_4_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_5_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_6_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_7_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_7_dummy2_2$Q_OUT));
|
|
|
|
// rule RL_m_m_initEmptyEntry
|
|
assign CAN_FIRE_RL_m_m_initEmptyEntry =
|
|
m_m_emptyEntryQ$FULL_N && !m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// rule RL_m_m_stateVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd0 ;
|
|
assign MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd0 ;
|
|
assign MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd1 ;
|
|
assign MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd1 ;
|
|
assign MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd2 ;
|
|
assign MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd2 ;
|
|
assign MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd3 ;
|
|
assign MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd3 ;
|
|
assign MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd4 ;
|
|
assign MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd4 ;
|
|
assign MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd5 ;
|
|
assign MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd5 ;
|
|
assign MUX_m_m_stateVec_6_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd6 ;
|
|
assign MUX_m_m_stateVec_6_dummy_1_0$wset_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd6 ;
|
|
assign MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd7 ;
|
|
assign MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd7 ;
|
|
assign MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd0 ;
|
|
assign MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd1 ;
|
|
assign MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd2 ;
|
|
assign MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd3 ;
|
|
assign MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd4 ;
|
|
assign MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd5 ;
|
|
assign MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd6 ;
|
|
assign MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_cRq_setWaitSt_setSlot_clearData &&
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_n == 3'd7 ;
|
|
|
|
// inlined wires
|
|
assign m_m_stateVec_0_lat_1$wget =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_0_lat_1$whas =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_0_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd0 ;
|
|
assign m_m_stateVec_0_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd0 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd0 ;
|
|
assign m_m_stateVec_1_lat_1$wget =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_1_lat_1$whas =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_1_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd1 ;
|
|
assign m_m_stateVec_1_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd1 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd1 ;
|
|
assign m_m_stateVec_2_lat_1$wget =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_2_lat_1$whas =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_2_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd2 ;
|
|
assign m_m_stateVec_2_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd2 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd2 ;
|
|
assign m_m_stateVec_3_lat_1$wget =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_3_lat_1$whas =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_3_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd3 ;
|
|
assign m_m_stateVec_3_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd3 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd3 ;
|
|
assign m_m_stateVec_4_lat_1$wget =
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_4_lat_1$whas =
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_4_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd4 ;
|
|
assign m_m_stateVec_4_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd4 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd4 ;
|
|
assign m_m_stateVec_5_lat_1$wget =
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_5_lat_1$whas =
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_5_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd5 ;
|
|
assign m_m_stateVec_5_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd5 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd5 ;
|
|
assign m_m_stateVec_6_lat_1$wget =
|
|
MUX_m_m_stateVec_6_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_6_lat_1$whas =
|
|
MUX_m_m_stateVec_6_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__SEL_2 ;
|
|
assign m_m_stateVec_6_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd6 ;
|
|
assign m_m_stateVec_6_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd6 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd6 ;
|
|
assign m_m_stateVec_7_lat_1$wget =
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_1 ?
|
|
3'd0 :
|
|
pipelineResp_setStateSlot_state ;
|
|
assign m_m_stateVec_7_lat_1$whas =
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_7_lat_2$whas =
|
|
EN_cRqTransfer_getEmptyEntryInit &&
|
|
m_m_emptyEntryQ$D_OUT == 3'd7 ;
|
|
assign m_m_stateVec_7_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 3'd7 ||
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd7 ;
|
|
assign m_m_dataValidVec_0_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd0 ;
|
|
assign m_m_dataValidVec_1_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd1 ;
|
|
assign m_m_dataValidVec_2_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd2 ;
|
|
assign m_m_dataValidVec_3_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd3 ;
|
|
assign m_m_dataValidVec_4_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd4 ;
|
|
assign m_m_dataValidVec_5_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd5 ;
|
|
assign m_m_dataValidVec_6_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd6 ;
|
|
assign m_m_dataValidVec_7_lat_1$whas =
|
|
EN_pipelineResp_setData && pipelineResp_setData_n == 3'd7 ;
|
|
assign m_m_succValidVec_0_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd0 ;
|
|
assign m_m_succValidVec_1_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd1 ;
|
|
assign m_m_succValidVec_2_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd2 ;
|
|
assign m_m_succValidVec_3_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd3 ;
|
|
assign m_m_succValidVec_4_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd4 ;
|
|
assign m_m_succValidVec_5_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd5 ;
|
|
assign m_m_succValidVec_6_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd6 ;
|
|
assign m_m_succValidVec_7_lat_1$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd7 ;
|
|
|
|
// register m_m_dataValidVec_0_rl
|
|
assign m_m_dataValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
IF_m_m_dataValidVec_0_lat_1_whas__43_THEN_m_m__ETC___d249 ;
|
|
assign m_m_dataValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_1_rl
|
|
assign m_m_dataValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
IF_m_m_dataValidVec_1_lat_1_whas__53_THEN_m_m__ETC___d259 ;
|
|
assign m_m_dataValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_2_rl
|
|
assign m_m_dataValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
IF_m_m_dataValidVec_2_lat_1_whas__63_THEN_m_m__ETC___d269 ;
|
|
assign m_m_dataValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_3_rl
|
|
assign m_m_dataValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
IF_m_m_dataValidVec_3_lat_1_whas__73_THEN_m_m__ETC___d279 ;
|
|
assign m_m_dataValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_4_rl
|
|
assign m_m_dataValidVec_4_rl$D_IN =
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
IF_m_m_dataValidVec_4_lat_1_whas__83_THEN_m_m__ETC___d289 ;
|
|
assign m_m_dataValidVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_5_rl
|
|
assign m_m_dataValidVec_5_rl$D_IN =
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
IF_m_m_dataValidVec_5_lat_1_whas__93_THEN_m_m__ETC___d299 ;
|
|
assign m_m_dataValidVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_6_rl
|
|
assign m_m_dataValidVec_6_rl$D_IN =
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
IF_m_m_dataValidVec_6_lat_1_whas__03_THEN_m_m__ETC___d309 ;
|
|
assign m_m_dataValidVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_7_rl
|
|
assign m_m_dataValidVec_7_rl$D_IN =
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
IF_m_m_dataValidVec_7_lat_1_whas__13_THEN_m_m__ETC___d319 ;
|
|
assign m_m_dataValidVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_initIdx
|
|
assign m_m_initIdx$D_IN = m_m_initIdx + 3'd1 ;
|
|
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// register m_m_inited
|
|
assign m_m_inited$D_IN = 1'd1 ;
|
|
assign m_m_inited$EN =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7 ;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
assign m_m_reqVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_0_rl ;
|
|
assign m_m_reqVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
assign m_m_reqVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_1_rl ;
|
|
assign m_m_reqVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
assign m_m_reqVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_2_rl ;
|
|
assign m_m_reqVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
assign m_m_reqVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_3_rl ;
|
|
assign m_m_reqVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
assign m_m_reqVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_4_rl ;
|
|
assign m_m_reqVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
assign m_m_reqVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_5_rl ;
|
|
assign m_m_reqVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
assign m_m_reqVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_6_rl ;
|
|
assign m_m_reqVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
assign m_m_reqVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
cRqTransfer_getEmptyEntryInit_r :
|
|
m_m_reqVec_7_rl ;
|
|
assign m_m_reqVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
assign m_m_slotVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_0_lat_1_whas__63_THEN_m_m_slotV_ETC___d169 ;
|
|
assign m_m_slotVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
assign m_m_slotVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_1_lat_1_whas__73_THEN_m_m_slotV_ETC___d179 ;
|
|
assign m_m_slotVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
assign m_m_slotVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_2_lat_1_whas__83_THEN_m_m_slotV_ETC___d189 ;
|
|
assign m_m_slotVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
assign m_m_slotVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_3_lat_1_whas__93_THEN_m_m_slotV_ETC___d199 ;
|
|
assign m_m_slotVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
assign m_m_slotVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_4_lat_1_whas__03_THEN_m_m_slotV_ETC___d209 ;
|
|
assign m_m_slotVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
assign m_m_slotVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_5_lat_1_whas__13_THEN_m_m_slotV_ETC___d219 ;
|
|
assign m_m_slotVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
assign m_m_slotVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_6_lat_1_whas__23_THEN_m_m_slotV_ETC___d229 ;
|
|
assign m_m_slotVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
assign m_m_slotVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
58'h155555555555554 :
|
|
IF_m_m_slotVec_7_lat_1_whas__33_THEN_m_m_slotV_ETC___d239 ;
|
|
assign m_m_slotVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
assign m_m_stateVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_0_lat_1$whas ?
|
|
m_m_stateVec_0_lat_1$wget :
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8) ;
|
|
assign m_m_stateVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
assign m_m_stateVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_1_lat_1$whas ?
|
|
m_m_stateVec_1_lat_1$wget :
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18) ;
|
|
assign m_m_stateVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
assign m_m_stateVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_2_lat_1$whas ?
|
|
m_m_stateVec_2_lat_1$wget :
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28) ;
|
|
assign m_m_stateVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
assign m_m_stateVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_3_lat_1$whas ?
|
|
m_m_stateVec_3_lat_1$wget :
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38) ;
|
|
assign m_m_stateVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
assign m_m_stateVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_4_lat_1$whas ?
|
|
m_m_stateVec_4_lat_1$wget :
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48) ;
|
|
assign m_m_stateVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
assign m_m_stateVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_5_lat_1$whas ?
|
|
m_m_stateVec_5_lat_1$wget :
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58) ;
|
|
assign m_m_stateVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
assign m_m_stateVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_6_lat_1$whas ?
|
|
m_m_stateVec_6_lat_1$wget :
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68) ;
|
|
assign m_m_stateVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
assign m_m_stateVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
3'd1 :
|
|
(m_m_stateVec_7_lat_1$whas ?
|
|
m_m_stateVec_7_lat_1$wget :
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78) ;
|
|
assign m_m_stateVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
assign m_m_succValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
(m_m_succValidVec_0_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_0_rl) ;
|
|
assign m_m_succValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
assign m_m_succValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
(m_m_succValidVec_1_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_1_rl) ;
|
|
assign m_m_succValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
assign m_m_succValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
(m_m_succValidVec_2_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_2_rl) ;
|
|
assign m_m_succValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
assign m_m_succValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
(m_m_succValidVec_3_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_3_rl) ;
|
|
assign m_m_succValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
assign m_m_succValidVec_4_rl$D_IN =
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
(m_m_succValidVec_4_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_4_rl) ;
|
|
assign m_m_succValidVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
assign m_m_succValidVec_5_rl$D_IN =
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
(m_m_succValidVec_5_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_5_rl) ;
|
|
assign m_m_succValidVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
assign m_m_succValidVec_6_rl$D_IN =
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
(m_m_succValidVec_6_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_6_rl) ;
|
|
assign m_m_succValidVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
assign m_m_succValidVec_7_rl$D_IN =
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
(m_m_succValidVec_7_lat_1$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_7_rl) ;
|
|
assign m_m_succValidVec_7_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_m_dataFile
|
|
assign m_m_dataFile$ADDR_1 = sendRsToP_cRq_getData_n ;
|
|
assign m_m_dataFile$ADDR_2 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_3 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_4 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_5 = 3'h0 ;
|
|
assign m_m_dataFile$ADDR_IN = pipelineResp_setData_n ;
|
|
assign m_m_dataFile$D_IN = pipelineResp_setData_d[511:0] ;
|
|
assign m_m_dataFile$WE = EN_pipelineResp_setData ;
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_0
|
|
assign m_m_dataValidVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_0_dummy2_0$EN =
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_1
|
|
assign m_m_dataValidVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_0_dummy2_1$EN = m_m_dataValidVec_0_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_2
|
|
assign m_m_dataValidVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_0
|
|
assign m_m_dataValidVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_1_dummy2_0$EN =
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_1
|
|
assign m_m_dataValidVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_1_dummy2_1$EN = m_m_dataValidVec_1_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_2
|
|
assign m_m_dataValidVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_0
|
|
assign m_m_dataValidVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_2_dummy2_0$EN =
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_1
|
|
assign m_m_dataValidVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_2_dummy2_1$EN = m_m_dataValidVec_2_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_2
|
|
assign m_m_dataValidVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_0
|
|
assign m_m_dataValidVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_3_dummy2_0$EN =
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_1
|
|
assign m_m_dataValidVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_3_dummy2_1$EN = m_m_dataValidVec_3_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_2
|
|
assign m_m_dataValidVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_4_dummy2_0
|
|
assign m_m_dataValidVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_4_dummy2_0$EN =
|
|
MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_4_dummy2_1
|
|
assign m_m_dataValidVec_4_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_4_dummy2_1$EN = m_m_dataValidVec_4_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_4_dummy2_2
|
|
assign m_m_dataValidVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_5_dummy2_0
|
|
assign m_m_dataValidVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_5_dummy2_0$EN =
|
|
MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_5_dummy2_1
|
|
assign m_m_dataValidVec_5_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_5_dummy2_1$EN = m_m_dataValidVec_5_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_5_dummy2_2
|
|
assign m_m_dataValidVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_6_dummy2_0
|
|
assign m_m_dataValidVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_6_dummy2_0$EN =
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_6_dummy2_1
|
|
assign m_m_dataValidVec_6_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_6_dummy2_1$EN = m_m_dataValidVec_6_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_6_dummy2_2
|
|
assign m_m_dataValidVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_7_dummy2_0
|
|
assign m_m_dataValidVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_7_dummy2_0$EN =
|
|
MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_dataValidVec_7_dummy2_1
|
|
assign m_m_dataValidVec_7_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_7_dummy2_1$EN = m_m_dataValidVec_7_lat_1$whas ;
|
|
|
|
// submodule m_m_dataValidVec_7_dummy2_2
|
|
assign m_m_dataValidVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
assign m_m_emptyEntryQ$D_IN =
|
|
EN_pipelineResp_releaseEntry ?
|
|
pipelineResp_releaseEntry_n :
|
|
m_m_initIdx ;
|
|
assign m_m_emptyEntryQ$ENQ =
|
|
EN_pipelineResp_releaseEntry || WILL_FIRE_RL_m_m_initEmptyEntry ;
|
|
assign m_m_emptyEntryQ$DEQ = EN_cRqTransfer_getEmptyEntryInit ;
|
|
assign m_m_emptyEntryQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_0
|
|
assign m_m_reqVec_0_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_0_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_1
|
|
assign m_m_reqVec_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_2
|
|
assign m_m_reqVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_0
|
|
assign m_m_reqVec_1_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_1_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_1
|
|
assign m_m_reqVec_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_2
|
|
assign m_m_reqVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_0
|
|
assign m_m_reqVec_2_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_2_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_1
|
|
assign m_m_reqVec_2_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_2_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_2
|
|
assign m_m_reqVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_0
|
|
assign m_m_reqVec_3_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_3_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_1
|
|
assign m_m_reqVec_3_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_3_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_2
|
|
assign m_m_reqVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_4_dummy2_0
|
|
assign m_m_reqVec_4_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_4_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_4_dummy2_1
|
|
assign m_m_reqVec_4_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_4_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_4_dummy2_2
|
|
assign m_m_reqVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_5_dummy2_0
|
|
assign m_m_reqVec_5_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_5_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_5_dummy2_1
|
|
assign m_m_reqVec_5_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_5_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_5_dummy2_2
|
|
assign m_m_reqVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_6_dummy2_0
|
|
assign m_m_reqVec_6_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_6_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_6_dummy2_1
|
|
assign m_m_reqVec_6_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_6_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_6_dummy2_2
|
|
assign m_m_reqVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_7_dummy2_0
|
|
assign m_m_reqVec_7_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_7_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_7_dummy2_1
|
|
assign m_m_reqVec_7_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_7_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_7_dummy2_2
|
|
assign m_m_reqVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_0_dummy2_0
|
|
assign m_m_slotVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_0_dummy2_0$EN =
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_0_dummy2_1
|
|
assign m_m_slotVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_0_dummy2_1$EN =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_0_dummy2_2
|
|
assign m_m_slotVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_1_dummy2_0
|
|
assign m_m_slotVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_1_dummy2_0$EN =
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_1_dummy2_1
|
|
assign m_m_slotVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_1_dummy2_1$EN =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_1_dummy2_2
|
|
assign m_m_slotVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_2_dummy2_0
|
|
assign m_m_slotVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_2_dummy2_0$EN =
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_2_dummy2_1
|
|
assign m_m_slotVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_2_dummy2_1$EN =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_2_dummy2_2
|
|
assign m_m_slotVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_3_dummy2_0
|
|
assign m_m_slotVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_3_dummy2_0$EN =
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_3_dummy2_1
|
|
assign m_m_slotVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_3_dummy2_1$EN =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_3_dummy2_2
|
|
assign m_m_slotVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_4_dummy2_0
|
|
assign m_m_slotVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_4_dummy2_0$EN =
|
|
MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_4_dummy2_1
|
|
assign m_m_slotVec_4_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_4_dummy2_1$EN =
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_4_dummy2_2
|
|
assign m_m_slotVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_5_dummy2_0
|
|
assign m_m_slotVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_5_dummy2_0$EN =
|
|
MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_5_dummy2_1
|
|
assign m_m_slotVec_5_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_5_dummy2_1$EN =
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_5_dummy2_2
|
|
assign m_m_slotVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_6_dummy2_0
|
|
assign m_m_slotVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_6_dummy2_0$EN =
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_6_dummy2_1
|
|
assign m_m_slotVec_6_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_6_dummy2_1$EN =
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_6_dummy2_2
|
|
assign m_m_slotVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_7_dummy2_0
|
|
assign m_m_slotVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_7_dummy2_0$EN =
|
|
MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_slotVec_7_dummy2_1
|
|
assign m_m_slotVec_7_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_7_dummy2_1$EN =
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_slotVec_7_dummy2_2
|
|
assign m_m_slotVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_0
|
|
assign m_m_stateVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_0$EN =
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_1
|
|
assign m_m_stateVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_1$EN = m_m_stateVec_0_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_2
|
|
assign m_m_stateVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_0
|
|
assign m_m_stateVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_0$EN =
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_1
|
|
assign m_m_stateVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_1$EN = m_m_stateVec_1_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_2
|
|
assign m_m_stateVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_0
|
|
assign m_m_stateVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_0$EN =
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_1
|
|
assign m_m_stateVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_1$EN = m_m_stateVec_2_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_2
|
|
assign m_m_stateVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_0
|
|
assign m_m_stateVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_0$EN =
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_1
|
|
assign m_m_stateVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_1$EN = m_m_stateVec_3_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_2
|
|
assign m_m_stateVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_4_dummy2_0
|
|
assign m_m_stateVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_4_dummy2_0$EN =
|
|
MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_4_dummy2_1
|
|
assign m_m_stateVec_4_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_4_dummy2_1$EN = m_m_stateVec_4_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_4_dummy2_2
|
|
assign m_m_stateVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_5_dummy2_0
|
|
assign m_m_stateVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_5_dummy2_0$EN =
|
|
MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_5_dummy2_1
|
|
assign m_m_stateVec_5_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_5_dummy2_1$EN = m_m_stateVec_5_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_5_dummy2_2
|
|
assign m_m_stateVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_6_dummy2_0
|
|
assign m_m_stateVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_6_dummy2_0$EN =
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_6_dummy2_1
|
|
assign m_m_stateVec_6_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_6_dummy2_1$EN = m_m_stateVec_6_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_6_dummy2_2
|
|
assign m_m_stateVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_7_dummy2_0
|
|
assign m_m_stateVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_7_dummy2_0$EN =
|
|
MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_7_dummy2_1
|
|
assign m_m_stateVec_7_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_7_dummy2_1$EN = m_m_stateVec_7_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_7_dummy2_2
|
|
assign m_m_stateVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_succFile
|
|
assign m_m_succFile$ADDR_1 = pipelineResp_getSucc_n ;
|
|
assign m_m_succFile$ADDR_2 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_3 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_4 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_5 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_IN = pipelineResp_setSucc_n ;
|
|
assign m_m_succFile$D_IN = pipelineResp_setSucc_succ[2:0] ;
|
|
assign m_m_succFile$WE = EN_pipelineResp_setSucc ;
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_0
|
|
assign m_m_succValidVec_0_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_0_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_1
|
|
assign m_m_succValidVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_0_dummy2_1$EN = m_m_succValidVec_0_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_2
|
|
assign m_m_succValidVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_0
|
|
assign m_m_succValidVec_1_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_1_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_1
|
|
assign m_m_succValidVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_1_dummy2_1$EN = m_m_succValidVec_1_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_2
|
|
assign m_m_succValidVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_0
|
|
assign m_m_succValidVec_2_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_2_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_1
|
|
assign m_m_succValidVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_2_dummy2_1$EN = m_m_succValidVec_2_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_2
|
|
assign m_m_succValidVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_0
|
|
assign m_m_succValidVec_3_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_3_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_1
|
|
assign m_m_succValidVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_3_dummy2_1$EN = m_m_succValidVec_3_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_2
|
|
assign m_m_succValidVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_0
|
|
assign m_m_succValidVec_4_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_4_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_1
|
|
assign m_m_succValidVec_4_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_4_dummy2_1$EN = m_m_succValidVec_4_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_2
|
|
assign m_m_succValidVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_0
|
|
assign m_m_succValidVec_5_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_5_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_1
|
|
assign m_m_succValidVec_5_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_5_dummy2_1$EN = m_m_succValidVec_5_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_2
|
|
assign m_m_succValidVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_0
|
|
assign m_m_succValidVec_6_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_6_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_1
|
|
assign m_m_succValidVec_6_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_6_dummy2_1$EN = m_m_succValidVec_6_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_2
|
|
assign m_m_succValidVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_0
|
|
assign m_m_succValidVec_7_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_7_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_1
|
|
assign m_m_succValidVec_7_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_7_dummy2_1$EN = m_m_succValidVec_7_lat_1$whas ;
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_2
|
|
assign m_m_succValidVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m__ETC___d2347 =
|
|
(IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d2299 &&
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d2304) ?
|
|
(IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d2310 ?
|
|
3'd3 :
|
|
3'd2) :
|
|
(IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d2299 ?
|
|
3'd1 :
|
|
3'd0) ;
|
|
assign IF_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m__ETC___d2348 =
|
|
(IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d2299 &&
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d2304 &&
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d2310 &&
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d2315) ?
|
|
IF_IF_m_m_stateVec_4_dummy2_1_read__310_AND_m__ETC___d2344 :
|
|
IF_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m__ETC___d2347 ;
|
|
assign IF_IF_m_m_stateVec_4_dummy2_1_read__310_AND_m__ETC___d2344 =
|
|
(IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d2322 &&
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d2327) ?
|
|
(IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d2333 ?
|
|
3'd7 :
|
|
3'd6) :
|
|
(IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d2322 ?
|
|
3'd5 :
|
|
3'd4) ;
|
|
assign IF_m_m_dataValidVec_0_lat_1_whas__43_THEN_m_m__ETC___d249 =
|
|
m_m_dataValidVec_0_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_0_rl ;
|
|
assign IF_m_m_dataValidVec_1_lat_1_whas__53_THEN_m_m__ETC___d259 =
|
|
m_m_dataValidVec_1_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_1_rl ;
|
|
assign IF_m_m_dataValidVec_2_lat_1_whas__63_THEN_m_m__ETC___d269 =
|
|
m_m_dataValidVec_2_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_2_rl ;
|
|
assign IF_m_m_dataValidVec_3_lat_1_whas__73_THEN_m_m__ETC___d279 =
|
|
m_m_dataValidVec_3_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_3_rl ;
|
|
assign IF_m_m_dataValidVec_4_lat_1_whas__83_THEN_m_m__ETC___d289 =
|
|
m_m_dataValidVec_4_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_4_rl ;
|
|
assign IF_m_m_dataValidVec_5_lat_1_whas__93_THEN_m_m__ETC___d299 =
|
|
m_m_dataValidVec_5_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_5_rl ;
|
|
assign IF_m_m_dataValidVec_6_lat_1_whas__03_THEN_m_m__ETC___d309 =
|
|
m_m_dataValidVec_6_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_6_rl ;
|
|
assign IF_m_m_dataValidVec_7_lat_1_whas__13_THEN_m_m__ETC___d319 =
|
|
m_m_dataValidVec_7_lat_1$whas ?
|
|
pipelineResp_setData_d[512] :
|
|
!MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 &&
|
|
m_m_dataValidVec_7_rl ;
|
|
assign IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1386 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1396 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1499 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_0_dummy2_1_read__335_AND_m_m_req_ETC___d2145 =
|
|
n__read_addr__h135385[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1387 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1397 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1500 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_1_dummy2_1_read__340_AND_m_m_req_ETC___d2164 =
|
|
n__read_addr__h135487[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1388 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1398 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1501 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_2_dummy2_1_read__345_AND_m_m_req_ETC___d2184 =
|
|
n__read_addr__h135589[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1389 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1399 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1502 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_3_dummy2_1_read__350_AND_m_m_req_ETC___d2203 =
|
|
n__read_addr__h135691[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1390 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1400 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1503 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_4_dummy2_1_read__355_AND_m_m_req_ETC___d2224 =
|
|
n__read_addr__h135793[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1391 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1401 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1504 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_5_dummy2_1_read__360_AND_m_m_req_ETC___d2243 =
|
|
n__read_addr__h135895[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1392 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1402 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1505 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_reqVec_6_dummy2_1_read__365_AND_m_m_req_ETC___d2263 =
|
|
n__read_addr__h135997[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1393 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[83:82] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1403 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[81:79] :
|
|
3'd0 ;
|
|
assign IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1506 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[6:3] :
|
|
4'd0 ;
|
|
assign IF_m_m_slotVec_0_dummy2_0_read__543_AND_m_m_sl_ETC___d1602 =
|
|
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_0_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_0_dummy2_1_read__544_AND_m_m_sl_ETC___d1991 =
|
|
(m_m_slotVec_0_dummy2_1$Q_OUT && m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_0_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_0_lat_1_whas__63_THEN_m_m_slotV_ETC___d169 =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_0_rl) ;
|
|
assign IF_m_m_slotVec_1_dummy2_0_read__550_AND_m_m_sl_ETC___d1604 =
|
|
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_1_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_1_dummy2_1_read__551_AND_m_m_sl_ETC___d1994 =
|
|
(m_m_slotVec_1_dummy2_1$Q_OUT && m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_1_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_1_lat_1_whas__73_THEN_m_m_slotV_ETC___d179 =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_1_rl) ;
|
|
assign IF_m_m_slotVec_2_dummy2_0_read__557_AND_m_m_sl_ETC___d1606 =
|
|
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_2_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_2_dummy2_1_read__558_AND_m_m_sl_ETC___d1997 =
|
|
(m_m_slotVec_2_dummy2_1$Q_OUT && m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_2_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_2_lat_1_whas__83_THEN_m_m_slotV_ETC___d189 =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_2_rl) ;
|
|
assign IF_m_m_slotVec_3_dummy2_0_read__564_AND_m_m_sl_ETC___d1608 =
|
|
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_3_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_3_dummy2_1_read__565_AND_m_m_sl_ETC___d2000 =
|
|
(m_m_slotVec_3_dummy2_1$Q_OUT && m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_3_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_3_lat_1_whas__93_THEN_m_m_slotV_ETC___d199 =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_3_rl) ;
|
|
assign IF_m_m_slotVec_4_dummy2_0_read__571_AND_m_m_sl_ETC___d1610 =
|
|
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_4_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_4_dummy2_1_read__572_AND_m_m_sl_ETC___d2003 =
|
|
(m_m_slotVec_4_dummy2_1$Q_OUT && m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_4_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_4_lat_1_whas__03_THEN_m_m_slotV_ETC___d209 =
|
|
MUX_m_m_stateVec_4_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_4_rl) ;
|
|
assign IF_m_m_slotVec_5_dummy2_0_read__578_AND_m_m_sl_ETC___d1612 =
|
|
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_5_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_5_dummy2_1_read__579_AND_m_m_sl_ETC___d2006 =
|
|
(m_m_slotVec_5_dummy2_1$Q_OUT && m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_5_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_5_lat_1_whas__13_THEN_m_m_slotV_ETC___d219 =
|
|
MUX_m_m_stateVec_5_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_5_rl) ;
|
|
assign IF_m_m_slotVec_6_dummy2_0_read__585_AND_m_m_sl_ETC___d1614 =
|
|
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_6_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_6_dummy2_1_read__586_AND_m_m_sl_ETC___d2009 =
|
|
(m_m_slotVec_6_dummy2_1$Q_OUT && m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_6_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_6_lat_1_whas__23_THEN_m_m_slotV_ETC___d229 =
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_6_rl) ;
|
|
assign IF_m_m_slotVec_7_dummy2_0_read__592_AND_m_m_sl_ETC___d1616 =
|
|
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_7_rl[54:53] :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_7_dummy2_1_read__593_AND_m_m_sl_ETC___d2012 =
|
|
(m_m_slotVec_7_dummy2_1$Q_OUT && m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[54:53] :
|
|
m_m_slotVec_7_rl[54:53]) :
|
|
2'd0 ;
|
|
assign IF_m_m_slotVec_7_lat_1_whas__33_THEN_m_m_slotV_ETC___d239 =
|
|
MUX_m_m_stateVec_7_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setStateSlot_slot :
|
|
(MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot :
|
|
m_m_slotVec_7_rl) ;
|
|
assign IF_m_m_stateVec_0_dummy2_0_read__285_AND_m_m_s_ETC___d1290 =
|
|
(m_m_stateVec_0_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_0_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_0_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 =
|
|
(m_m_stateVec_0_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_0_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d2299 =
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_0_dummy2_1_read__335_AND_m_m_req_ETC___d2145 ||
|
|
m_m_succValidVec_0_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_0_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_0_rl ;
|
|
assign IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 =
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_0_rl ;
|
|
assign IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d1296 =
|
|
(m_m_stateVec_1_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_1_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_1_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d2363 =
|
|
IF_m_m_stateVec_1_dummy2_0_read__291_AND_m_m_s_ETC___d1296 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_2_dummy2_0_read__297_AND_m_m_s_ETC___d1302 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_3_dummy2_0_read__303_AND_m_m_s_ETC___d1308 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_4_dummy2_0_read__309_AND_m_m_s_ETC___d1314 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_5_dummy2_0_read__315_AND_m_m_s_ETC___d1320 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_6_dummy2_0_read__321_AND_m_m_s_ETC___d1326 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_7_dummy2_0_read__327_AND_m_m_s_ETC___d1332 ==
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 =
|
|
(m_m_stateVec_1_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_1_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d2304 =
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_1_dummy2_1_read__340_AND_m_m_req_ETC___d2164 ||
|
|
m_m_succValidVec_1_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_1_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_1_rl ;
|
|
assign IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 =
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_1_rl ;
|
|
assign IF_m_m_stateVec_2_dummy2_0_read__297_AND_m_m_s_ETC___d1302 =
|
|
(m_m_stateVec_2_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_2_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_2_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 =
|
|
(m_m_stateVec_2_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_2_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d2310 =
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_2_dummy2_1_read__345_AND_m_m_req_ETC___d2184 ||
|
|
m_m_succValidVec_2_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_2_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_2_rl ;
|
|
assign IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 =
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_2_rl ;
|
|
assign IF_m_m_stateVec_3_dummy2_0_read__303_AND_m_m_s_ETC___d1308 =
|
|
(m_m_stateVec_3_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_3_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_3_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 =
|
|
(m_m_stateVec_3_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_3_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d2315 =
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_3_dummy2_1_read__350_AND_m_m_req_ETC___d2203 ||
|
|
m_m_succValidVec_3_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_3_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_3_rl ;
|
|
assign IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 =
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_3_rl ;
|
|
assign IF_m_m_stateVec_4_dummy2_0_read__309_AND_m_m_s_ETC___d1314 =
|
|
(m_m_stateVec_4_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_4_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_4_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 =
|
|
(m_m_stateVec_4_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_4_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d2322 =
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_4_dummy2_1_read__355_AND_m_m_req_ETC___d2224 ||
|
|
m_m_succValidVec_4_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_4_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_4_rl ;
|
|
assign IF_m_m_stateVec_4_lat_0_whas__5_THEN_m_m_state_ETC___d48 =
|
|
MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_4_rl ;
|
|
assign IF_m_m_stateVec_5_dummy2_0_read__315_AND_m_m_s_ETC___d1320 =
|
|
(m_m_stateVec_5_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_5_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_5_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 =
|
|
(m_m_stateVec_5_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_5_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d2327 =
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_5_dummy2_1_read__360_AND_m_m_req_ETC___d2243 ||
|
|
m_m_succValidVec_5_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_5_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_5_rl ;
|
|
assign IF_m_m_stateVec_5_lat_0_whas__5_THEN_m_m_state_ETC___d58 =
|
|
MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_5_rl ;
|
|
assign IF_m_m_stateVec_6_dummy2_0_read__321_AND_m_m_s_ETC___d1326 =
|
|
(m_m_stateVec_6_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_6_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_6_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 =
|
|
(m_m_stateVec_6_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_6_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d2333 =
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 ==
|
|
3'd4 ||
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_6_dummy2_1_read__365_AND_m_m_req_ETC___d2263 ||
|
|
m_m_succValidVec_6_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_6_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_6_rl ;
|
|
assign IF_m_m_stateVec_6_lat_0_whas__5_THEN_m_m_state_ETC___d68 =
|
|
MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_6_rl ;
|
|
assign IF_m_m_stateVec_7_dummy2_0_read__327_AND_m_m_s_ETC___d1332 =
|
|
(m_m_stateVec_7_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_7_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_7_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768 =
|
|
(m_m_stateVec_7_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_7_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78 :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_7_lat_0_whas__5_THEN_m_m_state_ETC___d78 =
|
|
MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ?
|
|
3'd3 :
|
|
m_m_stateVec_7_rl ;
|
|
assign NOT_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_ETC___d2154 =
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_m_s_ETC___d1754 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_0_dummy2_1_read__335_AND_m_m_req_ETC___d2145 &&
|
|
(!m_m_succValidVec_0_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_0_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_0_rl) ;
|
|
assign NOT_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_ETC___d2294 =
|
|
NOT_IF_m_m_stateVec_0_dummy2_1_read__286_AND_m_ETC___d2154 ||
|
|
NOT_IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_ETC___d2173 ||
|
|
NOT_IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_ETC___d2193 ||
|
|
NOT_IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_ETC___d2212 ||
|
|
NOT_IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_ETC___d2233 ||
|
|
NOT_IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_ETC___d2252 ||
|
|
NOT_IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_ETC___d2272 ||
|
|
NOT_IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_ETC___d2291 ;
|
|
assign NOT_IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_ETC___d2173 =
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_1_dummy2_1_read__292_AND_m_m_s_ETC___d1756 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_1_dummy2_1_read__340_AND_m_m_req_ETC___d2164 &&
|
|
(!m_m_succValidVec_1_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_1_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_1_rl) ;
|
|
assign NOT_IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_ETC___d2193 =
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_2_dummy2_1_read__298_AND_m_m_s_ETC___d1758 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_2_dummy2_1_read__345_AND_m_m_req_ETC___d2184 &&
|
|
(!m_m_succValidVec_2_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_2_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_2_rl) ;
|
|
assign NOT_IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_ETC___d2212 =
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_3_dummy2_1_read__304_AND_m_m_s_ETC___d1760 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_3_dummy2_1_read__350_AND_m_m_req_ETC___d2203 &&
|
|
(!m_m_succValidVec_3_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_3_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_3_rl) ;
|
|
assign NOT_IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_ETC___d2233 =
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_4_dummy2_1_read__310_AND_m_m_s_ETC___d1762 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_4_dummy2_1_read__355_AND_m_m_req_ETC___d2224 &&
|
|
(!m_m_succValidVec_4_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_4_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_4_rl) ;
|
|
assign NOT_IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_ETC___d2252 =
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_5_dummy2_1_read__316_AND_m_m_s_ETC___d1764 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_5_dummy2_1_read__360_AND_m_m_req_ETC___d2243 &&
|
|
(!m_m_succValidVec_5_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_5_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_5_rl) ;
|
|
assign NOT_IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_ETC___d2272 =
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_6_dummy2_1_read__322_AND_m_m_s_ETC___d1766 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_6_dummy2_1_read__365_AND_m_m_req_ETC___d2263 &&
|
|
(!m_m_succValidVec_6_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_6_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_6_rl) ;
|
|
assign NOT_IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_ETC___d2291 =
|
|
IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768 !=
|
|
3'd4 &&
|
|
IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_7_dummy2_1_read__328_AND_m_m_s_ETC___d1768 !=
|
|
3'd1 &&
|
|
n__read_addr__h136099[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] &&
|
|
(!m_m_succValidVec_7_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_7_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_7_rl) ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1406 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[78] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1416 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[77] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1426 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[76] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1437 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[75] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1447 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[74] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1458 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[73] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1468 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[72] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1479 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[71] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1509 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[2] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1519 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[1] ;
|
|
assign m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1529 =
|
|
m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[0] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1407 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[78] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1417 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[77] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1427 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[76] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1438 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[75] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1448 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[74] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1459 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[73] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1469 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[72] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1480 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[71] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1510 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[2] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1520 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[1] ;
|
|
assign m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1530 =
|
|
m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[0] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1408 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[78] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1418 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[77] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1428 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[76] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1439 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[75] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1449 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[74] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1460 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[73] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1470 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[72] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1481 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[71] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1511 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[2] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1521 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[1] ;
|
|
assign m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1531 =
|
|
m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[0] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1409 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[78] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1419 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[77] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1429 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[76] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1440 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[75] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1450 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[74] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1461 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[73] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1471 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[72] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1482 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[71] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1512 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[2] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1522 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[1] ;
|
|
assign m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1532 =
|
|
m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[0] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1410 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[78] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1420 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[77] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1430 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[76] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1441 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[75] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1451 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[74] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1462 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[73] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1472 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[72] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1483 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[71] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1513 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[2] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1523 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[1] ;
|
|
assign m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1533 =
|
|
m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[0] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1411 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[78] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1421 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[77] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1431 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[76] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1442 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[75] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1452 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[74] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1463 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[73] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1473 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[72] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1484 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[71] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1514 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[2] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1524 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[1] ;
|
|
assign m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1534 =
|
|
m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[0] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1412 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[78] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1422 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[77] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1432 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[76] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1443 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[75] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1453 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[74] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1464 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[73] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1474 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[72] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1485 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[71] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1515 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[2] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1525 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[1] ;
|
|
assign m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1535 =
|
|
m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[0] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1413 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[78] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1423 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[77] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1433 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[76] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1444 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[75] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1454 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[74] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1465 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[73] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1475 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[72] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1486 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[71] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1516 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[2] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1526 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[1] ;
|
|
assign m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1536 =
|
|
m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[0] ;
|
|
assign m_m_slotVec_0_dummy2_0_read__543_AND_m_m_slotV_ETC___d1638 =
|
|
m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_0_rl[0] ;
|
|
assign m_m_slotVec_0_dummy2_1_read__544_AND_m_m_slotV_ETC___d2043 =
|
|
m_m_slotVec_0_dummy2_1$Q_OUT && m_m_slotVec_0_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_0_rl[0]) ;
|
|
assign m_m_slotVec_1_dummy2_0_read__550_AND_m_m_slotV_ETC___d1640 =
|
|
m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_1_rl[0] ;
|
|
assign m_m_slotVec_1_dummy2_1_read__551_AND_m_m_slotV_ETC___d2046 =
|
|
m_m_slotVec_1_dummy2_1$Q_OUT && m_m_slotVec_1_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_1_rl[0]) ;
|
|
assign m_m_slotVec_2_dummy2_0_read__557_AND_m_m_slotV_ETC___d1642 =
|
|
m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_2_rl[0] ;
|
|
assign m_m_slotVec_2_dummy2_1_read__558_AND_m_m_slotV_ETC___d2049 =
|
|
m_m_slotVec_2_dummy2_1$Q_OUT && m_m_slotVec_2_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_2_rl[0]) ;
|
|
assign m_m_slotVec_3_dummy2_0_read__564_AND_m_m_slotV_ETC___d1644 =
|
|
m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_3_rl[0] ;
|
|
assign m_m_slotVec_3_dummy2_1_read__565_AND_m_m_slotV_ETC___d2052 =
|
|
m_m_slotVec_3_dummy2_1$Q_OUT && m_m_slotVec_3_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_3_rl[0]) ;
|
|
assign m_m_slotVec_4_dummy2_0_read__571_AND_m_m_slotV_ETC___d1646 =
|
|
m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_4_rl[0] ;
|
|
assign m_m_slotVec_4_dummy2_1_read__572_AND_m_m_slotV_ETC___d2055 =
|
|
m_m_slotVec_4_dummy2_1$Q_OUT && m_m_slotVec_4_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_4_rl[0]) ;
|
|
assign m_m_slotVec_5_dummy2_0_read__578_AND_m_m_slotV_ETC___d1648 =
|
|
m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_5_rl[0] ;
|
|
assign m_m_slotVec_5_dummy2_1_read__579_AND_m_m_slotV_ETC___d2058 =
|
|
m_m_slotVec_5_dummy2_1$Q_OUT && m_m_slotVec_5_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_5_rl[0]) ;
|
|
assign m_m_slotVec_6_dummy2_0_read__585_AND_m_m_slotV_ETC___d1650 =
|
|
m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_6_rl[0] ;
|
|
assign m_m_slotVec_6_dummy2_1_read__586_AND_m_m_slotV_ETC___d2061 =
|
|
m_m_slotVec_6_dummy2_1$Q_OUT && m_m_slotVec_6_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_6_rl[0]) ;
|
|
assign m_m_slotVec_7_dummy2_0_read__592_AND_m_m_slotV_ETC___d1652 =
|
|
m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_7_rl[0] ;
|
|
assign m_m_slotVec_7_dummy2_1_read__593_AND_m_m_slotV_ETC___d2064 =
|
|
m_m_slotVec_7_dummy2_1$Q_OUT && m_m_slotVec_7_dummy2_2$Q_OUT &&
|
|
(MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[0] :
|
|
m_m_slotVec_7_rl[0]) ;
|
|
assign n__read_addr__h122165 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122256 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122347 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122438 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122529 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122620 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122711 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h122802 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135385 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135487 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135589 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135691 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135793 =
|
|
(m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135895 =
|
|
(m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h135997 =
|
|
(m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h136099 =
|
|
(m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[147:84] :
|
|
64'd0 ;
|
|
assign n__read_addr__h86244 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT ? m_m_reqVec_0_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h86466 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT ? m_m_reqVec_1_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h86688 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT ? m_m_reqVec_2_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h86910 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT ? m_m_reqVec_3_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h87132 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT ? m_m_reqVec_4_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h87354 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT ? m_m_reqVec_5_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h87576 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT ? m_m_reqVec_6_rl[147:84] : 64'd0 ;
|
|
assign n__read_addr__h87798 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT ? m_m_reqVec_7_rl[147:84] : 64'd0 ;
|
|
assign n__read_data__h122169 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122260 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122351 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122442 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122533 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122624 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122715 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h122806 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h135389 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h135491 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h135593 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h135695 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h135797 =
|
|
(m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h135899 =
|
|
(m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h136001 =
|
|
(m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h136103 =
|
|
(m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[70:7] :
|
|
64'd0 ;
|
|
assign n__read_data__h86248 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT ? m_m_reqVec_0_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h86470 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT ? m_m_reqVec_1_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h86692 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT ? m_m_reqVec_2_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h86914 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT ? m_m_reqVec_3_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h87136 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT ? m_m_reqVec_4_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h87358 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT ? m_m_reqVec_5_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h87580 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT ? m_m_reqVec_6_rl[70:7] : 64'd0 ;
|
|
assign n__read_data__h87802 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT ? m_m_reqVec_7_rl[70:7] : 64'd0 ;
|
|
assign n__read_id__h122164 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122255 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122346 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122437 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122528 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122619 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122710 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h122801 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135384 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135486 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135588 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135690 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135792 =
|
|
(m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135894 =
|
|
(m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h135996 =
|
|
(m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h136098 =
|
|
(m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[152:148] :
|
|
5'd0 ;
|
|
assign n__read_id__h86243 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT ? m_m_reqVec_0_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h86465 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT ? m_m_reqVec_1_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h86687 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT ? m_m_reqVec_2_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h86909 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT ? m_m_reqVec_3_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h87131 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT ? m_m_reqVec_4_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h87353 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT ? m_m_reqVec_5_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h87575 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT ? m_m_reqVec_6_rl[152:148] : 5'd0 ;
|
|
assign n__read_id__h87797 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT ? m_m_reqVec_7_rl[152:148] : 5'd0 ;
|
|
assign n__read_repTag__h126904 =
|
|
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_0_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h126991 =
|
|
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_1_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h127078 =
|
|
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_2_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h127165 =
|
|
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_3_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h127252 =
|
|
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_4_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h127339 =
|
|
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_5_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h127426 =
|
|
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_6_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h127513 =
|
|
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_7_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140423 =
|
|
(m_m_slotVec_0_dummy2_1$Q_OUT && m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_0_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140516 =
|
|
(m_m_slotVec_1_dummy2_1$Q_OUT && m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_1_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140609 =
|
|
(m_m_slotVec_2_dummy2_1$Q_OUT && m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_2_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140702 =
|
|
(m_m_slotVec_3_dummy2_1$Q_OUT && m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_3_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140795 =
|
|
(m_m_slotVec_4_dummy2_1$Q_OUT && m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_4_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140888 =
|
|
(m_m_slotVec_5_dummy2_1$Q_OUT && m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_5_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h140981 =
|
|
(m_m_slotVec_6_dummy2_1$Q_OUT && m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_6_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_repTag__h141074 =
|
|
(m_m_slotVec_7_dummy2_1$Q_OUT && m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[52:1] :
|
|
m_m_slotVec_7_rl[52:1]) :
|
|
52'd0 ;
|
|
assign n__read_way__h126902 =
|
|
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_0_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h126989 =
|
|
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_1_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h127076 =
|
|
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_2_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h127163 =
|
|
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_3_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h127250 =
|
|
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_4_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h127337 =
|
|
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_5_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h127424 =
|
|
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_6_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h127511 =
|
|
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_7_rl[57:55] :
|
|
3'd0 ;
|
|
assign n__read_way__h140421 =
|
|
(m_m_slotVec_0_dummy2_1$Q_OUT && m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_0_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h140514 =
|
|
(m_m_slotVec_1_dummy2_1$Q_OUT && m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_1_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h140607 =
|
|
(m_m_slotVec_2_dummy2_1$Q_OUT && m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_2_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h140700 =
|
|
(m_m_slotVec_3_dummy2_1$Q_OUT && m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_3_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h140793 =
|
|
(m_m_slotVec_4_dummy2_1$Q_OUT && m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_4_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_4_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h140886 =
|
|
(m_m_slotVec_5_dummy2_1$Q_OUT && m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_5_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_5_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h140979 =
|
|
(m_m_slotVec_6_dummy2_1$Q_OUT && m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_6_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_6_rl[57:55]) :
|
|
3'd0 ;
|
|
assign n__read_way__h141072 =
|
|
(m_m_slotVec_7_dummy2_1$Q_OUT && m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
(MUX_m_m_stateVec_7_dummy_1_0$wset_1__VAL_1 ?
|
|
sendRsToP_cRq_setWaitSt_setSlot_clearData_slot[57:55] :
|
|
m_m_slotVec_7_rl[57:55]) :
|
|
3'd0 ;
|
|
always@(cRqTransfer_getRq_n or
|
|
n__read_addr__h86244 or
|
|
n__read_addr__h86466 or
|
|
n__read_addr__h86688 or
|
|
n__read_addr__h86910 or
|
|
n__read_addr__h87132 or
|
|
n__read_addr__h87354 or
|
|
n__read_addr__h87576 or n__read_addr__h87798)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0: x__h87830 = n__read_addr__h86244;
|
|
3'd1: x__h87830 = n__read_addr__h86466;
|
|
3'd2: x__h87830 = n__read_addr__h86688;
|
|
3'd3: x__h87830 = n__read_addr__h86910;
|
|
3'd4: x__h87830 = n__read_addr__h87132;
|
|
3'd5: x__h87830 = n__read_addr__h87354;
|
|
3'd6: x__h87830 = n__read_addr__h87576;
|
|
3'd7: x__h87830 = n__read_addr__h87798;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
n__read_data__h86248 or
|
|
n__read_data__h86470 or
|
|
n__read_data__h86692 or
|
|
n__read_data__h86914 or
|
|
n__read_data__h87136 or
|
|
n__read_data__h87358 or
|
|
n__read_data__h87580 or n__read_data__h87802)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0: x__h91840 = n__read_data__h86248;
|
|
3'd1: x__h91840 = n__read_data__h86470;
|
|
3'd2: x__h91840 = n__read_data__h86692;
|
|
3'd3: x__h91840 = n__read_data__h86914;
|
|
3'd4: x__h91840 = n__read_data__h87136;
|
|
3'd5: x__h91840 = n__read_data__h87358;
|
|
3'd6: x__h91840 = n__read_data__h87580;
|
|
3'd7: x__h91840 = n__read_data__h87802;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
n__read_addr__h122165 or
|
|
n__read_addr__h122256 or
|
|
n__read_addr__h122347 or
|
|
n__read_addr__h122438 or
|
|
n__read_addr__h122529 or
|
|
n__read_addr__h122620 or
|
|
n__read_addr__h122711 or n__read_addr__h122802)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0: x__h122834 = n__read_addr__h122165;
|
|
3'd1: x__h122834 = n__read_addr__h122256;
|
|
3'd2: x__h122834 = n__read_addr__h122347;
|
|
3'd3: x__h122834 = n__read_addr__h122438;
|
|
3'd4: x__h122834 = n__read_addr__h122529;
|
|
3'd5: x__h122834 = n__read_addr__h122620;
|
|
3'd6: x__h122834 = n__read_addr__h122711;
|
|
3'd7: x__h122834 = n__read_addr__h122802;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
n__read_addr__h122165 or
|
|
n__read_addr__h122256 or
|
|
n__read_addr__h122347 or
|
|
n__read_addr__h122438 or
|
|
n__read_addr__h122529 or
|
|
n__read_addr__h122620 or
|
|
n__read_addr__h122711 or n__read_addr__h122802)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0: x__h131672 = n__read_addr__h122165;
|
|
3'd1: x__h131672 = n__read_addr__h122256;
|
|
3'd2: x__h131672 = n__read_addr__h122347;
|
|
3'd3: x__h131672 = n__read_addr__h122438;
|
|
3'd4: x__h131672 = n__read_addr__h122529;
|
|
3'd5: x__h131672 = n__read_addr__h122620;
|
|
3'd6: x__h131672 = n__read_addr__h122711;
|
|
3'd7: x__h131672 = n__read_addr__h122802;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
n__read_data__h122169 or
|
|
n__read_data__h122260 or
|
|
n__read_data__h122351 or
|
|
n__read_data__h122442 or
|
|
n__read_data__h122533 or
|
|
n__read_data__h122624 or
|
|
n__read_data__h122715 or n__read_data__h122806)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0: x__h126540 = n__read_data__h122169;
|
|
3'd1: x__h126540 = n__read_data__h122260;
|
|
3'd2: x__h126540 = n__read_data__h122351;
|
|
3'd3: x__h126540 = n__read_data__h122442;
|
|
3'd4: x__h126540 = n__read_data__h122533;
|
|
3'd5: x__h126540 = n__read_data__h122624;
|
|
3'd6: x__h126540 = n__read_data__h122715;
|
|
3'd7: x__h126540 = n__read_data__h122806;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
n__read_data__h122169 or
|
|
n__read_data__h122260 or
|
|
n__read_data__h122351 or
|
|
n__read_data__h122442 or
|
|
n__read_data__h122533 or
|
|
n__read_data__h122624 or
|
|
n__read_data__h122715 or n__read_data__h122806)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0: x__h132330 = n__read_data__h122169;
|
|
3'd1: x__h132330 = n__read_data__h122260;
|
|
3'd2: x__h132330 = n__read_data__h122351;
|
|
3'd3: x__h132330 = n__read_data__h122442;
|
|
3'd4: x__h132330 = n__read_data__h122533;
|
|
3'd5: x__h132330 = n__read_data__h122624;
|
|
3'd6: x__h132330 = n__read_data__h122715;
|
|
3'd7: x__h132330 = n__read_data__h122806;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
n__read_repTag__h126904 or
|
|
n__read_repTag__h126991 or
|
|
n__read_repTag__h127078 or
|
|
n__read_repTag__h127165 or
|
|
n__read_repTag__h127252 or
|
|
n__read_repTag__h127339 or
|
|
n__read_repTag__h127426 or n__read_repTag__h127513)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h127575 = n__read_repTag__h126904;
|
|
3'd1: x__h127575 = n__read_repTag__h126991;
|
|
3'd2: x__h127575 = n__read_repTag__h127078;
|
|
3'd3: x__h127575 = n__read_repTag__h127165;
|
|
3'd4: x__h127575 = n__read_repTag__h127252;
|
|
3'd5: x__h127575 = n__read_repTag__h127339;
|
|
3'd6: x__h127575 = n__read_repTag__h127426;
|
|
3'd7: x__h127575 = n__read_repTag__h127513;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
n__read_repTag__h126904 or
|
|
n__read_repTag__h126991 or
|
|
n__read_repTag__h127078 or
|
|
n__read_repTag__h127165 or
|
|
n__read_repTag__h127252 or
|
|
n__read_repTag__h127339 or
|
|
n__read_repTag__h127426 or n__read_repTag__h127513)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h132397 = n__read_repTag__h126904;
|
|
3'd1: x__h132397 = n__read_repTag__h126991;
|
|
3'd2: x__h132397 = n__read_repTag__h127078;
|
|
3'd3: x__h132397 = n__read_repTag__h127165;
|
|
3'd4: x__h132397 = n__read_repTag__h127252;
|
|
3'd5: x__h132397 = n__read_repTag__h127339;
|
|
3'd6: x__h132397 = n__read_repTag__h127426;
|
|
3'd7: x__h132397 = n__read_repTag__h127513;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
n__read_addr__h135385 or
|
|
n__read_addr__h135487 or
|
|
n__read_addr__h135589 or
|
|
n__read_addr__h135691 or
|
|
n__read_addr__h135793 or
|
|
n__read_addr__h135895 or
|
|
n__read_addr__h135997 or n__read_addr__h136099)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0: x__h136131 = n__read_addr__h135385;
|
|
3'd1: x__h136131 = n__read_addr__h135487;
|
|
3'd2: x__h136131 = n__read_addr__h135589;
|
|
3'd3: x__h136131 = n__read_addr__h135691;
|
|
3'd4: x__h136131 = n__read_addr__h135793;
|
|
3'd5: x__h136131 = n__read_addr__h135895;
|
|
3'd6: x__h136131 = n__read_addr__h135997;
|
|
3'd7: x__h136131 = n__read_addr__h136099;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
n__read_data__h135389 or
|
|
n__read_data__h135491 or
|
|
n__read_data__h135593 or
|
|
n__read_data__h135695 or
|
|
n__read_data__h135797 or
|
|
n__read_data__h135899 or
|
|
n__read_data__h136001 or n__read_data__h136103)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0: x__h139989 = n__read_data__h135389;
|
|
3'd1: x__h139989 = n__read_data__h135491;
|
|
3'd2: x__h139989 = n__read_data__h135593;
|
|
3'd3: x__h139989 = n__read_data__h135695;
|
|
3'd4: x__h139989 = n__read_data__h135797;
|
|
3'd5: x__h139989 = n__read_data__h135899;
|
|
3'd6: x__h139989 = n__read_data__h136001;
|
|
3'd7: x__h139989 = n__read_data__h136103;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
n__read_id__h86243 or
|
|
n__read_id__h86465 or
|
|
n__read_id__h86687 or
|
|
n__read_id__h86909 or
|
|
n__read_id__h87131 or
|
|
n__read_id__h87353 or n__read_id__h87575 or n__read_id__h87797)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0: x__h85367 = n__read_id__h86243;
|
|
3'd1: x__h85367 = n__read_id__h86465;
|
|
3'd2: x__h85367 = n__read_id__h86687;
|
|
3'd3: x__h85367 = n__read_id__h86909;
|
|
3'd4: x__h85367 = n__read_id__h87131;
|
|
3'd5: x__h85367 = n__read_id__h87353;
|
|
3'd6: x__h85367 = n__read_id__h87575;
|
|
3'd7: x__h85367 = n__read_id__h87797;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
n__read_id__h122164 or
|
|
n__read_id__h122255 or
|
|
n__read_id__h122346 or
|
|
n__read_id__h122437 or
|
|
n__read_id__h122528 or
|
|
n__read_id__h122619 or n__read_id__h122710 or n__read_id__h122801)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0: x__h122029 = n__read_id__h122164;
|
|
3'd1: x__h122029 = n__read_id__h122255;
|
|
3'd2: x__h122029 = n__read_id__h122346;
|
|
3'd3: x__h122029 = n__read_id__h122437;
|
|
3'd4: x__h122029 = n__read_id__h122528;
|
|
3'd5: x__h122029 = n__read_id__h122619;
|
|
3'd6: x__h122029 = n__read_id__h122710;
|
|
3'd7: x__h122029 = n__read_id__h122801;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
n__read_way__h126902 or
|
|
n__read_way__h126989 or
|
|
n__read_way__h127076 or
|
|
n__read_way__h127163 or
|
|
n__read_way__h127250 or
|
|
n__read_way__h127337 or
|
|
n__read_way__h127424 or n__read_way__h127511)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h126768 = n__read_way__h126902;
|
|
3'd1: x__h126768 = n__read_way__h126989;
|
|
3'd2: x__h126768 = n__read_way__h127076;
|
|
3'd3: x__h126768 = n__read_way__h127163;
|
|
3'd4: x__h126768 = n__read_way__h127250;
|
|
3'd5: x__h126768 = n__read_way__h127337;
|
|
3'd6: x__h126768 = n__read_way__h127424;
|
|
3'd7: x__h126768 = n__read_way__h127511;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
n__read_id__h122164 or
|
|
n__read_id__h122255 or
|
|
n__read_id__h122346 or
|
|
n__read_id__h122437 or
|
|
n__read_id__h122528 or
|
|
n__read_id__h122619 or n__read_id__h122710 or n__read_id__h122801)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0: x__h131633 = n__read_id__h122164;
|
|
3'd1: x__h131633 = n__read_id__h122255;
|
|
3'd2: x__h131633 = n__read_id__h122346;
|
|
3'd3: x__h131633 = n__read_id__h122437;
|
|
3'd4: x__h131633 = n__read_id__h122528;
|
|
3'd5: x__h131633 = n__read_id__h122619;
|
|
3'd6: x__h131633 = n__read_id__h122710;
|
|
3'd7: x__h131633 = n__read_id__h122801;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
n__read_way__h126902 or
|
|
n__read_way__h126989 or
|
|
n__read_way__h127076 or
|
|
n__read_way__h127163 or
|
|
n__read_way__h127250 or
|
|
n__read_way__h127337 or
|
|
n__read_way__h127424 or n__read_way__h127511)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h132358 = n__read_way__h126902;
|
|
3'd1: x__h132358 = n__read_way__h126989;
|
|
3'd2: x__h132358 = n__read_way__h127076;
|
|
3'd3: x__h132358 = n__read_way__h127163;
|
|
3'd4: x__h132358 = n__read_way__h127250;
|
|
3'd5: x__h132358 = n__read_way__h127337;
|
|
3'd6: x__h132358 = n__read_way__h127424;
|
|
3'd7: x__h132358 = n__read_way__h127511;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
n__read_id__h135384 or
|
|
n__read_id__h135486 or
|
|
n__read_id__h135588 or
|
|
n__read_id__h135690 or
|
|
n__read_id__h135792 or
|
|
n__read_id__h135894 or n__read_id__h135996 or n__read_id__h136098)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0: x__h135238 = n__read_id__h135384;
|
|
3'd1: x__h135238 = n__read_id__h135486;
|
|
3'd2: x__h135238 = n__read_id__h135588;
|
|
3'd3: x__h135238 = n__read_id__h135690;
|
|
3'd4: x__h135238 = n__read_id__h135792;
|
|
3'd5: x__h135238 = n__read_id__h135894;
|
|
3'd6: x__h135238 = n__read_id__h135996;
|
|
3'd7: x__h135238 = n__read_id__h136098;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1406 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1407 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1408 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1409 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1410 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1411 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1412 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1413)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1406;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1407;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1408;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1409;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1410;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1411;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1412;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1415 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1413;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[78];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[78];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[78];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[78];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[78];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[78];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[78];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d665 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[78];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1416 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1417 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1418 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1419 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1420 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1421 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1422 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1423)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1416;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1417;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1418;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1419;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1420;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1421;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1422;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1425 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1423;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1426 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1427 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1428 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1429 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1430 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1431 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1432 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1433)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1426;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1427;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1428;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1429;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1430;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1431;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1432;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1435 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1433;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[77];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[77];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[77];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[77];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[77];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[77];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[77];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d715 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[77];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[76];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[76];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[76];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[76];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[76];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[76];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[76];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d765 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[76];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1437 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1438 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1439 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1440 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1441 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1442 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1443 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1444)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1437;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1438;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1439;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1440;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1441;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1442;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1443;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1446 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1444;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1447 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1448 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1449 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1450 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1451 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1452 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1453 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1454)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1447;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1448;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1449;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1450;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1451;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1452;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1453;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1456 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1454;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[75];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[75];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[75];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[75];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[75];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[75];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[75];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d816 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[75];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[74];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[74];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[74];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[74];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[74];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[74];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[74];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d866 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[74];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1519 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1520 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1521 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1522 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1523 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1524 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1525 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1526)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1519;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1520;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1521;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1522;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1523;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1524;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1525;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1528 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1526;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[1];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[1];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[1];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[1];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[1];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[1];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[1];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1218 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[1];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1499 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1500 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1501 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1502 or
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1503 or
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1504 or
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1505 or
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1506)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1499;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1500;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1501;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1502;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1503;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1504;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1505;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1508 =
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1506;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1458 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1459 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1460 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1461 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1462 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1463 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1464 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1465)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1458;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1459;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1460;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1461;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1462;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1463;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1464;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1467 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1465;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT ? m_m_reqVec_0_rl[6:3] : 4'd0;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT ? m_m_reqVec_1_rl[6:3] : 4'd0;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT ? m_m_reqVec_2_rl[6:3] : 4'd0;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT ? m_m_reqVec_3_rl[6:3] : 4'd0;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT ? m_m_reqVec_4_rl[6:3] : 4'd0;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT ? m_m_reqVec_5_rl[6:3] : 4'd0;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT ? m_m_reqVec_6_rl[6:3] : 4'd0;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d1118 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT ? m_m_reqVec_7_rl[6:3] : 4'd0;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1468 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1469 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1470 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1471 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1472 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1473 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1474 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1475)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1468;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1469;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1470;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1471;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1472;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1473;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1474;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1477 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1475;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[73];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[73];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[73];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[73];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[73];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[73];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[73];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d917 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[73];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[72];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[72];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[72];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[72];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[72];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[72];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[72];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d967 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[72];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1386 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1387 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1388 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1389 or
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1390 or
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1391 or
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1392 or
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1393)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1386;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1387;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1388;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1389;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1390;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1391;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1392;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1395 =
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1393;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT ? m_m_reqVec_0_rl[83:82] : 2'd0;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT ? m_m_reqVec_1_rl[83:82] : 2'd0;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT ? m_m_reqVec_2_rl[83:82] : 2'd0;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT ? m_m_reqVec_3_rl[83:82] : 2'd0;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT ? m_m_reqVec_4_rl[83:82] : 2'd0;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT ? m_m_reqVec_5_rl[83:82] : 2'd0;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT ? m_m_reqVec_6_rl[83:82] : 2'd0;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d565 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT ? m_m_reqVec_7_rl[83:82] : 2'd0;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1406 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1407 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1408 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1409 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1410 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1411 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1412 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1413)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1406;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1407;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1408;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1409;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1410;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1411;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1412;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1720 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1413;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1426 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1427 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1428 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1429 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1430 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1431 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1432 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1433)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1426;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1427;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1428;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1429;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1430;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1431;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1432;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1722 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1433;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1416 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1417 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1418 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1419 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1420 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1421 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1422 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1423)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1416;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1417;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1418;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1419;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1420;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1421;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1422;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1721 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1423;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1437 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1438 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1439 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1440 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1441 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1442 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1443 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1444)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1437;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1438;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1439;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1440;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1441;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1442;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1443;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1724 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1444;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1447 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1448 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1449 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1450 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1451 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1452 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1453 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1454)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1447;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1448;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1449;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1450;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1451;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1452;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1453;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1725 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1454;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1519 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1520 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1521 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1522 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1523 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1524 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1525 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1526)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1519;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1520;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1521;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1522;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1523;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1524;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1525;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1734 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1526;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1499 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1500 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1501 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1502 or
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1503 or
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1504 or
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1505 or
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1506)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1499;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1500;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1501;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1502;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1503;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1504;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1505;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1732 =
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1506;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1458 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1459 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1460 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1461 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1462 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1463 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1464 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1465)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1458;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1459;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1460;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1461;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1462;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1463;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1464;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1727 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1465;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1468 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1469 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1470 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1471 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1472 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1473 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1474 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1475)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1468;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1469;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1470;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1471;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1472;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1473;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1474;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1728 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1475;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1386 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1387 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1388 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1389 or
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1390 or
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1391 or
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1392 or
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1393)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1386;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1387;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1388;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1389;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1390;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1391;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1392;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1718 =
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1393;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[78];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[78];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[78];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[78];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[78];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[78];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[78];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1827 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[78];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[77];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[77];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[77];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[77];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[77];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[77];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[77];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1837 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[77];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[76];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[76];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[76];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[76];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[76];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[76];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[76];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1847 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[76];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[75];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[75];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[75];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[75];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[75];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[75];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[75];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1858 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[75];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[74];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[74];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[74];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[74];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[74];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[74];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[74];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1868 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[74];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[1];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[1];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[1];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[1];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[1];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[1];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[1];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1940 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[1];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[6:3] :
|
|
4'd0;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[6:3] :
|
|
4'd0;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[6:3] :
|
|
4'd0;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[6:3] :
|
|
4'd0;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[6:3] :
|
|
4'd0;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[6:3] :
|
|
4'd0;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[6:3] :
|
|
4'd0;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1920 =
|
|
(m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[6:3] :
|
|
4'd0;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[73];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[73];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[73];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[73];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[73];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[73];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[73];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1879 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[73];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[72];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[72];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[72];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[72];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[72];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[72];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[72];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1889 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[72];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[83:82] :
|
|
2'd0;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[83:82] :
|
|
2'd0;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[83:82] :
|
|
2'd0;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[83:82] :
|
|
2'd0;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[83:82] :
|
|
2'd0;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[83:82] :
|
|
2'd0;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[83:82] :
|
|
2'd0;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1807 =
|
|
(m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[83:82] :
|
|
2'd0;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getData_n or
|
|
m_m_dataValidVec_0_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_0_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_0_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_0_rl or
|
|
m_m_dataValidVec_1_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_1_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_1_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_1_rl or
|
|
m_m_dataValidVec_2_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_2_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_2_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_2_rl or
|
|
m_m_dataValidVec_3_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_3_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_3_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_3_rl or
|
|
m_m_dataValidVec_4_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_4_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_4_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_4_rl or
|
|
m_m_dataValidVec_5_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_5_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_5_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_5_rl or
|
|
m_m_dataValidVec_6_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_6_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_6_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_6_rl or
|
|
m_m_dataValidVec_7_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_7_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_7_dummy2_2$Q_OUT or m_m_dataValidVec_7_rl)
|
|
begin
|
|
case (sendRsToP_cRq_getData_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_0_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_0_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_0_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_0_rl;
|
|
3'd1:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_1_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_1_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_1_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_1_rl;
|
|
3'd2:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_2_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_2_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_2_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_2_rl;
|
|
3'd3:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_3_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_3_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_3_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_3_rl;
|
|
3'd4:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_4_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_4_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_4_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_4_rl;
|
|
3'd5:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_5_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_5_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_5_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_5_rl;
|
|
3'd6:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_6_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_6_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_6_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_6_rl;
|
|
3'd7:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__656__ETC___d1705 =
|
|
m_m_dataValidVec_7_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_7_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_7_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_7_rl;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSucc_n or
|
|
m_m_succValidVec_0_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_0_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_0_rl or
|
|
m_m_succValidVec_1_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_1_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_1_rl or
|
|
m_m_succValidVec_2_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_2_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_2_rl or
|
|
m_m_succValidVec_3_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_3_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_3_rl or
|
|
m_m_succValidVec_4_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_4_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_4_rl or
|
|
m_m_succValidVec_5_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_5_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_5_rl or
|
|
m_m_succValidVec_6_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_6_dummy2_2$Q_OUT or
|
|
m_m_succValidVec_6_rl or
|
|
m_m_succValidVec_7_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_7_dummy2_2$Q_OUT or m_m_succValidVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSucc_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_0_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_0_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_0_rl;
|
|
3'd1:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_1_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_1_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_1_rl;
|
|
3'd2:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_2_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_2_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_2_rl;
|
|
3'd3:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_3_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_3_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_3_rl;
|
|
3'd4:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_4_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_4_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_4_rl;
|
|
3'd5:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_5_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_5_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_5_rl;
|
|
3'd6:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_6_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_6_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_6_rl;
|
|
3'd7:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_1_read__088__ETC___d2121 =
|
|
m_m_succValidVec_7_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_7_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_7_rl;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1529 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1530 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1531 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1532 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1533 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1534 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1535 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1536)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1529;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1530;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1531;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1532;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1533;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1534;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1535;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1538 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1536;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1268 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1529 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1530 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1531 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1532 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1533 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1534 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1535 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1536)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1529;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1530;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1531;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1532;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1533;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1534;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1535;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1735 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1536;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[0];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[0];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[0];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[0];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[0];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[0];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[0];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1950 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[0];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1509 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1510 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1511 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1512 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1513 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1514 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1515 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1516)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1509;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1510;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1511;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1512;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1513;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1514;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1515;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1518 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1516;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[2];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[2];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[2];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[2];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[2];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[2];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[2];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1168 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[2];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1509 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1510 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1511 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1512 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1513 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1514 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1515 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1516)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1509;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1510;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1511;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1512;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1513;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1514;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1515;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1733 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1516;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[2];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[2];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[2];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[2];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[2];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[2];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[2];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1930 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[2];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_dummy2_0_read__543_AND_m_m_slotV_ETC___d1638 or
|
|
m_m_slotVec_1_dummy2_0_read__550_AND_m_m_slotV_ETC___d1640 or
|
|
m_m_slotVec_2_dummy2_0_read__557_AND_m_m_slotV_ETC___d1642 or
|
|
m_m_slotVec_3_dummy2_0_read__564_AND_m_m_slotV_ETC___d1644 or
|
|
m_m_slotVec_4_dummy2_0_read__571_AND_m_m_slotV_ETC___d1646 or
|
|
m_m_slotVec_5_dummy2_0_read__578_AND_m_m_slotV_ETC___d1648 or
|
|
m_m_slotVec_6_dummy2_0_read__585_AND_m_m_slotV_ETC___d1650 or
|
|
m_m_slotVec_7_dummy2_0_read__592_AND_m_m_slotV_ETC___d1652)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_0_dummy2_0_read__543_AND_m_m_slotV_ETC___d1638;
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_1_dummy2_0_read__550_AND_m_m_slotV_ETC___d1640;
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_2_dummy2_0_read__557_AND_m_m_slotV_ETC___d1642;
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_3_dummy2_0_read__564_AND_m_m_slotV_ETC___d1644;
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_4_dummy2_0_read__571_AND_m_m_slotV_ETC___d1646;
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_5_dummy2_0_read__578_AND_m_m_slotV_ETC___d1648;
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_6_dummy2_0_read__585_AND_m_m_slotV_ETC___d1650;
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1743 =
|
|
m_m_slotVec_7_dummy2_0_read__592_AND_m_m_slotV_ETC___d1652;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_dummy2_0_read__543_AND_m_m_slotV_ETC___d1638 or
|
|
m_m_slotVec_1_dummy2_0_read__550_AND_m_m_slotV_ETC___d1640 or
|
|
m_m_slotVec_2_dummy2_0_read__557_AND_m_m_slotV_ETC___d1642 or
|
|
m_m_slotVec_3_dummy2_0_read__564_AND_m_m_slotV_ETC___d1644 or
|
|
m_m_slotVec_4_dummy2_0_read__571_AND_m_m_slotV_ETC___d1646 or
|
|
m_m_slotVec_5_dummy2_0_read__578_AND_m_m_slotV_ETC___d1648 or
|
|
m_m_slotVec_6_dummy2_0_read__585_AND_m_m_slotV_ETC___d1650 or
|
|
m_m_slotVec_7_dummy2_0_read__592_AND_m_m_slotV_ETC___d1652)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_0_dummy2_0_read__543_AND_m_m_slotV_ETC___d1638;
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_1_dummy2_0_read__550_AND_m_m_slotV_ETC___d1640;
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_2_dummy2_0_read__557_AND_m_m_slotV_ETC___d1642;
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_3_dummy2_0_read__564_AND_m_m_slotV_ETC___d1644;
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_4_dummy2_0_read__571_AND_m_m_slotV_ETC___d1646;
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_5_dummy2_0_read__578_AND_m_m_slotV_ETC___d1648;
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_6_dummy2_0_read__585_AND_m_m_slotV_ETC___d1650;
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__543_AND_m_ETC___d1654 =
|
|
m_m_slotVec_7_dummy2_0_read__592_AND_m_m_slotV_ETC___d1652;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1479 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1480 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1481 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1482 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1483 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1484 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1485 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1486)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1479;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1480;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1481;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1482;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1483;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1484;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1485;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1488 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1486;
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT && m_m_reqVec_0_rl[71];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT && m_m_reqVec_1_rl[71];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT && m_m_reqVec_2_rl[71];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT && m_m_reqVec_3_rl[71];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT && m_m_reqVec_4_rl[71];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT && m_m_reqVec_5_rl[71];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT && m_m_reqVec_6_rl[71];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_2_read__08_AND_IF__ETC___d1018 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT && m_m_reqVec_7_rl[71];
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1479 or
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1480 or
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1481 or
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1482 or
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1483 or
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1484 or
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1485 or
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1486)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_0_dummy2_0_read__334_AND_m_m_reqVec_ETC___d1479;
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_1_dummy2_0_read__339_AND_m_m_reqVec_ETC___d1480;
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_2_dummy2_0_read__344_AND_m_m_reqVec_ETC___d1481;
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_3_dummy2_0_read__349_AND_m_m_reqVec_ETC___d1482;
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_4_dummy2_0_read__354_AND_m_m_reqVec_ETC___d1483;
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_5_dummy2_0_read__359_AND_m_m_reqVec_ETC___d1484;
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_6_dummy2_0_read__364_AND_m_m_reqVec_ETC___d1485;
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_0_read__334_AND_m__ETC___d1730 =
|
|
m_m_reqVec_7_dummy2_0_read__369_AND_m_m_reqVec_ETC___d1486;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1396 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1397 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1398 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1399 or
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1400 or
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1401 or
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1402 or
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1403)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1396;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1397;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1398;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1399;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1400;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1401;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1402;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1405 =
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1403;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_0_rl[71];
|
|
3'd1:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_1_rl[71];
|
|
3'd2:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_2_rl[71];
|
|
3'd3:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_3_rl[71];
|
|
3'd4:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_4_rl[71];
|
|
3'd5:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_5_rl[71];
|
|
3'd6:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_6_rl[71];
|
|
3'd7:
|
|
SEL_ARR_m_m_reqVec_0_dummy2_1_read__335_AND_m__ETC___d1900 =
|
|
m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT &&
|
|
m_m_reqVec_7_rl[71];
|
|
endcase
|
|
end
|
|
always@(cRqTransfer_getRq_n or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (cRqTransfer_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_0_dummy2_2$Q_OUT ? m_m_reqVec_0_rl[81:79] : 3'd0;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_1_dummy2_2$Q_OUT ? m_m_reqVec_1_rl[81:79] : 3'd0;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_2_dummy2_2$Q_OUT ? m_m_reqVec_2_rl[81:79] : 3'd0;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_3_dummy2_2$Q_OUT ? m_m_reqVec_3_rl[81:79] : 3'd0;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_4_dummy2_2$Q_OUT ? m_m_reqVec_4_rl[81:79] : 3'd0;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_5_dummy2_2$Q_OUT ? m_m_reqVec_5_rl[81:79] : 3'd0;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_6_dummy2_2$Q_OUT ? m_m_reqVec_6_rl[81:79] : 3'd0;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_2_read__08_THEN_ETC___d615 =
|
|
m_m_reqVec_7_dummy2_2$Q_OUT ? m_m_reqVec_7_rl[81:79] : 3'd0;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1396 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1397 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1398 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1399 or
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1400 or
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1401 or
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1402 or
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1403)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__334_AND_m_m_req_ETC___d1396;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__339_AND_m_m_req_ETC___d1397;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__344_AND_m_m_req_ETC___d1398;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__349_AND_m_m_req_ETC___d1399;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_4_dummy2_0_read__354_AND_m_m_req_ETC___d1400;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_5_dummy2_0_read__359_AND_m_m_req_ETC___d1401;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_6_dummy2_0_read__364_AND_m_m_req_ETC___d1402;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__334_AND_ETC___d1719 =
|
|
IF_m_m_reqVec_7_dummy2_0_read__369_AND_m_m_req_ETC___d1403;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or
|
|
m_m_reqVec_3_rl or
|
|
m_m_reqVec_4_dummy2_1$Q_OUT or
|
|
m_m_reqVec_4_dummy2_2$Q_OUT or
|
|
m_m_reqVec_4_rl or
|
|
m_m_reqVec_5_dummy2_1$Q_OUT or
|
|
m_m_reqVec_5_dummy2_2$Q_OUT or
|
|
m_m_reqVec_5_rl or
|
|
m_m_reqVec_6_dummy2_1$Q_OUT or
|
|
m_m_reqVec_6_dummy2_2$Q_OUT or
|
|
m_m_reqVec_6_rl or
|
|
m_m_reqVec_7_dummy2_1$Q_OUT or
|
|
m_m_reqVec_7_dummy2_2$Q_OUT or m_m_reqVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[81:79] :
|
|
3'd0;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[81:79] :
|
|
3'd0;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[81:79] :
|
|
3'd0;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[81:79] :
|
|
3'd0;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_4_dummy2_1$Q_OUT && m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl[81:79] :
|
|
3'd0;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_5_dummy2_1$Q_OUT && m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl[81:79] :
|
|
3'd0;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_6_dummy2_1$Q_OUT && m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl[81:79] :
|
|
3'd0;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__335_AND_ETC___d1817 =
|
|
(m_m_reqVec_7_dummy2_1$Q_OUT && m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl[81:79] :
|
|
3'd0;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
IF_m_m_slotVec_0_dummy2_0_read__543_AND_m_m_sl_ETC___d1602 or
|
|
IF_m_m_slotVec_1_dummy2_0_read__550_AND_m_m_sl_ETC___d1604 or
|
|
IF_m_m_slotVec_2_dummy2_0_read__557_AND_m_m_sl_ETC___d1606 or
|
|
IF_m_m_slotVec_3_dummy2_0_read__564_AND_m_m_sl_ETC___d1608 or
|
|
IF_m_m_slotVec_4_dummy2_0_read__571_AND_m_m_sl_ETC___d1610 or
|
|
IF_m_m_slotVec_5_dummy2_0_read__578_AND_m_m_sl_ETC___d1612 or
|
|
IF_m_m_slotVec_6_dummy2_0_read__585_AND_m_m_sl_ETC___d1614 or
|
|
IF_m_m_slotVec_7_dummy2_0_read__592_AND_m_m_sl_ETC___d1616)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_0_dummy2_0_read__543_AND_m_m_sl_ETC___d1602;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_1_dummy2_0_read__550_AND_m_m_sl_ETC___d1604;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_2_dummy2_0_read__557_AND_m_m_sl_ETC___d1606;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_3_dummy2_0_read__564_AND_m_m_sl_ETC___d1608;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_4_dummy2_0_read__571_AND_m_m_sl_ETC___d1610;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_5_dummy2_0_read__578_AND_m_m_sl_ETC___d1612;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_6_dummy2_0_read__585_AND_m_m_sl_ETC___d1614;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1618 =
|
|
IF_m_m_slotVec_7_dummy2_0_read__592_AND_m_m_sl_ETC___d1616;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
IF_m_m_slotVec_0_dummy2_0_read__543_AND_m_m_sl_ETC___d1602 or
|
|
IF_m_m_slotVec_1_dummy2_0_read__550_AND_m_m_sl_ETC___d1604 or
|
|
IF_m_m_slotVec_2_dummy2_0_read__557_AND_m_m_sl_ETC___d1606 or
|
|
IF_m_m_slotVec_3_dummy2_0_read__564_AND_m_m_sl_ETC___d1608 or
|
|
IF_m_m_slotVec_4_dummy2_0_read__571_AND_m_m_sl_ETC___d1610 or
|
|
IF_m_m_slotVec_5_dummy2_0_read__578_AND_m_m_sl_ETC___d1612 or
|
|
IF_m_m_slotVec_6_dummy2_0_read__585_AND_m_m_sl_ETC___d1614 or
|
|
IF_m_m_slotVec_7_dummy2_0_read__592_AND_m_m_sl_ETC___d1616)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_0_dummy2_0_read__543_AND_m_m_sl_ETC___d1602;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_1_dummy2_0_read__550_AND_m_m_sl_ETC___d1604;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_2_dummy2_0_read__557_AND_m_m_sl_ETC___d1606;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_3_dummy2_0_read__564_AND_m_m_sl_ETC___d1608;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_4_dummy2_0_read__571_AND_m_m_sl_ETC___d1610;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_5_dummy2_0_read__578_AND_m_m_sl_ETC___d1612;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_6_dummy2_0_read__585_AND_m_m_sl_ETC___d1614;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_0_read__543_AN_ETC___d1741 =
|
|
IF_m_m_slotVec_7_dummy2_0_read__592_AND_m_m_sl_ETC___d1616;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
n__read_repTag__h140423 or
|
|
n__read_repTag__h140516 or
|
|
n__read_repTag__h140609 or
|
|
n__read_repTag__h140702 or
|
|
n__read_repTag__h140795 or
|
|
n__read_repTag__h140888 or
|
|
n__read_repTag__h140981 or n__read_repTag__h141074)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0: x__h141144 = n__read_repTag__h140423;
|
|
3'd1: x__h141144 = n__read_repTag__h140516;
|
|
3'd2: x__h141144 = n__read_repTag__h140609;
|
|
3'd3: x__h141144 = n__read_repTag__h140702;
|
|
3'd4: x__h141144 = n__read_repTag__h140795;
|
|
3'd5: x__h141144 = n__read_repTag__h140888;
|
|
3'd6: x__h141144 = n__read_repTag__h140981;
|
|
3'd7: x__h141144 = n__read_repTag__h141074;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
n__read_way__h140421 or
|
|
n__read_way__h140514 or
|
|
n__read_way__h140607 or
|
|
n__read_way__h140700 or
|
|
n__read_way__h140793 or
|
|
n__read_way__h140886 or
|
|
n__read_way__h140979 or n__read_way__h141072)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0: x__h140281 = n__read_way__h140421;
|
|
3'd1: x__h140281 = n__read_way__h140514;
|
|
3'd2: x__h140281 = n__read_way__h140607;
|
|
3'd3: x__h140281 = n__read_way__h140700;
|
|
3'd4: x__h140281 = n__read_way__h140793;
|
|
3'd5: x__h140281 = n__read_way__h140886;
|
|
3'd6: x__h140281 = n__read_way__h140979;
|
|
3'd7: x__h140281 = n__read_way__h141072;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_slotVec_0_dummy2_1_read__544_AND_m_m_slotV_ETC___d2043 or
|
|
m_m_slotVec_1_dummy2_1_read__551_AND_m_m_slotV_ETC___d2046 or
|
|
m_m_slotVec_2_dummy2_1_read__558_AND_m_m_slotV_ETC___d2049 or
|
|
m_m_slotVec_3_dummy2_1_read__565_AND_m_m_slotV_ETC___d2052 or
|
|
m_m_slotVec_4_dummy2_1_read__572_AND_m_m_slotV_ETC___d2055 or
|
|
m_m_slotVec_5_dummy2_1_read__579_AND_m_m_slotV_ETC___d2058 or
|
|
m_m_slotVec_6_dummy2_1_read__586_AND_m_m_slotV_ETC___d2061 or
|
|
m_m_slotVec_7_dummy2_1_read__593_AND_m_m_slotV_ETC___d2064)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_0_dummy2_1_read__544_AND_m_m_slotV_ETC___d2043;
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_1_dummy2_1_read__551_AND_m_m_slotV_ETC___d2046;
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_2_dummy2_1_read__558_AND_m_m_slotV_ETC___d2049;
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_3_dummy2_1_read__565_AND_m_m_slotV_ETC___d2052;
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_4_dummy2_1_read__572_AND_m_m_slotV_ETC___d2055;
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_5_dummy2_1_read__579_AND_m_m_slotV_ETC___d2058;
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_6_dummy2_1_read__586_AND_m_m_slotV_ETC___d2061;
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_1_read__544_AND_m_ETC___d2066 =
|
|
m_m_slotVec_7_dummy2_1_read__593_AND_m_m_slotV_ETC___d2064;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
IF_m_m_slotVec_0_dummy2_1_read__544_AND_m_m_sl_ETC___d1991 or
|
|
IF_m_m_slotVec_1_dummy2_1_read__551_AND_m_m_sl_ETC___d1994 or
|
|
IF_m_m_slotVec_2_dummy2_1_read__558_AND_m_m_sl_ETC___d1997 or
|
|
IF_m_m_slotVec_3_dummy2_1_read__565_AND_m_m_sl_ETC___d2000 or
|
|
IF_m_m_slotVec_4_dummy2_1_read__572_AND_m_m_sl_ETC___d2003 or
|
|
IF_m_m_slotVec_5_dummy2_1_read__579_AND_m_m_sl_ETC___d2006 or
|
|
IF_m_m_slotVec_6_dummy2_1_read__586_AND_m_m_sl_ETC___d2009 or
|
|
IF_m_m_slotVec_7_dummy2_1_read__593_AND_m_m_sl_ETC___d2012)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_0_dummy2_1_read__544_AND_m_m_sl_ETC___d1991;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_1_dummy2_1_read__551_AND_m_m_sl_ETC___d1994;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_2_dummy2_1_read__558_AND_m_m_sl_ETC___d1997;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_3_dummy2_1_read__565_AND_m_m_sl_ETC___d2000;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_4_dummy2_1_read__572_AND_m_m_sl_ETC___d2003;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_5_dummy2_1_read__579_AND_m_m_sl_ETC___d2006;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_6_dummy2_1_read__586_AND_m_m_sl_ETC___d2009;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_slotVec_0_dummy2_1_read__544_AN_ETC___d2014 =
|
|
IF_m_m_slotVec_7_dummy2_1_read__593_AND_m_m_sl_ETC___d2012;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_dataValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY 58'h155555555555554;
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_dataValidVec_0_rl$EN)
|
|
m_m_dataValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_0_rl$D_IN;
|
|
if (m_m_dataValidVec_1_rl$EN)
|
|
m_m_dataValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_1_rl$D_IN;
|
|
if (m_m_dataValidVec_2_rl$EN)
|
|
m_m_dataValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_2_rl$D_IN;
|
|
if (m_m_dataValidVec_3_rl$EN)
|
|
m_m_dataValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_3_rl$D_IN;
|
|
if (m_m_dataValidVec_4_rl$EN)
|
|
m_m_dataValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_4_rl$D_IN;
|
|
if (m_m_dataValidVec_5_rl$EN)
|
|
m_m_dataValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_5_rl$D_IN;
|
|
if (m_m_dataValidVec_6_rl$EN)
|
|
m_m_dataValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_6_rl$D_IN;
|
|
if (m_m_dataValidVec_7_rl$EN)
|
|
m_m_dataValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_7_rl$D_IN;
|
|
if (m_m_initIdx$EN)
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
|
|
if (m_m_inited$EN)
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
|
|
if (m_m_reqVec_0_rl$EN)
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
|
|
if (m_m_reqVec_1_rl$EN)
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
|
|
if (m_m_reqVec_2_rl$EN)
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
|
|
if (m_m_reqVec_3_rl$EN)
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
|
|
if (m_m_reqVec_4_rl$EN)
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_4_rl$D_IN;
|
|
if (m_m_reqVec_5_rl$EN)
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_5_rl$D_IN;
|
|
if (m_m_reqVec_6_rl$EN)
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_6_rl$D_IN;
|
|
if (m_m_reqVec_7_rl$EN)
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_7_rl$D_IN;
|
|
if (m_m_slotVec_0_rl$EN)
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_0_rl$D_IN;
|
|
if (m_m_slotVec_1_rl$EN)
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_1_rl$D_IN;
|
|
if (m_m_slotVec_2_rl$EN)
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_2_rl$D_IN;
|
|
if (m_m_slotVec_3_rl$EN)
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_3_rl$D_IN;
|
|
if (m_m_slotVec_4_rl$EN)
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_4_rl$D_IN;
|
|
if (m_m_slotVec_5_rl$EN)
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_5_rl$D_IN;
|
|
if (m_m_slotVec_6_rl$EN)
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_6_rl$D_IN;
|
|
if (m_m_slotVec_7_rl$EN)
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_7_rl$D_IN;
|
|
if (m_m_stateVec_0_rl$EN)
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
|
|
if (m_m_stateVec_1_rl$EN)
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
|
|
if (m_m_stateVec_2_rl$EN)
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
|
|
if (m_m_stateVec_3_rl$EN)
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
|
|
if (m_m_stateVec_4_rl$EN)
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_4_rl$D_IN;
|
|
if (m_m_stateVec_5_rl$EN)
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_5_rl$D_IN;
|
|
if (m_m_stateVec_6_rl$EN)
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_6_rl$D_IN;
|
|
if (m_m_stateVec_7_rl$EN)
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_7_rl$D_IN;
|
|
if (m_m_succValidVec_0_rl$EN)
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_0_rl$D_IN;
|
|
if (m_m_succValidVec_1_rl$EN)
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_1_rl$D_IN;
|
|
if (m_m_succValidVec_2_rl$EN)
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_2_rl$D_IN;
|
|
if (m_m_succValidVec_3_rl$EN)
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_3_rl$D_IN;
|
|
if (m_m_succValidVec_4_rl$EN)
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_4_rl$D_IN;
|
|
if (m_m_succValidVec_5_rl$EN)
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_5_rl$D_IN;
|
|
if (m_m_succValidVec_6_rl$EN)
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_6_rl$D_IN;
|
|
if (m_m_succValidVec_7_rl$EN)
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_7_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_dataValidVec_0_rl = 1'h0;
|
|
m_m_dataValidVec_1_rl = 1'h0;
|
|
m_m_dataValidVec_2_rl = 1'h0;
|
|
m_m_dataValidVec_3_rl = 1'h0;
|
|
m_m_dataValidVec_4_rl = 1'h0;
|
|
m_m_dataValidVec_5_rl = 1'h0;
|
|
m_m_dataValidVec_6_rl = 1'h0;
|
|
m_m_dataValidVec_7_rl = 1'h0;
|
|
m_m_initIdx = 3'h2;
|
|
m_m_inited = 1'h0;
|
|
m_m_reqVec_0_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_4_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_5_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_6_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_7_rl = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_slotVec_0_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_1_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_2_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_3_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_4_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_5_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_6_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_slotVec_7_rl = 58'h2AAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl = 3'h2;
|
|
m_m_stateVec_1_rl = 3'h2;
|
|
m_m_stateVec_2_rl = 3'h2;
|
|
m_m_stateVec_3_rl = 3'h2;
|
|
m_m_stateVec_4_rl = 3'h2;
|
|
m_m_stateVec_5_rl = 3'h2;
|
|
m_m_stateVec_6_rl = 3'h2;
|
|
m_m_stateVec_7_rl = 3'h2;
|
|
m_m_succValidVec_0_rl = 1'h0;
|
|
m_m_succValidVec_1_rl = 1'h0;
|
|
m_m_succValidVec_2_rl = 1'h0;
|
|
m_m_succValidVec_3_rl = 1'h0;
|
|
m_m_succValidVec_4_rl = 1'h0;
|
|
m_m_succValidVec_5_rl = 1'h0;
|
|
m_m_succValidVec_6_rl = 1'h0;
|
|
m_m_succValidVec_7_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_state == 3'd0)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkDCRqMshrWrapper
|
|
|