1032 lines
31 KiB
Verilog
1032 lines
31 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// slave_awready O 1 reg
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// slave_wready O 1 reg
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// slave_bvalid O 1 reg
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// slave_bid O 4 reg
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// slave_bresp O 2 reg
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// slave_arready O 1 reg
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// slave_rvalid O 1 reg
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// slave_rid O 4 reg
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// slave_rdata O 64 reg
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// slave_rresp O 2 reg
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// slave_rlast O 1 reg
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// master_awvalid O 1 reg
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// master_awid O 4 reg
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// master_awaddr O 64 reg
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// master_awlen O 8 reg
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// master_awsize O 3 reg
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// master_awburst O 2 reg
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// master_awlock O 1 reg
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// master_awcache O 4 reg
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// master_awprot O 3 reg
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// master_awqos O 4 reg
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// master_awregion O 4 reg
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// master_wvalid O 1 reg
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// master_wid O 4 reg
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// master_wdata O 64 reg
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// master_wstrb O 8 reg
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// master_wlast O 1 reg
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// master_bready O 1 reg
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// master_arvalid O 1 reg
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// master_arid O 4 reg
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// master_araddr O 64 reg
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// master_arlen O 8 reg
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// master_arsize O 3 reg
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// master_arburst O 2 reg
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// master_arlock O 1 reg
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// master_arcache O 4 reg
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// master_arprot O 3 reg
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// master_arqos O 4 reg
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// master_arregion O 4 reg
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// master_rready O 1 reg
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// trace_data_out_get O 427 reg
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// RDY_trace_data_out_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// slave_awvalid I 1
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// slave_awid I 4 reg
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// slave_awaddr I 64 reg
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// slave_awlen I 8 reg
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// slave_awsize I 3 reg
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// slave_awburst I 2 reg
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// slave_awlock I 1 reg
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// slave_awcache I 4 reg
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// slave_awprot I 3 reg
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// slave_awqos I 4 reg
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// slave_awregion I 4 reg
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// slave_wvalid I 1
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// slave_wid I 4 reg
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// slave_wdata I 64 reg
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// slave_wstrb I 8 reg
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// slave_wlast I 1 reg
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// slave_bready I 1
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// slave_arvalid I 1
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// slave_arid I 4 reg
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// slave_araddr I 64 reg
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// slave_arlen I 8 reg
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// slave_arsize I 3 reg
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// slave_arburst I 2 reg
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// slave_arlock I 1 reg
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// slave_arcache I 4 reg
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// slave_arprot I 3 reg
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// slave_arqos I 4 reg
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// slave_arregion I 4 reg
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// slave_rready I 1
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// master_awready I 1
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// master_wready I 1
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// master_bvalid I 1
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// master_bid I 4 reg
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// master_bresp I 2 reg
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// master_arready I 1
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// master_rvalid I 1
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// master_rid I 4 reg
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// master_rdata I 64 reg
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// master_rresp I 2 reg
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// master_rlast I 1 reg
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// EN_trace_data_out_get I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDM_Mem_Tap(CLK,
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RST_N,
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slave_awvalid,
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slave_awid,
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slave_awaddr,
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slave_awlen,
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slave_awsize,
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slave_awburst,
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slave_awlock,
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slave_awcache,
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slave_awprot,
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slave_awqos,
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slave_awregion,
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slave_awready,
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slave_wvalid,
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slave_wid,
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slave_wdata,
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slave_wstrb,
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slave_wlast,
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slave_wready,
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slave_bvalid,
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slave_bid,
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slave_bresp,
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slave_bready,
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slave_arvalid,
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slave_arid,
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slave_araddr,
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slave_arlen,
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slave_arsize,
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slave_arburst,
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slave_arlock,
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slave_arcache,
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slave_arprot,
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slave_arqos,
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slave_arregion,
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slave_arready,
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slave_rvalid,
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slave_rid,
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slave_rdata,
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slave_rresp,
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slave_rlast,
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slave_rready,
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master_awvalid,
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master_awid,
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master_awaddr,
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master_awlen,
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master_awsize,
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master_awburst,
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master_awlock,
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master_awcache,
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master_awprot,
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master_awqos,
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master_awregion,
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master_awready,
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master_wvalid,
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master_wid,
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master_wdata,
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master_wstrb,
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master_wlast,
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master_wready,
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master_bvalid,
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master_bid,
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master_bresp,
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master_bready,
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master_arvalid,
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master_arid,
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master_araddr,
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master_arlen,
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master_arsize,
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master_arburst,
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master_arlock,
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master_arcache,
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master_arprot,
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master_arqos,
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master_arregion,
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master_arready,
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master_rvalid,
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master_rid,
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master_rdata,
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master_rresp,
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master_rlast,
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master_rready,
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EN_trace_data_out_get,
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trace_data_out_get,
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RDY_trace_data_out_get);
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input CLK;
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input RST_N;
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// action method slave_m_awvalid
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input slave_awvalid;
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input [3 : 0] slave_awid;
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input [63 : 0] slave_awaddr;
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input [7 : 0] slave_awlen;
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input [2 : 0] slave_awsize;
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input [1 : 0] slave_awburst;
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input slave_awlock;
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input [3 : 0] slave_awcache;
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input [2 : 0] slave_awprot;
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input [3 : 0] slave_awqos;
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input [3 : 0] slave_awregion;
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// value method slave_m_awready
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output slave_awready;
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// action method slave_m_wvalid
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input slave_wvalid;
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input [3 : 0] slave_wid;
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input [63 : 0] slave_wdata;
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input [7 : 0] slave_wstrb;
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input slave_wlast;
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// value method slave_m_wready
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output slave_wready;
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// value method slave_m_bvalid
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output slave_bvalid;
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// value method slave_m_bid
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output [3 : 0] slave_bid;
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// value method slave_m_bresp
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output [1 : 0] slave_bresp;
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// value method slave_m_buser
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// action method slave_m_bready
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input slave_bready;
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// action method slave_m_arvalid
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input slave_arvalid;
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input [3 : 0] slave_arid;
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input [63 : 0] slave_araddr;
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input [7 : 0] slave_arlen;
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input [2 : 0] slave_arsize;
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input [1 : 0] slave_arburst;
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input slave_arlock;
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input [3 : 0] slave_arcache;
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input [2 : 0] slave_arprot;
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input [3 : 0] slave_arqos;
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input [3 : 0] slave_arregion;
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// value method slave_m_arready
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output slave_arready;
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// value method slave_m_rvalid
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output slave_rvalid;
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// value method slave_m_rid
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output [3 : 0] slave_rid;
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// value method slave_m_rdata
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output [63 : 0] slave_rdata;
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// value method slave_m_rresp
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output [1 : 0] slave_rresp;
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// value method slave_m_rlast
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output slave_rlast;
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// value method slave_m_ruser
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// action method slave_m_rready
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input slave_rready;
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// value method master_m_awvalid
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output master_awvalid;
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// value method master_m_awid
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output [3 : 0] master_awid;
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// value method master_m_awaddr
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output [63 : 0] master_awaddr;
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// value method master_m_awlen
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output [7 : 0] master_awlen;
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// value method master_m_awsize
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output [2 : 0] master_awsize;
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// value method master_m_awburst
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output [1 : 0] master_awburst;
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// value method master_m_awlock
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output master_awlock;
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// value method master_m_awcache
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output [3 : 0] master_awcache;
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// value method master_m_awprot
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output [2 : 0] master_awprot;
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// value method master_m_awqos
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output [3 : 0] master_awqos;
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// value method master_m_awregion
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output [3 : 0] master_awregion;
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// value method master_m_awuser
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// action method master_m_awready
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input master_awready;
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// value method master_m_wvalid
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output master_wvalid;
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// value method master_m_wid
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output [3 : 0] master_wid;
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// value method master_m_wdata
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output [63 : 0] master_wdata;
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// value method master_m_wstrb
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output [7 : 0] master_wstrb;
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// value method master_m_wlast
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output master_wlast;
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// value method master_m_wuser
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// action method master_m_wready
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input master_wready;
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// action method master_m_bvalid
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input master_bvalid;
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input [3 : 0] master_bid;
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input [1 : 0] master_bresp;
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// value method master_m_bready
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output master_bready;
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// value method master_m_arvalid
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output master_arvalid;
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// value method master_m_arid
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output [3 : 0] master_arid;
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// value method master_m_araddr
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output [63 : 0] master_araddr;
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// value method master_m_arlen
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output [7 : 0] master_arlen;
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// value method master_m_arsize
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output [2 : 0] master_arsize;
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// value method master_m_arburst
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output [1 : 0] master_arburst;
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// value method master_m_arlock
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output master_arlock;
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// value method master_m_arcache
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output [3 : 0] master_arcache;
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// value method master_m_arprot
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output [2 : 0] master_arprot;
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// value method master_m_arqos
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output [3 : 0] master_arqos;
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// value method master_m_arregion
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output [3 : 0] master_arregion;
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// value method master_m_aruser
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// action method master_m_arready
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input master_arready;
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// action method master_m_rvalid
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input master_rvalid;
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input [3 : 0] master_rid;
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input [63 : 0] master_rdata;
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input [1 : 0] master_rresp;
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input master_rlast;
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// value method master_m_rready
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output master_rready;
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// actionvalue method trace_data_out_get
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input EN_trace_data_out_get;
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output [426 : 0] trace_data_out_get;
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output RDY_trace_data_out_get;
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// signals for module outputs
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wire [426 : 0] trace_data_out_get;
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wire [63 : 0] master_araddr, master_awaddr, master_wdata, slave_rdata;
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wire [7 : 0] master_arlen, master_awlen, master_wstrb;
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wire [3 : 0] master_arcache,
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master_arid,
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master_arqos,
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master_arregion,
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master_awcache,
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master_awid,
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master_awqos,
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master_awregion,
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master_wid,
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slave_bid,
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slave_rid;
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wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
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wire [1 : 0] master_arburst, master_awburst, slave_bresp, slave_rresp;
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wire RDY_trace_data_out_get,
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master_arlock,
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master_arvalid,
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master_awlock,
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master_awvalid,
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master_bready,
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master_rready,
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master_wlast,
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master_wvalid,
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slave_arready,
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slave_awready,
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slave_bvalid,
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slave_rlast,
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slave_rvalid,
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slave_wready;
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// ports of submodule f_trace_data
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wire [426 : 0] f_trace_data$D_IN, f_trace_data$D_OUT;
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wire f_trace_data$CLR,
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f_trace_data$DEQ,
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f_trace_data$EMPTY_N,
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f_trace_data$ENQ,
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f_trace_data$FULL_N;
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// ports of submodule master_xactor_f_rd_addr
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wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
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wire master_xactor_f_rd_addr$CLR,
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master_xactor_f_rd_addr$DEQ,
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master_xactor_f_rd_addr$EMPTY_N,
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master_xactor_f_rd_addr$ENQ,
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master_xactor_f_rd_addr$FULL_N;
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// ports of submodule master_xactor_f_rd_data
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wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
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wire master_xactor_f_rd_data$CLR,
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master_xactor_f_rd_data$DEQ,
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master_xactor_f_rd_data$EMPTY_N,
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master_xactor_f_rd_data$ENQ,
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master_xactor_f_rd_data$FULL_N;
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// ports of submodule master_xactor_f_wr_addr
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wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
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wire master_xactor_f_wr_addr$CLR,
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master_xactor_f_wr_addr$DEQ,
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master_xactor_f_wr_addr$EMPTY_N,
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master_xactor_f_wr_addr$ENQ,
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master_xactor_f_wr_addr$FULL_N;
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// ports of submodule master_xactor_f_wr_data
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wire [76 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
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wire master_xactor_f_wr_data$CLR,
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master_xactor_f_wr_data$DEQ,
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master_xactor_f_wr_data$EMPTY_N,
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master_xactor_f_wr_data$ENQ,
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master_xactor_f_wr_data$FULL_N;
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// ports of submodule master_xactor_f_wr_resp
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wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
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wire master_xactor_f_wr_resp$CLR,
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master_xactor_f_wr_resp$DEQ,
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master_xactor_f_wr_resp$EMPTY_N,
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master_xactor_f_wr_resp$ENQ,
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master_xactor_f_wr_resp$FULL_N;
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// ports of submodule slave_xactor_f_rd_addr
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wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
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wire slave_xactor_f_rd_addr$CLR,
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slave_xactor_f_rd_addr$DEQ,
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slave_xactor_f_rd_addr$EMPTY_N,
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slave_xactor_f_rd_addr$ENQ,
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slave_xactor_f_rd_addr$FULL_N;
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// ports of submodule slave_xactor_f_rd_data
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wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
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wire slave_xactor_f_rd_data$CLR,
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slave_xactor_f_rd_data$DEQ,
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slave_xactor_f_rd_data$EMPTY_N,
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slave_xactor_f_rd_data$ENQ,
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slave_xactor_f_rd_data$FULL_N;
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// ports of submodule slave_xactor_f_wr_addr
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wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
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wire slave_xactor_f_wr_addr$CLR,
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slave_xactor_f_wr_addr$DEQ,
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slave_xactor_f_wr_addr$EMPTY_N,
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slave_xactor_f_wr_addr$ENQ,
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slave_xactor_f_wr_addr$FULL_N;
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// ports of submodule slave_xactor_f_wr_data
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wire [76 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT;
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wire slave_xactor_f_wr_data$CLR,
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slave_xactor_f_wr_data$DEQ,
|
|
slave_xactor_f_wr_data$EMPTY_N,
|
|
slave_xactor_f_wr_data$ENQ,
|
|
slave_xactor_f_wr_data$FULL_N;
|
|
|
|
// ports of submodule slave_xactor_f_wr_resp
|
|
wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
|
|
wire slave_xactor_f_wr_resp$CLR,
|
|
slave_xactor_f_wr_resp$DEQ,
|
|
slave_xactor_f_wr_resp$EMPTY_N,
|
|
slave_xactor_f_wr_resp$ENQ,
|
|
slave_xactor_f_wr_resp$FULL_N;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_rl_connect,
|
|
CAN_FIRE_RL_rl_connect_1,
|
|
CAN_FIRE_RL_rl_connect_2,
|
|
CAN_FIRE_RL_write_reqs,
|
|
CAN_FIRE_master_m_arready,
|
|
CAN_FIRE_master_m_awready,
|
|
CAN_FIRE_master_m_bvalid,
|
|
CAN_FIRE_master_m_rvalid,
|
|
CAN_FIRE_master_m_wready,
|
|
CAN_FIRE_slave_m_arvalid,
|
|
CAN_FIRE_slave_m_awvalid,
|
|
CAN_FIRE_slave_m_bready,
|
|
CAN_FIRE_slave_m_rready,
|
|
CAN_FIRE_slave_m_wvalid,
|
|
CAN_FIRE_trace_data_out_get,
|
|
WILL_FIRE_RL_rl_connect,
|
|
WILL_FIRE_RL_rl_connect_1,
|
|
WILL_FIRE_RL_rl_connect_2,
|
|
WILL_FIRE_RL_write_reqs,
|
|
WILL_FIRE_master_m_arready,
|
|
WILL_FIRE_master_m_awready,
|
|
WILL_FIRE_master_m_bvalid,
|
|
WILL_FIRE_master_m_rvalid,
|
|
WILL_FIRE_master_m_wready,
|
|
WILL_FIRE_slave_m_arvalid,
|
|
WILL_FIRE_slave_m_awvalid,
|
|
WILL_FIRE_slave_m_bready,
|
|
WILL_FIRE_slave_m_rready,
|
|
WILL_FIRE_slave_m_wvalid,
|
|
WILL_FIRE_trace_data_out_get;
|
|
|
|
// remaining internal signals
|
|
wire [63 : 0] stval___1__h1532, x__h1527, y_avValue_fst__h1438;
|
|
|
|
// action method slave_m_awvalid
|
|
assign CAN_FIRE_slave_m_awvalid = 1'd1 ;
|
|
assign WILL_FIRE_slave_m_awvalid = 1'd1 ;
|
|
|
|
// value method slave_m_awready
|
|
assign slave_awready = slave_xactor_f_wr_addr$FULL_N ;
|
|
|
|
// action method slave_m_wvalid
|
|
assign CAN_FIRE_slave_m_wvalid = 1'd1 ;
|
|
assign WILL_FIRE_slave_m_wvalid = 1'd1 ;
|
|
|
|
// value method slave_m_wready
|
|
assign slave_wready = slave_xactor_f_wr_data$FULL_N ;
|
|
|
|
// value method slave_m_bvalid
|
|
assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
|
|
|
|
// value method slave_m_bid
|
|
assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ;
|
|
|
|
// value method slave_m_bresp
|
|
assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
|
|
|
|
// action method slave_m_bready
|
|
assign CAN_FIRE_slave_m_bready = 1'd1 ;
|
|
assign WILL_FIRE_slave_m_bready = 1'd1 ;
|
|
|
|
// action method slave_m_arvalid
|
|
assign CAN_FIRE_slave_m_arvalid = 1'd1 ;
|
|
assign WILL_FIRE_slave_m_arvalid = 1'd1 ;
|
|
|
|
// value method slave_m_arready
|
|
assign slave_arready = slave_xactor_f_rd_addr$FULL_N ;
|
|
|
|
// value method slave_m_rvalid
|
|
assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
|
|
|
|
// value method slave_m_rid
|
|
assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ;
|
|
|
|
// value method slave_m_rdata
|
|
assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
|
|
|
|
// value method slave_m_rresp
|
|
assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
|
|
|
|
// value method slave_m_rlast
|
|
assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
|
|
|
|
// action method slave_m_rready
|
|
assign CAN_FIRE_slave_m_rready = 1'd1 ;
|
|
assign WILL_FIRE_slave_m_rready = 1'd1 ;
|
|
|
|
// value method master_m_awvalid
|
|
assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
|
|
|
|
// value method master_m_awid
|
|
assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
|
|
|
|
// value method master_m_awaddr
|
|
assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
|
|
|
|
// value method master_m_awlen
|
|
assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
|
|
|
|
// value method master_m_awsize
|
|
assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
|
|
|
|
// value method master_m_awburst
|
|
assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
|
|
|
|
// value method master_m_awlock
|
|
assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
|
|
|
|
// value method master_m_awcache
|
|
assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
|
|
|
|
// value method master_m_awprot
|
|
assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
|
|
|
|
// value method master_m_awqos
|
|
assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
|
|
|
|
// value method master_m_awregion
|
|
assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
|
|
|
|
// action method master_m_awready
|
|
assign CAN_FIRE_master_m_awready = 1'd1 ;
|
|
assign WILL_FIRE_master_m_awready = 1'd1 ;
|
|
|
|
// value method master_m_wvalid
|
|
assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
|
|
|
|
// value method master_m_wid
|
|
assign master_wid = master_xactor_f_wr_data$D_OUT[76:73] ;
|
|
|
|
// value method master_m_wdata
|
|
assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
|
|
|
|
// value method master_m_wstrb
|
|
assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
|
|
|
|
// value method master_m_wlast
|
|
assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
|
|
|
|
// action method master_m_wready
|
|
assign CAN_FIRE_master_m_wready = 1'd1 ;
|
|
assign WILL_FIRE_master_m_wready = 1'd1 ;
|
|
|
|
// action method master_m_bvalid
|
|
assign CAN_FIRE_master_m_bvalid = 1'd1 ;
|
|
assign WILL_FIRE_master_m_bvalid = 1'd1 ;
|
|
|
|
// value method master_m_bready
|
|
assign master_bready = master_xactor_f_wr_resp$FULL_N ;
|
|
|
|
// value method master_m_arvalid
|
|
assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
|
|
|
|
// value method master_m_arid
|
|
assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
|
|
|
|
// value method master_m_araddr
|
|
assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
|
|
|
|
// value method master_m_arlen
|
|
assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
|
|
|
|
// value method master_m_arsize
|
|
assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
|
|
|
|
// value method master_m_arburst
|
|
assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
|
|
|
|
// value method master_m_arlock
|
|
assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
|
|
|
|
// value method master_m_arcache
|
|
assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
|
|
|
|
// value method master_m_arprot
|
|
assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
|
|
|
|
// value method master_m_arqos
|
|
assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
|
|
|
|
// value method master_m_arregion
|
|
assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
|
|
|
|
// action method master_m_arready
|
|
assign CAN_FIRE_master_m_arready = 1'd1 ;
|
|
assign WILL_FIRE_master_m_arready = 1'd1 ;
|
|
|
|
// action method master_m_rvalid
|
|
assign CAN_FIRE_master_m_rvalid = 1'd1 ;
|
|
assign WILL_FIRE_master_m_rvalid = 1'd1 ;
|
|
|
|
// value method master_m_rready
|
|
assign master_rready = master_xactor_f_rd_data$FULL_N ;
|
|
|
|
// actionvalue method trace_data_out_get
|
|
assign trace_data_out_get = f_trace_data$D_OUT ;
|
|
assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ;
|
|
assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ;
|
|
assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ;
|
|
|
|
// submodule f_trace_data
|
|
FIFO2 #(.width(32'd427), .guarded(32'd1)) f_trace_data(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(f_trace_data$D_IN),
|
|
.ENQ(f_trace_data$ENQ),
|
|
.DEQ(f_trace_data$DEQ),
|
|
.CLR(f_trace_data$CLR),
|
|
.D_OUT(f_trace_data$D_OUT),
|
|
.FULL_N(f_trace_data$FULL_N),
|
|
.EMPTY_N(f_trace_data$EMPTY_N));
|
|
|
|
// submodule master_xactor_f_rd_addr
|
|
FIFO2 #(.width(32'd97),
|
|
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(master_xactor_f_rd_addr$D_IN),
|
|
.ENQ(master_xactor_f_rd_addr$ENQ),
|
|
.DEQ(master_xactor_f_rd_addr$DEQ),
|
|
.CLR(master_xactor_f_rd_addr$CLR),
|
|
.D_OUT(master_xactor_f_rd_addr$D_OUT),
|
|
.FULL_N(master_xactor_f_rd_addr$FULL_N),
|
|
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
|
|
|
|
// submodule master_xactor_f_rd_data
|
|
FIFO2 #(.width(32'd71),
|
|
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(master_xactor_f_rd_data$D_IN),
|
|
.ENQ(master_xactor_f_rd_data$ENQ),
|
|
.DEQ(master_xactor_f_rd_data$DEQ),
|
|
.CLR(master_xactor_f_rd_data$CLR),
|
|
.D_OUT(master_xactor_f_rd_data$D_OUT),
|
|
.FULL_N(master_xactor_f_rd_data$FULL_N),
|
|
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
|
|
|
|
// submodule master_xactor_f_wr_addr
|
|
FIFO2 #(.width(32'd97),
|
|
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(master_xactor_f_wr_addr$D_IN),
|
|
.ENQ(master_xactor_f_wr_addr$ENQ),
|
|
.DEQ(master_xactor_f_wr_addr$DEQ),
|
|
.CLR(master_xactor_f_wr_addr$CLR),
|
|
.D_OUT(master_xactor_f_wr_addr$D_OUT),
|
|
.FULL_N(master_xactor_f_wr_addr$FULL_N),
|
|
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
|
|
|
|
// submodule master_xactor_f_wr_data
|
|
FIFO2 #(.width(32'd77),
|
|
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(master_xactor_f_wr_data$D_IN),
|
|
.ENQ(master_xactor_f_wr_data$ENQ),
|
|
.DEQ(master_xactor_f_wr_data$DEQ),
|
|
.CLR(master_xactor_f_wr_data$CLR),
|
|
.D_OUT(master_xactor_f_wr_data$D_OUT),
|
|
.FULL_N(master_xactor_f_wr_data$FULL_N),
|
|
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
|
|
|
|
// submodule master_xactor_f_wr_resp
|
|
FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(master_xactor_f_wr_resp$D_IN),
|
|
.ENQ(master_xactor_f_wr_resp$ENQ),
|
|
.DEQ(master_xactor_f_wr_resp$DEQ),
|
|
.CLR(master_xactor_f_wr_resp$CLR),
|
|
.D_OUT(master_xactor_f_wr_resp$D_OUT),
|
|
.FULL_N(master_xactor_f_wr_resp$FULL_N),
|
|
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
|
|
|
|
// submodule slave_xactor_f_rd_addr
|
|
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(slave_xactor_f_rd_addr$D_IN),
|
|
.ENQ(slave_xactor_f_rd_addr$ENQ),
|
|
.DEQ(slave_xactor_f_rd_addr$DEQ),
|
|
.CLR(slave_xactor_f_rd_addr$CLR),
|
|
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
|
|
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
|
|
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
|
|
|
|
// submodule slave_xactor_f_rd_data
|
|
FIFO2 #(.width(32'd71), .guarded(32'd1)) slave_xactor_f_rd_data(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(slave_xactor_f_rd_data$D_IN),
|
|
.ENQ(slave_xactor_f_rd_data$ENQ),
|
|
.DEQ(slave_xactor_f_rd_data$DEQ),
|
|
.CLR(slave_xactor_f_rd_data$CLR),
|
|
.D_OUT(slave_xactor_f_rd_data$D_OUT),
|
|
.FULL_N(slave_xactor_f_rd_data$FULL_N),
|
|
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
|
|
|
|
// submodule slave_xactor_f_wr_addr
|
|
FIFO2 #(.width(32'd97), .guarded(32'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(slave_xactor_f_wr_addr$D_IN),
|
|
.ENQ(slave_xactor_f_wr_addr$ENQ),
|
|
.DEQ(slave_xactor_f_wr_addr$DEQ),
|
|
.CLR(slave_xactor_f_wr_addr$CLR),
|
|
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
|
|
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
|
|
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
|
|
|
|
// submodule slave_xactor_f_wr_data
|
|
FIFO2 #(.width(32'd77), .guarded(32'd1)) slave_xactor_f_wr_data(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(slave_xactor_f_wr_data$D_IN),
|
|
.ENQ(slave_xactor_f_wr_data$ENQ),
|
|
.DEQ(slave_xactor_f_wr_data$DEQ),
|
|
.CLR(slave_xactor_f_wr_data$CLR),
|
|
.D_OUT(slave_xactor_f_wr_data$D_OUT),
|
|
.FULL_N(slave_xactor_f_wr_data$FULL_N),
|
|
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
|
|
|
|
// submodule slave_xactor_f_wr_resp
|
|
FIFO2 #(.width(32'd6), .guarded(32'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(slave_xactor_f_wr_resp$D_IN),
|
|
.ENQ(slave_xactor_f_wr_resp$ENQ),
|
|
.DEQ(slave_xactor_f_wr_resp$DEQ),
|
|
.CLR(slave_xactor_f_wr_resp$CLR),
|
|
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
|
|
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
|
|
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
|
|
|
|
// rule RL_write_reqs
|
|
assign CAN_FIRE_RL_write_reqs =
|
|
slave_xactor_f_wr_addr$EMPTY_N &&
|
|
slave_xactor_f_wr_data$EMPTY_N &&
|
|
master_xactor_f_wr_addr$FULL_N &&
|
|
master_xactor_f_wr_data$FULL_N &&
|
|
f_trace_data$FULL_N ;
|
|
assign WILL_FIRE_RL_write_reqs = CAN_FIRE_RL_write_reqs ;
|
|
|
|
// rule RL_rl_connect
|
|
assign CAN_FIRE_RL_rl_connect =
|
|
master_xactor_f_rd_addr$FULL_N &&
|
|
slave_xactor_f_rd_addr$EMPTY_N ;
|
|
assign WILL_FIRE_RL_rl_connect = CAN_FIRE_RL_rl_connect ;
|
|
|
|
// rule RL_rl_connect_1
|
|
assign CAN_FIRE_RL_rl_connect_1 =
|
|
slave_xactor_f_wr_resp$FULL_N &&
|
|
master_xactor_f_wr_resp$EMPTY_N ;
|
|
assign WILL_FIRE_RL_rl_connect_1 = CAN_FIRE_RL_rl_connect_1 ;
|
|
|
|
// rule RL_rl_connect_2
|
|
assign CAN_FIRE_RL_rl_connect_2 =
|
|
slave_xactor_f_rd_data$FULL_N &&
|
|
master_xactor_f_rd_data$EMPTY_N ;
|
|
assign WILL_FIRE_RL_rl_connect_2 = CAN_FIRE_RL_rl_connect_2 ;
|
|
|
|
// submodule f_trace_data
|
|
assign f_trace_data$D_IN =
|
|
{ 171'h12AAAAAAAAAAAAAAA955555554A0000000000000002,
|
|
x__h1527,
|
|
slave_xactor_f_wr_addr$D_OUT[92:29],
|
|
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
|
|
assign f_trace_data$ENQ = CAN_FIRE_RL_write_reqs ;
|
|
assign f_trace_data$DEQ = EN_trace_data_out_get ;
|
|
assign f_trace_data$CLR = 1'b0 ;
|
|
|
|
// submodule master_xactor_f_rd_addr
|
|
assign master_xactor_f_rd_addr$D_IN = slave_xactor_f_rd_addr$D_OUT ;
|
|
assign master_xactor_f_rd_addr$ENQ = CAN_FIRE_RL_rl_connect ;
|
|
assign master_xactor_f_rd_addr$DEQ =
|
|
master_xactor_f_rd_addr$EMPTY_N && master_arready ;
|
|
assign master_xactor_f_rd_addr$CLR = 1'b0 ;
|
|
|
|
// submodule master_xactor_f_rd_data
|
|
assign master_xactor_f_rd_data$D_IN =
|
|
{ master_rid, master_rdata, master_rresp, master_rlast } ;
|
|
assign master_xactor_f_rd_data$ENQ =
|
|
master_rvalid && master_xactor_f_rd_data$FULL_N ;
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assign master_xactor_f_rd_data$DEQ = CAN_FIRE_RL_rl_connect_2 ;
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assign master_xactor_f_rd_data$CLR = 1'b0 ;
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// submodule master_xactor_f_wr_addr
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assign master_xactor_f_wr_addr$D_IN = slave_xactor_f_wr_addr$D_OUT ;
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assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_write_reqs ;
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assign master_xactor_f_wr_addr$DEQ =
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master_xactor_f_wr_addr$EMPTY_N && master_awready ;
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assign master_xactor_f_wr_addr$CLR = 1'b0 ;
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// submodule master_xactor_f_wr_data
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assign master_xactor_f_wr_data$D_IN = slave_xactor_f_wr_data$D_OUT ;
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assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_write_reqs ;
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assign master_xactor_f_wr_data$DEQ =
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master_xactor_f_wr_data$EMPTY_N && master_wready ;
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assign master_xactor_f_wr_data$CLR = 1'b0 ;
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// submodule master_xactor_f_wr_resp
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assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ;
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assign master_xactor_f_wr_resp$ENQ =
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master_bvalid && master_xactor_f_wr_resp$FULL_N ;
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assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_connect_1 ;
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assign master_xactor_f_wr_resp$CLR = 1'b0 ;
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// submodule slave_xactor_f_rd_addr
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assign slave_xactor_f_rd_addr$D_IN =
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{ slave_arid,
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slave_araddr,
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slave_arlen,
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slave_arsize,
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slave_arburst,
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slave_arlock,
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slave_arcache,
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slave_arprot,
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slave_arqos,
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slave_arregion } ;
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assign slave_xactor_f_rd_addr$ENQ =
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slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
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assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_connect ;
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assign slave_xactor_f_rd_addr$CLR = 1'b0 ;
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// submodule slave_xactor_f_rd_data
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assign slave_xactor_f_rd_data$D_IN = master_xactor_f_rd_data$D_OUT ;
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assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_connect_2 ;
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assign slave_xactor_f_rd_data$DEQ =
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slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
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assign slave_xactor_f_rd_data$CLR = 1'b0 ;
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// submodule slave_xactor_f_wr_addr
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assign slave_xactor_f_wr_addr$D_IN =
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{ slave_awid,
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slave_awaddr,
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slave_awlen,
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slave_awsize,
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slave_awburst,
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|
slave_awlock,
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slave_awcache,
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slave_awprot,
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slave_awqos,
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|
slave_awregion } ;
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assign slave_xactor_f_wr_addr$ENQ =
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slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
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assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_write_reqs ;
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assign slave_xactor_f_wr_addr$CLR = 1'b0 ;
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// submodule slave_xactor_f_wr_data
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assign slave_xactor_f_wr_data$D_IN =
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{ slave_wid, slave_wdata, slave_wstrb, slave_wlast } ;
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assign slave_xactor_f_wr_data$ENQ =
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slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
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|
assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_write_reqs ;
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assign slave_xactor_f_wr_data$CLR = 1'b0 ;
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|
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// submodule slave_xactor_f_wr_resp
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assign slave_xactor_f_wr_resp$D_IN = master_xactor_f_wr_resp$D_OUT ;
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assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_connect_1 ;
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|
assign slave_xactor_f_wr_resp$DEQ =
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|
slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
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assign slave_xactor_f_wr_resp$CLR = 1'b0 ;
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// remaining internal signals
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assign stval___1__h1532 = { 32'd0, slave_xactor_f_wr_data$D_OUT[40:9] } ;
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assign x__h1527 =
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|
(slave_xactor_f_wr_data$D_OUT[8:1] == 8'h0F) ?
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|
stval___1__h1532 :
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|
y_avValue_fst__h1438 ;
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|
assign y_avValue_fst__h1438 =
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|
{ 32'd0, slave_xactor_f_wr_data$D_OUT[72:41] } ;
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endmodule // mkDM_Mem_Tap
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