423 lines
12 KiB
Verilog
423 lines
12 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// pred_0_pred O 9
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// RDY_pred_0_pred O 1 const
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// pred_1_pred O 9
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// RDY_pred_1_pred O 1 const
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// RDY_update O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// pred_0_pred_pc I 64
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// pred_1_pred_pc I 64
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// update_pc I 64
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// update_taken I 1
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// update_train I 8
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// update_mispred I 1
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// EN_update I 1
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// EN_flush I 1 unused
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// EN_pred_0_pred I 1
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// EN_pred_1_pred I 1
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//
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// Combinational paths from inputs to outputs:
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// EN_pred_0_pred -> pred_1_pred
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkGSharePred(CLK,
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RST_N,
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pred_0_pred_pc,
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EN_pred_0_pred,
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pred_0_pred,
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RDY_pred_0_pred,
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pred_1_pred_pc,
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EN_pred_1_pred,
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pred_1_pred,
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RDY_pred_1_pred,
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update_pc,
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update_taken,
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update_train,
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update_mispred,
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EN_update,
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RDY_update,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done);
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input CLK;
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input RST_N;
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// actionvalue method pred_0_pred
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input [63 : 0] pred_0_pred_pc;
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input EN_pred_0_pred;
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output [8 : 0] pred_0_pred;
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output RDY_pred_0_pred;
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// actionvalue method pred_1_pred
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input [63 : 0] pred_1_pred_pc;
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input EN_pred_1_pred;
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output [8 : 0] pred_1_pred;
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output RDY_pred_1_pred;
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// action method update
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input [63 : 0] update_pc;
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input update_taken;
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input [7 : 0] update_train;
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input update_mispred;
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input EN_update;
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output RDY_update;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// signals for module outputs
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wire [8 : 0] pred_0_pred, pred_1_pred;
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wire RDY_flush,
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RDY_flush_done,
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RDY_pred_0_pred,
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RDY_pred_1_pred,
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RDY_update,
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flush_done;
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// register predCnt_rl
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reg [1 : 0] predCnt_rl;
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wire [1 : 0] predCnt_rl$D_IN;
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wire predCnt_rl$EN;
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// register predRes_rl
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reg [1 : 0] predRes_rl;
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wire [1 : 0] predRes_rl$D_IN;
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wire predRes_rl$EN;
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// ports of submodule globalHist
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wire [7 : 0] globalHist$history, globalHist$redirect_newHist;
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wire [1 : 0] globalHist$addHistory_num, globalHist$addHistory_taken;
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wire globalHist$EN_addHistory, globalHist$EN_redirect;
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// ports of submodule predCnt_dummy2_0
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wire predCnt_dummy2_0$D_IN, predCnt_dummy2_0$EN, predCnt_dummy2_0$Q_OUT;
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// ports of submodule predCnt_dummy2_1
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wire predCnt_dummy2_1$D_IN, predCnt_dummy2_1$EN, predCnt_dummy2_1$Q_OUT;
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// ports of submodule predCnt_dummy2_2
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wire predCnt_dummy2_2$D_IN, predCnt_dummy2_2$EN, predCnt_dummy2_2$Q_OUT;
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// ports of submodule predRes_dummy2_0
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wire predRes_dummy2_0$D_IN, predRes_dummy2_0$EN, predRes_dummy2_0$Q_OUT;
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// ports of submodule predRes_dummy2_1
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wire predRes_dummy2_1$D_IN, predRes_dummy2_1$EN, predRes_dummy2_1$Q_OUT;
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// ports of submodule predRes_dummy2_2
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wire predRes_dummy2_2$D_IN, predRes_dummy2_2$EN, predRes_dummy2_2$Q_OUT;
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// ports of submodule tab
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wire [7 : 0] tab$ADDR_1,
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tab$ADDR_2,
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tab$ADDR_3,
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tab$ADDR_4,
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tab$ADDR_5,
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tab$ADDR_IN;
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wire [1 : 0] tab$D_IN, tab$D_OUT_1, tab$D_OUT_2, tab$D_OUT_3;
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wire tab$WE;
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// rule scheduling signals
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wire CAN_FIRE_RL_canonGlobalHist,
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CAN_FIRE_RL_predCnt_canon,
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CAN_FIRE_RL_predRes_canon,
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CAN_FIRE_flush,
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CAN_FIRE_pred_0_pred,
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CAN_FIRE_pred_1_pred,
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CAN_FIRE_update,
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WILL_FIRE_RL_canonGlobalHist,
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WILL_FIRE_RL_predCnt_canon,
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WILL_FIRE_RL_predRes_canon,
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WILL_FIRE_flush,
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WILL_FIRE_pred_0_pred,
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WILL_FIRE_pred_1_pred,
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WILL_FIRE_update;
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// remaining internal signals
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wire [7 : 0] gHist__h4961, gHist__h5519;
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wire [1 : 0] IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8,
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18,
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n__read__h4984,
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n__read__h5542,
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res__h5165,
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res__h5898,
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upd__h3631,
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upd__h3881,
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upd__h5652,
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upd__h6126,
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x__h5220,
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x__h5953,
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y__h5428,
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y__h6160;
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// actionvalue method pred_0_pred
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assign pred_0_pred = { tab$D_OUT_2[1], gHist__h4961 } ;
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assign RDY_pred_0_pred = 1'd1 ;
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assign CAN_FIRE_pred_0_pred = 1'd1 ;
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assign WILL_FIRE_pred_0_pred = EN_pred_0_pred ;
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// actionvalue method pred_1_pred
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assign pred_1_pred = { tab$D_OUT_1[1], gHist__h5519 } ;
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assign RDY_pred_1_pred = 1'd1 ;
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assign CAN_FIRE_pred_1_pred = 1'd1 ;
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assign WILL_FIRE_pred_1_pred = EN_pred_1_pred ;
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// action method update
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assign RDY_update = 1'd1 ;
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assign CAN_FIRE_update = 1'd1 ;
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assign WILL_FIRE_update = EN_update ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = 1'd1 ;
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assign RDY_flush_done = 1'd1 ;
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// submodule globalHist
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mkGShareGHistReg globalHist(.CLK(CLK),
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.RST_N(RST_N),
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.addHistory_num(globalHist$addHistory_num),
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.addHistory_taken(globalHist$addHistory_taken),
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.redirect_newHist(globalHist$redirect_newHist),
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.EN_addHistory(globalHist$EN_addHistory),
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.EN_redirect(globalHist$EN_redirect),
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.history(globalHist$history),
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.RDY_history(),
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.RDY_addHistory(),
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.RDY_redirect());
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// submodule predCnt_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) predCnt_dummy2_0(.CLK(CLK),
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.D_IN(predCnt_dummy2_0$D_IN),
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.EN(predCnt_dummy2_0$EN),
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.Q_OUT(predCnt_dummy2_0$Q_OUT));
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// submodule predCnt_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) predCnt_dummy2_1(.CLK(CLK),
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.D_IN(predCnt_dummy2_1$D_IN),
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.EN(predCnt_dummy2_1$EN),
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.Q_OUT(predCnt_dummy2_1$Q_OUT));
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// submodule predCnt_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) predCnt_dummy2_2(.CLK(CLK),
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.D_IN(predCnt_dummy2_2$D_IN),
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.EN(predCnt_dummy2_2$EN),
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.Q_OUT(predCnt_dummy2_2$Q_OUT));
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// submodule predRes_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) predRes_dummy2_0(.CLK(CLK),
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.D_IN(predRes_dummy2_0$D_IN),
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.EN(predRes_dummy2_0$EN),
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.Q_OUT(predRes_dummy2_0$Q_OUT));
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// submodule predRes_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) predRes_dummy2_1(.CLK(CLK),
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.D_IN(predRes_dummy2_1$D_IN),
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.EN(predRes_dummy2_1$EN),
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.Q_OUT(predRes_dummy2_1$Q_OUT));
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// submodule predRes_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) predRes_dummy2_2(.CLK(CLK),
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.D_IN(predRes_dummy2_2$D_IN),
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.EN(predRes_dummy2_2$EN),
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.Q_OUT(predRes_dummy2_2$Q_OUT));
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// submodule tab
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RegFile #(.addr_width(32'd8),
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.data_width(32'd2),
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.lo(8'd0),
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.hi(8'd255)) tab(.CLK(CLK),
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.ADDR_1(tab$ADDR_1),
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.ADDR_2(tab$ADDR_2),
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.ADDR_3(tab$ADDR_3),
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.ADDR_4(tab$ADDR_4),
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.ADDR_5(tab$ADDR_5),
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.ADDR_IN(tab$ADDR_IN),
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.D_IN(tab$D_IN),
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.WE(tab$WE),
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.D_OUT_1(tab$D_OUT_1),
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.D_OUT_2(tab$D_OUT_2),
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.D_OUT_3(tab$D_OUT_3),
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.D_OUT_4(),
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.D_OUT_5());
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// rule RL_canonGlobalHist
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assign CAN_FIRE_RL_canonGlobalHist = 1'd1 ;
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assign WILL_FIRE_RL_canonGlobalHist = 1'd1 ;
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// rule RL_predCnt_canon
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assign CAN_FIRE_RL_predCnt_canon = 1'd1 ;
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assign WILL_FIRE_RL_predCnt_canon = 1'd1 ;
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// rule RL_predRes_canon
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assign CAN_FIRE_RL_predRes_canon = 1'd1 ;
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assign WILL_FIRE_RL_predRes_canon = 1'd1 ;
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// register predCnt_rl
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assign predCnt_rl$D_IN = 2'd0 ;
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assign predCnt_rl$EN = 1'd1 ;
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// register predRes_rl
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assign predRes_rl$D_IN = 2'd0 ;
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assign predRes_rl$EN = 1'd1 ;
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// submodule globalHist
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assign globalHist$addHistory_num =
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predCnt_dummy2_2$Q_OUT ?
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(EN_pred_1_pred ?
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upd__h3881 :
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IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8) :
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2'd0 ;
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assign globalHist$addHistory_taken =
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predRes_dummy2_2$Q_OUT ?
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(EN_pred_1_pred ?
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upd__h3631 :
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18) :
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2'd0 ;
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assign globalHist$redirect_newHist = { update_taken, update_train[7:1] } ;
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assign globalHist$EN_addHistory = 1'd1 ;
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assign globalHist$EN_redirect = EN_update && update_mispred ;
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// submodule predCnt_dummy2_0
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assign predCnt_dummy2_0$D_IN = 1'd1 ;
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assign predCnt_dummy2_0$EN = EN_pred_0_pred ;
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// submodule predCnt_dummy2_1
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assign predCnt_dummy2_1$D_IN = 1'd1 ;
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assign predCnt_dummy2_1$EN = EN_pred_1_pred ;
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// submodule predCnt_dummy2_2
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assign predCnt_dummy2_2$D_IN = 1'd1 ;
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assign predCnt_dummy2_2$EN = 1'd1 ;
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// submodule predRes_dummy2_0
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assign predRes_dummy2_0$D_IN = 1'd1 ;
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assign predRes_dummy2_0$EN = EN_pred_0_pred ;
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// submodule predRes_dummy2_1
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assign predRes_dummy2_1$D_IN = 1'd1 ;
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assign predRes_dummy2_1$EN = EN_pred_1_pred ;
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// submodule predRes_dummy2_2
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assign predRes_dummy2_2$D_IN = 1'd1 ;
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assign predRes_dummy2_2$EN = 1'd1 ;
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// submodule tab
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assign tab$ADDR_1 = gHist__h5519 ^ pred_1_pred_pc[9:2] ;
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assign tab$ADDR_2 = gHist__h4961 ^ pred_0_pred_pc[9:2] ;
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assign tab$ADDR_3 = update_train ^ update_pc[9:2] ;
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assign tab$ADDR_4 = 8'h0 ;
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assign tab$ADDR_5 = 8'h0 ;
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assign tab$ADDR_IN = update_train ^ update_pc[9:2] ;
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assign tab$D_IN =
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update_taken ?
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((tab$D_OUT_3 == 2'd3) ? tab$D_OUT_3 : tab$D_OUT_3 + 2'd1) :
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((tab$D_OUT_3 == 2'd0) ? tab$D_OUT_3 : tab$D_OUT_3 - 2'd1) ;
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assign tab$WE = EN_update ;
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// remaining internal signals
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assign IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 =
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EN_pred_0_pred ? upd__h5652 : predCnt_rl ;
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assign IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18 =
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EN_pred_0_pred ? upd__h6126 : predRes_rl ;
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assign gHist__h4961 = globalHist$history >> n__read__h4984 ;
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assign gHist__h5519 = globalHist$history >> n__read__h5542 ;
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assign n__read__h4984 =
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(predCnt_dummy2_0$Q_OUT && predCnt_dummy2_1$Q_OUT &&
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predCnt_dummy2_2$Q_OUT) ?
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predCnt_rl :
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2'd0 ;
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assign n__read__h5542 =
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(predCnt_dummy2_1$Q_OUT && predCnt_dummy2_2$Q_OUT) ?
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IF_predCnt_lat_0_whas_THEN_predCnt_lat_0_wget__ETC___d8 :
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2'd0 ;
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assign res__h5165 =
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(predRes_dummy2_0$Q_OUT && predRes_dummy2_1$Q_OUT &&
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predRes_dummy2_2$Q_OUT) ?
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predRes_rl :
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2'd0 ;
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assign res__h5898 =
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(predRes_dummy2_1$Q_OUT && predRes_dummy2_2$Q_OUT) ?
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IF_predRes_lat_0_whas__5_THEN_predRes_lat_0_wg_ETC___d18 :
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2'd0 ;
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assign upd__h3631 =
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tab$D_OUT_1[1] ? res__h5898 | x__h5953 : res__h5898 & y__h6160 ;
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assign upd__h3881 = n__read__h5542 + 2'd1 ;
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assign upd__h5652 = n__read__h4984 + 2'd1 ;
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assign upd__h6126 =
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tab$D_OUT_2[1] ? res__h5165 | x__h5220 : res__h5165 & y__h5428 ;
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assign x__h5220 = 2'd1 << n__read__h4984 ;
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assign x__h5953 = 2'd1 << n__read__h5542 ;
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assign y__h5428 = ~x__h5220 ;
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assign y__h6160 = ~x__h5953 ;
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// handling of inlined registers
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always@(posedge CLK)
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begin
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if (RST_N == `BSV_RESET_VALUE)
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begin
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predCnt_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
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predRes_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
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end
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else
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begin
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if (predCnt_rl$EN)
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predCnt_rl <= `BSV_ASSIGNMENT_DELAY predCnt_rl$D_IN;
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if (predRes_rl$EN)
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predRes_rl <= `BSV_ASSIGNMENT_DELAY predRes_rl$D_IN;
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end
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end
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// synopsys translate_off
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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initial
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begin
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predCnt_rl = 2'h2;
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predRes_rl = 2'h2;
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end
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`endif // BSV_NO_INITIAL_BLOCKS
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// synopsys translate_on
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endmodule // mkGSharePred
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