4867 lines
182 KiB
Verilog
4867 lines
182 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
|
|
//
|
|
//
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// getEmptyEntryInit O 3 reg
|
|
// RDY_getEmptyEntryInit O 1
|
|
// RDY_sendRsToC_releaseEntry O 1
|
|
// sendRsToC_getResult O 67
|
|
// RDY_sendRsToC_getResult O 1 const
|
|
// sendRsToP_cRq_getRq O 64
|
|
// RDY_sendRsToP_cRq_getRq O 1 const
|
|
// sendRsToP_cRq_getSlot O 56
|
|
// RDY_sendRsToP_cRq_getSlot O 1 const
|
|
// sendRqToP_getRq O 64
|
|
// RDY_sendRqToP_getRq O 1 const
|
|
// sendRqToP_getSlot O 56
|
|
// RDY_sendRqToP_getSlot O 1 const
|
|
// pipelineResp_getState O 3
|
|
// RDY_pipelineResp_getState O 1 const
|
|
// pipelineResp_getRq O 64
|
|
// RDY_pipelineResp_getRq O 1 const
|
|
// pipelineResp_getSlot O 56
|
|
// RDY_pipelineResp_getSlot O 1 const
|
|
// RDY_pipelineResp_setResult O 1 const
|
|
// RDY_pipelineResp_setStateSlot O 1 const
|
|
// pipelineResp_getSucc O 4
|
|
// RDY_pipelineResp_getSucc O 1 const
|
|
// RDY_pipelineResp_setSucc O 1 const
|
|
// pipelineResp_searchEndOfChain O 4
|
|
// RDY_pipelineResp_searchEndOfChain O 1 const
|
|
// emptyForFlush O 1
|
|
// RDY_emptyForFlush O 1 const
|
|
// stuck_get O 68 const
|
|
// RDY_stuck_get O 1 const
|
|
// CLK I 1 clock
|
|
// RST_N I 1 reset
|
|
// getEmptyEntryInit_r I 64
|
|
// sendRsToC_releaseEntry_n I 3
|
|
// sendRsToC_getResult_n I 3
|
|
// sendRsToP_cRq_getRq_n I 3
|
|
// sendRsToP_cRq_getSlot_n I 3
|
|
// sendRqToP_getRq_n I 3
|
|
// sendRqToP_getSlot_n I 3
|
|
// pipelineResp_getState_n I 3
|
|
// pipelineResp_getRq_n I 3
|
|
// pipelineResp_getSlot_n I 3
|
|
// pipelineResp_setResult_n I 3
|
|
// pipelineResp_setResult_r I 66
|
|
// pipelineResp_setStateSlot_n I 3
|
|
// pipelineResp_setStateSlot_state I 3
|
|
// pipelineResp_setStateSlot_slot I 56
|
|
// pipelineResp_getSucc_n I 3
|
|
// pipelineResp_setSucc_n I 3
|
|
// pipelineResp_setSucc_succ I 4
|
|
// pipelineResp_searchEndOfChain_addr I 64
|
|
// EN_sendRsToC_releaseEntry I 1
|
|
// EN_pipelineResp_setResult I 1
|
|
// EN_pipelineResp_setStateSlot I 1
|
|
// EN_pipelineResp_setSucc I 1
|
|
// EN_getEmptyEntryInit I 1
|
|
// EN_stuck_get I 1 unused
|
|
//
|
|
// Combinational paths from inputs to outputs:
|
|
// (sendRsToC_getResult_n,
|
|
// pipelineResp_setResult_n,
|
|
// pipelineResp_setResult_r,
|
|
// EN_pipelineResp_setResult) -> sendRsToC_getResult
|
|
// sendRsToP_cRq_getRq_n -> sendRsToP_cRq_getRq
|
|
// sendRsToP_cRq_getSlot_n -> sendRsToP_cRq_getSlot
|
|
// sendRqToP_getRq_n -> sendRqToP_getRq
|
|
// sendRqToP_getSlot_n -> sendRqToP_getSlot
|
|
// pipelineResp_getState_n -> pipelineResp_getState
|
|
// pipelineResp_getRq_n -> pipelineResp_getRq
|
|
// pipelineResp_getSlot_n -> pipelineResp_getSlot
|
|
// pipelineResp_getSucc_n -> pipelineResp_getSucc
|
|
// pipelineResp_searchEndOfChain_addr -> pipelineResp_searchEndOfChain
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module mkICRqMshrWrapper(CLK,
|
|
RST_N,
|
|
|
|
getEmptyEntryInit_r,
|
|
EN_getEmptyEntryInit,
|
|
getEmptyEntryInit,
|
|
RDY_getEmptyEntryInit,
|
|
|
|
sendRsToC_releaseEntry_n,
|
|
EN_sendRsToC_releaseEntry,
|
|
RDY_sendRsToC_releaseEntry,
|
|
|
|
sendRsToC_getResult_n,
|
|
sendRsToC_getResult,
|
|
RDY_sendRsToC_getResult,
|
|
|
|
sendRsToP_cRq_getRq_n,
|
|
sendRsToP_cRq_getRq,
|
|
RDY_sendRsToP_cRq_getRq,
|
|
|
|
sendRsToP_cRq_getSlot_n,
|
|
sendRsToP_cRq_getSlot,
|
|
RDY_sendRsToP_cRq_getSlot,
|
|
|
|
sendRqToP_getRq_n,
|
|
sendRqToP_getRq,
|
|
RDY_sendRqToP_getRq,
|
|
|
|
sendRqToP_getSlot_n,
|
|
sendRqToP_getSlot,
|
|
RDY_sendRqToP_getSlot,
|
|
|
|
pipelineResp_getState_n,
|
|
pipelineResp_getState,
|
|
RDY_pipelineResp_getState,
|
|
|
|
pipelineResp_getRq_n,
|
|
pipelineResp_getRq,
|
|
RDY_pipelineResp_getRq,
|
|
|
|
pipelineResp_getSlot_n,
|
|
pipelineResp_getSlot,
|
|
RDY_pipelineResp_getSlot,
|
|
|
|
pipelineResp_setResult_n,
|
|
pipelineResp_setResult_r,
|
|
EN_pipelineResp_setResult,
|
|
RDY_pipelineResp_setResult,
|
|
|
|
pipelineResp_setStateSlot_n,
|
|
pipelineResp_setStateSlot_state,
|
|
pipelineResp_setStateSlot_slot,
|
|
EN_pipelineResp_setStateSlot,
|
|
RDY_pipelineResp_setStateSlot,
|
|
|
|
pipelineResp_getSucc_n,
|
|
pipelineResp_getSucc,
|
|
RDY_pipelineResp_getSucc,
|
|
|
|
pipelineResp_setSucc_n,
|
|
pipelineResp_setSucc_succ,
|
|
EN_pipelineResp_setSucc,
|
|
RDY_pipelineResp_setSucc,
|
|
|
|
pipelineResp_searchEndOfChain_addr,
|
|
pipelineResp_searchEndOfChain,
|
|
RDY_pipelineResp_searchEndOfChain,
|
|
|
|
emptyForFlush,
|
|
RDY_emptyForFlush,
|
|
|
|
EN_stuck_get,
|
|
stuck_get,
|
|
RDY_stuck_get);
|
|
input CLK;
|
|
input RST_N;
|
|
|
|
// actionvalue method getEmptyEntryInit
|
|
input [63 : 0] getEmptyEntryInit_r;
|
|
input EN_getEmptyEntryInit;
|
|
output [2 : 0] getEmptyEntryInit;
|
|
output RDY_getEmptyEntryInit;
|
|
|
|
// action method sendRsToC_releaseEntry
|
|
input [2 : 0] sendRsToC_releaseEntry_n;
|
|
input EN_sendRsToC_releaseEntry;
|
|
output RDY_sendRsToC_releaseEntry;
|
|
|
|
// value method sendRsToC_getResult
|
|
input [2 : 0] sendRsToC_getResult_n;
|
|
output [66 : 0] sendRsToC_getResult;
|
|
output RDY_sendRsToC_getResult;
|
|
|
|
// value method sendRsToP_cRq_getRq
|
|
input [2 : 0] sendRsToP_cRq_getRq_n;
|
|
output [63 : 0] sendRsToP_cRq_getRq;
|
|
output RDY_sendRsToP_cRq_getRq;
|
|
|
|
// value method sendRsToP_cRq_getSlot
|
|
input [2 : 0] sendRsToP_cRq_getSlot_n;
|
|
output [55 : 0] sendRsToP_cRq_getSlot;
|
|
output RDY_sendRsToP_cRq_getSlot;
|
|
|
|
// value method sendRqToP_getRq
|
|
input [2 : 0] sendRqToP_getRq_n;
|
|
output [63 : 0] sendRqToP_getRq;
|
|
output RDY_sendRqToP_getRq;
|
|
|
|
// value method sendRqToP_getSlot
|
|
input [2 : 0] sendRqToP_getSlot_n;
|
|
output [55 : 0] sendRqToP_getSlot;
|
|
output RDY_sendRqToP_getSlot;
|
|
|
|
// value method pipelineResp_getState
|
|
input [2 : 0] pipelineResp_getState_n;
|
|
output [2 : 0] pipelineResp_getState;
|
|
output RDY_pipelineResp_getState;
|
|
|
|
// value method pipelineResp_getRq
|
|
input [2 : 0] pipelineResp_getRq_n;
|
|
output [63 : 0] pipelineResp_getRq;
|
|
output RDY_pipelineResp_getRq;
|
|
|
|
// value method pipelineResp_getSlot
|
|
input [2 : 0] pipelineResp_getSlot_n;
|
|
output [55 : 0] pipelineResp_getSlot;
|
|
output RDY_pipelineResp_getSlot;
|
|
|
|
// action method pipelineResp_setResult
|
|
input [2 : 0] pipelineResp_setResult_n;
|
|
input [65 : 0] pipelineResp_setResult_r;
|
|
input EN_pipelineResp_setResult;
|
|
output RDY_pipelineResp_setResult;
|
|
|
|
// action method pipelineResp_setStateSlot
|
|
input [2 : 0] pipelineResp_setStateSlot_n;
|
|
input [2 : 0] pipelineResp_setStateSlot_state;
|
|
input [55 : 0] pipelineResp_setStateSlot_slot;
|
|
input EN_pipelineResp_setStateSlot;
|
|
output RDY_pipelineResp_setStateSlot;
|
|
|
|
// value method pipelineResp_getSucc
|
|
input [2 : 0] pipelineResp_getSucc_n;
|
|
output [3 : 0] pipelineResp_getSucc;
|
|
output RDY_pipelineResp_getSucc;
|
|
|
|
// action method pipelineResp_setSucc
|
|
input [2 : 0] pipelineResp_setSucc_n;
|
|
input [3 : 0] pipelineResp_setSucc_succ;
|
|
input EN_pipelineResp_setSucc;
|
|
output RDY_pipelineResp_setSucc;
|
|
|
|
// value method pipelineResp_searchEndOfChain
|
|
input [63 : 0] pipelineResp_searchEndOfChain_addr;
|
|
output [3 : 0] pipelineResp_searchEndOfChain;
|
|
output RDY_pipelineResp_searchEndOfChain;
|
|
|
|
// value method emptyForFlush
|
|
output emptyForFlush;
|
|
output RDY_emptyForFlush;
|
|
|
|
// actionvalue method stuck_get
|
|
input EN_stuck_get;
|
|
output [67 : 0] stuck_get;
|
|
output RDY_stuck_get;
|
|
|
|
// signals for module outputs
|
|
reg [63 : 0] pipelineResp_getRq, sendRqToP_getRq, sendRsToP_cRq_getRq;
|
|
reg [2 : 0] pipelineResp_getState;
|
|
wire [67 : 0] stuck_get;
|
|
wire [66 : 0] sendRsToC_getResult;
|
|
wire [55 : 0] pipelineResp_getSlot,
|
|
sendRqToP_getSlot,
|
|
sendRsToP_cRq_getSlot;
|
|
wire [3 : 0] pipelineResp_getSucc, pipelineResp_searchEndOfChain;
|
|
wire [2 : 0] getEmptyEntryInit;
|
|
wire RDY_emptyForFlush,
|
|
RDY_getEmptyEntryInit,
|
|
RDY_pipelineResp_getRq,
|
|
RDY_pipelineResp_getSlot,
|
|
RDY_pipelineResp_getState,
|
|
RDY_pipelineResp_getSucc,
|
|
RDY_pipelineResp_searchEndOfChain,
|
|
RDY_pipelineResp_setResult,
|
|
RDY_pipelineResp_setStateSlot,
|
|
RDY_pipelineResp_setSucc,
|
|
RDY_sendRqToP_getRq,
|
|
RDY_sendRqToP_getSlot,
|
|
RDY_sendRsToC_getResult,
|
|
RDY_sendRsToC_releaseEntry,
|
|
RDY_sendRsToP_cRq_getRq,
|
|
RDY_sendRsToP_cRq_getSlot,
|
|
RDY_stuck_get,
|
|
emptyForFlush;
|
|
|
|
// inlined wires
|
|
wire [66 : 0] m_m_resultVec_0_lat_0$wget;
|
|
wire m_m_resultVec_0_lat_0$whas,
|
|
m_m_resultVec_1_lat_0$whas,
|
|
m_m_resultVec_2_lat_0$whas,
|
|
m_m_resultVec_3_lat_0$whas,
|
|
m_m_resultVec_4_lat_0$whas,
|
|
m_m_resultVec_5_lat_0$whas,
|
|
m_m_resultVec_6_lat_0$whas,
|
|
m_m_resultVec_7_lat_0$whas,
|
|
m_m_stateVec_0_lat_0$whas,
|
|
m_m_stateVec_0_lat_1$whas,
|
|
m_m_stateVec_0_lat_2$whas,
|
|
m_m_stateVec_1_lat_0$whas,
|
|
m_m_stateVec_1_lat_1$whas,
|
|
m_m_stateVec_1_lat_2$whas,
|
|
m_m_stateVec_2_lat_0$whas,
|
|
m_m_stateVec_2_lat_1$whas,
|
|
m_m_stateVec_2_lat_2$whas,
|
|
m_m_stateVec_3_lat_0$whas,
|
|
m_m_stateVec_3_lat_1$whas,
|
|
m_m_stateVec_3_lat_2$whas,
|
|
m_m_stateVec_4_dummy_1_0$wget,
|
|
m_m_stateVec_4_lat_1$whas,
|
|
m_m_stateVec_4_lat_2$whas,
|
|
m_m_stateVec_5_lat_0$whas,
|
|
m_m_stateVec_5_lat_1$whas,
|
|
m_m_stateVec_5_lat_2$whas,
|
|
m_m_stateVec_6_lat_0$whas,
|
|
m_m_stateVec_6_lat_1$whas,
|
|
m_m_stateVec_6_lat_2$whas,
|
|
m_m_stateVec_7_lat_0$whas,
|
|
m_m_stateVec_7_lat_1$whas,
|
|
m_m_stateVec_7_lat_2$whas,
|
|
m_m_succValidVec_0_lat_0$whas,
|
|
m_m_succValidVec_1_lat_0$whas,
|
|
m_m_succValidVec_2_lat_0$whas,
|
|
m_m_succValidVec_3_lat_0$whas,
|
|
m_m_succValidVec_4_lat_0$whas,
|
|
m_m_succValidVec_5_lat_0$whas,
|
|
m_m_succValidVec_6_lat_0$whas,
|
|
m_m_succValidVec_7_lat_0$whas;
|
|
|
|
// register m_m_initIdx
|
|
reg [2 : 0] m_m_initIdx;
|
|
wire [2 : 0] m_m_initIdx$D_IN;
|
|
wire m_m_initIdx$EN;
|
|
|
|
// register m_m_inited
|
|
reg m_m_inited;
|
|
wire m_m_inited$D_IN, m_m_inited$EN;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
reg [63 : 0] m_m_reqVec_0_rl;
|
|
wire [63 : 0] m_m_reqVec_0_rl$D_IN;
|
|
wire m_m_reqVec_0_rl$EN;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
reg [63 : 0] m_m_reqVec_1_rl;
|
|
wire [63 : 0] m_m_reqVec_1_rl$D_IN;
|
|
wire m_m_reqVec_1_rl$EN;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
reg [63 : 0] m_m_reqVec_2_rl;
|
|
wire [63 : 0] m_m_reqVec_2_rl$D_IN;
|
|
wire m_m_reqVec_2_rl$EN;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
reg [63 : 0] m_m_reqVec_3_rl;
|
|
wire [63 : 0] m_m_reqVec_3_rl$D_IN;
|
|
wire m_m_reqVec_3_rl$EN;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
reg [63 : 0] m_m_reqVec_4_rl;
|
|
wire [63 : 0] m_m_reqVec_4_rl$D_IN;
|
|
wire m_m_reqVec_4_rl$EN;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
reg [63 : 0] m_m_reqVec_5_rl;
|
|
wire [63 : 0] m_m_reqVec_5_rl$D_IN;
|
|
wire m_m_reqVec_5_rl$EN;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
reg [63 : 0] m_m_reqVec_6_rl;
|
|
wire [63 : 0] m_m_reqVec_6_rl$D_IN;
|
|
wire m_m_reqVec_6_rl$EN;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
reg [63 : 0] m_m_reqVec_7_rl;
|
|
wire [63 : 0] m_m_reqVec_7_rl$D_IN;
|
|
wire m_m_reqVec_7_rl$EN;
|
|
|
|
// register m_m_resultVec_0_rl
|
|
reg [66 : 0] m_m_resultVec_0_rl;
|
|
wire [66 : 0] m_m_resultVec_0_rl$D_IN;
|
|
wire m_m_resultVec_0_rl$EN;
|
|
|
|
// register m_m_resultVec_1_rl
|
|
reg [66 : 0] m_m_resultVec_1_rl;
|
|
wire [66 : 0] m_m_resultVec_1_rl$D_IN;
|
|
wire m_m_resultVec_1_rl$EN;
|
|
|
|
// register m_m_resultVec_2_rl
|
|
reg [66 : 0] m_m_resultVec_2_rl;
|
|
wire [66 : 0] m_m_resultVec_2_rl$D_IN;
|
|
wire m_m_resultVec_2_rl$EN;
|
|
|
|
// register m_m_resultVec_3_rl
|
|
reg [66 : 0] m_m_resultVec_3_rl;
|
|
wire [66 : 0] m_m_resultVec_3_rl$D_IN;
|
|
wire m_m_resultVec_3_rl$EN;
|
|
|
|
// register m_m_resultVec_4_rl
|
|
reg [66 : 0] m_m_resultVec_4_rl;
|
|
wire [66 : 0] m_m_resultVec_4_rl$D_IN;
|
|
wire m_m_resultVec_4_rl$EN;
|
|
|
|
// register m_m_resultVec_5_rl
|
|
reg [66 : 0] m_m_resultVec_5_rl;
|
|
wire [66 : 0] m_m_resultVec_5_rl$D_IN;
|
|
wire m_m_resultVec_5_rl$EN;
|
|
|
|
// register m_m_resultVec_6_rl
|
|
reg [66 : 0] m_m_resultVec_6_rl;
|
|
wire [66 : 0] m_m_resultVec_6_rl$D_IN;
|
|
wire m_m_resultVec_6_rl$EN;
|
|
|
|
// register m_m_resultVec_7_rl
|
|
reg [66 : 0] m_m_resultVec_7_rl;
|
|
wire [66 : 0] m_m_resultVec_7_rl$D_IN;
|
|
wire m_m_resultVec_7_rl$EN;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
reg [55 : 0] m_m_slotVec_0_rl;
|
|
wire [55 : 0] m_m_slotVec_0_rl$D_IN;
|
|
wire m_m_slotVec_0_rl$EN;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
reg [55 : 0] m_m_slotVec_1_rl;
|
|
wire [55 : 0] m_m_slotVec_1_rl$D_IN;
|
|
wire m_m_slotVec_1_rl$EN;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
reg [55 : 0] m_m_slotVec_2_rl;
|
|
wire [55 : 0] m_m_slotVec_2_rl$D_IN;
|
|
wire m_m_slotVec_2_rl$EN;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
reg [55 : 0] m_m_slotVec_3_rl;
|
|
wire [55 : 0] m_m_slotVec_3_rl$D_IN;
|
|
wire m_m_slotVec_3_rl$EN;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
reg [55 : 0] m_m_slotVec_4_rl;
|
|
wire [55 : 0] m_m_slotVec_4_rl$D_IN;
|
|
wire m_m_slotVec_4_rl$EN;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
reg [55 : 0] m_m_slotVec_5_rl;
|
|
wire [55 : 0] m_m_slotVec_5_rl$D_IN;
|
|
wire m_m_slotVec_5_rl$EN;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
reg [55 : 0] m_m_slotVec_6_rl;
|
|
wire [55 : 0] m_m_slotVec_6_rl$D_IN;
|
|
wire m_m_slotVec_6_rl$EN;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
reg [55 : 0] m_m_slotVec_7_rl;
|
|
wire [55 : 0] m_m_slotVec_7_rl$D_IN;
|
|
wire m_m_slotVec_7_rl$EN;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
reg [2 : 0] m_m_stateVec_0_rl;
|
|
wire [2 : 0] m_m_stateVec_0_rl$D_IN;
|
|
wire m_m_stateVec_0_rl$EN;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
reg [2 : 0] m_m_stateVec_1_rl;
|
|
wire [2 : 0] m_m_stateVec_1_rl$D_IN;
|
|
wire m_m_stateVec_1_rl$EN;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
reg [2 : 0] m_m_stateVec_2_rl;
|
|
wire [2 : 0] m_m_stateVec_2_rl$D_IN;
|
|
wire m_m_stateVec_2_rl$EN;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
reg [2 : 0] m_m_stateVec_3_rl;
|
|
wire [2 : 0] m_m_stateVec_3_rl$D_IN;
|
|
wire m_m_stateVec_3_rl$EN;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
reg [2 : 0] m_m_stateVec_4_rl;
|
|
wire [2 : 0] m_m_stateVec_4_rl$D_IN;
|
|
wire m_m_stateVec_4_rl$EN;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
reg [2 : 0] m_m_stateVec_5_rl;
|
|
wire [2 : 0] m_m_stateVec_5_rl$D_IN;
|
|
wire m_m_stateVec_5_rl$EN;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
reg [2 : 0] m_m_stateVec_6_rl;
|
|
wire [2 : 0] m_m_stateVec_6_rl$D_IN;
|
|
wire m_m_stateVec_6_rl$EN;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
reg [2 : 0] m_m_stateVec_7_rl;
|
|
wire [2 : 0] m_m_stateVec_7_rl$D_IN;
|
|
wire m_m_stateVec_7_rl$EN;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
reg m_m_succValidVec_0_rl;
|
|
wire m_m_succValidVec_0_rl$D_IN, m_m_succValidVec_0_rl$EN;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
reg m_m_succValidVec_1_rl;
|
|
wire m_m_succValidVec_1_rl$D_IN, m_m_succValidVec_1_rl$EN;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
reg m_m_succValidVec_2_rl;
|
|
wire m_m_succValidVec_2_rl$D_IN, m_m_succValidVec_2_rl$EN;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
reg m_m_succValidVec_3_rl;
|
|
wire m_m_succValidVec_3_rl$D_IN, m_m_succValidVec_3_rl$EN;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
reg m_m_succValidVec_4_rl;
|
|
wire m_m_succValidVec_4_rl$D_IN, m_m_succValidVec_4_rl$EN;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
reg m_m_succValidVec_5_rl;
|
|
wire m_m_succValidVec_5_rl$D_IN, m_m_succValidVec_5_rl$EN;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
reg m_m_succValidVec_6_rl;
|
|
wire m_m_succValidVec_6_rl$D_IN, m_m_succValidVec_6_rl$EN;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
reg m_m_succValidVec_7_rl;
|
|
wire m_m_succValidVec_7_rl$D_IN, m_m_succValidVec_7_rl$EN;
|
|
|
|
// ports of submodule m_m_emptyEntryQ
|
|
wire [2 : 0] m_m_emptyEntryQ$D_IN, m_m_emptyEntryQ$D_OUT;
|
|
wire m_m_emptyEntryQ$CLR,
|
|
m_m_emptyEntryQ$DEQ,
|
|
m_m_emptyEntryQ$EMPTY_N,
|
|
m_m_emptyEntryQ$ENQ,
|
|
m_m_emptyEntryQ$FULL_N;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_0
|
|
wire m_m_reqVec_0_dummy2_0$D_IN,
|
|
m_m_reqVec_0_dummy2_0$EN,
|
|
m_m_reqVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_1
|
|
wire m_m_reqVec_0_dummy2_1$D_IN,
|
|
m_m_reqVec_0_dummy2_1$EN,
|
|
m_m_reqVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_2
|
|
wire m_m_reqVec_0_dummy2_2$D_IN,
|
|
m_m_reqVec_0_dummy2_2$EN,
|
|
m_m_reqVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_0
|
|
wire m_m_reqVec_1_dummy2_0$D_IN,
|
|
m_m_reqVec_1_dummy2_0$EN,
|
|
m_m_reqVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_1
|
|
wire m_m_reqVec_1_dummy2_1$D_IN,
|
|
m_m_reqVec_1_dummy2_1$EN,
|
|
m_m_reqVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_2
|
|
wire m_m_reqVec_1_dummy2_2$D_IN,
|
|
m_m_reqVec_1_dummy2_2$EN,
|
|
m_m_reqVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_0
|
|
wire m_m_reqVec_2_dummy2_0$D_IN,
|
|
m_m_reqVec_2_dummy2_0$EN,
|
|
m_m_reqVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_1
|
|
wire m_m_reqVec_2_dummy2_1$D_IN,
|
|
m_m_reqVec_2_dummy2_1$EN,
|
|
m_m_reqVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_2
|
|
wire m_m_reqVec_2_dummy2_2$D_IN,
|
|
m_m_reqVec_2_dummy2_2$EN,
|
|
m_m_reqVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_0
|
|
wire m_m_reqVec_3_dummy2_0$D_IN,
|
|
m_m_reqVec_3_dummy2_0$EN,
|
|
m_m_reqVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_1
|
|
wire m_m_reqVec_3_dummy2_1$D_IN,
|
|
m_m_reqVec_3_dummy2_1$EN,
|
|
m_m_reqVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_2
|
|
wire m_m_reqVec_3_dummy2_2$D_IN,
|
|
m_m_reqVec_3_dummy2_2$EN,
|
|
m_m_reqVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_4_dummy2_0
|
|
wire m_m_reqVec_4_dummy2_0$D_IN,
|
|
m_m_reqVec_4_dummy2_0$EN,
|
|
m_m_reqVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_4_dummy2_1
|
|
wire m_m_reqVec_4_dummy2_1$D_IN,
|
|
m_m_reqVec_4_dummy2_1$EN,
|
|
m_m_reqVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_4_dummy2_2
|
|
wire m_m_reqVec_4_dummy2_2$D_IN,
|
|
m_m_reqVec_4_dummy2_2$EN,
|
|
m_m_reqVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_5_dummy2_0
|
|
wire m_m_reqVec_5_dummy2_0$D_IN,
|
|
m_m_reqVec_5_dummy2_0$EN,
|
|
m_m_reqVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_5_dummy2_1
|
|
wire m_m_reqVec_5_dummy2_1$D_IN,
|
|
m_m_reqVec_5_dummy2_1$EN,
|
|
m_m_reqVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_5_dummy2_2
|
|
wire m_m_reqVec_5_dummy2_2$D_IN,
|
|
m_m_reqVec_5_dummy2_2$EN,
|
|
m_m_reqVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_6_dummy2_0
|
|
wire m_m_reqVec_6_dummy2_0$D_IN,
|
|
m_m_reqVec_6_dummy2_0$EN,
|
|
m_m_reqVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_6_dummy2_1
|
|
wire m_m_reqVec_6_dummy2_1$D_IN,
|
|
m_m_reqVec_6_dummy2_1$EN,
|
|
m_m_reqVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_6_dummy2_2
|
|
wire m_m_reqVec_6_dummy2_2$D_IN,
|
|
m_m_reqVec_6_dummy2_2$EN,
|
|
m_m_reqVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_7_dummy2_0
|
|
wire m_m_reqVec_7_dummy2_0$D_IN,
|
|
m_m_reqVec_7_dummy2_0$EN,
|
|
m_m_reqVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_7_dummy2_1
|
|
wire m_m_reqVec_7_dummy2_1$D_IN,
|
|
m_m_reqVec_7_dummy2_1$EN,
|
|
m_m_reqVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_7_dummy2_2
|
|
wire m_m_reqVec_7_dummy2_2$D_IN,
|
|
m_m_reqVec_7_dummy2_2$EN,
|
|
m_m_reqVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_0_dummy2_0
|
|
wire m_m_resultVec_0_dummy2_0$D_IN, m_m_resultVec_0_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_0_dummy2_1
|
|
wire m_m_resultVec_0_dummy2_1$D_IN,
|
|
m_m_resultVec_0_dummy2_1$EN,
|
|
m_m_resultVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_0_dummy2_2
|
|
wire m_m_resultVec_0_dummy2_2$D_IN,
|
|
m_m_resultVec_0_dummy2_2$EN,
|
|
m_m_resultVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_1_dummy2_0
|
|
wire m_m_resultVec_1_dummy2_0$D_IN, m_m_resultVec_1_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_1_dummy2_1
|
|
wire m_m_resultVec_1_dummy2_1$D_IN,
|
|
m_m_resultVec_1_dummy2_1$EN,
|
|
m_m_resultVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_1_dummy2_2
|
|
wire m_m_resultVec_1_dummy2_2$D_IN,
|
|
m_m_resultVec_1_dummy2_2$EN,
|
|
m_m_resultVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_2_dummy2_0
|
|
wire m_m_resultVec_2_dummy2_0$D_IN, m_m_resultVec_2_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_2_dummy2_1
|
|
wire m_m_resultVec_2_dummy2_1$D_IN,
|
|
m_m_resultVec_2_dummy2_1$EN,
|
|
m_m_resultVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_2_dummy2_2
|
|
wire m_m_resultVec_2_dummy2_2$D_IN,
|
|
m_m_resultVec_2_dummy2_2$EN,
|
|
m_m_resultVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_3_dummy2_0
|
|
wire m_m_resultVec_3_dummy2_0$D_IN, m_m_resultVec_3_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_3_dummy2_1
|
|
wire m_m_resultVec_3_dummy2_1$D_IN,
|
|
m_m_resultVec_3_dummy2_1$EN,
|
|
m_m_resultVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_3_dummy2_2
|
|
wire m_m_resultVec_3_dummy2_2$D_IN,
|
|
m_m_resultVec_3_dummy2_2$EN,
|
|
m_m_resultVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_4_dummy2_0
|
|
wire m_m_resultVec_4_dummy2_0$D_IN, m_m_resultVec_4_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_4_dummy2_1
|
|
wire m_m_resultVec_4_dummy2_1$D_IN,
|
|
m_m_resultVec_4_dummy2_1$EN,
|
|
m_m_resultVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_4_dummy2_2
|
|
wire m_m_resultVec_4_dummy2_2$D_IN,
|
|
m_m_resultVec_4_dummy2_2$EN,
|
|
m_m_resultVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_5_dummy2_0
|
|
wire m_m_resultVec_5_dummy2_0$D_IN, m_m_resultVec_5_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_5_dummy2_1
|
|
wire m_m_resultVec_5_dummy2_1$D_IN,
|
|
m_m_resultVec_5_dummy2_1$EN,
|
|
m_m_resultVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_5_dummy2_2
|
|
wire m_m_resultVec_5_dummy2_2$D_IN,
|
|
m_m_resultVec_5_dummy2_2$EN,
|
|
m_m_resultVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_6_dummy2_0
|
|
wire m_m_resultVec_6_dummy2_0$D_IN, m_m_resultVec_6_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_6_dummy2_1
|
|
wire m_m_resultVec_6_dummy2_1$D_IN,
|
|
m_m_resultVec_6_dummy2_1$EN,
|
|
m_m_resultVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_6_dummy2_2
|
|
wire m_m_resultVec_6_dummy2_2$D_IN,
|
|
m_m_resultVec_6_dummy2_2$EN,
|
|
m_m_resultVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_7_dummy2_0
|
|
wire m_m_resultVec_7_dummy2_0$D_IN, m_m_resultVec_7_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_resultVec_7_dummy2_1
|
|
wire m_m_resultVec_7_dummy2_1$D_IN,
|
|
m_m_resultVec_7_dummy2_1$EN,
|
|
m_m_resultVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_resultVec_7_dummy2_2
|
|
wire m_m_resultVec_7_dummy2_2$D_IN,
|
|
m_m_resultVec_7_dummy2_2$EN,
|
|
m_m_resultVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_0_dummy2_0
|
|
wire m_m_slotVec_0_dummy2_0$D_IN,
|
|
m_m_slotVec_0_dummy2_0$EN,
|
|
m_m_slotVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_0_dummy2_1
|
|
wire m_m_slotVec_0_dummy2_1$D_IN,
|
|
m_m_slotVec_0_dummy2_1$EN,
|
|
m_m_slotVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_0_dummy2_2
|
|
wire m_m_slotVec_0_dummy2_2$D_IN,
|
|
m_m_slotVec_0_dummy2_2$EN,
|
|
m_m_slotVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_1_dummy2_0
|
|
wire m_m_slotVec_1_dummy2_0$D_IN,
|
|
m_m_slotVec_1_dummy2_0$EN,
|
|
m_m_slotVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_1_dummy2_1
|
|
wire m_m_slotVec_1_dummy2_1$D_IN,
|
|
m_m_slotVec_1_dummy2_1$EN,
|
|
m_m_slotVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_1_dummy2_2
|
|
wire m_m_slotVec_1_dummy2_2$D_IN,
|
|
m_m_slotVec_1_dummy2_2$EN,
|
|
m_m_slotVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_2_dummy2_0
|
|
wire m_m_slotVec_2_dummy2_0$D_IN,
|
|
m_m_slotVec_2_dummy2_0$EN,
|
|
m_m_slotVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_2_dummy2_1
|
|
wire m_m_slotVec_2_dummy2_1$D_IN,
|
|
m_m_slotVec_2_dummy2_1$EN,
|
|
m_m_slotVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_2_dummy2_2
|
|
wire m_m_slotVec_2_dummy2_2$D_IN,
|
|
m_m_slotVec_2_dummy2_2$EN,
|
|
m_m_slotVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_3_dummy2_0
|
|
wire m_m_slotVec_3_dummy2_0$D_IN,
|
|
m_m_slotVec_3_dummy2_0$EN,
|
|
m_m_slotVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_3_dummy2_1
|
|
wire m_m_slotVec_3_dummy2_1$D_IN,
|
|
m_m_slotVec_3_dummy2_1$EN,
|
|
m_m_slotVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_3_dummy2_2
|
|
wire m_m_slotVec_3_dummy2_2$D_IN,
|
|
m_m_slotVec_3_dummy2_2$EN,
|
|
m_m_slotVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_4_dummy2_0
|
|
wire m_m_slotVec_4_dummy2_0$D_IN,
|
|
m_m_slotVec_4_dummy2_0$EN,
|
|
m_m_slotVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_4_dummy2_1
|
|
wire m_m_slotVec_4_dummy2_1$D_IN,
|
|
m_m_slotVec_4_dummy2_1$EN,
|
|
m_m_slotVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_4_dummy2_2
|
|
wire m_m_slotVec_4_dummy2_2$D_IN,
|
|
m_m_slotVec_4_dummy2_2$EN,
|
|
m_m_slotVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_5_dummy2_0
|
|
wire m_m_slotVec_5_dummy2_0$D_IN,
|
|
m_m_slotVec_5_dummy2_0$EN,
|
|
m_m_slotVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_5_dummy2_1
|
|
wire m_m_slotVec_5_dummy2_1$D_IN,
|
|
m_m_slotVec_5_dummy2_1$EN,
|
|
m_m_slotVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_5_dummy2_2
|
|
wire m_m_slotVec_5_dummy2_2$D_IN,
|
|
m_m_slotVec_5_dummy2_2$EN,
|
|
m_m_slotVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_6_dummy2_0
|
|
wire m_m_slotVec_6_dummy2_0$D_IN,
|
|
m_m_slotVec_6_dummy2_0$EN,
|
|
m_m_slotVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_6_dummy2_1
|
|
wire m_m_slotVec_6_dummy2_1$D_IN,
|
|
m_m_slotVec_6_dummy2_1$EN,
|
|
m_m_slotVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_6_dummy2_2
|
|
wire m_m_slotVec_6_dummy2_2$D_IN,
|
|
m_m_slotVec_6_dummy2_2$EN,
|
|
m_m_slotVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_7_dummy2_0
|
|
wire m_m_slotVec_7_dummy2_0$D_IN,
|
|
m_m_slotVec_7_dummy2_0$EN,
|
|
m_m_slotVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_7_dummy2_1
|
|
wire m_m_slotVec_7_dummy2_1$D_IN,
|
|
m_m_slotVec_7_dummy2_1$EN,
|
|
m_m_slotVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_slotVec_7_dummy2_2
|
|
wire m_m_slotVec_7_dummy2_2$D_IN,
|
|
m_m_slotVec_7_dummy2_2$EN,
|
|
m_m_slotVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_0
|
|
wire m_m_stateVec_0_dummy2_0$D_IN,
|
|
m_m_stateVec_0_dummy2_0$EN,
|
|
m_m_stateVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_1
|
|
wire m_m_stateVec_0_dummy2_1$D_IN,
|
|
m_m_stateVec_0_dummy2_1$EN,
|
|
m_m_stateVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_2
|
|
wire m_m_stateVec_0_dummy2_2$D_IN,
|
|
m_m_stateVec_0_dummy2_2$EN,
|
|
m_m_stateVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_0
|
|
wire m_m_stateVec_1_dummy2_0$D_IN,
|
|
m_m_stateVec_1_dummy2_0$EN,
|
|
m_m_stateVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_1
|
|
wire m_m_stateVec_1_dummy2_1$D_IN,
|
|
m_m_stateVec_1_dummy2_1$EN,
|
|
m_m_stateVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_2
|
|
wire m_m_stateVec_1_dummy2_2$D_IN,
|
|
m_m_stateVec_1_dummy2_2$EN,
|
|
m_m_stateVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_0
|
|
wire m_m_stateVec_2_dummy2_0$D_IN,
|
|
m_m_stateVec_2_dummy2_0$EN,
|
|
m_m_stateVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_1
|
|
wire m_m_stateVec_2_dummy2_1$D_IN,
|
|
m_m_stateVec_2_dummy2_1$EN,
|
|
m_m_stateVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_2
|
|
wire m_m_stateVec_2_dummy2_2$D_IN,
|
|
m_m_stateVec_2_dummy2_2$EN,
|
|
m_m_stateVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_0
|
|
wire m_m_stateVec_3_dummy2_0$D_IN,
|
|
m_m_stateVec_3_dummy2_0$EN,
|
|
m_m_stateVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_1
|
|
wire m_m_stateVec_3_dummy2_1$D_IN,
|
|
m_m_stateVec_3_dummy2_1$EN,
|
|
m_m_stateVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_2
|
|
wire m_m_stateVec_3_dummy2_2$D_IN,
|
|
m_m_stateVec_3_dummy2_2$EN,
|
|
m_m_stateVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_4_dummy2_0
|
|
wire m_m_stateVec_4_dummy2_0$D_IN,
|
|
m_m_stateVec_4_dummy2_0$EN,
|
|
m_m_stateVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_4_dummy2_1
|
|
wire m_m_stateVec_4_dummy2_1$D_IN,
|
|
m_m_stateVec_4_dummy2_1$EN,
|
|
m_m_stateVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_4_dummy2_2
|
|
wire m_m_stateVec_4_dummy2_2$D_IN,
|
|
m_m_stateVec_4_dummy2_2$EN,
|
|
m_m_stateVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_5_dummy2_0
|
|
wire m_m_stateVec_5_dummy2_0$D_IN,
|
|
m_m_stateVec_5_dummy2_0$EN,
|
|
m_m_stateVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_5_dummy2_1
|
|
wire m_m_stateVec_5_dummy2_1$D_IN,
|
|
m_m_stateVec_5_dummy2_1$EN,
|
|
m_m_stateVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_5_dummy2_2
|
|
wire m_m_stateVec_5_dummy2_2$D_IN,
|
|
m_m_stateVec_5_dummy2_2$EN,
|
|
m_m_stateVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_6_dummy2_0
|
|
wire m_m_stateVec_6_dummy2_0$D_IN,
|
|
m_m_stateVec_6_dummy2_0$EN,
|
|
m_m_stateVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_6_dummy2_1
|
|
wire m_m_stateVec_6_dummy2_1$D_IN,
|
|
m_m_stateVec_6_dummy2_1$EN,
|
|
m_m_stateVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_6_dummy2_2
|
|
wire m_m_stateVec_6_dummy2_2$D_IN,
|
|
m_m_stateVec_6_dummy2_2$EN,
|
|
m_m_stateVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_7_dummy2_0
|
|
wire m_m_stateVec_7_dummy2_0$D_IN,
|
|
m_m_stateVec_7_dummy2_0$EN,
|
|
m_m_stateVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_7_dummy2_1
|
|
wire m_m_stateVec_7_dummy2_1$D_IN,
|
|
m_m_stateVec_7_dummy2_1$EN,
|
|
m_m_stateVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_7_dummy2_2
|
|
wire m_m_stateVec_7_dummy2_2$D_IN,
|
|
m_m_stateVec_7_dummy2_2$EN,
|
|
m_m_stateVec_7_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succFile
|
|
wire [2 : 0] m_m_succFile$ADDR_1,
|
|
m_m_succFile$ADDR_2,
|
|
m_m_succFile$ADDR_3,
|
|
m_m_succFile$ADDR_4,
|
|
m_m_succFile$ADDR_5,
|
|
m_m_succFile$ADDR_IN,
|
|
m_m_succFile$D_IN,
|
|
m_m_succFile$D_OUT_1;
|
|
wire m_m_succFile$WE;
|
|
|
|
// ports of submodule m_m_succValidVec_0_dummy2_0
|
|
wire m_m_succValidVec_0_dummy2_0$D_IN,
|
|
m_m_succValidVec_0_dummy2_0$EN,
|
|
m_m_succValidVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_0_dummy2_1
|
|
wire m_m_succValidVec_0_dummy2_1$D_IN,
|
|
m_m_succValidVec_0_dummy2_1$EN,
|
|
m_m_succValidVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_0_dummy2_2
|
|
wire m_m_succValidVec_0_dummy2_2$D_IN,
|
|
m_m_succValidVec_0_dummy2_2$EN,
|
|
m_m_succValidVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_1_dummy2_0
|
|
wire m_m_succValidVec_1_dummy2_0$D_IN,
|
|
m_m_succValidVec_1_dummy2_0$EN,
|
|
m_m_succValidVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_1_dummy2_1
|
|
wire m_m_succValidVec_1_dummy2_1$D_IN,
|
|
m_m_succValidVec_1_dummy2_1$EN,
|
|
m_m_succValidVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_1_dummy2_2
|
|
wire m_m_succValidVec_1_dummy2_2$D_IN,
|
|
m_m_succValidVec_1_dummy2_2$EN,
|
|
m_m_succValidVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_2_dummy2_0
|
|
wire m_m_succValidVec_2_dummy2_0$D_IN,
|
|
m_m_succValidVec_2_dummy2_0$EN,
|
|
m_m_succValidVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_2_dummy2_1
|
|
wire m_m_succValidVec_2_dummy2_1$D_IN,
|
|
m_m_succValidVec_2_dummy2_1$EN,
|
|
m_m_succValidVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_2_dummy2_2
|
|
wire m_m_succValidVec_2_dummy2_2$D_IN,
|
|
m_m_succValidVec_2_dummy2_2$EN,
|
|
m_m_succValidVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_3_dummy2_0
|
|
wire m_m_succValidVec_3_dummy2_0$D_IN,
|
|
m_m_succValidVec_3_dummy2_0$EN,
|
|
m_m_succValidVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_3_dummy2_1
|
|
wire m_m_succValidVec_3_dummy2_1$D_IN,
|
|
m_m_succValidVec_3_dummy2_1$EN,
|
|
m_m_succValidVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_3_dummy2_2
|
|
wire m_m_succValidVec_3_dummy2_2$D_IN,
|
|
m_m_succValidVec_3_dummy2_2$EN,
|
|
m_m_succValidVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_4_dummy2_0
|
|
wire m_m_succValidVec_4_dummy2_0$D_IN,
|
|
m_m_succValidVec_4_dummy2_0$EN,
|
|
m_m_succValidVec_4_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_4_dummy2_1
|
|
wire m_m_succValidVec_4_dummy2_1$D_IN,
|
|
m_m_succValidVec_4_dummy2_1$EN,
|
|
m_m_succValidVec_4_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_4_dummy2_2
|
|
wire m_m_succValidVec_4_dummy2_2$D_IN,
|
|
m_m_succValidVec_4_dummy2_2$EN,
|
|
m_m_succValidVec_4_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_5_dummy2_0
|
|
wire m_m_succValidVec_5_dummy2_0$D_IN,
|
|
m_m_succValidVec_5_dummy2_0$EN,
|
|
m_m_succValidVec_5_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_5_dummy2_1
|
|
wire m_m_succValidVec_5_dummy2_1$D_IN,
|
|
m_m_succValidVec_5_dummy2_1$EN,
|
|
m_m_succValidVec_5_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_5_dummy2_2
|
|
wire m_m_succValidVec_5_dummy2_2$D_IN,
|
|
m_m_succValidVec_5_dummy2_2$EN,
|
|
m_m_succValidVec_5_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_6_dummy2_0
|
|
wire m_m_succValidVec_6_dummy2_0$D_IN,
|
|
m_m_succValidVec_6_dummy2_0$EN,
|
|
m_m_succValidVec_6_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_6_dummy2_1
|
|
wire m_m_succValidVec_6_dummy2_1$D_IN,
|
|
m_m_succValidVec_6_dummy2_1$EN,
|
|
m_m_succValidVec_6_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_6_dummy2_2
|
|
wire m_m_succValidVec_6_dummy2_2$D_IN,
|
|
m_m_succValidVec_6_dummy2_2$EN,
|
|
m_m_succValidVec_6_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_7_dummy2_0
|
|
wire m_m_succValidVec_7_dummy2_0$D_IN,
|
|
m_m_succValidVec_7_dummy2_0$EN,
|
|
m_m_succValidVec_7_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_7_dummy2_1
|
|
wire m_m_succValidVec_7_dummy2_1$D_IN,
|
|
m_m_succValidVec_7_dummy2_1$EN,
|
|
m_m_succValidVec_7_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_succValidVec_7_dummy2_2
|
|
wire m_m_succValidVec_7_dummy2_2$D_IN,
|
|
m_m_succValidVec_7_dummy2_2$EN,
|
|
m_m_succValidVec_7_dummy2_2$Q_OUT;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_m_initEmptyEntry,
|
|
CAN_FIRE_RL_m_m_reqVec_0_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_1_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_2_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_3_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_4_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_5_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_6_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_7_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_0_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_1_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_2_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_3_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_4_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_5_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_6_canon,
|
|
CAN_FIRE_RL_m_m_resultVec_7_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_0_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_1_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_2_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_3_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_4_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_5_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_6_canon,
|
|
CAN_FIRE_RL_m_m_slotVec_7_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_0_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_1_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_2_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_3_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_4_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_5_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_6_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_7_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_4_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_5_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_6_canon,
|
|
CAN_FIRE_RL_m_m_succValidVec_7_canon,
|
|
CAN_FIRE_getEmptyEntryInit,
|
|
CAN_FIRE_pipelineResp_setResult,
|
|
CAN_FIRE_pipelineResp_setStateSlot,
|
|
CAN_FIRE_pipelineResp_setSucc,
|
|
CAN_FIRE_sendRsToC_releaseEntry,
|
|
CAN_FIRE_stuck_get,
|
|
WILL_FIRE_RL_m_m_initEmptyEntry,
|
|
WILL_FIRE_RL_m_m_reqVec_0_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_1_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_2_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_3_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_4_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_5_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_6_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_7_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_0_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_1_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_2_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_3_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_4_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_5_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_6_canon,
|
|
WILL_FIRE_RL_m_m_resultVec_7_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_0_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_1_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_2_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_3_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_4_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_5_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_6_canon,
|
|
WILL_FIRE_RL_m_m_slotVec_7_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_0_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_1_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_2_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_3_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_4_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_5_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_6_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_7_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_4_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_5_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_6_canon,
|
|
WILL_FIRE_RL_m_m_succValidVec_7_canon,
|
|
WILL_FIRE_getEmptyEntryInit,
|
|
WILL_FIRE_pipelineResp_setResult,
|
|
WILL_FIRE_pipelineResp_setStateSlot,
|
|
WILL_FIRE_pipelineResp_setSucc,
|
|
WILL_FIRE_sendRsToC_releaseEntry,
|
|
WILL_FIRE_stuck_get;
|
|
|
|
// remaining internal signals
|
|
reg [51 : 0] x__h100325, x__h99419, x__h99547;
|
|
reg [31 : 0] SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953;
|
|
reg [2 : 0] x__h100288, x__h98662, x__h99510;
|
|
reg SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950,
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154,
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230;
|
|
wire [65 : 0] IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306,
|
|
IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374,
|
|
IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442,
|
|
IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510,
|
|
IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578,
|
|
IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646,
|
|
IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714,
|
|
IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782;
|
|
wire [63 : 0] n__read_addr__h98084,
|
|
n__read_addr__h98165,
|
|
n__read_addr__h98246,
|
|
n__read_addr__h98327,
|
|
n__read_addr__h98408,
|
|
n__read_addr__h98489,
|
|
n__read_addr__h98570,
|
|
n__read_addr__h98651;
|
|
wire [51 : 0] n__read_repTag__h98796,
|
|
n__read_repTag__h98881,
|
|
n__read_repTag__h98966,
|
|
n__read_repTag__h99051,
|
|
n__read_repTag__h99136,
|
|
n__read_repTag__h99221,
|
|
n__read_repTag__h99306,
|
|
n__read_repTag__h99391;
|
|
wire [31 : 0] IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280,
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302,
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348,
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370,
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416,
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438,
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484,
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506,
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552,
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574,
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620,
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642,
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688,
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710,
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756,
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778;
|
|
wire [2 : 0] IF_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m__ETC___d1456,
|
|
IF_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m__ETC___d1457,
|
|
IF_IF_m_m_stateVec_4_dummy2_0_read__127_AND_m__ETC___d1453,
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108,
|
|
IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9,
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114,
|
|
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19,
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120,
|
|
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29,
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126,
|
|
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39,
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132,
|
|
IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49,
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138,
|
|
IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59,
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144,
|
|
IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69,
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150,
|
|
IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79,
|
|
n__read_way__h98795,
|
|
n__read_way__h98880,
|
|
n__read_way__h98965,
|
|
n__read_way__h99050,
|
|
n__read_way__h99135,
|
|
n__read_way__h99220,
|
|
n__read_way__h99305,
|
|
n__read_way__h99390;
|
|
wire IF_m_m_reqVec_0_dummy2_0_read__57_AND_m_m_reqV_ETC___d1254,
|
|
IF_m_m_reqVec_1_dummy2_0_read__63_AND_m_m_reqV_ETC___d1273,
|
|
IF_m_m_reqVec_2_dummy2_0_read__69_AND_m_m_reqV_ETC___d1293,
|
|
IF_m_m_reqVec_3_dummy2_0_read__75_AND_m_m_reqV_ETC___d1312,
|
|
IF_m_m_reqVec_4_dummy2_0_read__81_AND_m_m_reqV_ETC___d1333,
|
|
IF_m_m_reqVec_5_dummy2_0_read__87_AND_m_m_reqV_ETC___d1352,
|
|
IF_m_m_reqVec_6_dummy2_0_read__93_AND_m_m_reqV_ETC___d1372,
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1408,
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1413,
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1464,
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1419,
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1431,
|
|
NOT_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_ETC___d1263,
|
|
NOT_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_ETC___d1403,
|
|
NOT_IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_ETC___d1282,
|
|
NOT_IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_ETC___d1302,
|
|
NOT_IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_ETC___d1321,
|
|
NOT_IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_ETC___d1342,
|
|
NOT_IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_ETC___d1361,
|
|
NOT_IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_ETC___d1381,
|
|
NOT_IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_ETC___d1400,
|
|
NOT_m_m_resultVec_0_dummy2_1_read__92_93_OR_NO_ETC___d897,
|
|
NOT_m_m_resultVec_1_dummy2_1_read__98_99_OR_NO_ETC___d903,
|
|
NOT_m_m_resultVec_2_dummy2_1_read__04_05_OR_NO_ETC___d909,
|
|
NOT_m_m_resultVec_3_dummy2_1_read__10_11_OR_NO_ETC___d915,
|
|
NOT_m_m_resultVec_4_dummy2_1_read__16_17_OR_NO_ETC___d921,
|
|
NOT_m_m_resultVec_5_dummy2_1_read__22_23_OR_NO_ETC___d927,
|
|
NOT_m_m_resultVec_6_dummy2_1_read__28_29_OR_NO_ETC___d933,
|
|
NOT_m_m_resultVec_7_dummy2_1_read__34_35_OR_NO_ETC___d939,
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083,
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085,
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087,
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089,
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091,
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093,
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095,
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097,
|
|
m_m_succValidVec_0_dummy2_0_read__181_AND_m_m__ETC___d1186,
|
|
m_m_succValidVec_1_dummy2_0_read__187_AND_m_m__ETC___d1192,
|
|
m_m_succValidVec_2_dummy2_0_read__193_AND_m_m__ETC___d1198,
|
|
m_m_succValidVec_3_dummy2_0_read__199_AND_m_m__ETC___d1204,
|
|
m_m_succValidVec_4_dummy2_0_read__205_AND_m_m__ETC___d1210,
|
|
m_m_succValidVec_5_dummy2_0_read__211_AND_m_m__ETC___d1216,
|
|
m_m_succValidVec_6_dummy2_0_read__217_AND_m_m__ETC___d1222;
|
|
|
|
// actionvalue method getEmptyEntryInit
|
|
assign getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
|
|
assign RDY_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign CAN_FIRE_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign WILL_FIRE_getEmptyEntryInit = EN_getEmptyEntryInit ;
|
|
|
|
// action method sendRsToC_releaseEntry
|
|
assign RDY_sendRsToC_releaseEntry = m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign CAN_FIRE_sendRsToC_releaseEntry =
|
|
m_m_inited && m_m_emptyEntryQ$FULL_N ;
|
|
assign WILL_FIRE_sendRsToC_releaseEntry = EN_sendRsToC_releaseEntry ;
|
|
|
|
// value method sendRsToC_getResult
|
|
assign sendRsToC_getResult =
|
|
{ !SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941,
|
|
!SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947,
|
|
!SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950,
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 } ;
|
|
assign RDY_sendRsToC_getResult = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getRq
|
|
always@(sendRsToP_cRq_getRq_n or
|
|
n__read_addr__h98084 or
|
|
n__read_addr__h98165 or
|
|
n__read_addr__h98246 or
|
|
n__read_addr__h98327 or
|
|
n__read_addr__h98408 or
|
|
n__read_addr__h98489 or
|
|
n__read_addr__h98570 or n__read_addr__h98651)
|
|
begin
|
|
case (sendRsToP_cRq_getRq_n)
|
|
3'd0: sendRsToP_cRq_getRq = n__read_addr__h98084;
|
|
3'd1: sendRsToP_cRq_getRq = n__read_addr__h98165;
|
|
3'd2: sendRsToP_cRq_getRq = n__read_addr__h98246;
|
|
3'd3: sendRsToP_cRq_getRq = n__read_addr__h98327;
|
|
3'd4: sendRsToP_cRq_getRq = n__read_addr__h98408;
|
|
3'd5: sendRsToP_cRq_getRq = n__read_addr__h98489;
|
|
3'd6: sendRsToP_cRq_getRq = n__read_addr__h98570;
|
|
3'd7: sendRsToP_cRq_getRq = n__read_addr__h98651;
|
|
endcase
|
|
end
|
|
assign RDY_sendRsToP_cRq_getRq = 1'd1 ;
|
|
|
|
// value method sendRsToP_cRq_getSlot
|
|
assign sendRsToP_cRq_getSlot =
|
|
{ x__h98662,
|
|
x__h99419,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 } ;
|
|
assign RDY_sendRsToP_cRq_getSlot = 1'd1 ;
|
|
|
|
// value method sendRqToP_getRq
|
|
always@(sendRqToP_getRq_n or
|
|
n__read_addr__h98084 or
|
|
n__read_addr__h98165 or
|
|
n__read_addr__h98246 or
|
|
n__read_addr__h98327 or
|
|
n__read_addr__h98408 or
|
|
n__read_addr__h98489 or
|
|
n__read_addr__h98570 or n__read_addr__h98651)
|
|
begin
|
|
case (sendRqToP_getRq_n)
|
|
3'd0: sendRqToP_getRq = n__read_addr__h98084;
|
|
3'd1: sendRqToP_getRq = n__read_addr__h98165;
|
|
3'd2: sendRqToP_getRq = n__read_addr__h98246;
|
|
3'd3: sendRqToP_getRq = n__read_addr__h98327;
|
|
3'd4: sendRqToP_getRq = n__read_addr__h98408;
|
|
3'd5: sendRqToP_getRq = n__read_addr__h98489;
|
|
3'd6: sendRqToP_getRq = n__read_addr__h98570;
|
|
3'd7: sendRqToP_getRq = n__read_addr__h98651;
|
|
endcase
|
|
end
|
|
assign RDY_sendRqToP_getRq = 1'd1 ;
|
|
|
|
// value method sendRqToP_getSlot
|
|
assign sendRqToP_getSlot =
|
|
{ x__h99510,
|
|
x__h99547,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 } ;
|
|
assign RDY_sendRqToP_getSlot = 1'd1 ;
|
|
|
|
// value method pipelineResp_getState
|
|
always@(pipelineResp_getState_n or
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 or
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 or
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 or
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 or
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 or
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 or
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 or
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150)
|
|
begin
|
|
case (pipelineResp_getState_n)
|
|
3'd0:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108;
|
|
3'd1:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114;
|
|
3'd2:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120;
|
|
3'd3:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126;
|
|
3'd4:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132;
|
|
3'd5:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138;
|
|
3'd6:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144;
|
|
3'd7:
|
|
pipelineResp_getState =
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getState = 1'd1 ;
|
|
|
|
// value method pipelineResp_getRq
|
|
always@(pipelineResp_getRq_n or
|
|
n__read_addr__h98084 or
|
|
n__read_addr__h98165 or
|
|
n__read_addr__h98246 or
|
|
n__read_addr__h98327 or
|
|
n__read_addr__h98408 or
|
|
n__read_addr__h98489 or
|
|
n__read_addr__h98570 or n__read_addr__h98651)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
3'd0: pipelineResp_getRq = n__read_addr__h98084;
|
|
3'd1: pipelineResp_getRq = n__read_addr__h98165;
|
|
3'd2: pipelineResp_getRq = n__read_addr__h98246;
|
|
3'd3: pipelineResp_getRq = n__read_addr__h98327;
|
|
3'd4: pipelineResp_getRq = n__read_addr__h98408;
|
|
3'd5: pipelineResp_getRq = n__read_addr__h98489;
|
|
3'd6: pipelineResp_getRq = n__read_addr__h98570;
|
|
3'd7: pipelineResp_getRq = n__read_addr__h98651;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getRq = 1'd1 ;
|
|
|
|
// value method pipelineResp_getSlot
|
|
assign pipelineResp_getSlot =
|
|
{ x__h100288,
|
|
x__h100325,
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 } ;
|
|
assign RDY_pipelineResp_getSlot = 1'd1 ;
|
|
|
|
// action method pipelineResp_setResult
|
|
assign RDY_pipelineResp_setResult = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setResult = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setResult = EN_pipelineResp_setResult ;
|
|
|
|
// action method pipelineResp_setStateSlot
|
|
assign RDY_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setStateSlot = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setStateSlot = EN_pipelineResp_setStateSlot ;
|
|
|
|
// value method pipelineResp_getSucc
|
|
assign pipelineResp_getSucc =
|
|
{ SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230,
|
|
m_m_succFile$D_OUT_1 } ;
|
|
assign RDY_pipelineResp_getSucc = 1'd1 ;
|
|
|
|
// action method pipelineResp_setSucc
|
|
assign RDY_pipelineResp_setSucc = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setSucc = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setSucc = EN_pipelineResp_setSucc ;
|
|
|
|
// value method pipelineResp_searchEndOfChain
|
|
assign pipelineResp_searchEndOfChain =
|
|
{ NOT_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_ETC___d1403,
|
|
IF_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m__ETC___d1457 } ;
|
|
assign RDY_pipelineResp_searchEndOfChain = 1'd1 ;
|
|
|
|
// value method emptyForFlush
|
|
assign emptyForFlush =
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1464 ;
|
|
assign RDY_emptyForFlush = 1'd1 ;
|
|
|
|
// actionvalue method stuck_get
|
|
assign stuck_get = 68'hAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_stuck_get = 1'd0 ;
|
|
assign CAN_FIRE_stuck_get = 1'd0 ;
|
|
assign WILL_FIRE_stuck_get = EN_stuck_get ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_m_emptyEntryQ$D_IN),
|
|
.ENQ(m_m_emptyEntryQ$ENQ),
|
|
.DEQ(m_m_emptyEntryQ$DEQ),
|
|
.CLR(m_m_emptyEntryQ$CLR),
|
|
.D_OUT(m_m_emptyEntryQ$D_OUT),
|
|
.FULL_N(m_m_emptyEntryQ$FULL_N),
|
|
.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_1_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_2_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_3_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_4_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_5_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_6_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_resultVec_7_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_resultVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_resultVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_resultVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_resultVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_resultVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_resultVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_resultVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_resultVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_slotVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_slotVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_slotVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_slotVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_slotVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_slotVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_slotVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_slotVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_slotVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_stateVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_7_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succFile
|
|
RegFile #(.addr_width(32'd3),
|
|
.data_width(32'd3),
|
|
.lo(3'd0),
|
|
.hi(3'd7)) m_m_succFile(.CLK(CLK),
|
|
.ADDR_1(m_m_succFile$ADDR_1),
|
|
.ADDR_2(m_m_succFile$ADDR_2),
|
|
.ADDR_3(m_m_succFile$ADDR_3),
|
|
.ADDR_4(m_m_succFile$ADDR_4),
|
|
.ADDR_5(m_m_succFile$ADDR_5),
|
|
.ADDR_IN(m_m_succFile$ADDR_IN),
|
|
.D_IN(m_m_succFile$D_IN),
|
|
.WE(m_m_succFile$WE),
|
|
.D_OUT_1(m_m_succFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_4_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_4_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_4_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_4_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_4_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_4_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_4_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_4_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_4_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_4_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_4_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_4_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_5_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_5_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_5_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_5_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_5_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_5_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_5_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_5_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_5_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_5_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_5_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_5_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_6_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_6_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_6_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_6_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_6_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_6_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_6_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_6_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_6_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_6_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_6_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_6_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_7_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_7_dummy2_0$D_IN),
|
|
.EN(m_m_succValidVec_7_dummy2_0$EN),
|
|
.Q_OUT(m_m_succValidVec_7_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_7_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_7_dummy2_1$D_IN),
|
|
.EN(m_m_succValidVec_7_dummy2_1$EN),
|
|
.Q_OUT(m_m_succValidVec_7_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_succValidVec_7_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_succValidVec_7_dummy2_2$D_IN),
|
|
.EN(m_m_succValidVec_7_dummy2_2$EN),
|
|
.Q_OUT(m_m_succValidVec_7_dummy2_2$Q_OUT));
|
|
|
|
// rule RL_m_m_initEmptyEntry
|
|
assign CAN_FIRE_RL_m_m_initEmptyEntry =
|
|
m_m_emptyEntryQ$FULL_N && !m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// rule RL_m_m_stateVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_slotVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_slotVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_resultVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_resultVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_resultVec_7_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_4_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_4_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_5_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_5_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_6_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_6_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_succValidVec_7_canon
|
|
assign CAN_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_succValidVec_7_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign m_m_stateVec_0_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd0 ;
|
|
assign m_m_stateVec_0_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd0 ;
|
|
assign m_m_stateVec_0_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd0 ;
|
|
assign m_m_stateVec_1_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd1 ;
|
|
assign m_m_stateVec_1_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd1 ;
|
|
assign m_m_stateVec_1_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd1 ;
|
|
assign m_m_stateVec_2_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd2 ;
|
|
assign m_m_stateVec_2_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd2 ;
|
|
assign m_m_stateVec_2_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd2 ;
|
|
assign m_m_stateVec_3_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd3 ;
|
|
assign m_m_stateVec_3_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd3 ;
|
|
assign m_m_stateVec_3_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd3 ;
|
|
assign m_m_stateVec_4_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd4 ;
|
|
assign m_m_stateVec_4_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd4 ;
|
|
assign m_m_stateVec_4_dummy_1_0$wget =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd4 ;
|
|
assign m_m_stateVec_5_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd5 ;
|
|
assign m_m_stateVec_5_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd5 ;
|
|
assign m_m_stateVec_5_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd5 ;
|
|
assign m_m_stateVec_6_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd6 ;
|
|
assign m_m_stateVec_6_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd6 ;
|
|
assign m_m_stateVec_6_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd6 ;
|
|
assign m_m_stateVec_7_lat_0$whas =
|
|
EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_n == 3'd7 ;
|
|
assign m_m_stateVec_7_lat_1$whas =
|
|
EN_sendRsToC_releaseEntry && sendRsToC_releaseEntry_n == 3'd7 ;
|
|
assign m_m_stateVec_7_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 3'd7 ;
|
|
assign m_m_resultVec_0_lat_0$wget = { 1'd1, pipelineResp_setResult_r } ;
|
|
assign m_m_resultVec_0_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd0 ;
|
|
assign m_m_resultVec_1_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd1 ;
|
|
assign m_m_resultVec_2_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd2 ;
|
|
assign m_m_resultVec_3_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd3 ;
|
|
assign m_m_resultVec_4_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd4 ;
|
|
assign m_m_resultVec_5_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd5 ;
|
|
assign m_m_resultVec_6_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd6 ;
|
|
assign m_m_resultVec_7_lat_0$whas =
|
|
EN_pipelineResp_setResult && pipelineResp_setResult_n == 3'd7 ;
|
|
assign m_m_succValidVec_0_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd0 ;
|
|
assign m_m_succValidVec_1_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd1 ;
|
|
assign m_m_succValidVec_2_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd2 ;
|
|
assign m_m_succValidVec_3_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd3 ;
|
|
assign m_m_succValidVec_4_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd4 ;
|
|
assign m_m_succValidVec_5_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd5 ;
|
|
assign m_m_succValidVec_6_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd6 ;
|
|
assign m_m_succValidVec_7_lat_0$whas =
|
|
EN_pipelineResp_setSucc && pipelineResp_setSucc_n == 3'd7 ;
|
|
|
|
// register m_m_initIdx
|
|
assign m_m_initIdx$D_IN = m_m_initIdx + 3'd1 ;
|
|
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// register m_m_inited
|
|
assign m_m_inited$D_IN = 1'd1 ;
|
|
assign m_m_inited$EN =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 3'd7 ;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
assign m_m_reqVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_0_rl ;
|
|
assign m_m_reqVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
assign m_m_reqVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_1_rl ;
|
|
assign m_m_reqVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
assign m_m_reqVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_2_rl ;
|
|
assign m_m_reqVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
assign m_m_reqVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_3_rl ;
|
|
assign m_m_reqVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_4_rl
|
|
assign m_m_reqVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_4_rl ;
|
|
assign m_m_reqVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_5_rl
|
|
assign m_m_reqVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_5_rl ;
|
|
assign m_m_reqVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_6_rl
|
|
assign m_m_reqVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_6_rl ;
|
|
assign m_m_reqVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_7_rl
|
|
assign m_m_reqVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_7_rl ;
|
|
assign m_m_reqVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_0_rl
|
|
assign m_m_resultVec_0_rl$D_IN =
|
|
{ !m_m_stateVec_0_lat_2$whas &&
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_0_rl[66]),
|
|
IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306 } ;
|
|
assign m_m_resultVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_1_rl
|
|
assign m_m_resultVec_1_rl$D_IN =
|
|
{ !m_m_stateVec_1_lat_2$whas &&
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_1_rl[66]),
|
|
IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374 } ;
|
|
assign m_m_resultVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_2_rl
|
|
assign m_m_resultVec_2_rl$D_IN =
|
|
{ !m_m_stateVec_2_lat_2$whas &&
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_2_rl[66]),
|
|
IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442 } ;
|
|
assign m_m_resultVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_3_rl
|
|
assign m_m_resultVec_3_rl$D_IN =
|
|
{ !m_m_stateVec_3_lat_2$whas &&
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_3_rl[66]),
|
|
IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510 } ;
|
|
assign m_m_resultVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_4_rl
|
|
assign m_m_resultVec_4_rl$D_IN =
|
|
{ !m_m_stateVec_4_lat_2$whas &&
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_4_rl[66]),
|
|
IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578 } ;
|
|
assign m_m_resultVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_5_rl
|
|
assign m_m_resultVec_5_rl$D_IN =
|
|
{ !m_m_stateVec_5_lat_2$whas &&
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_5_rl[66]),
|
|
IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646 } ;
|
|
assign m_m_resultVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_6_rl
|
|
assign m_m_resultVec_6_rl$D_IN =
|
|
{ !m_m_stateVec_6_lat_2$whas &&
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_6_rl[66]),
|
|
IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714 } ;
|
|
assign m_m_resultVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_resultVec_7_rl
|
|
assign m_m_resultVec_7_rl$D_IN =
|
|
{ !m_m_stateVec_7_lat_2$whas &&
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[66] :
|
|
m_m_resultVec_7_rl[66]),
|
|
IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782 } ;
|
|
assign m_m_resultVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_0_rl
|
|
assign m_m_slotVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_0_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_0_rl) ;
|
|
assign m_m_slotVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_1_rl
|
|
assign m_m_slotVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_1_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_1_rl) ;
|
|
assign m_m_slotVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_2_rl
|
|
assign m_m_slotVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_2_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_2_rl) ;
|
|
assign m_m_slotVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_3_rl
|
|
assign m_m_slotVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_3_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_3_rl) ;
|
|
assign m_m_slotVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_4_rl
|
|
assign m_m_slotVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_4_dummy_1_0$wget ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_4_rl) ;
|
|
assign m_m_slotVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_5_rl
|
|
assign m_m_slotVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_5_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_5_rl) ;
|
|
assign m_m_slotVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_6_rl
|
|
assign m_m_slotVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_6_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_6_rl) ;
|
|
assign m_m_slotVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_slotVec_7_rl
|
|
assign m_m_slotVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
56'h55555555555554 :
|
|
(m_m_stateVec_7_lat_0$whas ?
|
|
pipelineResp_setStateSlot_slot :
|
|
m_m_slotVec_7_rl) ;
|
|
assign m_m_slotVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
assign m_m_stateVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 ;
|
|
assign m_m_stateVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
assign m_m_stateVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 ;
|
|
assign m_m_stateVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
assign m_m_stateVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 ;
|
|
assign m_m_stateVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
assign m_m_stateVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 ;
|
|
assign m_m_stateVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_4_rl
|
|
assign m_m_stateVec_4_rl$D_IN =
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49 ;
|
|
assign m_m_stateVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_5_rl
|
|
assign m_m_stateVec_5_rl$D_IN =
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59 ;
|
|
assign m_m_stateVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_6_rl
|
|
assign m_m_stateVec_6_rl$D_IN =
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69 ;
|
|
assign m_m_stateVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_7_rl
|
|
assign m_m_stateVec_7_rl$D_IN =
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
3'd1 :
|
|
IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79 ;
|
|
assign m_m_stateVec_7_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_0_rl
|
|
assign m_m_succValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
(m_m_succValidVec_0_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_0_rl) ;
|
|
assign m_m_succValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_1_rl
|
|
assign m_m_succValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
(m_m_succValidVec_1_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_1_rl) ;
|
|
assign m_m_succValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_2_rl
|
|
assign m_m_succValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
(m_m_succValidVec_2_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_2_rl) ;
|
|
assign m_m_succValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_3_rl
|
|
assign m_m_succValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
(m_m_succValidVec_3_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_3_rl) ;
|
|
assign m_m_succValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_4_rl
|
|
assign m_m_succValidVec_4_rl$D_IN =
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
(m_m_succValidVec_4_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_4_rl) ;
|
|
assign m_m_succValidVec_4_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_5_rl
|
|
assign m_m_succValidVec_5_rl$D_IN =
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
(m_m_succValidVec_5_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_5_rl) ;
|
|
assign m_m_succValidVec_5_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_6_rl
|
|
assign m_m_succValidVec_6_rl$D_IN =
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
(m_m_succValidVec_6_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_6_rl) ;
|
|
assign m_m_succValidVec_6_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_succValidVec_7_rl
|
|
assign m_m_succValidVec_7_rl$D_IN =
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
(m_m_succValidVec_7_lat_0$whas ?
|
|
pipelineResp_setSucc_succ[3] :
|
|
m_m_succValidVec_7_rl) ;
|
|
assign m_m_succValidVec_7_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
assign m_m_emptyEntryQ$D_IN =
|
|
EN_sendRsToC_releaseEntry ?
|
|
sendRsToC_releaseEntry_n :
|
|
m_m_initIdx ;
|
|
assign m_m_emptyEntryQ$ENQ =
|
|
EN_sendRsToC_releaseEntry || WILL_FIRE_RL_m_m_initEmptyEntry ;
|
|
assign m_m_emptyEntryQ$DEQ = EN_getEmptyEntryInit ;
|
|
assign m_m_emptyEntryQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_0
|
|
assign m_m_reqVec_0_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_0_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_1
|
|
assign m_m_reqVec_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_2
|
|
assign m_m_reqVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_0
|
|
assign m_m_reqVec_1_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_1_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_1
|
|
assign m_m_reqVec_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_2
|
|
assign m_m_reqVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_0
|
|
assign m_m_reqVec_2_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_2_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_1
|
|
assign m_m_reqVec_2_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_2_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_2
|
|
assign m_m_reqVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_0
|
|
assign m_m_reqVec_3_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_3_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_1
|
|
assign m_m_reqVec_3_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_3_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_2
|
|
assign m_m_reqVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_4_dummy2_0
|
|
assign m_m_reqVec_4_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_4_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_4_dummy2_1
|
|
assign m_m_reqVec_4_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_4_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_4_dummy2_2
|
|
assign m_m_reqVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_5_dummy2_0
|
|
assign m_m_reqVec_5_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_5_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_5_dummy2_1
|
|
assign m_m_reqVec_5_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_5_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_5_dummy2_2
|
|
assign m_m_reqVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_6_dummy2_0
|
|
assign m_m_reqVec_6_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_6_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_6_dummy2_1
|
|
assign m_m_reqVec_6_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_6_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_6_dummy2_2
|
|
assign m_m_reqVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_7_dummy2_0
|
|
assign m_m_reqVec_7_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_7_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_7_dummy2_1
|
|
assign m_m_reqVec_7_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_7_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_7_dummy2_2
|
|
assign m_m_reqVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_0_dummy2_0
|
|
assign m_m_resultVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_0_dummy2_0$EN = m_m_resultVec_0_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_0_dummy2_1
|
|
assign m_m_resultVec_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_0_dummy2_2
|
|
assign m_m_resultVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_1_dummy2_0
|
|
assign m_m_resultVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_1_dummy2_0$EN = m_m_resultVec_1_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_1_dummy2_1
|
|
assign m_m_resultVec_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_1_dummy2_2
|
|
assign m_m_resultVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_2_dummy2_0
|
|
assign m_m_resultVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_2_dummy2_0$EN = m_m_resultVec_2_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_2_dummy2_1
|
|
assign m_m_resultVec_2_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_2_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_2_dummy2_2
|
|
assign m_m_resultVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_3_dummy2_0
|
|
assign m_m_resultVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_3_dummy2_0$EN = m_m_resultVec_3_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_3_dummy2_1
|
|
assign m_m_resultVec_3_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_3_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_3_dummy2_2
|
|
assign m_m_resultVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_4_dummy2_0
|
|
assign m_m_resultVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_4_dummy2_0$EN = m_m_resultVec_4_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_4_dummy2_1
|
|
assign m_m_resultVec_4_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_4_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_4_dummy2_2
|
|
assign m_m_resultVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_5_dummy2_0
|
|
assign m_m_resultVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_5_dummy2_0$EN = m_m_resultVec_5_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_5_dummy2_1
|
|
assign m_m_resultVec_5_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_5_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_5_dummy2_2
|
|
assign m_m_resultVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_6_dummy2_0
|
|
assign m_m_resultVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_6_dummy2_0$EN = m_m_resultVec_6_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_6_dummy2_1
|
|
assign m_m_resultVec_6_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_6_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_6_dummy2_2
|
|
assign m_m_resultVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_resultVec_7_dummy2_0
|
|
assign m_m_resultVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_7_dummy2_0$EN = m_m_resultVec_7_lat_0$whas ;
|
|
|
|
// submodule m_m_resultVec_7_dummy2_1
|
|
assign m_m_resultVec_7_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_resultVec_7_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_resultVec_7_dummy2_2
|
|
assign m_m_resultVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_resultVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_0_dummy2_0
|
|
assign m_m_slotVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_0_dummy2_0$EN = m_m_stateVec_0_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_0_dummy2_1
|
|
assign m_m_slotVec_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_0_dummy2_2
|
|
assign m_m_slotVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_1_dummy2_0
|
|
assign m_m_slotVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_1_dummy2_0$EN = m_m_stateVec_1_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_1_dummy2_1
|
|
assign m_m_slotVec_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_1_dummy2_2
|
|
assign m_m_slotVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_2_dummy2_0
|
|
assign m_m_slotVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_2_dummy2_0$EN = m_m_stateVec_2_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_2_dummy2_1
|
|
assign m_m_slotVec_2_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_2_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_2_dummy2_2
|
|
assign m_m_slotVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_3_dummy2_0
|
|
assign m_m_slotVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_3_dummy2_0$EN = m_m_stateVec_3_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_3_dummy2_1
|
|
assign m_m_slotVec_3_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_3_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_3_dummy2_2
|
|
assign m_m_slotVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_4_dummy2_0
|
|
assign m_m_slotVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_4_dummy2_0$EN = m_m_stateVec_4_dummy_1_0$wget ;
|
|
|
|
// submodule m_m_slotVec_4_dummy2_1
|
|
assign m_m_slotVec_4_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_4_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_4_dummy2_2
|
|
assign m_m_slotVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_5_dummy2_0
|
|
assign m_m_slotVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_5_dummy2_0$EN = m_m_stateVec_5_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_5_dummy2_1
|
|
assign m_m_slotVec_5_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_5_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_5_dummy2_2
|
|
assign m_m_slotVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_6_dummy2_0
|
|
assign m_m_slotVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_6_dummy2_0$EN = m_m_stateVec_6_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_6_dummy2_1
|
|
assign m_m_slotVec_6_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_6_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_6_dummy2_2
|
|
assign m_m_slotVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_slotVec_7_dummy2_0
|
|
assign m_m_slotVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_7_dummy2_0$EN = m_m_stateVec_7_lat_0$whas ;
|
|
|
|
// submodule m_m_slotVec_7_dummy2_1
|
|
assign m_m_slotVec_7_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_slotVec_7_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_slotVec_7_dummy2_2
|
|
assign m_m_slotVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_slotVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_0
|
|
assign m_m_stateVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_0$EN = m_m_stateVec_0_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_1
|
|
assign m_m_stateVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_1$EN = m_m_stateVec_0_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_2
|
|
assign m_m_stateVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_0
|
|
assign m_m_stateVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_0$EN = m_m_stateVec_1_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_1
|
|
assign m_m_stateVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_1$EN = m_m_stateVec_1_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_2
|
|
assign m_m_stateVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_0
|
|
assign m_m_stateVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_0$EN = m_m_stateVec_2_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_1
|
|
assign m_m_stateVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_1$EN = m_m_stateVec_2_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_2
|
|
assign m_m_stateVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_0
|
|
assign m_m_stateVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_0$EN = m_m_stateVec_3_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_1
|
|
assign m_m_stateVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_1$EN = m_m_stateVec_3_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_2
|
|
assign m_m_stateVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_4_dummy2_0
|
|
assign m_m_stateVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_4_dummy2_0$EN = m_m_stateVec_4_dummy_1_0$wget ;
|
|
|
|
// submodule m_m_stateVec_4_dummy2_1
|
|
assign m_m_stateVec_4_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_4_dummy2_1$EN = m_m_stateVec_4_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_4_dummy2_2
|
|
assign m_m_stateVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_5_dummy2_0
|
|
assign m_m_stateVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_5_dummy2_0$EN = m_m_stateVec_5_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_5_dummy2_1
|
|
assign m_m_stateVec_5_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_5_dummy2_1$EN = m_m_stateVec_5_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_5_dummy2_2
|
|
assign m_m_stateVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_6_dummy2_0
|
|
assign m_m_stateVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_6_dummy2_0$EN = m_m_stateVec_6_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_6_dummy2_1
|
|
assign m_m_stateVec_6_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_6_dummy2_1$EN = m_m_stateVec_6_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_6_dummy2_2
|
|
assign m_m_stateVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_7_dummy2_0
|
|
assign m_m_stateVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_7_dummy2_0$EN = m_m_stateVec_7_lat_0$whas ;
|
|
|
|
// submodule m_m_stateVec_7_dummy2_1
|
|
assign m_m_stateVec_7_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_7_dummy2_1$EN = m_m_stateVec_7_lat_1$whas ;
|
|
|
|
// submodule m_m_stateVec_7_dummy2_2
|
|
assign m_m_stateVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// submodule m_m_succFile
|
|
assign m_m_succFile$ADDR_1 = pipelineResp_getSucc_n ;
|
|
assign m_m_succFile$ADDR_2 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_3 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_4 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_5 = 3'h0 ;
|
|
assign m_m_succFile$ADDR_IN = pipelineResp_setSucc_n ;
|
|
assign m_m_succFile$D_IN = pipelineResp_setSucc_succ[2:0] ;
|
|
assign m_m_succFile$WE = EN_pipelineResp_setSucc ;
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_0
|
|
assign m_m_succValidVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_0_dummy2_0$EN = m_m_succValidVec_0_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_1
|
|
assign m_m_succValidVec_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_0_dummy2_2
|
|
assign m_m_succValidVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_0
|
|
assign m_m_succValidVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_1_dummy2_0$EN = m_m_succValidVec_1_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_1
|
|
assign m_m_succValidVec_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_1_dummy2_2
|
|
assign m_m_succValidVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_0
|
|
assign m_m_succValidVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_2_dummy2_0$EN = m_m_succValidVec_2_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_1
|
|
assign m_m_succValidVec_2_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_2_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_2_dummy2_2
|
|
assign m_m_succValidVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_0
|
|
assign m_m_succValidVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_3_dummy2_0$EN = m_m_succValidVec_3_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_1
|
|
assign m_m_succValidVec_3_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_3_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_3_dummy2_2
|
|
assign m_m_succValidVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_0
|
|
assign m_m_succValidVec_4_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_4_dummy2_0$EN = m_m_succValidVec_4_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_1
|
|
assign m_m_succValidVec_4_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_4_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_4_dummy2_2
|
|
assign m_m_succValidVec_4_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_4_dummy2_2$EN = m_m_stateVec_4_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_0
|
|
assign m_m_succValidVec_5_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_5_dummy2_0$EN = m_m_succValidVec_5_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_1
|
|
assign m_m_succValidVec_5_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_5_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_5_dummy2_2
|
|
assign m_m_succValidVec_5_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_5_dummy2_2$EN = m_m_stateVec_5_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_0
|
|
assign m_m_succValidVec_6_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_6_dummy2_0$EN = m_m_succValidVec_6_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_1
|
|
assign m_m_succValidVec_6_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_6_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_6_dummy2_2
|
|
assign m_m_succValidVec_6_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_6_dummy2_2$EN = m_m_stateVec_6_lat_2$whas ;
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_0
|
|
assign m_m_succValidVec_7_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_7_dummy2_0$EN = m_m_succValidVec_7_lat_0$whas ;
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_1
|
|
assign m_m_succValidVec_7_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_succValidVec_7_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_succValidVec_7_dummy2_2
|
|
assign m_m_succValidVec_7_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_succValidVec_7_dummy2_2$EN = m_m_stateVec_7_lat_2$whas ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m__ETC___d1456 =
|
|
(IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1408 &&
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1413) ?
|
|
(IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1419 ?
|
|
3'd3 :
|
|
3'd2) :
|
|
(IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1408 ?
|
|
3'd1 :
|
|
3'd0) ;
|
|
assign IF_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m__ETC___d1457 =
|
|
(IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1408 &&
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1413 &&
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1419 &&
|
|
(IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_3_dummy2_0_read__75_AND_m_m_reqV_ETC___d1312 ||
|
|
m_m_succValidVec_3_dummy2_0_read__199_AND_m_m__ETC___d1204)) ?
|
|
IF_IF_m_m_stateVec_4_dummy2_0_read__127_AND_m__ETC___d1453 :
|
|
IF_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m__ETC___d1456 ;
|
|
assign IF_IF_m_m_stateVec_4_dummy2_0_read__127_AND_m__ETC___d1453 =
|
|
(IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1431 &&
|
|
(IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_5_dummy2_0_read__87_AND_m_m_reqV_ETC___d1352 ||
|
|
m_m_succValidVec_5_dummy2_0_read__211_AND_m_m__ETC___d1216)) ?
|
|
((IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_6_dummy2_0_read__93_AND_m_m_reqV_ETC___d1372 ||
|
|
m_m_succValidVec_6_dummy2_0_read__217_AND_m_m__ETC___d1222) ?
|
|
3'd7 :
|
|
3'd6) :
|
|
(IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1431 ?
|
|
3'd5 :
|
|
3'd4) ;
|
|
assign IF_m_m_reqVec_0_dummy2_0_read__57_AND_m_m_reqV_ETC___d1254 =
|
|
n__read_addr__h98084[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_1_dummy2_0_read__63_AND_m_m_reqV_ETC___d1273 =
|
|
n__read_addr__h98165[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_2_dummy2_0_read__69_AND_m_m_reqV_ETC___d1293 =
|
|
n__read_addr__h98246[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_3_dummy2_0_read__75_AND_m_m_reqV_ETC___d1312 =
|
|
n__read_addr__h98327[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_4_dummy2_0_read__81_AND_m_m_reqV_ETC___d1333 =
|
|
n__read_addr__h98408[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_5_dummy2_0_read__87_AND_m_m_reqV_ETC___d1352 =
|
|
n__read_addr__h98489[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_reqVec_6_dummy2_0_read__93_AND_m_m_reqV_ETC___d1372 =
|
|
n__read_addr__h98570[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] ;
|
|
assign IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_0_rl[64:33] ;
|
|
assign IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_0_rl[31:0] ;
|
|
assign IF_m_m_resultVec_0_lat_2_whas__41_THEN_m_m_res_ETC___d306 =
|
|
{ m_m_stateVec_0_lat_2$whas ||
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_0_rl[65]),
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280,
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_0_rl[32]),
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 } ;
|
|
assign IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_1_rl[64:33] ;
|
|
assign IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_1_rl[31:0] ;
|
|
assign IF_m_m_resultVec_1_lat_2_whas__09_THEN_m_m_res_ETC___d374 =
|
|
{ m_m_stateVec_1_lat_2$whas ||
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_1_rl[65]),
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348,
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_1_rl[32]),
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 } ;
|
|
assign IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_2_rl[64:33] ;
|
|
assign IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_2_rl[31:0] ;
|
|
assign IF_m_m_resultVec_2_lat_2_whas__77_THEN_m_m_res_ETC___d442 =
|
|
{ m_m_stateVec_2_lat_2$whas ||
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_2_rl[65]),
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416,
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_2_rl[32]),
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 } ;
|
|
assign IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_3_rl[64:33] ;
|
|
assign IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_3_rl[31:0] ;
|
|
assign IF_m_m_resultVec_3_lat_2_whas__45_THEN_m_m_res_ETC___d510 =
|
|
{ m_m_stateVec_3_lat_2$whas ||
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_3_rl[65]),
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484,
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_3_rl[32]),
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 } ;
|
|
assign IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_4_rl[64:33] ;
|
|
assign IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_4_rl[31:0] ;
|
|
assign IF_m_m_resultVec_4_lat_2_whas__13_THEN_m_m_res_ETC___d578 =
|
|
{ m_m_stateVec_4_lat_2$whas ||
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_4_rl[65]),
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552,
|
|
!m_m_stateVec_4_lat_2$whas &&
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_4_rl[32]),
|
|
m_m_stateVec_4_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 } ;
|
|
assign IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_5_rl[64:33] ;
|
|
assign IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_5_rl[31:0] ;
|
|
assign IF_m_m_resultVec_5_lat_2_whas__81_THEN_m_m_res_ETC___d646 =
|
|
{ m_m_stateVec_5_lat_2$whas ||
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_5_rl[65]),
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620,
|
|
!m_m_stateVec_5_lat_2$whas &&
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_5_rl[32]),
|
|
m_m_stateVec_5_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 } ;
|
|
assign IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_6_rl[64:33] ;
|
|
assign IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_6_rl[31:0] ;
|
|
assign IF_m_m_resultVec_6_lat_2_whas__49_THEN_m_m_res_ETC___d714 =
|
|
{ m_m_stateVec_6_lat_2$whas ||
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_6_rl[65]),
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688,
|
|
!m_m_stateVec_6_lat_2$whas &&
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_6_rl[32]),
|
|
m_m_stateVec_6_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 } ;
|
|
assign IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[64:33] :
|
|
m_m_resultVec_7_rl[64:33] ;
|
|
assign IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[31:0] :
|
|
m_m_resultVec_7_rl[31:0] ;
|
|
assign IF_m_m_resultVec_7_lat_2_whas__17_THEN_m_m_res_ETC___d782 =
|
|
{ m_m_stateVec_7_lat_2$whas ||
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[65] :
|
|
m_m_resultVec_7_rl[65]),
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
32'b01010101010101010101010101010101 :
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756,
|
|
!m_m_stateVec_7_lat_2$whas &&
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
m_m_resultVec_0_lat_0$wget[32] :
|
|
m_m_resultVec_7_rl[32]),
|
|
m_m_stateVec_7_lat_2$whas ?
|
|
32'hAAAAAAAA :
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778 } ;
|
|
assign IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 =
|
|
(m_m_stateVec_0_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_0_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_0_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1408 =
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_0_dummy2_0_read__57_AND_m_m_reqV_ETC___d1254 ||
|
|
m_m_succValidVec_0_dummy2_0_read__181_AND_m_m__ETC___d1186 ;
|
|
assign IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 =
|
|
m_m_stateVec_0_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_0_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_0_rl) ;
|
|
assign IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 =
|
|
(m_m_stateVec_1_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_1_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_1_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1413 =
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_1_dummy2_0_read__63_AND_m_m_reqV_ETC___d1273 ||
|
|
m_m_succValidVec_1_dummy2_0_read__187_AND_m_m__ETC___d1192 ;
|
|
assign IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1464 =
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 ==
|
|
3'd0 &&
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150 ==
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 =
|
|
m_m_stateVec_1_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_1_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_1_rl) ;
|
|
assign IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 =
|
|
(m_m_stateVec_2_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_2_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_2_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1419 =
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_2_dummy2_0_read__69_AND_m_m_reqV_ETC___d1293 ||
|
|
m_m_succValidVec_2_dummy2_0_read__193_AND_m_m__ETC___d1198 ;
|
|
assign IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 =
|
|
m_m_stateVec_2_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_2_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_2_rl) ;
|
|
assign IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 =
|
|
(m_m_stateVec_3_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_3_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_3_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 =
|
|
m_m_stateVec_3_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_3_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_3_rl) ;
|
|
assign IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 =
|
|
(m_m_stateVec_4_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_4_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_4_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1431 =
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 ==
|
|
3'd3 ||
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 ==
|
|
3'd0 ||
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 ==
|
|
3'd1 ||
|
|
!IF_m_m_reqVec_4_dummy2_0_read__81_AND_m_m_reqV_ETC___d1333 ||
|
|
m_m_succValidVec_4_dummy2_0_read__205_AND_m_m__ETC___d1210 ;
|
|
assign IF_m_m_stateVec_4_lat_1_whas__3_THEN_m_m_state_ETC___d49 =
|
|
m_m_stateVec_4_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_4_dummy_1_0$wget ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_4_rl) ;
|
|
assign IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 =
|
|
(m_m_stateVec_5_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_5_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_5_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_5_lat_1_whas__3_THEN_m_m_state_ETC___d59 =
|
|
m_m_stateVec_5_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_5_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_5_rl) ;
|
|
assign IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 =
|
|
(m_m_stateVec_6_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_6_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_6_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_6_lat_1_whas__3_THEN_m_m_state_ETC___d69 =
|
|
m_m_stateVec_6_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_6_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_6_rl) ;
|
|
assign IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150 =
|
|
(m_m_stateVec_7_dummy2_0$Q_OUT &&
|
|
m_m_stateVec_7_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_stateVec_7_rl :
|
|
3'd0 ;
|
|
assign IF_m_m_stateVec_7_lat_1_whas__3_THEN_m_m_state_ETC___d79 =
|
|
m_m_stateVec_7_lat_1$whas ?
|
|
3'd0 :
|
|
(m_m_stateVec_7_lat_0$whas ?
|
|
pipelineResp_setStateSlot_state :
|
|
m_m_stateVec_7_rl) ;
|
|
assign NOT_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_ETC___d1263 =
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_m_s_ETC___d1108 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_0_dummy2_0_read__57_AND_m_m_reqV_ETC___d1254 &&
|
|
(!m_m_succValidVec_0_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_0_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_0_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_0_rl) ;
|
|
assign NOT_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_ETC___d1403 =
|
|
NOT_IF_m_m_stateVec_0_dummy2_0_read__103_AND_m_ETC___d1263 ||
|
|
NOT_IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_ETC___d1282 ||
|
|
NOT_IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_ETC___d1302 ||
|
|
NOT_IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_ETC___d1321 ||
|
|
NOT_IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_ETC___d1342 ||
|
|
NOT_IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_ETC___d1361 ||
|
|
NOT_IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_ETC___d1381 ||
|
|
NOT_IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_ETC___d1400 ;
|
|
assign NOT_IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_ETC___d1282 =
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_1_dummy2_0_read__109_AND_m_m_s_ETC___d1114 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_1_dummy2_0_read__63_AND_m_m_reqV_ETC___d1273 &&
|
|
(!m_m_succValidVec_1_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_1_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_1_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_1_rl) ;
|
|
assign NOT_IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_ETC___d1302 =
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_2_dummy2_0_read__115_AND_m_m_s_ETC___d1120 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_2_dummy2_0_read__69_AND_m_m_reqV_ETC___d1293 &&
|
|
(!m_m_succValidVec_2_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_2_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_2_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_2_rl) ;
|
|
assign NOT_IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_ETC___d1321 =
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_3_dummy2_0_read__121_AND_m_m_s_ETC___d1126 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_3_dummy2_0_read__75_AND_m_m_reqV_ETC___d1312 &&
|
|
(!m_m_succValidVec_3_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_3_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_3_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_3_rl) ;
|
|
assign NOT_IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_ETC___d1342 =
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_4_dummy2_0_read__127_AND_m_m_s_ETC___d1132 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_4_dummy2_0_read__81_AND_m_m_reqV_ETC___d1333 &&
|
|
(!m_m_succValidVec_4_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_4_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_4_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_4_rl) ;
|
|
assign NOT_IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_ETC___d1361 =
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_5_dummy2_0_read__133_AND_m_m_s_ETC___d1138 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_5_dummy2_0_read__87_AND_m_m_reqV_ETC___d1352 &&
|
|
(!m_m_succValidVec_5_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_5_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_5_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_5_rl) ;
|
|
assign NOT_IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_ETC___d1381 =
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_6_dummy2_0_read__139_AND_m_m_s_ETC___d1144 !=
|
|
3'd1 &&
|
|
IF_m_m_reqVec_6_dummy2_0_read__93_AND_m_m_reqV_ETC___d1372 &&
|
|
(!m_m_succValidVec_6_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_6_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_6_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_6_rl) ;
|
|
assign NOT_IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_ETC___d1400 =
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150 !=
|
|
3'd3 &&
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150 !=
|
|
3'd0 &&
|
|
IF_m_m_stateVec_7_dummy2_0_read__145_AND_m_m_s_ETC___d1150 !=
|
|
3'd1 &&
|
|
n__read_addr__h98651[63:6] ==
|
|
pipelineResp_searchEndOfChain_addr[63:6] &&
|
|
(!m_m_succValidVec_7_dummy2_0$Q_OUT ||
|
|
!m_m_succValidVec_7_dummy2_1$Q_OUT ||
|
|
!m_m_succValidVec_7_dummy2_2$Q_OUT ||
|
|
!m_m_succValidVec_7_rl) ;
|
|
assign NOT_m_m_resultVec_0_dummy2_1_read__92_93_OR_NO_ETC___d897 =
|
|
!m_m_resultVec_0_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_0_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_0_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_0_rl[66]) ;
|
|
assign NOT_m_m_resultVec_1_dummy2_1_read__98_99_OR_NO_ETC___d903 =
|
|
!m_m_resultVec_1_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_1_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_1_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_1_rl[66]) ;
|
|
assign NOT_m_m_resultVec_2_dummy2_1_read__04_05_OR_NO_ETC___d909 =
|
|
!m_m_resultVec_2_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_2_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_2_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_2_rl[66]) ;
|
|
assign NOT_m_m_resultVec_3_dummy2_1_read__10_11_OR_NO_ETC___d915 =
|
|
!m_m_resultVec_3_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_3_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_3_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_3_rl[66]) ;
|
|
assign NOT_m_m_resultVec_4_dummy2_1_read__16_17_OR_NO_ETC___d921 =
|
|
!m_m_resultVec_4_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_4_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_4_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_4_rl[66]) ;
|
|
assign NOT_m_m_resultVec_5_dummy2_1_read__22_23_OR_NO_ETC___d927 =
|
|
!m_m_resultVec_5_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_5_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_5_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_5_rl[66]) ;
|
|
assign NOT_m_m_resultVec_6_dummy2_1_read__28_29_OR_NO_ETC___d933 =
|
|
!m_m_resultVec_6_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_6_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_6_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_6_rl[66]) ;
|
|
assign NOT_m_m_resultVec_7_dummy2_1_read__34_35_OR_NO_ETC___d939 =
|
|
!m_m_resultVec_7_dummy2_1$Q_OUT ||
|
|
!m_m_resultVec_7_dummy2_2$Q_OUT ||
|
|
(m_m_resultVec_7_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[66] :
|
|
!m_m_resultVec_7_rl[66]) ;
|
|
assign m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083 =
|
|
m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_0_rl[0] ;
|
|
assign m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085 =
|
|
m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_1_rl[0] ;
|
|
assign m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087 =
|
|
m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_2_rl[0] ;
|
|
assign m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089 =
|
|
m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_3_rl[0] ;
|
|
assign m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091 =
|
|
m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_4_rl[0] ;
|
|
assign m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093 =
|
|
m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_5_rl[0] ;
|
|
assign m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095 =
|
|
m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_6_rl[0] ;
|
|
assign m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097 =
|
|
m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT &&
|
|
m_m_slotVec_7_rl[0] ;
|
|
assign m_m_succValidVec_0_dummy2_0_read__181_AND_m_m__ETC___d1186 =
|
|
m_m_succValidVec_0_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_0_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_0_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_0_rl ;
|
|
assign m_m_succValidVec_1_dummy2_0_read__187_AND_m_m__ETC___d1192 =
|
|
m_m_succValidVec_1_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_1_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_1_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_1_rl ;
|
|
assign m_m_succValidVec_2_dummy2_0_read__193_AND_m_m__ETC___d1198 =
|
|
m_m_succValidVec_2_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_2_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_2_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_2_rl ;
|
|
assign m_m_succValidVec_3_dummy2_0_read__199_AND_m_m__ETC___d1204 =
|
|
m_m_succValidVec_3_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_3_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_3_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_3_rl ;
|
|
assign m_m_succValidVec_4_dummy2_0_read__205_AND_m_m__ETC___d1210 =
|
|
m_m_succValidVec_4_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_4_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_4_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_4_rl ;
|
|
assign m_m_succValidVec_5_dummy2_0_read__211_AND_m_m__ETC___d1216 =
|
|
m_m_succValidVec_5_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_5_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_5_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_5_rl ;
|
|
assign m_m_succValidVec_6_dummy2_0_read__217_AND_m_m__ETC___d1222 =
|
|
m_m_succValidVec_6_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_6_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_6_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_6_rl ;
|
|
assign n__read_addr__h98084 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98165 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98246 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98327 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98408 =
|
|
(m_m_reqVec_4_dummy2_0$Q_OUT && m_m_reqVec_4_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_4_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98489 =
|
|
(m_m_reqVec_5_dummy2_0$Q_OUT && m_m_reqVec_5_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_5_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98570 =
|
|
(m_m_reqVec_6_dummy2_0$Q_OUT && m_m_reqVec_6_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_6_rl :
|
|
64'd0 ;
|
|
assign n__read_addr__h98651 =
|
|
(m_m_reqVec_7_dummy2_0$Q_OUT && m_m_reqVec_7_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_7_rl :
|
|
64'd0 ;
|
|
assign n__read_repTag__h98796 =
|
|
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_0_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h98881 =
|
|
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_1_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h98966 =
|
|
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_2_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h99051 =
|
|
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_3_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h99136 =
|
|
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_4_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h99221 =
|
|
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_5_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h99306 =
|
|
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_6_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_repTag__h99391 =
|
|
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_7_rl[52:1] :
|
|
52'd0 ;
|
|
assign n__read_way__h98795 =
|
|
(m_m_slotVec_0_dummy2_0$Q_OUT && m_m_slotVec_0_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_0_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h98880 =
|
|
(m_m_slotVec_1_dummy2_0$Q_OUT && m_m_slotVec_1_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_1_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h98965 =
|
|
(m_m_slotVec_2_dummy2_0$Q_OUT && m_m_slotVec_2_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_2_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h99050 =
|
|
(m_m_slotVec_3_dummy2_0$Q_OUT && m_m_slotVec_3_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_3_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h99135 =
|
|
(m_m_slotVec_4_dummy2_0$Q_OUT && m_m_slotVec_4_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_4_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_4_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h99220 =
|
|
(m_m_slotVec_5_dummy2_0$Q_OUT && m_m_slotVec_5_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_5_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_5_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h99305 =
|
|
(m_m_slotVec_6_dummy2_0$Q_OUT && m_m_slotVec_6_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_6_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_6_rl[55:53] :
|
|
3'd0 ;
|
|
assign n__read_way__h99390 =
|
|
(m_m_slotVec_7_dummy2_0$Q_OUT && m_m_slotVec_7_dummy2_1$Q_OUT &&
|
|
m_m_slotVec_7_dummy2_2$Q_OUT) ?
|
|
m_m_slotVec_7_rl[55:53] :
|
|
3'd0 ;
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
n__read_repTag__h98796 or
|
|
n__read_repTag__h98881 or
|
|
n__read_repTag__h98966 or
|
|
n__read_repTag__h99051 or
|
|
n__read_repTag__h99136 or
|
|
n__read_repTag__h99221 or
|
|
n__read_repTag__h99306 or n__read_repTag__h99391)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h99419 = n__read_repTag__h98796;
|
|
3'd1: x__h99419 = n__read_repTag__h98881;
|
|
3'd2: x__h99419 = n__read_repTag__h98966;
|
|
3'd3: x__h99419 = n__read_repTag__h99051;
|
|
3'd4: x__h99419 = n__read_repTag__h99136;
|
|
3'd5: x__h99419 = n__read_repTag__h99221;
|
|
3'd6: x__h99419 = n__read_repTag__h99306;
|
|
3'd7: x__h99419 = n__read_repTag__h99391;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
n__read_repTag__h98796 or
|
|
n__read_repTag__h98881 or
|
|
n__read_repTag__h98966 or
|
|
n__read_repTag__h99051 or
|
|
n__read_repTag__h99136 or
|
|
n__read_repTag__h99221 or
|
|
n__read_repTag__h99306 or n__read_repTag__h99391)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h99547 = n__read_repTag__h98796;
|
|
3'd1: x__h99547 = n__read_repTag__h98881;
|
|
3'd2: x__h99547 = n__read_repTag__h98966;
|
|
3'd3: x__h99547 = n__read_repTag__h99051;
|
|
3'd4: x__h99547 = n__read_repTag__h99136;
|
|
3'd5: x__h99547 = n__read_repTag__h99221;
|
|
3'd6: x__h99547 = n__read_repTag__h99306;
|
|
3'd7: x__h99547 = n__read_repTag__h99391;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
n__read_repTag__h98796 or
|
|
n__read_repTag__h98881 or
|
|
n__read_repTag__h98966 or
|
|
n__read_repTag__h99051 or
|
|
n__read_repTag__h99136 or
|
|
n__read_repTag__h99221 or
|
|
n__read_repTag__h99306 or n__read_repTag__h99391)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0: x__h100325 = n__read_repTag__h98796;
|
|
3'd1: x__h100325 = n__read_repTag__h98881;
|
|
3'd2: x__h100325 = n__read_repTag__h98966;
|
|
3'd3: x__h100325 = n__read_repTag__h99051;
|
|
3'd4: x__h100325 = n__read_repTag__h99136;
|
|
3'd5: x__h100325 = n__read_repTag__h99221;
|
|
3'd6: x__h100325 = n__read_repTag__h99306;
|
|
3'd7: x__h100325 = n__read_repTag__h99391;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
n__read_way__h98795 or
|
|
n__read_way__h98880 or
|
|
n__read_way__h98965 or
|
|
n__read_way__h99050 or
|
|
n__read_way__h99135 or
|
|
n__read_way__h99220 or n__read_way__h99305 or n__read_way__h99390)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0: x__h98662 = n__read_way__h98795;
|
|
3'd1: x__h98662 = n__read_way__h98880;
|
|
3'd2: x__h98662 = n__read_way__h98965;
|
|
3'd3: x__h98662 = n__read_way__h99050;
|
|
3'd4: x__h98662 = n__read_way__h99135;
|
|
3'd5: x__h98662 = n__read_way__h99220;
|
|
3'd6: x__h98662 = n__read_way__h99305;
|
|
3'd7: x__h98662 = n__read_way__h99390;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
n__read_way__h98795 or
|
|
n__read_way__h98880 or
|
|
n__read_way__h98965 or
|
|
n__read_way__h99050 or
|
|
n__read_way__h99135 or
|
|
n__read_way__h99220 or n__read_way__h99305 or n__read_way__h99390)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0: x__h99510 = n__read_way__h98795;
|
|
3'd1: x__h99510 = n__read_way__h98880;
|
|
3'd2: x__h99510 = n__read_way__h98965;
|
|
3'd3: x__h99510 = n__read_way__h99050;
|
|
3'd4: x__h99510 = n__read_way__h99135;
|
|
3'd5: x__h99510 = n__read_way__h99220;
|
|
3'd6: x__h99510 = n__read_way__h99305;
|
|
3'd7: x__h99510 = n__read_way__h99390;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
n__read_way__h98795 or
|
|
n__read_way__h98880 or
|
|
n__read_way__h98965 or
|
|
n__read_way__h99050 or
|
|
n__read_way__h99135 or
|
|
n__read_way__h99220 or n__read_way__h99305 or n__read_way__h99390)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0: x__h100288 = n__read_way__h98795;
|
|
3'd1: x__h100288 = n__read_way__h98880;
|
|
3'd2: x__h100288 = n__read_way__h98965;
|
|
3'd3: x__h100288 = n__read_way__h99050;
|
|
3'd4: x__h100288 = n__read_way__h99135;
|
|
3'd5: x__h100288 = n__read_way__h99220;
|
|
3'd6: x__h100288 = n__read_way__h99305;
|
|
3'd7: x__h100288 = n__read_way__h99390;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSucc_n or
|
|
m_m_succValidVec_0_dummy2_0_read__181_AND_m_m__ETC___d1186 or
|
|
m_m_succValidVec_1_dummy2_0_read__187_AND_m_m__ETC___d1192 or
|
|
m_m_succValidVec_2_dummy2_0_read__193_AND_m_m__ETC___d1198 or
|
|
m_m_succValidVec_3_dummy2_0_read__199_AND_m_m__ETC___d1204 or
|
|
m_m_succValidVec_4_dummy2_0_read__205_AND_m_m__ETC___d1210 or
|
|
m_m_succValidVec_5_dummy2_0_read__211_AND_m_m__ETC___d1216 or
|
|
m_m_succValidVec_6_dummy2_0_read__217_AND_m_m__ETC___d1222 or
|
|
m_m_succValidVec_7_dummy2_0$Q_OUT or
|
|
m_m_succValidVec_7_dummy2_1$Q_OUT or
|
|
m_m_succValidVec_7_dummy2_2$Q_OUT or m_m_succValidVec_7_rl)
|
|
begin
|
|
case (pipelineResp_getSucc_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_0_dummy2_0_read__181_AND_m_m__ETC___d1186;
|
|
3'd1:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_1_dummy2_0_read__187_AND_m_m__ETC___d1192;
|
|
3'd2:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_2_dummy2_0_read__193_AND_m_m__ETC___d1198;
|
|
3'd3:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_3_dummy2_0_read__199_AND_m_m__ETC___d1204;
|
|
3'd4:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_4_dummy2_0_read__205_AND_m_m__ETC___d1210;
|
|
3'd5:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_5_dummy2_0_read__211_AND_m_m__ETC___d1216;
|
|
3'd6:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_6_dummy2_0_read__217_AND_m_m__ETC___d1222;
|
|
3'd7:
|
|
SEL_ARR_m_m_succValidVec_0_dummy2_0_read__181__ETC___d1230 =
|
|
m_m_succValidVec_7_dummy2_0$Q_OUT &&
|
|
m_m_succValidVec_7_dummy2_1$Q_OUT &&
|
|
m_m_succValidVec_7_dummy2_2$Q_OUT &&
|
|
m_m_succValidVec_7_rl;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_cRq_getSlot_n or
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083 or
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085 or
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087 or
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089 or
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091 or
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093 or
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095 or
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097)
|
|
begin
|
|
case (sendRsToP_cRq_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083;
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085;
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087;
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089;
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091;
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093;
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095;
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1099 =
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097;
|
|
endcase
|
|
end
|
|
always@(sendRqToP_getSlot_n or
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083 or
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085 or
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087 or
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089 or
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091 or
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093 or
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095 or
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097)
|
|
begin
|
|
case (sendRqToP_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083;
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085;
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087;
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089;
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091;
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093;
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095;
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1102 =
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getSlot_n or
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083 or
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085 or
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087 or
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089 or
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091 or
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093 or
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095 or
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097)
|
|
begin
|
|
case (pipelineResp_getSlot_n)
|
|
3'd0:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_0_dummy2_0_read__006_AND_m_m_slotV_ETC___d1083;
|
|
3'd1:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_1_dummy2_0_read__013_AND_m_m_slotV_ETC___d1085;
|
|
3'd2:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_2_dummy2_0_read__020_AND_m_m_slotV_ETC___d1087;
|
|
3'd3:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_3_dummy2_0_read__027_AND_m_m_slotV_ETC___d1089;
|
|
3'd4:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_4_dummy2_0_read__034_AND_m_m_slotV_ETC___d1091;
|
|
3'd5:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_5_dummy2_0_read__041_AND_m_m_slotV_ETC___d1093;
|
|
3'd6:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_6_dummy2_0_read__048_AND_m_m_slotV_ETC___d1095;
|
|
3'd7:
|
|
SEL_ARR_m_m_slotVec_0_dummy2_0_read__006_AND_m_ETC___d1154 =
|
|
m_m_slotVec_7_dummy2_0_read__055_AND_m_m_slotV_ETC___d1097;
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
NOT_m_m_resultVec_0_dummy2_1_read__92_93_OR_NO_ETC___d897 or
|
|
NOT_m_m_resultVec_1_dummy2_1_read__98_99_OR_NO_ETC___d903 or
|
|
NOT_m_m_resultVec_2_dummy2_1_read__04_05_OR_NO_ETC___d909 or
|
|
NOT_m_m_resultVec_3_dummy2_1_read__10_11_OR_NO_ETC___d915 or
|
|
NOT_m_m_resultVec_4_dummy2_1_read__16_17_OR_NO_ETC___d921 or
|
|
NOT_m_m_resultVec_5_dummy2_1_read__22_23_OR_NO_ETC___d927 or
|
|
NOT_m_m_resultVec_6_dummy2_1_read__28_29_OR_NO_ETC___d933 or
|
|
NOT_m_m_resultVec_7_dummy2_1_read__34_35_OR_NO_ETC___d939)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_0_dummy2_1_read__92_93_OR_NO_ETC___d897;
|
|
3'd1:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_1_dummy2_1_read__98_99_OR_NO_ETC___d903;
|
|
3'd2:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_2_dummy2_1_read__04_05_OR_NO_ETC___d909;
|
|
3'd3:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_3_dummy2_1_read__10_11_OR_NO_ETC___d915;
|
|
3'd4:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_4_dummy2_1_read__16_17_OR_NO_ETC___d921;
|
|
3'd5:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_5_dummy2_1_read__22_23_OR_NO_ETC___d927;
|
|
3'd6:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_6_dummy2_1_read__28_29_OR_NO_ETC___d933;
|
|
3'd7:
|
|
SEL_ARR_NOT_m_m_resultVec_0_dummy2_1_read__92__ETC___d941 =
|
|
NOT_m_m_resultVec_7_dummy2_1_read__34_35_OR_NO_ETC___d939;
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
m_m_resultVec_0_lat_0$whas or
|
|
m_m_resultVec_0_lat_0$wget or
|
|
m_m_resultVec_0_rl or
|
|
m_m_resultVec_1_lat_0$whas or
|
|
m_m_resultVec_1_rl or
|
|
m_m_resultVec_2_lat_0$whas or
|
|
m_m_resultVec_2_rl or
|
|
m_m_resultVec_3_lat_0$whas or
|
|
m_m_resultVec_3_rl or
|
|
m_m_resultVec_4_lat_0$whas or
|
|
m_m_resultVec_4_rl or
|
|
m_m_resultVec_5_lat_0$whas or
|
|
m_m_resultVec_5_rl or
|
|
m_m_resultVec_6_lat_0$whas or
|
|
m_m_resultVec_6_rl or
|
|
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_0_rl[65];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_1_rl[65];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_2_rl[65];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_3_rl[65];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_4_rl[65];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_5_rl[65];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_6_rl[65];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d944 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[65] :
|
|
!m_m_resultVec_7_rl[65];
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
m_m_resultVec_0_lat_0$whas or
|
|
m_m_resultVec_0_lat_0$wget or
|
|
m_m_resultVec_0_rl or
|
|
m_m_resultVec_1_lat_0$whas or
|
|
m_m_resultVec_1_rl or
|
|
m_m_resultVec_2_lat_0$whas or
|
|
m_m_resultVec_2_rl or
|
|
m_m_resultVec_3_lat_0$whas or
|
|
m_m_resultVec_3_rl or
|
|
m_m_resultVec_4_lat_0$whas or
|
|
m_m_resultVec_4_rl or
|
|
m_m_resultVec_5_lat_0$whas or
|
|
m_m_resultVec_5_rl or
|
|
m_m_resultVec_6_lat_0$whas or
|
|
m_m_resultVec_6_rl or
|
|
m_m_resultVec_7_lat_0$whas or m_m_resultVec_7_rl)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_0_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_0_rl[32];
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_1_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_1_rl[32];
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_2_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_2_rl[32];
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_3_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_3_rl[32];
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_4_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_4_rl[32];
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_5_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_5_rl[32];
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_6_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_6_rl[32];
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d950 =
|
|
m_m_resultVec_7_lat_0$whas ?
|
|
!m_m_resultVec_0_lat_0$wget[32] :
|
|
!m_m_resultVec_7_rl[32];
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280 or
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348 or
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416 or
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484 or
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552 or
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620 or
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688 or
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d280;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d348;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d416;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d484;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d552;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d620;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d688;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d947 =
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d756;
|
|
endcase
|
|
end
|
|
always@(sendRsToC_getResult_n or
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302 or
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370 or
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438 or
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506 or
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574 or
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642 or
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710 or
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778)
|
|
begin
|
|
case (sendRsToC_getResult_n)
|
|
3'd0:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_0_lat_0_whas__47_THEN_m_m_res_ETC___d302;
|
|
3'd1:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_1_lat_0_whas__15_THEN_m_m_res_ETC___d370;
|
|
3'd2:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_2_lat_0_whas__83_THEN_m_m_res_ETC___d438;
|
|
3'd3:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_3_lat_0_whas__51_THEN_m_m_res_ETC___d506;
|
|
3'd4:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_4_lat_0_whas__19_THEN_m_m_res_ETC___d574;
|
|
3'd5:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_5_lat_0_whas__87_THEN_m_m_res_ETC___d642;
|
|
3'd6:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_6_lat_0_whas__55_THEN_m_m_res_ETC___d710;
|
|
3'd7:
|
|
SEL_ARR_IF_m_m_resultVec_0_lat_0_whas__47_THEN_ETC___d953 =
|
|
IF_m_m_resultVec_7_lat_0_whas__23_THEN_m_m_res_ETC___d778;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_0_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_1_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_2_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_3_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_4_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_5_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_6_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_7_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY 56'h55555555555554;
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_initIdx$EN)
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
|
|
if (m_m_inited$EN)
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
|
|
if (m_m_reqVec_0_rl$EN)
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
|
|
if (m_m_reqVec_1_rl$EN)
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
|
|
if (m_m_reqVec_2_rl$EN)
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
|
|
if (m_m_reqVec_3_rl$EN)
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
|
|
if (m_m_reqVec_4_rl$EN)
|
|
m_m_reqVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_4_rl$D_IN;
|
|
if (m_m_reqVec_5_rl$EN)
|
|
m_m_reqVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_5_rl$D_IN;
|
|
if (m_m_reqVec_6_rl$EN)
|
|
m_m_reqVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_6_rl$D_IN;
|
|
if (m_m_reqVec_7_rl$EN)
|
|
m_m_reqVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_7_rl$D_IN;
|
|
if (m_m_resultVec_0_rl$EN)
|
|
m_m_resultVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_0_rl$D_IN;
|
|
if (m_m_resultVec_1_rl$EN)
|
|
m_m_resultVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_1_rl$D_IN;
|
|
if (m_m_resultVec_2_rl$EN)
|
|
m_m_resultVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_2_rl$D_IN;
|
|
if (m_m_resultVec_3_rl$EN)
|
|
m_m_resultVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_3_rl$D_IN;
|
|
if (m_m_resultVec_4_rl$EN)
|
|
m_m_resultVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_4_rl$D_IN;
|
|
if (m_m_resultVec_5_rl$EN)
|
|
m_m_resultVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_5_rl$D_IN;
|
|
if (m_m_resultVec_6_rl$EN)
|
|
m_m_resultVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_6_rl$D_IN;
|
|
if (m_m_resultVec_7_rl$EN)
|
|
m_m_resultVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_resultVec_7_rl$D_IN;
|
|
if (m_m_slotVec_0_rl$EN)
|
|
m_m_slotVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_0_rl$D_IN;
|
|
if (m_m_slotVec_1_rl$EN)
|
|
m_m_slotVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_1_rl$D_IN;
|
|
if (m_m_slotVec_2_rl$EN)
|
|
m_m_slotVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_2_rl$D_IN;
|
|
if (m_m_slotVec_3_rl$EN)
|
|
m_m_slotVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_3_rl$D_IN;
|
|
if (m_m_slotVec_4_rl$EN)
|
|
m_m_slotVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_4_rl$D_IN;
|
|
if (m_m_slotVec_5_rl$EN)
|
|
m_m_slotVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_5_rl$D_IN;
|
|
if (m_m_slotVec_6_rl$EN)
|
|
m_m_slotVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_6_rl$D_IN;
|
|
if (m_m_slotVec_7_rl$EN)
|
|
m_m_slotVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_slotVec_7_rl$D_IN;
|
|
if (m_m_stateVec_0_rl$EN)
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
|
|
if (m_m_stateVec_1_rl$EN)
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
|
|
if (m_m_stateVec_2_rl$EN)
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
|
|
if (m_m_stateVec_3_rl$EN)
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
|
|
if (m_m_stateVec_4_rl$EN)
|
|
m_m_stateVec_4_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_4_rl$D_IN;
|
|
if (m_m_stateVec_5_rl$EN)
|
|
m_m_stateVec_5_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_5_rl$D_IN;
|
|
if (m_m_stateVec_6_rl$EN)
|
|
m_m_stateVec_6_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_6_rl$D_IN;
|
|
if (m_m_stateVec_7_rl$EN)
|
|
m_m_stateVec_7_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_7_rl$D_IN;
|
|
if (m_m_succValidVec_0_rl$EN)
|
|
m_m_succValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_0_rl$D_IN;
|
|
if (m_m_succValidVec_1_rl$EN)
|
|
m_m_succValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_1_rl$D_IN;
|
|
if (m_m_succValidVec_2_rl$EN)
|
|
m_m_succValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_2_rl$D_IN;
|
|
if (m_m_succValidVec_3_rl$EN)
|
|
m_m_succValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_3_rl$D_IN;
|
|
if (m_m_succValidVec_4_rl$EN)
|
|
m_m_succValidVec_4_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_4_rl$D_IN;
|
|
if (m_m_succValidVec_5_rl$EN)
|
|
m_m_succValidVec_5_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_5_rl$D_IN;
|
|
if (m_m_succValidVec_6_rl$EN)
|
|
m_m_succValidVec_6_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_6_rl$D_IN;
|
|
if (m_m_succValidVec_7_rl$EN)
|
|
m_m_succValidVec_7_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_succValidVec_7_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_initIdx = 3'h2;
|
|
m_m_inited = 1'h0;
|
|
m_m_reqVec_0_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_4_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_5_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_6_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_7_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_0_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_1_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_2_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_3_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_4_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_5_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_6_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_resultVec_7_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
m_m_slotVec_0_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_1_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_2_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_3_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_4_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_5_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_6_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_slotVec_7_rl = 56'hAAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl = 3'h2;
|
|
m_m_stateVec_1_rl = 3'h2;
|
|
m_m_stateVec_2_rl = 3'h2;
|
|
m_m_stateVec_3_rl = 3'h2;
|
|
m_m_stateVec_4_rl = 3'h2;
|
|
m_m_stateVec_5_rl = 3'h2;
|
|
m_m_stateVec_6_rl = 3'h2;
|
|
m_m_stateVec_7_rl = 3'h2;
|
|
m_m_succValidVec_0_rl = 1'h0;
|
|
m_m_succValidVec_1_rl = 1'h0;
|
|
m_m_succValidVec_2_rl = 1'h0;
|
|
m_m_succValidVec_3_rl = 1'h0;
|
|
m_m_succValidVec_4_rl = 1'h0;
|
|
m_m_succValidVec_5_rl = 1'h0;
|
|
m_m_succValidVec_6_rl = 1'h0;
|
|
m_m_succValidVec_7_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_pipelineResp_setStateSlot &&
|
|
pipelineResp_setStateSlot_state == 3'd0)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkICRqMshrWrapper
|
|
|