735 lines
24 KiB
Verilog
735 lines
24 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_to_proc_request_put O 1
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// to_proc_response_get O 66
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// RDY_to_proc_response_get O 1
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 66
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// to_parent_rsToP_notEmpty O 1
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// RDY_to_parent_rsToP_notEmpty O 1 const
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// RDY_to_parent_rsToP_deq O 1
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// to_parent_rsToP_first O 579
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// RDY_to_parent_rsToP_first O 1
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// to_parent_rqToP_notEmpty O 1
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// RDY_to_parent_rqToP_notEmpty O 1 const
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// RDY_to_parent_rqToP_deq O 1
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// to_parent_rqToP_first O 72
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// RDY_to_parent_rqToP_first O 1
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// to_parent_fromP_notFull O 1
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// RDY_to_parent_fromP_notFull O 1 const
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// RDY_to_parent_fromP_enq O 1
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// cRqStuck_get O 68 const
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// RDY_cRqStuck_get O 1 const
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// pRqStuck_get O 68 const
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// RDY_pRqStuck_get O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// to_proc_request_put I 64
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 2
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// to_parent_fromP_enq_x I 583
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// EN_to_proc_request_put I 1
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// EN_flush I 1 unused
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_to_parent_rsToP_deq I 1
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// EN_to_parent_rqToP_deq I 1
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// EN_to_parent_fromP_enq I 1
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// EN_to_proc_response_get I 1
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// EN_perf_resp I 1
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// EN_cRqStuck_get I 1 unused
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// EN_pRqStuck_get I 1 unused
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkICoCache(CLK,
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RST_N,
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to_proc_request_put,
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EN_to_proc_request_put,
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RDY_to_proc_request_put,
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EN_to_proc_response_get,
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to_proc_response_get,
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RDY_to_proc_response_get,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid,
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to_parent_rsToP_notEmpty,
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RDY_to_parent_rsToP_notEmpty,
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EN_to_parent_rsToP_deq,
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RDY_to_parent_rsToP_deq,
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to_parent_rsToP_first,
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RDY_to_parent_rsToP_first,
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to_parent_rqToP_notEmpty,
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RDY_to_parent_rqToP_notEmpty,
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EN_to_parent_rqToP_deq,
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RDY_to_parent_rqToP_deq,
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to_parent_rqToP_first,
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RDY_to_parent_rqToP_first,
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to_parent_fromP_notFull,
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RDY_to_parent_fromP_notFull,
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to_parent_fromP_enq_x,
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EN_to_parent_fromP_enq,
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RDY_to_parent_fromP_enq,
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EN_cRqStuck_get,
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cRqStuck_get,
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RDY_cRqStuck_get,
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EN_pRqStuck_get,
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pRqStuck_get,
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RDY_pRqStuck_get);
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input CLK;
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input RST_N;
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// action method to_proc_request_put
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input [63 : 0] to_proc_request_put;
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input EN_to_proc_request_put;
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output RDY_to_proc_request_put;
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// actionvalue method to_proc_response_get
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input EN_to_proc_response_get;
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output [65 : 0] to_proc_response_get;
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output RDY_to_proc_response_get;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [1 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [65 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// value method to_parent_rsToP_notEmpty
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output to_parent_rsToP_notEmpty;
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output RDY_to_parent_rsToP_notEmpty;
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// action method to_parent_rsToP_deq
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input EN_to_parent_rsToP_deq;
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output RDY_to_parent_rsToP_deq;
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// value method to_parent_rsToP_first
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output [578 : 0] to_parent_rsToP_first;
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output RDY_to_parent_rsToP_first;
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// value method to_parent_rqToP_notEmpty
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output to_parent_rqToP_notEmpty;
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output RDY_to_parent_rqToP_notEmpty;
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// action method to_parent_rqToP_deq
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input EN_to_parent_rqToP_deq;
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output RDY_to_parent_rqToP_deq;
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// value method to_parent_rqToP_first
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output [71 : 0] to_parent_rqToP_first;
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output RDY_to_parent_rqToP_first;
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// value method to_parent_fromP_notFull
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output to_parent_fromP_notFull;
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output RDY_to_parent_fromP_notFull;
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// action method to_parent_fromP_enq
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input [582 : 0] to_parent_fromP_enq_x;
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input EN_to_parent_fromP_enq;
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output RDY_to_parent_fromP_enq;
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// actionvalue method cRqStuck_get
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input EN_cRqStuck_get;
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output [67 : 0] cRqStuck_get;
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output RDY_cRqStuck_get;
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// actionvalue method pRqStuck_get
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input EN_pRqStuck_get;
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output [67 : 0] pRqStuck_get;
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output RDY_pRqStuck_get;
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// signals for module outputs
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wire [578 : 0] to_parent_rsToP_first;
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wire [71 : 0] to_parent_rqToP_first;
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wire [67 : 0] cRqStuck_get, pRqStuck_get;
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wire [65 : 0] perf_resp, to_proc_response_get;
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wire RDY_cRqStuck_get,
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RDY_flush,
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RDY_flush_done,
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RDY_pRqStuck_get,
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RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_to_parent_fromP_enq,
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RDY_to_parent_fromP_notFull,
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RDY_to_parent_rqToP_deq,
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RDY_to_parent_rqToP_first,
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RDY_to_parent_rqToP_notEmpty,
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RDY_to_parent_rsToP_deq,
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RDY_to_parent_rsToP_first,
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RDY_to_parent_rsToP_notEmpty,
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RDY_to_proc_request_put,
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RDY_to_proc_response_get,
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flush_done,
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perf_respValid,
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to_parent_fromP_notFull,
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to_parent_rqToP_notEmpty,
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to_parent_rsToP_notEmpty;
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// inlined wires
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wire [2 : 0] perfReqQ_enqReq_lat_0$wget;
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// register perfReqQ_clearReq_rl
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reg perfReqQ_clearReq_rl;
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wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
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// register perfReqQ_data_0
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reg [1 : 0] perfReqQ_data_0;
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wire [1 : 0] perfReqQ_data_0$D_IN;
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wire perfReqQ_data_0$EN;
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// register perfReqQ_deqReq_rl
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reg perfReqQ_deqReq_rl;
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wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
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// register perfReqQ_empty
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reg perfReqQ_empty;
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wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
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// register perfReqQ_enqReq_rl
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reg [2 : 0] perfReqQ_enqReq_rl;
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wire [2 : 0] perfReqQ_enqReq_rl$D_IN;
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wire perfReqQ_enqReq_rl$EN;
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// register perfReqQ_full
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reg perfReqQ_full;
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wire perfReqQ_full$D_IN, perfReqQ_full$EN;
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// ports of submodule cache
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wire [582 : 0] cache$to_parent_fromP_enq_x;
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wire [578 : 0] cache$to_parent_rsToP_first;
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wire [71 : 0] cache$to_parent_rqToP_first;
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wire [67 : 0] cache$cRqStuck_get, cache$pRqStuck_get;
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wire [65 : 0] cache$to_proc_resp_get;
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wire [63 : 0] cache$to_proc_req_put;
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wire [1 : 0] cache$getPerfData_t;
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wire cache$EN_cRqStuck_get,
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cache$EN_flush,
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cache$EN_pRqStuck_get,
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cache$EN_setPerfStatus,
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cache$EN_to_parent_fromP_enq,
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cache$EN_to_parent_rqToP_deq,
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cache$EN_to_parent_rsToP_deq,
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cache$EN_to_proc_req_put,
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cache$EN_to_proc_resp_get,
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cache$RDY_cRqStuck_get,
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cache$RDY_pRqStuck_get,
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cache$RDY_to_parent_fromP_enq,
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cache$RDY_to_parent_rqToP_deq,
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cache$RDY_to_parent_rqToP_first,
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cache$RDY_to_parent_rsToP_deq,
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cache$RDY_to_parent_rsToP_first,
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cache$RDY_to_proc_req_put,
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cache$RDY_to_proc_resp_get,
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cache$flush_done,
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cache$setPerfStatus_stats,
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cache$to_parent_fromP_notFull,
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cache$to_parent_rqToP_notEmpty,
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cache$to_parent_rsToP_notEmpty;
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// ports of submodule perfReqQ_clearReq_dummy2_0
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wire perfReqQ_clearReq_dummy2_0$D_IN, perfReqQ_clearReq_dummy2_0$EN;
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// ports of submodule perfReqQ_clearReq_dummy2_1
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wire perfReqQ_clearReq_dummy2_1$D_IN,
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perfReqQ_clearReq_dummy2_1$EN,
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perfReqQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule perfReqQ_deqReq_dummy2_0
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wire perfReqQ_deqReq_dummy2_0$D_IN, perfReqQ_deqReq_dummy2_0$EN;
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// ports of submodule perfReqQ_deqReq_dummy2_1
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wire perfReqQ_deqReq_dummy2_1$D_IN, perfReqQ_deqReq_dummy2_1$EN;
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// ports of submodule perfReqQ_deqReq_dummy2_2
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wire perfReqQ_deqReq_dummy2_2$D_IN,
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perfReqQ_deqReq_dummy2_2$EN,
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perfReqQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule perfReqQ_enqReq_dummy2_0
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wire perfReqQ_enqReq_dummy2_0$D_IN, perfReqQ_enqReq_dummy2_0$EN;
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// ports of submodule perfReqQ_enqReq_dummy2_1
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wire perfReqQ_enqReq_dummy2_1$D_IN, perfReqQ_enqReq_dummy2_1$EN;
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// ports of submodule perfReqQ_enqReq_dummy2_2
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wire perfReqQ_enqReq_dummy2_2$D_IN,
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perfReqQ_enqReq_dummy2_2$EN,
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perfReqQ_enqReq_dummy2_2$Q_OUT;
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// rule scheduling signals
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wire CAN_FIRE_RL_perfReqQ_canonicalize,
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CAN_FIRE_RL_perfReqQ_clearReq_canon,
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CAN_FIRE_RL_perfReqQ_deqReq_canon,
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CAN_FIRE_RL_perfReqQ_enqReq_canon,
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CAN_FIRE_cRqStuck_get,
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CAN_FIRE_flush,
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CAN_FIRE_pRqStuck_get,
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CAN_FIRE_perf_req,
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CAN_FIRE_perf_resp,
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CAN_FIRE_perf_setStatus,
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CAN_FIRE_to_parent_fromP_enq,
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CAN_FIRE_to_parent_rqToP_deq,
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CAN_FIRE_to_parent_rsToP_deq,
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CAN_FIRE_to_proc_request_put,
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CAN_FIRE_to_proc_response_get,
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WILL_FIRE_RL_perfReqQ_canonicalize,
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WILL_FIRE_RL_perfReqQ_clearReq_canon,
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WILL_FIRE_RL_perfReqQ_deqReq_canon,
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WILL_FIRE_RL_perfReqQ_enqReq_canon,
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WILL_FIRE_cRqStuck_get,
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WILL_FIRE_flush,
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WILL_FIRE_pRqStuck_get,
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WILL_FIRE_perf_req,
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WILL_FIRE_perf_resp,
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WILL_FIRE_perf_setStatus,
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WILL_FIRE_to_parent_fromP_enq,
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WILL_FIRE_to_parent_rqToP_deq,
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WILL_FIRE_to_parent_rsToP_deq,
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WILL_FIRE_to_proc_request_put,
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WILL_FIRE_to_proc_response_get;
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// remaining internal signals
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wire IF_perfReqQ_enqReq_lat_1_whas_THEN_perfReqQ_en_ETC___d13,
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NOT_perfReqQ_clearReq_dummy2_1_read__8_9_OR_IF_ETC___d53,
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NOT_perfReqQ_enqReq_dummy2_2_read__4_9_OR_IF_p_ETC___d74,
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perfReqQ_enqReq_dummy2_2_read__4_AND_IF_perfRe_ETC___d66;
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// action method to_proc_request_put
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assign RDY_to_proc_request_put = cache$RDY_to_proc_req_put ;
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assign CAN_FIRE_to_proc_request_put = cache$RDY_to_proc_req_put ;
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assign WILL_FIRE_to_proc_request_put = EN_to_proc_request_put ;
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// actionvalue method to_proc_response_get
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assign to_proc_response_get =
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{ cache$to_proc_resp_get[65],
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cache$to_proc_resp_get[65] ?
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cache$to_proc_resp_get[64:33] :
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32'hAAAAAAAA,
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cache$to_proc_resp_get[32],
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cache$to_proc_resp_get[32] ?
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cache$to_proc_resp_get[31:0] :
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32'hAAAAAAAA } ;
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assign RDY_to_proc_response_get = cache$RDY_to_proc_resp_get ;
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assign CAN_FIRE_to_proc_response_get = cache$RDY_to_proc_resp_get ;
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assign WILL_FIRE_to_proc_response_get = EN_to_proc_response_get ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = cache$flush_done ;
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assign RDY_flush_done = 1'd1 ;
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// action method perf_setStatus
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assign RDY_perf_setStatus = 1'd1 ;
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assign CAN_FIRE_perf_setStatus = 1'd1 ;
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assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
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// action method perf_req
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assign RDY_perf_req = !perfReqQ_full ;
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assign CAN_FIRE_perf_req = !perfReqQ_full ;
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assign WILL_FIRE_perf_req = EN_perf_req ;
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// actionvalue method perf_resp
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assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
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assign RDY_perf_resp = !perfReqQ_empty ;
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assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
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assign WILL_FIRE_perf_resp = EN_perf_resp ;
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// value method perf_respValid
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assign perf_respValid = !perfReqQ_empty ;
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assign RDY_perf_respValid = 1'd1 ;
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// value method to_parent_rsToP_notEmpty
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assign to_parent_rsToP_notEmpty = cache$to_parent_rsToP_notEmpty ;
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assign RDY_to_parent_rsToP_notEmpty = 1'd1 ;
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// action method to_parent_rsToP_deq
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assign RDY_to_parent_rsToP_deq = cache$RDY_to_parent_rsToP_deq ;
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assign CAN_FIRE_to_parent_rsToP_deq = cache$RDY_to_parent_rsToP_deq ;
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assign WILL_FIRE_to_parent_rsToP_deq = EN_to_parent_rsToP_deq ;
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// value method to_parent_rsToP_first
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assign to_parent_rsToP_first = cache$to_parent_rsToP_first ;
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assign RDY_to_parent_rsToP_first = cache$RDY_to_parent_rsToP_first ;
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// value method to_parent_rqToP_notEmpty
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assign to_parent_rqToP_notEmpty = cache$to_parent_rqToP_notEmpty ;
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assign RDY_to_parent_rqToP_notEmpty = 1'd1 ;
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// action method to_parent_rqToP_deq
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assign RDY_to_parent_rqToP_deq = cache$RDY_to_parent_rqToP_deq ;
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assign CAN_FIRE_to_parent_rqToP_deq = cache$RDY_to_parent_rqToP_deq ;
|
|
assign WILL_FIRE_to_parent_rqToP_deq = EN_to_parent_rqToP_deq ;
|
|
|
|
// value method to_parent_rqToP_first
|
|
assign to_parent_rqToP_first = cache$to_parent_rqToP_first ;
|
|
assign RDY_to_parent_rqToP_first = cache$RDY_to_parent_rqToP_first ;
|
|
|
|
// value method to_parent_fromP_notFull
|
|
assign to_parent_fromP_notFull = cache$to_parent_fromP_notFull ;
|
|
assign RDY_to_parent_fromP_notFull = 1'd1 ;
|
|
|
|
// action method to_parent_fromP_enq
|
|
assign RDY_to_parent_fromP_enq = cache$RDY_to_parent_fromP_enq ;
|
|
assign CAN_FIRE_to_parent_fromP_enq = cache$RDY_to_parent_fromP_enq ;
|
|
assign WILL_FIRE_to_parent_fromP_enq = EN_to_parent_fromP_enq ;
|
|
|
|
// actionvalue method cRqStuck_get
|
|
assign cRqStuck_get = cache$cRqStuck_get ;
|
|
assign RDY_cRqStuck_get = cache$RDY_cRqStuck_get ;
|
|
assign CAN_FIRE_cRqStuck_get = cache$RDY_cRqStuck_get ;
|
|
assign WILL_FIRE_cRqStuck_get = EN_cRqStuck_get ;
|
|
|
|
// actionvalue method pRqStuck_get
|
|
assign pRqStuck_get = cache$pRqStuck_get ;
|
|
assign RDY_pRqStuck_get = cache$RDY_pRqStuck_get ;
|
|
assign CAN_FIRE_pRqStuck_get = cache$RDY_pRqStuck_get ;
|
|
assign WILL_FIRE_pRqStuck_get = EN_pRqStuck_get ;
|
|
|
|
// submodule cache
|
|
mkIBankWrapper cache(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.getPerfData_t(cache$getPerfData_t),
|
|
.setPerfStatus_stats(cache$setPerfStatus_stats),
|
|
.to_parent_fromP_enq_x(cache$to_parent_fromP_enq_x),
|
|
.to_proc_req_put(cache$to_proc_req_put),
|
|
.EN_to_parent_rsToP_deq(cache$EN_to_parent_rsToP_deq),
|
|
.EN_to_parent_rqToP_deq(cache$EN_to_parent_rqToP_deq),
|
|
.EN_to_parent_fromP_enq(cache$EN_to_parent_fromP_enq),
|
|
.EN_to_proc_req_put(cache$EN_to_proc_req_put),
|
|
.EN_to_proc_resp_get(cache$EN_to_proc_resp_get),
|
|
.EN_cRqStuck_get(cache$EN_cRqStuck_get),
|
|
.EN_pRqStuck_get(cache$EN_pRqStuck_get),
|
|
.EN_flush(cache$EN_flush),
|
|
.EN_setPerfStatus(cache$EN_setPerfStatus),
|
|
.to_parent_rsToP_notEmpty(cache$to_parent_rsToP_notEmpty),
|
|
.RDY_to_parent_rsToP_notEmpty(),
|
|
.RDY_to_parent_rsToP_deq(cache$RDY_to_parent_rsToP_deq),
|
|
.to_parent_rsToP_first(cache$to_parent_rsToP_first),
|
|
.RDY_to_parent_rsToP_first(cache$RDY_to_parent_rsToP_first),
|
|
.to_parent_rqToP_notEmpty(cache$to_parent_rqToP_notEmpty),
|
|
.RDY_to_parent_rqToP_notEmpty(),
|
|
.RDY_to_parent_rqToP_deq(cache$RDY_to_parent_rqToP_deq),
|
|
.to_parent_rqToP_first(cache$to_parent_rqToP_first),
|
|
.RDY_to_parent_rqToP_first(cache$RDY_to_parent_rqToP_first),
|
|
.to_parent_fromP_notFull(cache$to_parent_fromP_notFull),
|
|
.RDY_to_parent_fromP_notFull(),
|
|
.RDY_to_parent_fromP_enq(cache$RDY_to_parent_fromP_enq),
|
|
.RDY_to_proc_req_put(cache$RDY_to_proc_req_put),
|
|
.to_proc_resp_get(cache$to_proc_resp_get),
|
|
.RDY_to_proc_resp_get(cache$RDY_to_proc_resp_get),
|
|
.cRqStuck_get(cache$cRqStuck_get),
|
|
.RDY_cRqStuck_get(cache$RDY_cRqStuck_get),
|
|
.pRqStuck_get(cache$pRqStuck_get),
|
|
.RDY_pRqStuck_get(cache$RDY_pRqStuck_get),
|
|
.RDY_flush(),
|
|
.flush_done(cache$flush_done),
|
|
.RDY_flush_done(),
|
|
.RDY_setPerfStatus(),
|
|
.getPerfData(),
|
|
.RDY_getPerfData());
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) perfReqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(perfReqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(perfReqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) perfReqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(perfReqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(perfReqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(perfReqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(perfReqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(perfReqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(perfReqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(perfReqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(perfReqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(perfReqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(perfReqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(perfReqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(perfReqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(perfReqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(perfReqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(perfReqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(perfReqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(perfReqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// rule RL_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_data_0
|
|
assign perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[1:0] :
|
|
perfReqQ_enqReq_rl[1:0] ;
|
|
assign perfReqQ_data_0$EN =
|
|
NOT_perfReqQ_clearReq_dummy2_1_read__8_9_OR_IF_ETC___d53 &&
|
|
perfReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_perfReqQ_enqReq_lat_1_whas_THEN_perfReqQ_en_ETC___d13 ;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_empty
|
|
assign perfReqQ_empty$D_IN =
|
|
perfReqQ_clearReq_dummy2_1$Q_OUT && perfReqQ_clearReq_rl ||
|
|
NOT_perfReqQ_enqReq_dummy2_2_read__4_9_OR_IF_p_ETC___d74 ;
|
|
assign perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
assign perfReqQ_enqReq_rl$D_IN = 3'b010 ;
|
|
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_full
|
|
assign perfReqQ_full$D_IN =
|
|
NOT_perfReqQ_clearReq_dummy2_1_read__8_9_OR_IF_ETC___d53 &&
|
|
perfReqQ_enqReq_dummy2_2_read__4_AND_IF_perfRe_ETC___d66 ;
|
|
assign perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// submodule cache
|
|
assign cache$getPerfData_t = 2'h0 ;
|
|
assign cache$setPerfStatus_stats = perf_setStatus_doStats ;
|
|
assign cache$to_parent_fromP_enq_x = to_parent_fromP_enq_x ;
|
|
assign cache$to_proc_req_put = to_proc_request_put ;
|
|
assign cache$EN_to_parent_rsToP_deq = EN_to_parent_rsToP_deq ;
|
|
assign cache$EN_to_parent_rqToP_deq = EN_to_parent_rqToP_deq ;
|
|
assign cache$EN_to_parent_fromP_enq = EN_to_parent_fromP_enq ;
|
|
assign cache$EN_to_proc_req_put = EN_to_proc_request_put ;
|
|
assign cache$EN_to_proc_resp_get = EN_to_proc_response_get ;
|
|
assign cache$EN_cRqStuck_get = EN_cRqStuck_get ;
|
|
assign cache$EN_pRqStuck_get = EN_pRqStuck_get ;
|
|
assign cache$EN_flush = EN_flush ;
|
|
assign cache$EN_setPerfStatus = EN_perf_setStatus ;
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_0
|
|
assign perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_1
|
|
assign perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_0
|
|
assign perfReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign perfReqQ_deqReq_dummy2_0$EN = EN_perf_resp ;
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_1
|
|
assign perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_2
|
|
assign perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_0
|
|
assign perfReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign perfReqQ_enqReq_dummy2_0$EN = EN_perf_req ;
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_1
|
|
assign perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_2
|
|
assign perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_perfReqQ_enqReq_lat_1_whas_THEN_perfReqQ_en_ETC___d13 =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[2] :
|
|
perfReqQ_enqReq_rl[2] ;
|
|
assign NOT_perfReqQ_clearReq_dummy2_1_read__8_9_OR_IF_ETC___d53 =
|
|
!perfReqQ_clearReq_dummy2_1$Q_OUT || !perfReqQ_clearReq_rl ;
|
|
assign NOT_perfReqQ_enqReq_dummy2_2_read__4_9_OR_IF_p_ETC___d74 =
|
|
(!perfReqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_perf_req ?
|
|
!perfReqQ_enqReq_lat_0$wget[2] :
|
|
!perfReqQ_enqReq_rl[2])) &&
|
|
(perfReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_perf_resp || perfReqQ_deqReq_rl) ||
|
|
perfReqQ_empty) ;
|
|
assign perfReqQ_enqReq_dummy2_2_read__4_AND_IF_perfRe_ETC___d66 =
|
|
perfReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_perfReqQ_enqReq_lat_1_whas_THEN_perfReqQ_en_ETC___d13 ||
|
|
(!perfReqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_perf_resp && !perfReqQ_deqReq_rl) &&
|
|
perfReqQ_full ;
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 3'd2;
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (perfReqQ_clearReq_rl$EN)
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
perfReqQ_clearReq_rl$D_IN;
|
|
if (perfReqQ_data_0$EN)
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
|
|
if (perfReqQ_deqReq_rl$EN)
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
|
|
if (perfReqQ_empty$EN)
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
|
|
if (perfReqQ_enqReq_rl$EN)
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
|
|
if (perfReqQ_full$EN)
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
perfReqQ_clearReq_rl = 1'h0;
|
|
perfReqQ_data_0 = 2'h2;
|
|
perfReqQ_deqReq_rl = 1'h0;
|
|
perfReqQ_empty = 1'h0;
|
|
perfReqQ_enqReq_rl = 3'h2;
|
|
perfReqQ_full = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkICoCache
|
|
|