7758 lines
311 KiB
Verilog
7758 lines
311 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_updateVMInfo O 1 const
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// RDY_toChildren_rqFromC_put O 1
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// toChildren_rsToC_notEmpty O 1
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// RDY_toChildren_rsToC_notEmpty O 1 const
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// RDY_toChildren_rsToC_deq O 1
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// toChildren_rsToC_first O 84
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// RDY_toChildren_rsToC_first O 1
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// RDY_toChildren_iTlbReqFlush_put O 1
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// RDY_toChildren_dTlbReqFlush_put O 1
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// RDY_toChildren_flushDone_get O 1
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// toMem_memReq_notEmpty O 1
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// RDY_toMem_memReq_notEmpty O 1 const
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// RDY_toMem_memReq_deq O 1
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// toMem_memReq_first O 65
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// RDY_toMem_memReq_first O 1
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// toMem_respLd_notFull O 1
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// RDY_toMem_respLd_notFull O 1 const
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// RDY_toMem_respLd_enq O 1
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 68
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// updateVMInfo_vmI I 49 reg
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// updateVMInfo_vmD I 49 reg
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// toChildren_rqFromC_put I 30
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// toMem_respLd_enq_x I 65
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 4
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// EN_updateVMInfo I 1
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// EN_toChildren_rqFromC_put I 1
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// EN_toChildren_rsToC_deq I 1
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// EN_toChildren_iTlbReqFlush_put I 1
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// EN_toChildren_dTlbReqFlush_put I 1
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// EN_toChildren_flushDone_get I 1
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// EN_toMem_memReq_deq I 1
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// EN_toMem_respLd_enq I 1
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_perf_resp I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkL2Tlb(CLK,
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RST_N,
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updateVMInfo_vmI,
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updateVMInfo_vmD,
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EN_updateVMInfo,
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RDY_updateVMInfo,
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toChildren_rqFromC_put,
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EN_toChildren_rqFromC_put,
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RDY_toChildren_rqFromC_put,
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toChildren_rsToC_notEmpty,
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RDY_toChildren_rsToC_notEmpty,
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EN_toChildren_rsToC_deq,
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RDY_toChildren_rsToC_deq,
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toChildren_rsToC_first,
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RDY_toChildren_rsToC_first,
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EN_toChildren_iTlbReqFlush_put,
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RDY_toChildren_iTlbReqFlush_put,
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EN_toChildren_dTlbReqFlush_put,
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RDY_toChildren_dTlbReqFlush_put,
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EN_toChildren_flushDone_get,
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RDY_toChildren_flushDone_get,
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toMem_memReq_notEmpty,
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RDY_toMem_memReq_notEmpty,
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EN_toMem_memReq_deq,
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RDY_toMem_memReq_deq,
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toMem_memReq_first,
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RDY_toMem_memReq_first,
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toMem_respLd_notFull,
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RDY_toMem_respLd_notFull,
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toMem_respLd_enq_x,
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EN_toMem_respLd_enq,
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RDY_toMem_respLd_enq,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid);
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input CLK;
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input RST_N;
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// action method updateVMInfo
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input [48 : 0] updateVMInfo_vmI;
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input [48 : 0] updateVMInfo_vmD;
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input EN_updateVMInfo;
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output RDY_updateVMInfo;
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// action method toChildren_rqFromC_put
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input [29 : 0] toChildren_rqFromC_put;
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input EN_toChildren_rqFromC_put;
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output RDY_toChildren_rqFromC_put;
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// value method toChildren_rsToC_notEmpty
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output toChildren_rsToC_notEmpty;
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output RDY_toChildren_rsToC_notEmpty;
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// action method toChildren_rsToC_deq
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input EN_toChildren_rsToC_deq;
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output RDY_toChildren_rsToC_deq;
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// value method toChildren_rsToC_first
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output [83 : 0] toChildren_rsToC_first;
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output RDY_toChildren_rsToC_first;
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// action method toChildren_iTlbReqFlush_put
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input EN_toChildren_iTlbReqFlush_put;
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output RDY_toChildren_iTlbReqFlush_put;
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// action method toChildren_dTlbReqFlush_put
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input EN_toChildren_dTlbReqFlush_put;
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output RDY_toChildren_dTlbReqFlush_put;
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// action method toChildren_flushDone_get
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input EN_toChildren_flushDone_get;
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output RDY_toChildren_flushDone_get;
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// value method toMem_memReq_notEmpty
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output toMem_memReq_notEmpty;
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output RDY_toMem_memReq_notEmpty;
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// action method toMem_memReq_deq
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input EN_toMem_memReq_deq;
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output RDY_toMem_memReq_deq;
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// value method toMem_memReq_first
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output [64 : 0] toMem_memReq_first;
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output RDY_toMem_memReq_first;
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// value method toMem_respLd_notFull
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output toMem_respLd_notFull;
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output RDY_toMem_respLd_notFull;
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// action method toMem_respLd_enq
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input [64 : 0] toMem_respLd_enq_x;
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input EN_toMem_respLd_enq;
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output RDY_toMem_respLd_enq;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [3 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [67 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// signals for module outputs
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wire [83 : 0] toChildren_rsToC_first;
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wire [67 : 0] perf_resp;
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wire [64 : 0] toMem_memReq_first;
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wire RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_toChildren_dTlbReqFlush_put,
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RDY_toChildren_flushDone_get,
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RDY_toChildren_iTlbReqFlush_put,
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RDY_toChildren_rqFromC_put,
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RDY_toChildren_rsToC_deq,
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RDY_toChildren_rsToC_first,
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RDY_toChildren_rsToC_notEmpty,
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RDY_toMem_memReq_deq,
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RDY_toMem_memReq_first,
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RDY_toMem_memReq_notEmpty,
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RDY_toMem_respLd_enq,
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RDY_toMem_respLd_notFull,
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RDY_updateVMInfo,
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perf_respValid,
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toChildren_rsToC_notEmpty,
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toMem_memReq_notEmpty,
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toMem_respLd_notFull;
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// inlined wires
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wire [83 : 0] rsToCQ_data_0_lat_0$wget;
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wire [81 : 0] tlb4KB_m_pendReq_lat_1$wget;
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wire [65 : 0] memReqQ_enqReq_lat_0$wget, respLdQ_enqReq_lat_0$wget;
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wire [8 : 0] tlb4KB_m_pendIndex$wget;
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wire [4 : 0] perfReqQ_enqReq_lat_0$wget;
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wire [3 : 0] tlbMG_m_updRepIdx_lat_1$wget;
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wire [2 : 0] pendWait_0_lat_0$wget, pendWait_1_lat_0$wget;
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wire memReqQ_enqReq_lat_0$whas,
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pendValid_0_lat_0$whas,
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pendValid_0_lat_1$whas,
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pendValid_1_lat_0$whas,
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pendValid_1_lat_1$whas,
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pendWait_0_lat_0$whas,
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pendWait_1_lat_0$whas,
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respLdQ_deqReq_lat_0$whas,
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rsToCQ_data_0_lat_0$whas,
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rsToCQ_empty_lat_0$whas,
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rsToCQ_full_lat_0$whas,
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tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas,
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tlbMG_m_updRepIdx_lat_1$whas,
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transCacheReqQ_enqP_lat_0$whas;
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// register dFlushReq
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reg dFlushReq;
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wire dFlushReq$D_IN, dFlushReq$EN;
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// register flushDoneQ_clearReq_rl
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reg flushDoneQ_clearReq_rl;
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wire flushDoneQ_clearReq_rl$D_IN, flushDoneQ_clearReq_rl$EN;
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// register flushDoneQ_deqReq_rl
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reg flushDoneQ_deqReq_rl;
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wire flushDoneQ_deqReq_rl$D_IN, flushDoneQ_deqReq_rl$EN;
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// register flushDoneQ_empty
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reg flushDoneQ_empty;
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wire flushDoneQ_empty$D_IN, flushDoneQ_empty$EN;
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// register flushDoneQ_enqReq_rl
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reg flushDoneQ_enqReq_rl;
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wire flushDoneQ_enqReq_rl$D_IN, flushDoneQ_enqReq_rl$EN;
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// register flushDoneQ_full
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reg flushDoneQ_full;
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wire flushDoneQ_full$D_IN, flushDoneQ_full$EN;
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// register iFlushReq
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reg iFlushReq;
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wire iFlushReq$D_IN, iFlushReq$EN;
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// register memReqQ_clearReq_rl
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reg memReqQ_clearReq_rl;
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wire memReqQ_clearReq_rl$D_IN, memReqQ_clearReq_rl$EN;
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// register memReqQ_data_0
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reg [64 : 0] memReqQ_data_0;
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wire [64 : 0] memReqQ_data_0$D_IN;
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wire memReqQ_data_0$EN;
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// register memReqQ_data_1
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reg [64 : 0] memReqQ_data_1;
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wire [64 : 0] memReqQ_data_1$D_IN;
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wire memReqQ_data_1$EN;
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// register memReqQ_deqP
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reg memReqQ_deqP;
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wire memReqQ_deqP$D_IN, memReqQ_deqP$EN;
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// register memReqQ_deqReq_rl
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reg memReqQ_deqReq_rl;
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wire memReqQ_deqReq_rl$D_IN, memReqQ_deqReq_rl$EN;
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// register memReqQ_empty
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reg memReqQ_empty;
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wire memReqQ_empty$D_IN, memReqQ_empty$EN;
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// register memReqQ_enqP
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reg memReqQ_enqP;
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wire memReqQ_enqP$D_IN, memReqQ_enqP$EN;
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// register memReqQ_enqReq_rl
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reg [65 : 0] memReqQ_enqReq_rl;
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wire [65 : 0] memReqQ_enqReq_rl$D_IN;
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wire memReqQ_enqReq_rl$EN;
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// register memReqQ_full
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reg memReqQ_full;
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wire memReqQ_full$D_IN, memReqQ_full$EN;
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// register pendReq_0
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reg [29 : 0] pendReq_0;
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wire [29 : 0] pendReq_0$D_IN;
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wire pendReq_0$EN;
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// register pendReq_1
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reg [29 : 0] pendReq_1;
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wire [29 : 0] pendReq_1$D_IN;
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wire pendReq_1$EN;
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// register pendValid_0_rl
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reg pendValid_0_rl;
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wire pendValid_0_rl$D_IN, pendValid_0_rl$EN;
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// register pendValid_1_rl
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reg pendValid_1_rl;
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wire pendValid_1_rl$D_IN, pendValid_1_rl$EN;
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// register pendWait_0_rl
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reg [2 : 0] pendWait_0_rl;
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wire [2 : 0] pendWait_0_rl$D_IN;
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wire pendWait_0_rl$EN;
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// register pendWait_1_rl
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reg [2 : 0] pendWait_1_rl;
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wire [2 : 0] pendWait_1_rl$D_IN;
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wire pendWait_1_rl$EN;
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// register pendWalkAddr_0
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reg [63 : 0] pendWalkAddr_0;
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wire [63 : 0] pendWalkAddr_0$D_IN;
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wire pendWalkAddr_0$EN;
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// register pendWalkAddr_1
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reg [63 : 0] pendWalkAddr_1;
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wire [63 : 0] pendWalkAddr_1$D_IN;
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wire pendWalkAddr_1$EN;
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// register pendWalkLevel_0
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reg [1 : 0] pendWalkLevel_0;
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wire [1 : 0] pendWalkLevel_0$D_IN;
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wire pendWalkLevel_0$EN;
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// register pendWalkLevel_1
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reg [1 : 0] pendWalkLevel_1;
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wire [1 : 0] pendWalkLevel_1$D_IN;
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wire pendWalkLevel_1$EN;
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// register perfReqQ_clearReq_rl
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reg perfReqQ_clearReq_rl;
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wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
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// register perfReqQ_data_0
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reg [3 : 0] perfReqQ_data_0;
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wire [3 : 0] perfReqQ_data_0$D_IN;
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wire perfReqQ_data_0$EN;
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// register perfReqQ_deqReq_rl
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reg perfReqQ_deqReq_rl;
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wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
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// register perfReqQ_empty
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reg perfReqQ_empty;
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wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
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// register perfReqQ_enqReq_rl
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reg [4 : 0] perfReqQ_enqReq_rl;
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wire [4 : 0] perfReqQ_enqReq_rl$D_IN;
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wire perfReqQ_enqReq_rl$EN;
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// register perfReqQ_full
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reg perfReqQ_full;
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wire perfReqQ_full$D_IN, perfReqQ_full$EN;
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// register respForOtherReq
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reg [1 : 0] respForOtherReq;
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wire [1 : 0] respForOtherReq$D_IN;
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wire respForOtherReq$EN;
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// register respLdQ_clearReq_rl
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reg respLdQ_clearReq_rl;
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wire respLdQ_clearReq_rl$D_IN, respLdQ_clearReq_rl$EN;
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// register respLdQ_data_0
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reg [64 : 0] respLdQ_data_0;
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wire [64 : 0] respLdQ_data_0$D_IN;
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wire respLdQ_data_0$EN;
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// register respLdQ_data_1
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reg [64 : 0] respLdQ_data_1;
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wire [64 : 0] respLdQ_data_1$D_IN;
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wire respLdQ_data_1$EN;
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// register respLdQ_deqP
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reg respLdQ_deqP;
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wire respLdQ_deqP$D_IN, respLdQ_deqP$EN;
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// register respLdQ_deqReq_rl
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reg respLdQ_deqReq_rl;
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wire respLdQ_deqReq_rl$D_IN, respLdQ_deqReq_rl$EN;
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// register respLdQ_empty
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reg respLdQ_empty;
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wire respLdQ_empty$D_IN, respLdQ_empty$EN;
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// register respLdQ_enqP
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reg respLdQ_enqP;
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wire respLdQ_enqP$D_IN, respLdQ_enqP$EN;
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// register respLdQ_enqReq_rl
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reg [65 : 0] respLdQ_enqReq_rl;
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wire [65 : 0] respLdQ_enqReq_rl$D_IN;
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wire respLdQ_enqReq_rl$EN;
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// register respLdQ_full
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reg respLdQ_full;
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wire respLdQ_full$D_IN, respLdQ_full$EN;
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// register rqFromCQ_data_0_rl
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reg [29 : 0] rqFromCQ_data_0_rl;
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wire [29 : 0] rqFromCQ_data_0_rl$D_IN;
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wire rqFromCQ_data_0_rl$EN;
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// register rqFromCQ_empty_rl
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reg rqFromCQ_empty_rl;
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wire rqFromCQ_empty_rl$D_IN, rqFromCQ_empty_rl$EN;
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// register rqFromCQ_full_rl
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reg rqFromCQ_full_rl;
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wire rqFromCQ_full_rl$D_IN, rqFromCQ_full_rl$EN;
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// register rsToCQ_data_0_rl
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reg [83 : 0] rsToCQ_data_0_rl;
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wire [83 : 0] rsToCQ_data_0_rl$D_IN;
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wire rsToCQ_data_0_rl$EN;
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// register rsToCQ_empty_rl
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reg rsToCQ_empty_rl;
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wire rsToCQ_empty_rl$D_IN, rsToCQ_empty_rl$EN;
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// register rsToCQ_full_rl
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reg rsToCQ_full_rl;
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wire rsToCQ_full_rl$D_IN, rsToCQ_full_rl$EN;
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// register tlb4KB_m_flushIdx
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reg [7 : 0] tlb4KB_m_flushIdx;
|
|
wire [7 : 0] tlb4KB_m_flushIdx$D_IN;
|
|
wire tlb4KB_m_flushIdx$EN;
|
|
|
|
// register tlb4KB_m_pendReq_rl
|
|
reg [81 : 0] tlb4KB_m_pendReq_rl;
|
|
wire [81 : 0] tlb4KB_m_pendReq_rl$D_IN;
|
|
wire tlb4KB_m_pendReq_rl$EN;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_empty_rl
|
|
reg tlb4KB_m_repRam_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_full_rl
|
|
reg tlb4KB_m_repRam_rdReqQ_full_rl;
|
|
wire tlb4KB_m_repRam_rdReqQ_full_rl$D_IN, tlb4KB_m_repRam_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_state
|
|
reg tlb4KB_m_state;
|
|
wire tlb4KB_m_state$D_IN, tlb4KB_m_state$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_0_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_0_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_1_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_1_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_2_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_2_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_empty_rl
|
|
reg tlb4KB_m_tlbRam_3_rdReqQ_empty_rl;
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_full_rl
|
|
reg tlb4KB_m_tlbRam_3_rdReqQ_full_rl;
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN;
|
|
|
|
// register tlbMG_m_entryVec_0
|
|
reg [79 : 0] tlbMG_m_entryVec_0;
|
|
wire [79 : 0] tlbMG_m_entryVec_0$D_IN;
|
|
wire tlbMG_m_entryVec_0$EN;
|
|
|
|
// register tlbMG_m_entryVec_1
|
|
reg [79 : 0] tlbMG_m_entryVec_1;
|
|
wire [79 : 0] tlbMG_m_entryVec_1$D_IN;
|
|
wire tlbMG_m_entryVec_1$EN;
|
|
|
|
// register tlbMG_m_entryVec_2
|
|
reg [79 : 0] tlbMG_m_entryVec_2;
|
|
wire [79 : 0] tlbMG_m_entryVec_2$D_IN;
|
|
wire tlbMG_m_entryVec_2$EN;
|
|
|
|
// register tlbMG_m_entryVec_3
|
|
reg [79 : 0] tlbMG_m_entryVec_3;
|
|
wire [79 : 0] tlbMG_m_entryVec_3$D_IN;
|
|
wire tlbMG_m_entryVec_3$EN;
|
|
|
|
// register tlbMG_m_entryVec_4
|
|
reg [79 : 0] tlbMG_m_entryVec_4;
|
|
wire [79 : 0] tlbMG_m_entryVec_4$D_IN;
|
|
wire tlbMG_m_entryVec_4$EN;
|
|
|
|
// register tlbMG_m_entryVec_5
|
|
reg [79 : 0] tlbMG_m_entryVec_5;
|
|
wire [79 : 0] tlbMG_m_entryVec_5$D_IN;
|
|
wire tlbMG_m_entryVec_5$EN;
|
|
|
|
// register tlbMG_m_entryVec_6
|
|
reg [79 : 0] tlbMG_m_entryVec_6;
|
|
wire [79 : 0] tlbMG_m_entryVec_6$D_IN;
|
|
wire tlbMG_m_entryVec_6$EN;
|
|
|
|
// register tlbMG_m_entryVec_7
|
|
reg [79 : 0] tlbMG_m_entryVec_7;
|
|
wire [79 : 0] tlbMG_m_entryVec_7$D_IN;
|
|
wire tlbMG_m_entryVec_7$EN;
|
|
|
|
// register tlbMG_m_lruBit_rl
|
|
reg [7 : 0] tlbMG_m_lruBit_rl;
|
|
wire [7 : 0] tlbMG_m_lruBit_rl$D_IN;
|
|
wire tlbMG_m_lruBit_rl$EN;
|
|
|
|
// register tlbMG_m_randIdx
|
|
reg [2 : 0] tlbMG_m_randIdx;
|
|
wire [2 : 0] tlbMG_m_randIdx$D_IN;
|
|
wire tlbMG_m_randIdx$EN;
|
|
|
|
// register tlbMG_m_updRepIdx_rl
|
|
reg [3 : 0] tlbMG_m_updRepIdx_rl;
|
|
wire [3 : 0] tlbMG_m_updRepIdx_rl$D_IN;
|
|
wire tlbMG_m_updRepIdx_rl$EN;
|
|
|
|
// register tlbMG_m_validVec_0
|
|
reg tlbMG_m_validVec_0;
|
|
wire tlbMG_m_validVec_0$D_IN, tlbMG_m_validVec_0$EN;
|
|
|
|
// register tlbMG_m_validVec_1
|
|
reg tlbMG_m_validVec_1;
|
|
wire tlbMG_m_validVec_1$D_IN, tlbMG_m_validVec_1$EN;
|
|
|
|
// register tlbMG_m_validVec_2
|
|
reg tlbMG_m_validVec_2;
|
|
wire tlbMG_m_validVec_2$D_IN, tlbMG_m_validVec_2$EN;
|
|
|
|
// register tlbMG_m_validVec_3
|
|
reg tlbMG_m_validVec_3;
|
|
wire tlbMG_m_validVec_3$D_IN, tlbMG_m_validVec_3$EN;
|
|
|
|
// register tlbMG_m_validVec_4
|
|
reg tlbMG_m_validVec_4;
|
|
wire tlbMG_m_validVec_4$D_IN, tlbMG_m_validVec_4$EN;
|
|
|
|
// register tlbMG_m_validVec_5
|
|
reg tlbMG_m_validVec_5;
|
|
wire tlbMG_m_validVec_5$D_IN, tlbMG_m_validVec_5$EN;
|
|
|
|
// register tlbMG_m_validVec_6
|
|
reg tlbMG_m_validVec_6;
|
|
wire tlbMG_m_validVec_6$D_IN, tlbMG_m_validVec_6$EN;
|
|
|
|
// register tlbMG_m_validVec_7
|
|
reg tlbMG_m_validVec_7;
|
|
wire tlbMG_m_validVec_7$D_IN, tlbMG_m_validVec_7$EN;
|
|
|
|
// register tlbReqQ_data_0
|
|
reg tlbReqQ_data_0;
|
|
wire tlbReqQ_data_0$D_IN, tlbReqQ_data_0$EN;
|
|
|
|
// register tlbReqQ_empty_rl
|
|
reg tlbReqQ_empty_rl;
|
|
wire tlbReqQ_empty_rl$D_IN, tlbReqQ_empty_rl$EN;
|
|
|
|
// register tlbReqQ_full_rl
|
|
reg tlbReqQ_full_rl;
|
|
wire tlbReqQ_full_rl$D_IN, tlbReqQ_full_rl$EN;
|
|
|
|
// register transCacheReqQ_data_0
|
|
reg transCacheReqQ_data_0;
|
|
wire transCacheReqQ_data_0$D_IN, transCacheReqQ_data_0$EN;
|
|
|
|
// register transCacheReqQ_empty_rl
|
|
reg transCacheReqQ_empty_rl;
|
|
wire transCacheReqQ_empty_rl$D_IN, transCacheReqQ_empty_rl$EN;
|
|
|
|
// register transCacheReqQ_full_rl
|
|
reg transCacheReqQ_full_rl;
|
|
wire transCacheReqQ_full_rl$D_IN, transCacheReqQ_full_rl$EN;
|
|
|
|
// register vm_info_D
|
|
reg [48 : 0] vm_info_D;
|
|
wire [48 : 0] vm_info_D$D_IN;
|
|
wire vm_info_D$EN;
|
|
|
|
// register vm_info_I
|
|
reg [48 : 0] vm_info_I;
|
|
wire [48 : 0] vm_info_I$D_IN;
|
|
wire vm_info_I$EN;
|
|
|
|
// register waitFlushDone
|
|
reg waitFlushDone;
|
|
wire waitFlushDone$D_IN, waitFlushDone$EN;
|
|
|
|
// ports of submodule flushDoneQ_clearReq_dummy2_0
|
|
wire flushDoneQ_clearReq_dummy2_0$D_IN, flushDoneQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule flushDoneQ_clearReq_dummy2_1
|
|
wire flushDoneQ_clearReq_dummy2_1$D_IN,
|
|
flushDoneQ_clearReq_dummy2_1$EN,
|
|
flushDoneQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule flushDoneQ_deqReq_dummy2_0
|
|
wire flushDoneQ_deqReq_dummy2_0$D_IN, flushDoneQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule flushDoneQ_deqReq_dummy2_1
|
|
wire flushDoneQ_deqReq_dummy2_1$D_IN, flushDoneQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule flushDoneQ_deqReq_dummy2_2
|
|
wire flushDoneQ_deqReq_dummy2_2$D_IN,
|
|
flushDoneQ_deqReq_dummy2_2$EN,
|
|
flushDoneQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule flushDoneQ_enqReq_dummy2_0
|
|
wire flushDoneQ_enqReq_dummy2_0$D_IN, flushDoneQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule flushDoneQ_enqReq_dummy2_1
|
|
wire flushDoneQ_enqReq_dummy2_1$D_IN, flushDoneQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule flushDoneQ_enqReq_dummy2_2
|
|
wire flushDoneQ_enqReq_dummy2_2$D_IN,
|
|
flushDoneQ_enqReq_dummy2_2$EN,
|
|
flushDoneQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule memReqQ_clearReq_dummy2_0
|
|
wire memReqQ_clearReq_dummy2_0$D_IN, memReqQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule memReqQ_clearReq_dummy2_1
|
|
wire memReqQ_clearReq_dummy2_1$D_IN,
|
|
memReqQ_clearReq_dummy2_1$EN,
|
|
memReqQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule memReqQ_deqReq_dummy2_0
|
|
wire memReqQ_deqReq_dummy2_0$D_IN, memReqQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule memReqQ_deqReq_dummy2_1
|
|
wire memReqQ_deqReq_dummy2_1$D_IN, memReqQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule memReqQ_deqReq_dummy2_2
|
|
wire memReqQ_deqReq_dummy2_2$D_IN,
|
|
memReqQ_deqReq_dummy2_2$EN,
|
|
memReqQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule memReqQ_enqReq_dummy2_0
|
|
wire memReqQ_enqReq_dummy2_0$D_IN, memReqQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule memReqQ_enqReq_dummy2_1
|
|
wire memReqQ_enqReq_dummy2_1$D_IN, memReqQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule memReqQ_enqReq_dummy2_2
|
|
wire memReqQ_enqReq_dummy2_2$D_IN,
|
|
memReqQ_enqReq_dummy2_2$EN,
|
|
memReqQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule pendValid_0_dummy2_0
|
|
wire pendValid_0_dummy2_0$D_IN,
|
|
pendValid_0_dummy2_0$EN,
|
|
pendValid_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule pendValid_0_dummy2_1
|
|
wire pendValid_0_dummy2_1$D_IN,
|
|
pendValid_0_dummy2_1$EN,
|
|
pendValid_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule pendValid_1_dummy2_0
|
|
wire pendValid_1_dummy2_0$D_IN,
|
|
pendValid_1_dummy2_0$EN,
|
|
pendValid_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule pendValid_1_dummy2_1
|
|
wire pendValid_1_dummy2_1$D_IN,
|
|
pendValid_1_dummy2_1$EN,
|
|
pendValid_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule pendWait_0_dummy2_0
|
|
wire pendWait_0_dummy2_0$D_IN,
|
|
pendWait_0_dummy2_0$EN,
|
|
pendWait_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule pendWait_0_dummy2_1
|
|
wire pendWait_0_dummy2_1$D_IN,
|
|
pendWait_0_dummy2_1$EN,
|
|
pendWait_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule pendWait_1_dummy2_0
|
|
wire pendWait_1_dummy2_0$D_IN,
|
|
pendWait_1_dummy2_0$EN,
|
|
pendWait_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule pendWait_1_dummy2_1
|
|
wire pendWait_1_dummy2_1$D_IN,
|
|
pendWait_1_dummy2_1$EN,
|
|
pendWait_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule perfReqQ_clearReq_dummy2_0
|
|
wire perfReqQ_clearReq_dummy2_0$D_IN, perfReqQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule perfReqQ_clearReq_dummy2_1
|
|
wire perfReqQ_clearReq_dummy2_1$D_IN,
|
|
perfReqQ_clearReq_dummy2_1$EN,
|
|
perfReqQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule perfReqQ_deqReq_dummy2_0
|
|
wire perfReqQ_deqReq_dummy2_0$D_IN, perfReqQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule perfReqQ_deqReq_dummy2_1
|
|
wire perfReqQ_deqReq_dummy2_1$D_IN, perfReqQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule perfReqQ_deqReq_dummy2_2
|
|
wire perfReqQ_deqReq_dummy2_2$D_IN,
|
|
perfReqQ_deqReq_dummy2_2$EN,
|
|
perfReqQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule perfReqQ_enqReq_dummy2_0
|
|
wire perfReqQ_enqReq_dummy2_0$D_IN, perfReqQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule perfReqQ_enqReq_dummy2_1
|
|
wire perfReqQ_enqReq_dummy2_1$D_IN, perfReqQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule perfReqQ_enqReq_dummy2_2
|
|
wire perfReqQ_enqReq_dummy2_2$D_IN,
|
|
perfReqQ_enqReq_dummy2_2$EN,
|
|
perfReqQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule respLdQ_clearReq_dummy2_0
|
|
wire respLdQ_clearReq_dummy2_0$D_IN, respLdQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule respLdQ_clearReq_dummy2_1
|
|
wire respLdQ_clearReq_dummy2_1$D_IN,
|
|
respLdQ_clearReq_dummy2_1$EN,
|
|
respLdQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule respLdQ_deqReq_dummy2_0
|
|
wire respLdQ_deqReq_dummy2_0$D_IN, respLdQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule respLdQ_deqReq_dummy2_1
|
|
wire respLdQ_deqReq_dummy2_1$D_IN, respLdQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule respLdQ_deqReq_dummy2_2
|
|
wire respLdQ_deqReq_dummy2_2$D_IN,
|
|
respLdQ_deqReq_dummy2_2$EN,
|
|
respLdQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule respLdQ_enqReq_dummy2_0
|
|
wire respLdQ_enqReq_dummy2_0$D_IN, respLdQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule respLdQ_enqReq_dummy2_1
|
|
wire respLdQ_enqReq_dummy2_1$D_IN, respLdQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule respLdQ_enqReq_dummy2_2
|
|
wire respLdQ_enqReq_dummy2_2$D_IN,
|
|
respLdQ_enqReq_dummy2_2$EN,
|
|
respLdQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule rqFromCQ_data_0_dummy2_0
|
|
wire rqFromCQ_data_0_dummy2_0$D_IN, rqFromCQ_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule rqFromCQ_data_0_dummy2_1
|
|
wire rqFromCQ_data_0_dummy2_1$D_IN,
|
|
rqFromCQ_data_0_dummy2_1$EN,
|
|
rqFromCQ_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule rqFromCQ_deqP_dummy2_0
|
|
wire rqFromCQ_deqP_dummy2_0$D_IN, rqFromCQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule rqFromCQ_deqP_dummy2_1
|
|
wire rqFromCQ_deqP_dummy2_1$D_IN, rqFromCQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule rqFromCQ_empty_dummy2_0
|
|
wire rqFromCQ_empty_dummy2_0$D_IN, rqFromCQ_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule rqFromCQ_empty_dummy2_1
|
|
wire rqFromCQ_empty_dummy2_1$D_IN,
|
|
rqFromCQ_empty_dummy2_1$EN,
|
|
rqFromCQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule rqFromCQ_empty_dummy2_2
|
|
wire rqFromCQ_empty_dummy2_2$D_IN,
|
|
rqFromCQ_empty_dummy2_2$EN,
|
|
rqFromCQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule rqFromCQ_enqP_dummy2_0
|
|
wire rqFromCQ_enqP_dummy2_0$D_IN, rqFromCQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule rqFromCQ_enqP_dummy2_1
|
|
wire rqFromCQ_enqP_dummy2_1$D_IN, rqFromCQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule rqFromCQ_full_dummy2_0
|
|
wire rqFromCQ_full_dummy2_0$D_IN,
|
|
rqFromCQ_full_dummy2_0$EN,
|
|
rqFromCQ_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule rqFromCQ_full_dummy2_1
|
|
wire rqFromCQ_full_dummy2_1$D_IN,
|
|
rqFromCQ_full_dummy2_1$EN,
|
|
rqFromCQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule rqFromCQ_full_dummy2_2
|
|
wire rqFromCQ_full_dummy2_2$D_IN,
|
|
rqFromCQ_full_dummy2_2$EN,
|
|
rqFromCQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule rsToCQ_data_0_dummy2_0
|
|
wire rsToCQ_data_0_dummy2_0$D_IN, rsToCQ_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule rsToCQ_data_0_dummy2_1
|
|
wire rsToCQ_data_0_dummy2_1$D_IN,
|
|
rsToCQ_data_0_dummy2_1$EN,
|
|
rsToCQ_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule rsToCQ_deqP_dummy2_0
|
|
wire rsToCQ_deqP_dummy2_0$D_IN, rsToCQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule rsToCQ_deqP_dummy2_1
|
|
wire rsToCQ_deqP_dummy2_1$D_IN, rsToCQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule rsToCQ_empty_dummy2_0
|
|
wire rsToCQ_empty_dummy2_0$D_IN, rsToCQ_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule rsToCQ_empty_dummy2_1
|
|
wire rsToCQ_empty_dummy2_1$D_IN,
|
|
rsToCQ_empty_dummy2_1$EN,
|
|
rsToCQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule rsToCQ_empty_dummy2_2
|
|
wire rsToCQ_empty_dummy2_2$D_IN,
|
|
rsToCQ_empty_dummy2_2$EN,
|
|
rsToCQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule rsToCQ_enqP_dummy2_0
|
|
wire rsToCQ_enqP_dummy2_0$D_IN, rsToCQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule rsToCQ_enqP_dummy2_1
|
|
wire rsToCQ_enqP_dummy2_1$D_IN, rsToCQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule rsToCQ_full_dummy2_0
|
|
wire rsToCQ_full_dummy2_0$D_IN,
|
|
rsToCQ_full_dummy2_0$EN,
|
|
rsToCQ_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule rsToCQ_full_dummy2_1
|
|
wire rsToCQ_full_dummy2_1$D_IN,
|
|
rsToCQ_full_dummy2_1$EN,
|
|
rsToCQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule rsToCQ_full_dummy2_2
|
|
wire rsToCQ_full_dummy2_2$D_IN,
|
|
rsToCQ_full_dummy2_2$EN,
|
|
rsToCQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_pendReq_dummy2_0
|
|
wire tlb4KB_m_pendReq_dummy2_0$D_IN,
|
|
tlb4KB_m_pendReq_dummy2_0$EN,
|
|
tlb4KB_m_pendReq_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_pendReq_dummy2_1
|
|
wire tlb4KB_m_pendReq_dummy2_1$D_IN,
|
|
tlb4KB_m_pendReq_dummy2_1$EN,
|
|
tlb4KB_m_pendReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_bram
|
|
reg [7 : 0] tlb4KB_m_repRam_bram$ADDRA, tlb4KB_m_repRam_bram$DIA;
|
|
wire [7 : 0] tlb4KB_m_repRam_bram$ADDRB,
|
|
tlb4KB_m_repRam_bram$DIB,
|
|
tlb4KB_m_repRam_bram$DOB;
|
|
wire tlb4KB_m_repRam_bram$ENA,
|
|
tlb4KB_m_repRam_bram$ENB,
|
|
tlb4KB_m_repRam_bram$WEA,
|
|
tlb4KB_m_repRam_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0
|
|
wire tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1
|
|
wire tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_0
|
|
wire tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$EN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_1
|
|
wire tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$EN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_2
|
|
wire tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$EN,
|
|
tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0
|
|
wire tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1
|
|
wire tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_0
|
|
wire tlb4KB_m_repRam_rdReqQ_full_dummy2_0$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_1
|
|
wire tlb4KB_m_repRam_rdReqQ_full_dummy2_1$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_full_dummy2_1$EN,
|
|
tlb4KB_m_repRam_rdReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_2
|
|
wire tlb4KB_m_repRam_rdReqQ_full_dummy2_2$D_IN,
|
|
tlb4KB_m_repRam_rdReqQ_full_dummy2_2$EN,
|
|
tlb4KB_m_repRam_rdReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_0_bram$DIA,
|
|
tlb4KB_m_tlbRam_0_bram$DIB,
|
|
tlb4KB_m_tlbRam_0_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_0_bram$ADDRA, tlb4KB_m_tlbRam_0_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_0_bram$ENA,
|
|
tlb4KB_m_tlbRam_0_bram$ENB,
|
|
tlb4KB_m_tlbRam_0_bram$WEA,
|
|
tlb4KB_m_tlbRam_0_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$EN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2
|
|
wire tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_1_bram$DIA,
|
|
tlb4KB_m_tlbRam_1_bram$DIB,
|
|
tlb4KB_m_tlbRam_1_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_1_bram$ADDRA, tlb4KB_m_tlbRam_1_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_1_bram$ENA,
|
|
tlb4KB_m_tlbRam_1_bram$ENB,
|
|
tlb4KB_m_tlbRam_1_bram$WEA,
|
|
tlb4KB_m_tlbRam_1_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$EN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2
|
|
wire tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_2_bram$DIA,
|
|
tlb4KB_m_tlbRam_2_bram$DIB,
|
|
tlb4KB_m_tlbRam_2_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_2_bram$ADDRA, tlb4KB_m_tlbRam_2_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_2_bram$ENA,
|
|
tlb4KB_m_tlbRam_2_bram$ENB,
|
|
tlb4KB_m_tlbRam_2_bram$WEA,
|
|
tlb4KB_m_tlbRam_2_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$EN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2
|
|
wire tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_bram
|
|
wire [80 : 0] tlb4KB_m_tlbRam_3_bram$DIA,
|
|
tlb4KB_m_tlbRam_3_bram$DIB,
|
|
tlb4KB_m_tlbRam_3_bram$DOB;
|
|
wire [7 : 0] tlb4KB_m_tlbRam_3_bram$ADDRA, tlb4KB_m_tlbRam_3_bram$ADDRB;
|
|
wire tlb4KB_m_tlbRam_3_bram$ENA,
|
|
tlb4KB_m_tlbRam_3_bram$ENB,
|
|
tlb4KB_m_tlbRam_3_bram$WEA,
|
|
tlb4KB_m_tlbRam_3_bram$WEB;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$EN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$EN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2
|
|
wire tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$D_IN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$EN,
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlbMG_m_lruBit_dummy2_0
|
|
wire tlbMG_m_lruBit_dummy2_0$D_IN,
|
|
tlbMG_m_lruBit_dummy2_0$EN,
|
|
tlbMG_m_lruBit_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlbMG_m_lruBit_dummy2_1
|
|
wire tlbMG_m_lruBit_dummy2_1$D_IN,
|
|
tlbMG_m_lruBit_dummy2_1$EN,
|
|
tlbMG_m_lruBit_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlbMG_m_updRepIdx_dummy2_0
|
|
wire tlbMG_m_updRepIdx_dummy2_0$D_IN,
|
|
tlbMG_m_updRepIdx_dummy2_0$EN,
|
|
tlbMG_m_updRepIdx_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlbMG_m_updRepIdx_dummy2_1
|
|
wire tlbMG_m_updRepIdx_dummy2_1$D_IN,
|
|
tlbMG_m_updRepIdx_dummy2_1$EN,
|
|
tlbMG_m_updRepIdx_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlbReqQ_deqP_dummy2_0
|
|
wire tlbReqQ_deqP_dummy2_0$D_IN, tlbReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlbReqQ_deqP_dummy2_1
|
|
wire tlbReqQ_deqP_dummy2_1$D_IN, tlbReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlbReqQ_empty_dummy2_0
|
|
wire tlbReqQ_empty_dummy2_0$D_IN,
|
|
tlbReqQ_empty_dummy2_0$EN,
|
|
tlbReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule tlbReqQ_empty_dummy2_1
|
|
wire tlbReqQ_empty_dummy2_1$D_IN,
|
|
tlbReqQ_empty_dummy2_1$EN,
|
|
tlbReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlbReqQ_empty_dummy2_2
|
|
wire tlbReqQ_empty_dummy2_2$D_IN,
|
|
tlbReqQ_empty_dummy2_2$EN,
|
|
tlbReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule tlbReqQ_enqP_dummy2_0
|
|
wire tlbReqQ_enqP_dummy2_0$D_IN, tlbReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule tlbReqQ_enqP_dummy2_1
|
|
wire tlbReqQ_enqP_dummy2_1$D_IN, tlbReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule tlbReqQ_full_dummy2_0
|
|
wire tlbReqQ_full_dummy2_0$D_IN, tlbReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule tlbReqQ_full_dummy2_1
|
|
wire tlbReqQ_full_dummy2_1$D_IN,
|
|
tlbReqQ_full_dummy2_1$EN,
|
|
tlbReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule tlbReqQ_full_dummy2_2
|
|
wire tlbReqQ_full_dummy2_2$D_IN,
|
|
tlbReqQ_full_dummy2_2$EN,
|
|
tlbReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule transCache
|
|
wire [45 : 0] transCache$resp;
|
|
wire [43 : 0] transCache$addEntry_ppn;
|
|
wire [26 : 0] transCache$addEntry_vpn, transCache$req_vpn;
|
|
wire [1 : 0] transCache$addEntry_level;
|
|
wire transCache$EN_addEntry,
|
|
transCache$EN_deqResp,
|
|
transCache$EN_flush,
|
|
transCache$EN_req,
|
|
transCache$RDY_addEntry,
|
|
transCache$RDY_deqResp,
|
|
transCache$RDY_req,
|
|
transCache$RDY_resp,
|
|
transCache$flush_done;
|
|
|
|
// ports of submodule transCacheReqQ_deqP_dummy2_0
|
|
wire transCacheReqQ_deqP_dummy2_0$D_IN, transCacheReqQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule transCacheReqQ_deqP_dummy2_1
|
|
wire transCacheReqQ_deqP_dummy2_1$D_IN, transCacheReqQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule transCacheReqQ_empty_dummy2_0
|
|
wire transCacheReqQ_empty_dummy2_0$D_IN,
|
|
transCacheReqQ_empty_dummy2_0$EN,
|
|
transCacheReqQ_empty_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule transCacheReqQ_empty_dummy2_1
|
|
wire transCacheReqQ_empty_dummy2_1$D_IN,
|
|
transCacheReqQ_empty_dummy2_1$EN,
|
|
transCacheReqQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule transCacheReqQ_empty_dummy2_2
|
|
wire transCacheReqQ_empty_dummy2_2$D_IN,
|
|
transCacheReqQ_empty_dummy2_2$EN,
|
|
transCacheReqQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule transCacheReqQ_enqP_dummy2_0
|
|
wire transCacheReqQ_enqP_dummy2_0$D_IN, transCacheReqQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule transCacheReqQ_enqP_dummy2_1
|
|
wire transCacheReqQ_enqP_dummy2_1$D_IN, transCacheReqQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule transCacheReqQ_full_dummy2_0
|
|
wire transCacheReqQ_full_dummy2_0$D_IN, transCacheReqQ_full_dummy2_0$EN;
|
|
|
|
// ports of submodule transCacheReqQ_full_dummy2_1
|
|
wire transCacheReqQ_full_dummy2_1$D_IN,
|
|
transCacheReqQ_full_dummy2_1$EN,
|
|
transCacheReqQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule transCacheReqQ_full_dummy2_2
|
|
wire transCacheReqQ_full_dummy2_2$D_IN,
|
|
transCacheReqQ_full_dummy2_2$EN,
|
|
transCacheReqQ_full_dummy2_2$Q_OUT;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_doPageWalk,
|
|
CAN_FIRE_RL_doStartFlush,
|
|
CAN_FIRE_RL_doTlbReq,
|
|
CAN_FIRE_RL_doTlbResp,
|
|
CAN_FIRE_RL_doTranslationCacheResp,
|
|
CAN_FIRE_RL_doWaitFlush,
|
|
CAN_FIRE_RL_flushDoneQ_canonicalize,
|
|
CAN_FIRE_RL_flushDoneQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushDoneQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushDoneQ_enqReq_canon,
|
|
CAN_FIRE_RL_memReqQ_canonicalize,
|
|
CAN_FIRE_RL_memReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_memReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_memReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_pendValid_0_canon,
|
|
CAN_FIRE_RL_pendValid_1_canon,
|
|
CAN_FIRE_RL_pendWait_0_canon,
|
|
CAN_FIRE_RL_pendWait_1_canon,
|
|
CAN_FIRE_RL_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_respLdQ_canonicalize,
|
|
CAN_FIRE_RL_respLdQ_clearReq_canon,
|
|
CAN_FIRE_RL_respLdQ_deqReq_canon,
|
|
CAN_FIRE_RL_respLdQ_enqReq_canon,
|
|
CAN_FIRE_RL_rqFromCQ_data_0_canon,
|
|
CAN_FIRE_RL_rqFromCQ_empty_canon,
|
|
CAN_FIRE_RL_rqFromCQ_full_canon,
|
|
CAN_FIRE_RL_rsToCQ_data_0_canon,
|
|
CAN_FIRE_RL_rsToCQ_empty_canon,
|
|
CAN_FIRE_RL_rsToCQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_doAddEntry,
|
|
CAN_FIRE_RL_tlb4KB_m_doFlush,
|
|
CAN_FIRE_RL_tlb4KB_m_pendReq_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_setPendIndex,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon,
|
|
CAN_FIRE_RL_tlbMG_m_doUpdateRep,
|
|
CAN_FIRE_RL_tlbMG_m_incRandIdx,
|
|
CAN_FIRE_RL_tlbMG_m_lruBit_canon,
|
|
CAN_FIRE_RL_tlbMG_m_updRepIdx_canon,
|
|
CAN_FIRE_RL_tlbReqQ_empty_canon,
|
|
CAN_FIRE_RL_tlbReqQ_full_canon,
|
|
CAN_FIRE_RL_transCacheReqQ_empty_canon,
|
|
CAN_FIRE_RL_transCacheReqQ_full_canon,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_toChildren_dTlbReqFlush_put,
|
|
CAN_FIRE_toChildren_flushDone_get,
|
|
CAN_FIRE_toChildren_iTlbReqFlush_put,
|
|
CAN_FIRE_toChildren_rqFromC_put,
|
|
CAN_FIRE_toChildren_rsToC_deq,
|
|
CAN_FIRE_toMem_memReq_deq,
|
|
CAN_FIRE_toMem_respLd_enq,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_doPageWalk,
|
|
WILL_FIRE_RL_doStartFlush,
|
|
WILL_FIRE_RL_doTlbReq,
|
|
WILL_FIRE_RL_doTlbResp,
|
|
WILL_FIRE_RL_doTranslationCacheResp,
|
|
WILL_FIRE_RL_doWaitFlush,
|
|
WILL_FIRE_RL_flushDoneQ_canonicalize,
|
|
WILL_FIRE_RL_flushDoneQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushDoneQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushDoneQ_enqReq_canon,
|
|
WILL_FIRE_RL_memReqQ_canonicalize,
|
|
WILL_FIRE_RL_memReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_memReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_memReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_pendValid_0_canon,
|
|
WILL_FIRE_RL_pendValid_1_canon,
|
|
WILL_FIRE_RL_pendWait_0_canon,
|
|
WILL_FIRE_RL_pendWait_1_canon,
|
|
WILL_FIRE_RL_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_respLdQ_canonicalize,
|
|
WILL_FIRE_RL_respLdQ_clearReq_canon,
|
|
WILL_FIRE_RL_respLdQ_deqReq_canon,
|
|
WILL_FIRE_RL_respLdQ_enqReq_canon,
|
|
WILL_FIRE_RL_rqFromCQ_data_0_canon,
|
|
WILL_FIRE_RL_rqFromCQ_empty_canon,
|
|
WILL_FIRE_RL_rqFromCQ_full_canon,
|
|
WILL_FIRE_RL_rsToCQ_data_0_canon,
|
|
WILL_FIRE_RL_rsToCQ_empty_canon,
|
|
WILL_FIRE_RL_rsToCQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry,
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush,
|
|
WILL_FIRE_RL_tlb4KB_m_pendReq_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_setPendIndex,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon,
|
|
WILL_FIRE_RL_tlbMG_m_doUpdateRep,
|
|
WILL_FIRE_RL_tlbMG_m_incRandIdx,
|
|
WILL_FIRE_RL_tlbMG_m_lruBit_canon,
|
|
WILL_FIRE_RL_tlbMG_m_updRepIdx_canon,
|
|
WILL_FIRE_RL_tlbReqQ_empty_canon,
|
|
WILL_FIRE_RL_tlbReqQ_full_canon,
|
|
WILL_FIRE_RL_transCacheReqQ_empty_canon,
|
|
WILL_FIRE_RL_transCacheReqQ_full_canon,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_toChildren_dTlbReqFlush_put,
|
|
WILL_FIRE_toChildren_flushDone_get,
|
|
WILL_FIRE_toChildren_iTlbReqFlush_put,
|
|
WILL_FIRE_toChildren_rqFromC_put,
|
|
WILL_FIRE_toChildren_rsToC_deq,
|
|
WILL_FIRE_toMem_memReq_deq,
|
|
WILL_FIRE_toMem_respLd_enq,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [83 : 0] MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1,
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2;
|
|
wire [81 : 0] MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1,
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2;
|
|
wire [80 : 0] MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1;
|
|
wire [65 : 0] MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [7 : 0] MUX_tlb4KB_m_flushIdx$write_1__VAL_1,
|
|
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1,
|
|
MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3,
|
|
MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [3 : 0] MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire [2 : 0] MUX_pendWait_0_lat_0$wset_1__VAL_1,
|
|
MUX_pendWait_0_lat_0$wset_1__VAL_2,
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_1,
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_2;
|
|
wire MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1,
|
|
MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_2,
|
|
MUX_pendValid_0_lat_0$wset_1__SEL_1,
|
|
MUX_pendValid_0_lat_0$wset_1__SEL_2,
|
|
MUX_pendValid_1_lat_0$wset_1__SEL_1,
|
|
MUX_pendValid_1_lat_0$wset_1__SEL_2,
|
|
MUX_pendWait_0_dummy2_0$write_1__SEL_1,
|
|
MUX_pendWait_1_dummy2_0$write_1__SEL_1,
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1,
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2,
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1,
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1,
|
|
MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_state$write_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1,
|
|
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1,
|
|
MUX_tlbMG_m_updRepIdx_dummy2_1$write_1__SEL_1,
|
|
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1,
|
|
MUX_tlbMG_m_validVec_0$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_1$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_2$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_3$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_4$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_5$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_6$write_1__SEL_1,
|
|
MUX_tlbMG_m_validVec_7$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684;
|
|
reg [43 : 0] CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q18,
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1472,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387,
|
|
masked_ppn__h136484;
|
|
reg [26 : 0] CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn16705_ETC__q4,
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn16705_ETC__q5,
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn16705_ETC__q8,
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn16705_ETC__q10,
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn16705_ETC__q12,
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn16705_ETC__q14,
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn16705_ETC__q16,
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn16705_ETC__q17,
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q19,
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748,
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610,
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1466,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377,
|
|
masked_vpn__h136483,
|
|
vpn__h116705;
|
|
reg [8 : 0] x__h133171, x__h136122;
|
|
reg [1 : 0] CASE_idx35081_0_pendReq_0_BITS_28_TO_27_1_pend_ETC__q21,
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q20,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462,
|
|
walkLevel__h136014,
|
|
x__h121246;
|
|
reg CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2,
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6,
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7,
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9,
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11,
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13,
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_NOT_tlbR_ETC__q15,
|
|
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q22,
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3,
|
|
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q23,
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107,
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986,
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1079,
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1679,
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1662,
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1790,
|
|
SEL_ARR_NOT_respLdQ_data_0_672_BIT_0_673_719_N_ETC___d1722,
|
|
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046,
|
|
SEL_ARR_pendWait_0_dummy2_0_read__585_AND_pend_ETC___d1651,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1478,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1484,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1486,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1492,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1498,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1504,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1510,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397,
|
|
def__h135309;
|
|
wire [80 : 0] IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138;
|
|
wire [79 : 0] IF_IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_ETC___d1522,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136;
|
|
wire [63 : 0] baseAddr__h132858,
|
|
newPTBase__h136016,
|
|
newPTEAddr__h136017,
|
|
pteAddr__h132859;
|
|
wire [55 : 0] x__h133131, x__h136105;
|
|
wire [43 : 0] basePpn__h133127, rootPPN__h132857;
|
|
wire [26 : 0] IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130,
|
|
vpn__h104314;
|
|
wire [7 : 0] IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d286,
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976,
|
|
IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321,
|
|
upd__h144892,
|
|
val__h41243,
|
|
val__h41244,
|
|
x__h41318;
|
|
wire [2 : 0] IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1371,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1373,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1375,
|
|
IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d342,
|
|
IF_tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_ETC___d2023,
|
|
IF_tlbMG_m_validVec_4_198_AND_tlbMG_m_validVec_ETC___d2020,
|
|
_dfoo68,
|
|
_dfoo72,
|
|
addIdx__h146150,
|
|
addIdx__h147417,
|
|
idx__h118141,
|
|
v__h143350,
|
|
v__h144607,
|
|
v__h145083;
|
|
wire [1 : 0] IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1561,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1562,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d282,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d283,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1332,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d269,
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528,
|
|
newWalkLevel__h136015,
|
|
w__h118766,
|
|
way__h129824,
|
|
way__h36041;
|
|
wire IF_IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BI_ETC___d1347,
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_ETC___d1351,
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_ETC___d1766,
|
|
IF_IF_respForOtherReq_669_BIT_1_670_THEN_NOT_r_ETC___d1727,
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136,
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1213,
|
|
IF_NOT_SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_ETC___d1764,
|
|
IF_NOT_pendWait_0_dummy2_0_read__585_586_OR_NO_ETC___d1787,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1329,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d263,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d264,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d265,
|
|
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1348,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1185,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1210,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1236,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1239,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1263,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1349,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1296,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1297,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1298,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1299,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1300,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1301,
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302,
|
|
IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1807,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1863,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1868,
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1730,
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1761,
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813,
|
|
IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705,
|
|
IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674,
|
|
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648,
|
|
IF_pendValid_0_dummy2_1_read__29_AND_IF_pendVa_ETC___d1020,
|
|
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573,
|
|
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580,
|
|
IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1702,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1703,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1723,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1850,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_respForO_ETC___d1797,
|
|
IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802,
|
|
IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771,
|
|
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745,
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120,
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121,
|
|
IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144,
|
|
IF_tlbMG_m_entryVec_2_151_BITS_1_TO_0_152_EQ_0_ETC___d1168,
|
|
IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193,
|
|
IF_tlbMG_m_entryVec_4_200_BITS_1_TO_0_201_EQ_0_ETC___d1219,
|
|
IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246,
|
|
IF_tlbMG_m_entryVec_6_253_BITS_1_TO_0_254_EQ_0_ETC___d1274,
|
|
IF_tlbMG_m_entryVec_7_279_BITS_1_TO_0_280_EQ_0_ETC___d1288,
|
|
IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d332,
|
|
IF_transCacheReqQ_data_0_583_AND_pendWait_0_du_ETC___d1629,
|
|
IF_transCache_RDY_resp__571_AND_transCache_res_ETC___d1596,
|
|
NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1762,
|
|
NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1878,
|
|
NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1891,
|
|
NOT_flushDoneQ_enqReq_dummy2_2_read__36_51_OR__ETC___d461,
|
|
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688,
|
|
NOT_memReqQ_enqReq_dummy2_2_read__89_19_OR_IF__ETC___d723,
|
|
NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881,
|
|
NOT_perfReqQ_enqReq_dummy2_2_read__82_97_OR_IF_ETC___d902,
|
|
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785,
|
|
NOT_respLdQ_enqReq_dummy2_2_read__86_16_OR_IF__ETC___d820,
|
|
NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927,
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096,
|
|
NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943,
|
|
NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205,
|
|
NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1323,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250,
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1315,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1318,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1357,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165,
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953,
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175,
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d1757,
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962,
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185,
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971,
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195,
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d1024,
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980,
|
|
NOT_tlbMG_m_entryVec_0_099_BITS_79_TO_53_120_E_ETC___d1904,
|
|
NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1912,
|
|
NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1966,
|
|
NOT_tlbMG_m_entryVec_2_151_BITS_79_TO_53_167_E_ETC___d1920,
|
|
NOT_tlbMG_m_entryVec_3_175_BITS_79_TO_53_192_E_ETC___d1928,
|
|
NOT_tlbMG_m_entryVec_4_200_BITS_79_TO_53_218_E_ETC___d1936,
|
|
NOT_tlbMG_m_entryVec_5_226_BITS_79_TO_53_245_E_ETC___d1944,
|
|
NOT_tlbMG_m_entryVec_6_253_BITS_79_TO_53_273_E_ETC___d1952,
|
|
NOT_tlbMG_m_entryVec_7_279_BITS_79_TO_53_287_E_ETC___d1960,
|
|
NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_304_OR_ETC___d1305,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1148,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1172,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1188,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1250,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1269,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1546,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1548,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1569,
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_tlbMG_m__ETC___d2017,
|
|
NOT_tlbMG_m_validVec_1_124_125_OR_NOT_tlbMG_m__ETC___d2056,
|
|
NOT_tlbMG_m_validVec_3_173_174_OR_NOT_tlbMG_m__ETC___d2054,
|
|
NOT_tlbMG_m_validVec_5_224_225_OR_NOT_tlbMG_m__ETC___d2052,
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070,
|
|
NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591,
|
|
NOT_transCacheReqQ_empty_dummy2_0_read__573_57_ETC___d1582,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1816,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2009,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061,
|
|
_dfoo101,
|
|
_dfoo103,
|
|
_dfoo13,
|
|
_dfoo41,
|
|
_dfoo45,
|
|
_dfoo65,
|
|
_dfoo67,
|
|
_dfoo69,
|
|
_dfoo71,
|
|
_dfoo89,
|
|
_dfoo9,
|
|
_dfoo91,
|
|
_dfoo93,
|
|
_dfoo95,
|
|
_dfoo97,
|
|
_dfoo99,
|
|
_theResult_____2__h82166,
|
|
_theResult_____2__h89736,
|
|
flushDoneQ_enqReq_dummy2_2_read__36_AND_IF_flu_ETC___d448,
|
|
i__h135439,
|
|
idx__h135081,
|
|
memReqQ_enqReq_dummy2_2_read__89_AND_IF_memReq_ETC___d715,
|
|
next_deqP___1__h82485,
|
|
next_deqP___1__h90055,
|
|
pendValid_0_dummy2_0_read__28_AND_pendValid_0__ETC___d936,
|
|
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051,
|
|
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056,
|
|
pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1784,
|
|
pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618,
|
|
pendWalkAddr_1_636_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1725,
|
|
perfReqQ_enqReq_dummy2_2_read__82_AND_IF_perfR_ETC___d894,
|
|
respLdQ_enqReq_dummy2_2_read__86_AND_IF_respLd_ETC___d812,
|
|
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1553,
|
|
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271,
|
|
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287,
|
|
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308,
|
|
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311,
|
|
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231,
|
|
tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234,
|
|
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1320,
|
|
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243,
|
|
tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246,
|
|
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1324,
|
|
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254,
|
|
tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256,
|
|
tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_1__ETC___d1974,
|
|
tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_1__ETC___d2004,
|
|
transCache_RDY_deqResp__572_AND_NOT_transCache_ETC___d1644,
|
|
transCache_resp__592_BITS_45_TO_44_593_ULT_2___d1594,
|
|
v__h101631,
|
|
v__h81624,
|
|
v__h81907,
|
|
v__h89194,
|
|
v__h89477;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// action method toChildren_rqFromC_put
|
|
assign RDY_toChildren_rqFromC_put =
|
|
!rqFromCQ_full_dummy2_0$Q_OUT || !rqFromCQ_full_dummy2_1$Q_OUT ||
|
|
!rqFromCQ_full_dummy2_2$Q_OUT ||
|
|
!rqFromCQ_full_rl ;
|
|
assign CAN_FIRE_toChildren_rqFromC_put =
|
|
!rqFromCQ_full_dummy2_0$Q_OUT || !rqFromCQ_full_dummy2_1$Q_OUT ||
|
|
!rqFromCQ_full_dummy2_2$Q_OUT ||
|
|
!rqFromCQ_full_rl ;
|
|
assign WILL_FIRE_toChildren_rqFromC_put = EN_toChildren_rqFromC_put ;
|
|
|
|
// value method toChildren_rsToC_notEmpty
|
|
assign toChildren_rsToC_notEmpty = RDY_toChildren_rsToC_first ;
|
|
assign RDY_toChildren_rsToC_notEmpty = 1'd1 ;
|
|
|
|
// action method toChildren_rsToC_deq
|
|
assign RDY_toChildren_rsToC_deq = RDY_toChildren_rsToC_first ;
|
|
assign CAN_FIRE_toChildren_rsToC_deq = RDY_toChildren_rsToC_first ;
|
|
assign WILL_FIRE_toChildren_rsToC_deq = EN_toChildren_rsToC_deq ;
|
|
|
|
// value method toChildren_rsToC_first
|
|
assign toChildren_rsToC_first =
|
|
{ rsToCQ_data_0_dummy2_1$Q_OUT &&
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528,
|
|
rsToCQ_data_0_dummy2_1$Q_OUT &&
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544 } ;
|
|
assign RDY_toChildren_rsToC_first =
|
|
!rsToCQ_empty_dummy2_1$Q_OUT || !rsToCQ_empty_dummy2_2$Q_OUT ||
|
|
(rsToCQ_empty_lat_0$whas ? !1'd0 : !rsToCQ_empty_rl) ;
|
|
|
|
// action method toChildren_iTlbReqFlush_put
|
|
assign RDY_toChildren_iTlbReqFlush_put = !iFlushReq ;
|
|
assign CAN_FIRE_toChildren_iTlbReqFlush_put = !iFlushReq ;
|
|
assign WILL_FIRE_toChildren_iTlbReqFlush_put =
|
|
EN_toChildren_iTlbReqFlush_put ;
|
|
|
|
// action method toChildren_dTlbReqFlush_put
|
|
assign RDY_toChildren_dTlbReqFlush_put = !dFlushReq ;
|
|
assign CAN_FIRE_toChildren_dTlbReqFlush_put = !dFlushReq ;
|
|
assign WILL_FIRE_toChildren_dTlbReqFlush_put =
|
|
EN_toChildren_dTlbReqFlush_put ;
|
|
|
|
// action method toChildren_flushDone_get
|
|
assign RDY_toChildren_flushDone_get = !flushDoneQ_empty ;
|
|
assign CAN_FIRE_toChildren_flushDone_get = !flushDoneQ_empty ;
|
|
assign WILL_FIRE_toChildren_flushDone_get = EN_toChildren_flushDone_get ;
|
|
|
|
// value method toMem_memReq_notEmpty
|
|
assign toMem_memReq_notEmpty = !memReqQ_empty ;
|
|
assign RDY_toMem_memReq_notEmpty = 1'd1 ;
|
|
|
|
// action method toMem_memReq_deq
|
|
assign RDY_toMem_memReq_deq = !memReqQ_empty ;
|
|
assign CAN_FIRE_toMem_memReq_deq = !memReqQ_empty ;
|
|
assign WILL_FIRE_toMem_memReq_deq = EN_toMem_memReq_deq ;
|
|
|
|
// value method toMem_memReq_first
|
|
assign toMem_memReq_first =
|
|
{ CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1,
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 } ;
|
|
assign RDY_toMem_memReq_first = !memReqQ_empty ;
|
|
|
|
// value method toMem_respLd_notFull
|
|
assign toMem_respLd_notFull = !respLdQ_full ;
|
|
assign RDY_toMem_respLd_notFull = 1'd1 ;
|
|
|
|
// action method toMem_respLd_enq
|
|
assign RDY_toMem_respLd_enq = !respLdQ_full ;
|
|
assign CAN_FIRE_toMem_respLd_enq = !respLdQ_full ;
|
|
assign WILL_FIRE_toMem_respLd_enq = EN_toMem_respLd_enq ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// submodule flushDoneQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(flushDoneQ_clearReq_dummy2_0$D_IN),
|
|
.EN(flushDoneQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule flushDoneQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(flushDoneQ_clearReq_dummy2_1$D_IN),
|
|
.EN(flushDoneQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(flushDoneQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule flushDoneQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(flushDoneQ_deqReq_dummy2_0$D_IN),
|
|
.EN(flushDoneQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule flushDoneQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(flushDoneQ_deqReq_dummy2_1$D_IN),
|
|
.EN(flushDoneQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule flushDoneQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(flushDoneQ_deqReq_dummy2_2$D_IN),
|
|
.EN(flushDoneQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(flushDoneQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule flushDoneQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(flushDoneQ_enqReq_dummy2_0$D_IN),
|
|
.EN(flushDoneQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule flushDoneQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(flushDoneQ_enqReq_dummy2_1$D_IN),
|
|
.EN(flushDoneQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule flushDoneQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) flushDoneQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(flushDoneQ_enqReq_dummy2_2$D_IN),
|
|
.EN(flushDoneQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(flushDoneQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule memReqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(memReqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(memReqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(memReqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(memReqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(memReqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule memReqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(memReqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(memReqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(memReqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(memReqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(memReqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(memReqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(memReqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule memReqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(memReqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(memReqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(memReqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(memReqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(memReqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(memReqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(memReqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule pendValid_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendValid_0_dummy2_0$D_IN),
|
|
.EN(pendValid_0_dummy2_0$EN),
|
|
.Q_OUT(pendValid_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule pendValid_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendValid_0_dummy2_1$D_IN),
|
|
.EN(pendValid_0_dummy2_1$EN),
|
|
.Q_OUT(pendValid_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule pendValid_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendValid_1_dummy2_0$D_IN),
|
|
.EN(pendValid_1_dummy2_0$EN),
|
|
.Q_OUT(pendValid_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule pendValid_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendValid_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendValid_1_dummy2_1$D_IN),
|
|
.EN(pendValid_1_dummy2_1$EN),
|
|
.Q_OUT(pendValid_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule pendWait_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendWait_0_dummy2_0$D_IN),
|
|
.EN(pendWait_0_dummy2_0$EN),
|
|
.Q_OUT(pendWait_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule pendWait_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendWait_0_dummy2_1$D_IN),
|
|
.EN(pendWait_0_dummy2_1$EN),
|
|
.Q_OUT(pendWait_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule pendWait_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendWait_1_dummy2_0$D_IN),
|
|
.EN(pendWait_1_dummy2_0$EN),
|
|
.Q_OUT(pendWait_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule pendWait_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendWait_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendWait_1_dummy2_1$D_IN),
|
|
.EN(pendWait_1_dummy2_1$EN),
|
|
.Q_OUT(pendWait_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) perfReqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(perfReqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(perfReqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) perfReqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(perfReqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(perfReqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(perfReqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(perfReqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(perfReqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(perfReqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(perfReqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(perfReqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(perfReqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(perfReqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(perfReqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(perfReqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(perfReqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(perfReqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(perfReqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(perfReqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(perfReqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule respLdQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respLdQ_clearReq_dummy2_0$D_IN),
|
|
.EN(respLdQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respLdQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respLdQ_clearReq_dummy2_1$D_IN),
|
|
.EN(respLdQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(respLdQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule respLdQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respLdQ_deqReq_dummy2_0$D_IN),
|
|
.EN(respLdQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respLdQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respLdQ_deqReq_dummy2_1$D_IN),
|
|
.EN(respLdQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respLdQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(respLdQ_deqReq_dummy2_2$D_IN),
|
|
.EN(respLdQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(respLdQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule respLdQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respLdQ_enqReq_dummy2_0$D_IN),
|
|
.EN(respLdQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respLdQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respLdQ_enqReq_dummy2_1$D_IN),
|
|
.EN(respLdQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respLdQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respLdQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(respLdQ_enqReq_dummy2_2$D_IN),
|
|
.EN(respLdQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(respLdQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule rqFromCQ_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(rqFromCQ_data_0_dummy2_0$D_IN),
|
|
.EN(rqFromCQ_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rqFromCQ_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(rqFromCQ_data_0_dummy2_1$D_IN),
|
|
.EN(rqFromCQ_data_0_dummy2_1$EN),
|
|
.Q_OUT(rqFromCQ_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule rqFromCQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(rqFromCQ_deqP_dummy2_0$D_IN),
|
|
.EN(rqFromCQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rqFromCQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(rqFromCQ_deqP_dummy2_1$D_IN),
|
|
.EN(rqFromCQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rqFromCQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(rqFromCQ_empty_dummy2_0$D_IN),
|
|
.EN(rqFromCQ_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rqFromCQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(rqFromCQ_empty_dummy2_1$D_IN),
|
|
.EN(rqFromCQ_empty_dummy2_1$EN),
|
|
.Q_OUT(rqFromCQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule rqFromCQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(rqFromCQ_empty_dummy2_2$D_IN),
|
|
.EN(rqFromCQ_empty_dummy2_2$EN),
|
|
.Q_OUT(rqFromCQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule rqFromCQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(rqFromCQ_enqP_dummy2_0$D_IN),
|
|
.EN(rqFromCQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rqFromCQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(rqFromCQ_enqP_dummy2_1$D_IN),
|
|
.EN(rqFromCQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rqFromCQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(rqFromCQ_full_dummy2_0$D_IN),
|
|
.EN(rqFromCQ_full_dummy2_0$EN),
|
|
.Q_OUT(rqFromCQ_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule rqFromCQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(rqFromCQ_full_dummy2_1$D_IN),
|
|
.EN(rqFromCQ_full_dummy2_1$EN),
|
|
.Q_OUT(rqFromCQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule rqFromCQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rqFromCQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(rqFromCQ_full_dummy2_2$D_IN),
|
|
.EN(rqFromCQ_full_dummy2_2$EN),
|
|
.Q_OUT(rqFromCQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule rsToCQ_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(rsToCQ_data_0_dummy2_0$D_IN),
|
|
.EN(rsToCQ_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rsToCQ_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(rsToCQ_data_0_dummy2_1$D_IN),
|
|
.EN(rsToCQ_data_0_dummy2_1$EN),
|
|
.Q_OUT(rsToCQ_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule rsToCQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(rsToCQ_deqP_dummy2_0$D_IN),
|
|
.EN(rsToCQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rsToCQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(rsToCQ_deqP_dummy2_1$D_IN),
|
|
.EN(rsToCQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rsToCQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(rsToCQ_empty_dummy2_0$D_IN),
|
|
.EN(rsToCQ_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rsToCQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(rsToCQ_empty_dummy2_1$D_IN),
|
|
.EN(rsToCQ_empty_dummy2_1$EN),
|
|
.Q_OUT(rsToCQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule rsToCQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(rsToCQ_empty_dummy2_2$D_IN),
|
|
.EN(rsToCQ_empty_dummy2_2$EN),
|
|
.Q_OUT(rsToCQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule rsToCQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(rsToCQ_enqP_dummy2_0$D_IN),
|
|
.EN(rsToCQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rsToCQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(rsToCQ_enqP_dummy2_1$D_IN),
|
|
.EN(rsToCQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule rsToCQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(rsToCQ_full_dummy2_0$D_IN),
|
|
.EN(rsToCQ_full_dummy2_0$EN),
|
|
.Q_OUT(rsToCQ_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule rsToCQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(rsToCQ_full_dummy2_1$D_IN),
|
|
.EN(rsToCQ_full_dummy2_1$EN),
|
|
.Q_OUT(rsToCQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule rsToCQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) rsToCQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(rsToCQ_full_dummy2_2$D_IN),
|
|
.EN(rsToCQ_full_dummy2_2$EN),
|
|
.Q_OUT(rsToCQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_pendReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlb4KB_m_pendReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_pendReq_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_pendReq_dummy2_0$EN),
|
|
.Q_OUT(tlb4KB_m_pendReq_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_pendReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlb4KB_m_pendReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_pendReq_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_pendReq_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_pendReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_repRam_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd8),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_repRam_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_repRam_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_repRam_bram$ADDRB),
|
|
.DIA(tlb4KB_m_repRam_bram$DIA),
|
|
.DIB(tlb4KB_m_repRam_bram$DIB),
|
|
.WEA(tlb4KB_m_repRam_bram$WEA),
|
|
.WEB(tlb4KB_m_repRam_bram$WEB),
|
|
.ENA(tlb4KB_m_repRam_bram$ENA),
|
|
.ENB(tlb4KB_m_repRam_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_repRam_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_full_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_full_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_repRam_rdReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_repRam_rdReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_repRam_rdReqQ_full_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_repRam_rdReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_repRam_rdReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_0_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_0_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_0_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_0_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_0_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_0_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_0_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_0_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_0_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_0_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_1_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_1_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_1_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_1_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_1_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_1_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_1_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_1_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_1_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_1_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_2_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_2_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_2_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_2_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_2_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_2_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_2_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_2_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_2_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_2_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_bram
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd8),
|
|
.DATA_WIDTH(32'd81),
|
|
.MEMSIZE(9'd256)) tlb4KB_m_tlbRam_3_bram(.CLKA(CLK),
|
|
.CLKB(CLK),
|
|
.ADDRA(tlb4KB_m_tlbRam_3_bram$ADDRA),
|
|
.ADDRB(tlb4KB_m_tlbRam_3_bram$ADDRB),
|
|
.DIA(tlb4KB_m_tlbRam_3_bram$DIA),
|
|
.DIB(tlb4KB_m_tlbRam_3_bram$DIB),
|
|
.WEA(tlb4KB_m_tlbRam_3_bram$WEA),
|
|
.WEB(tlb4KB_m_tlbRam_3_bram$WEB),
|
|
.ENA(tlb4KB_m_tlbRam_3_bram$ENA),
|
|
.ENB(tlb4KB_m_tlbRam_3_bram$ENB),
|
|
.DOA(),
|
|
.DOB(tlb4KB_m_tlbRam_3_bram$DOB));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$D_IN),
|
|
.EN(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlbMG_m_lruBit_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbMG_m_lruBit_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlbMG_m_lruBit_dummy2_0$D_IN),
|
|
.EN(tlbMG_m_lruBit_dummy2_0$EN),
|
|
.Q_OUT(tlbMG_m_lruBit_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlbMG_m_lruBit_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbMG_m_lruBit_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlbMG_m_lruBit_dummy2_1$D_IN),
|
|
.EN(tlbMG_m_lruBit_dummy2_1$EN),
|
|
.Q_OUT(tlbMG_m_lruBit_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlbMG_m_updRepIdx_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlbMG_m_updRepIdx_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlbMG_m_updRepIdx_dummy2_0$D_IN),
|
|
.EN(tlbMG_m_updRepIdx_dummy2_0$EN),
|
|
.Q_OUT(tlbMG_m_updRepIdx_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlbMG_m_updRepIdx_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) tlbMG_m_updRepIdx_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlbMG_m_updRepIdx_dummy2_1$D_IN),
|
|
.EN(tlbMG_m_updRepIdx_dummy2_1$EN),
|
|
.Q_OUT(tlbMG_m_updRepIdx_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlbReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlbReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(tlbReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlbReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlbReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(tlbReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlbReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlbReqQ_empty_dummy2_0$D_IN),
|
|
.EN(tlbReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(tlbReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule tlbReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlbReqQ_empty_dummy2_1$D_IN),
|
|
.EN(tlbReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(tlbReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlbReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlbReqQ_empty_dummy2_2$D_IN),
|
|
.EN(tlbReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(tlbReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule tlbReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlbReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(tlbReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlbReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlbReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(tlbReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlbReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(tlbReqQ_full_dummy2_0$D_IN),
|
|
.EN(tlbReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule tlbReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(tlbReqQ_full_dummy2_1$D_IN),
|
|
.EN(tlbReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(tlbReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule tlbReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) tlbReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(tlbReqQ_full_dummy2_2$D_IN),
|
|
.EN(tlbReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(tlbReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule transCache
|
|
mkSplitTransCache transCache(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.addEntry_level(transCache$addEntry_level),
|
|
.addEntry_ppn(transCache$addEntry_ppn),
|
|
.addEntry_vpn(transCache$addEntry_vpn),
|
|
.req_vpn(transCache$req_vpn),
|
|
.EN_req(transCache$EN_req),
|
|
.EN_deqResp(transCache$EN_deqResp),
|
|
.EN_addEntry(transCache$EN_addEntry),
|
|
.EN_flush(transCache$EN_flush),
|
|
.RDY_req(transCache$RDY_req),
|
|
.resp(transCache$resp),
|
|
.RDY_resp(transCache$RDY_resp),
|
|
.RDY_deqResp(transCache$RDY_deqResp),
|
|
.RDY_addEntry(transCache$RDY_addEntry),
|
|
.RDY_flush(),
|
|
.flush_done(transCache$flush_done),
|
|
.RDY_flush_done());
|
|
|
|
// submodule transCacheReqQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_deqP_dummy2_0$D_IN),
|
|
.EN(transCacheReqQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule transCacheReqQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_deqP_dummy2_1$D_IN),
|
|
.EN(transCacheReqQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule transCacheReqQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_empty_dummy2_0$D_IN),
|
|
.EN(transCacheReqQ_empty_dummy2_0$EN),
|
|
.Q_OUT(transCacheReqQ_empty_dummy2_0$Q_OUT));
|
|
|
|
// submodule transCacheReqQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_empty_dummy2_1$D_IN),
|
|
.EN(transCacheReqQ_empty_dummy2_1$EN),
|
|
.Q_OUT(transCacheReqQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule transCacheReqQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_empty_dummy2_2$D_IN),
|
|
.EN(transCacheReqQ_empty_dummy2_2$EN),
|
|
.Q_OUT(transCacheReqQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule transCacheReqQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_enqP_dummy2_0$D_IN),
|
|
.EN(transCacheReqQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule transCacheReqQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_enqP_dummy2_1$D_IN),
|
|
.EN(transCacheReqQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule transCacheReqQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_full_dummy2_0$D_IN),
|
|
.EN(transCacheReqQ_full_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule transCacheReqQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_full_dummy2_1$D_IN),
|
|
.EN(transCacheReqQ_full_dummy2_1$EN),
|
|
.Q_OUT(transCacheReqQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule transCacheReqQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) transCacheReqQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(transCacheReqQ_full_dummy2_2$D_IN),
|
|
.EN(transCacheReqQ_full_dummy2_2$EN),
|
|
.Q_OUT(transCacheReqQ_full_dummy2_2$Q_OUT));
|
|
|
|
// rule RL_doStartFlush
|
|
assign CAN_FIRE_RL_doStartFlush =
|
|
tlb4KB_m_state &&
|
|
(!tlb4KB_m_pendReq_dummy2_0$Q_OUT ||
|
|
!tlb4KB_m_pendReq_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_pendReq_rl[81]) &&
|
|
iFlushReq &&
|
|
dFlushReq &&
|
|
!waitFlushDone ;
|
|
assign WILL_FIRE_RL_doStartFlush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doTranslationCacheResp
|
|
assign CAN_FIRE_RL_doTranslationCacheResp =
|
|
transCache$RDY_resp &&
|
|
transCache_RDY_deqResp__572_AND_NOT_transCache_ETC___d1644 ;
|
|
assign WILL_FIRE_RL_doTranslationCacheResp =
|
|
CAN_FIRE_RL_doTranslationCacheResp ;
|
|
|
|
// rule RL_tlb4KB_m_setPendIndex
|
|
assign CAN_FIRE_RL_tlb4KB_m_setPendIndex = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_setPendIndex = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_doAddEntry
|
|
assign CAN_FIRE_RL_tlb4KB_m_doAddEntry =
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 &&
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 &&
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195 &&
|
|
NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205 &&
|
|
tlb4KB_m_state &&
|
|
tlb4KB_m_pendReq_dummy2_0$Q_OUT &&
|
|
tlb4KB_m_pendReq_dummy2_1$Q_OUT &&
|
|
tlb4KB_m_pendReq_rl[81] &&
|
|
tlb4KB_m_pendReq_rl[80] ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_doAddEntry = CAN_FIRE_RL_tlb4KB_m_doAddEntry ;
|
|
|
|
// rule RL_tlbMG_m_doUpdateRep
|
|
assign CAN_FIRE_RL_tlbMG_m_doUpdateRep =
|
|
!CAN_FIRE_RL_doStartFlush && tlbMG_m_updRepIdx_dummy2_0$Q_OUT &&
|
|
tlbMG_m_updRepIdx_dummy2_1$Q_OUT &&
|
|
tlbMG_m_updRepIdx_rl[3] ;
|
|
assign WILL_FIRE_RL_tlbMG_m_doUpdateRep =
|
|
CAN_FIRE_RL_tlbMG_m_doUpdateRep && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doTlbResp
|
|
assign CAN_FIRE_RL_doTlbResp =
|
|
tlb4KB_m_state && tlb4KB_m_pendReq_dummy2_0$Q_OUT &&
|
|
tlb4KB_m_pendReq_dummy2_1$Q_OUT &&
|
|
tlb4KB_m_pendReq_rl[81] &&
|
|
!tlb4KB_m_pendReq_rl[80] &&
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1357 ;
|
|
assign WILL_FIRE_RL_doTlbResp = CAN_FIRE_RL_doTlbResp ;
|
|
|
|
// rule RL_doPageWalk
|
|
assign CAN_FIRE_RL_doPageWalk =
|
|
!respLdQ_empty &&
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_ETC___d1766 &&
|
|
tlbReqQ_empty_dummy2_0$Q_OUT &&
|
|
tlbReqQ_empty_dummy2_1$Q_OUT &&
|
|
tlbReqQ_empty_dummy2_2$Q_OUT &&
|
|
tlbReqQ_empty_rl &&
|
|
transCacheReqQ_empty_dummy2_0$Q_OUT &&
|
|
transCacheReqQ_empty_dummy2_1$Q_OUT &&
|
|
transCacheReqQ_empty_dummy2_2$Q_OUT &&
|
|
transCacheReqQ_empty_rl ;
|
|
assign WILL_FIRE_RL_doPageWalk =
|
|
CAN_FIRE_RL_doPageWalk && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doWaitFlush
|
|
assign CAN_FIRE_RL_doWaitFlush =
|
|
!flushDoneQ_full && iFlushReq && dFlushReq && waitFlushDone &&
|
|
tlb4KB_m_state &&
|
|
transCache$flush_done ;
|
|
assign WILL_FIRE_RL_doWaitFlush = CAN_FIRE_RL_doWaitFlush ;
|
|
|
|
// rule RL_doTlbReq
|
|
assign CAN_FIRE_RL_doTlbReq =
|
|
tlb4KB_m_state &&
|
|
NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943 &&
|
|
NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927 &&
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953 &&
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962 &&
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971 &&
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d1024 &&
|
|
(!iFlushReq || !dFlushReq) &&
|
|
respLdQ_empty ;
|
|
assign WILL_FIRE_RL_doTlbReq = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// rule RL_tlb4KB_m_doFlush
|
|
assign CAN_FIRE_RL_tlb4KB_m_doFlush = !tlb4KB_m_state ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_doFlush = CAN_FIRE_RL_tlb4KB_m_doFlush ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_0_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_1_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_2_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_tlbRam_3_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_repRam_rdReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_repRam_rdReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_repRam_rdReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb4KB_m_pendReq_canon
|
|
assign CAN_FIRE_RL_tlb4KB_m_pendReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb4KB_m_pendReq_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbMG_m_incRandIdx
|
|
assign CAN_FIRE_RL_tlbMG_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbMG_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_tlbMG_m_lruBit_canon
|
|
assign CAN_FIRE_RL_tlbMG_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbMG_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbMG_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_tlbMG_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbMG_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbReqQ_empty_canon
|
|
assign CAN_FIRE_RL_tlbReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_tlbReqQ_full_canon
|
|
assign CAN_FIRE_RL_tlbReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlbReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_transCacheReqQ_empty_canon
|
|
assign CAN_FIRE_RL_transCacheReqQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_transCacheReqQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_transCacheReqQ_full_canon
|
|
assign CAN_FIRE_RL_transCacheReqQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_transCacheReqQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_canonicalize
|
|
assign CAN_FIRE_RL_flushDoneQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushDoneQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushDoneQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushDoneQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushDoneQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushDoneQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqFromCQ_data_0_canon
|
|
assign CAN_FIRE_RL_rqFromCQ_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqFromCQ_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_rqFromCQ_empty_canon
|
|
assign CAN_FIRE_RL_rqFromCQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqFromCQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_rqFromCQ_full_canon
|
|
assign CAN_FIRE_RL_rqFromCQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqFromCQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_rsToCQ_data_0_canon
|
|
assign CAN_FIRE_RL_rsToCQ_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsToCQ_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_rsToCQ_empty_canon
|
|
assign CAN_FIRE_RL_rsToCQ_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsToCQ_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_rsToCQ_full_canon
|
|
assign CAN_FIRE_RL_rsToCQ_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsToCQ_full_canon = 1'd1 ;
|
|
|
|
// rule RL_pendValid_0_canon
|
|
assign CAN_FIRE_RL_pendValid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendValid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_pendValid_1_canon
|
|
assign CAN_FIRE_RL_pendValid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendValid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_pendWait_0_canon
|
|
assign CAN_FIRE_RL_pendWait_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendWait_0_canon = 1'd1 ;
|
|
|
|
// rule RL_pendWait_1_canon
|
|
assign CAN_FIRE_RL_pendWait_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendWait_1_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_canonicalize
|
|
assign CAN_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_canonicalize
|
|
assign CAN_FIRE_RL_respLdQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_enqReq_canon
|
|
assign CAN_FIRE_RL_respLdQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_deqReq_canon
|
|
assign CAN_FIRE_RL_respLdQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respLdQ_clearReq_canon
|
|
assign CAN_FIRE_RL_respLdQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respLdQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
!IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639 ;
|
|
assign MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_2 =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 ;
|
|
assign MUX_pendValid_0_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp && _dfoo13 ;
|
|
assign MUX_pendValid_0_lat_0$wset_1__SEL_2 =
|
|
WILL_FIRE_RL_doPageWalk && _dfoo103 ;
|
|
assign MUX_pendValid_1_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp && _dfoo9 ;
|
|
assign MUX_pendValid_1_lat_0$wset_1__SEL_2 =
|
|
WILL_FIRE_RL_doPageWalk && _dfoo99 ;
|
|
assign MUX_pendWait_0_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ;
|
|
assign MUX_pendWait_1_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ;
|
|
assign MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
(IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086 ||
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ||
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330) ;
|
|
assign MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2 =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1807 ;
|
|
assign MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1868 ;
|
|
assign MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1548 ;
|
|
assign MUX_tlb4KB_m_state$write_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush && tlb4KB_m_flushIdx == 8'd255 ;
|
|
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd0 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
|
|
assign MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd1 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
|
|
assign MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd2 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
|
|
assign MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd3 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ;
|
|
assign MUX_tlbMG_m_updRepIdx_dummy2_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ;
|
|
assign MUX_tlbMG_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd2 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd3 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd4 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd5 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd6 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_tlbMG_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd7 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1, pteAddr__h132859, transCacheReqQ_data_0 } ;
|
|
assign MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1, newPTEAddr__h136017, idx__h135081 } ;
|
|
assign MUX_pendWait_0_lat_0$wset_1__VAL_1 =
|
|
(transCacheReqQ_data_0 == 1'd0 &&
|
|
IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639) ?
|
|
{ 2'd2,
|
|
NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 ||
|
|
!pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618 } :
|
|
3'd2 ;
|
|
assign MUX_pendWait_0_lat_0$wset_1__VAL_2 =
|
|
(idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680) ?
|
|
3'd0 :
|
|
((idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837) ?
|
|
3'd0 :
|
|
_dfoo72) ;
|
|
assign MUX_pendWait_1_lat_0$wset_1__VAL_1 =
|
|
(transCacheReqQ_data_0 == 1'd1 &&
|
|
IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639) ?
|
|
{ 2'd2,
|
|
NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 ||
|
|
!pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618 } :
|
|
3'd2 ;
|
|
assign MUX_pendWait_1_lat_0$wset_1__VAL_2 =
|
|
(idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680) ?
|
|
3'd0 :
|
|
((idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837) ?
|
|
3'd0 :
|
|
_dfoo68) ;
|
|
assign MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1 =
|
|
{ !SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1079,
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q20,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368,
|
|
IF_IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_ETC___d1522 } ;
|
|
assign MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2 =
|
|
{ !SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1679,
|
|
CASE_idx35081_0_pendReq_0_BITS_28_TO_27_1_pend_ETC__q21,
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1816,
|
|
masked_vpn__h136483,
|
|
masked_ppn__h136484,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[7:1],
|
|
walkLevel__h136014 } ;
|
|
assign MUX_tlb4KB_m_flushIdx$write_1__VAL_1 = tlb4KB_m_flushIdx + 8'd1 ;
|
|
assign MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 =
|
|
WILL_FIRE_RL_doTlbResp || WILL_FIRE_RL_tlb4KB_m_doAddEntry ;
|
|
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1 =
|
|
{ 2'd3,
|
|
masked_vpn__h136483,
|
|
masked_ppn__h136484,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[7:1],
|
|
walkLevel__h136014 } ;
|
|
assign MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2 =
|
|
{ 55'h4AAAAAAAAAAAAA, vpn__h104314 } ;
|
|
assign MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1 =
|
|
{ IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1561,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1562,
|
|
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1553 ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[1:0],
|
|
way__h129824 } ;
|
|
assign MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3 =
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d265 ?
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d286 :
|
|
{ (!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] !=
|
|
tlb4KB_m_repRam_bram$DOB[7:6] &&
|
|
tlb4KB_m_repRam_bram$DOB[5:4] !=
|
|
tlb4KB_m_repRam_bram$DOB[7:6]) ?
|
|
tlb4KB_m_repRam_bram$DOB[5:4] :
|
|
tlb4KB_m_repRam_bram$DOB[7:6],
|
|
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] !=
|
|
tlb4KB_m_repRam_bram$DOB[7:6]) ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[5:4],
|
|
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[1:0],
|
|
tlb4KB_m_repRam_bram$DOB[7:6] } ;
|
|
assign MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 =
|
|
{ 1'd1, tlb4KB_m_pendReq_rl[79:0] } ;
|
|
assign MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h41244 == 8'd255) ? x__h41318 : val__h41244 ;
|
|
assign MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 =
|
|
WILL_FIRE_RL_tlbMG_m_doUpdateRep || WILL_FIRE_RL_doStartFlush ;
|
|
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, idx__h118141 } ;
|
|
assign MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, v__h143350 } ;
|
|
|
|
// inlined wires
|
|
assign tlb4KB_m_pendReq_lat_1$wget =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_1 :
|
|
MUX_tlb4KB_m_pendReq_lat_1$wset_1__VAL_2 ;
|
|
assign tlbMG_m_updRepIdx_lat_1$wget =
|
|
MUX_tlbMG_m_updRepIdx_dummy2_1$write_1__SEL_1 ?
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_tlbMG_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign tlbMG_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ||
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ;
|
|
assign rsToCQ_data_0_lat_0$wget =
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 ?
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_1 :
|
|
MUX_rsToCQ_data_0_lat_0$wset_1__VAL_2 ;
|
|
assign rsToCQ_data_0_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
(IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086 ||
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ||
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330) ||
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1807 ;
|
|
assign rsToCQ_empty_lat_0$whas =
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 ||
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2 ;
|
|
assign rsToCQ_full_lat_0$whas =
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_1 ||
|
|
MUX_rsToCQ_data_0_dummy2_0$write_1__SEL_2 ;
|
|
assign pendValid_0_lat_0$whas =
|
|
MUX_pendValid_0_lat_0$wset_1__SEL_1 ||
|
|
MUX_pendValid_0_lat_0$wset_1__SEL_2 ;
|
|
assign pendValid_0_lat_1$whas =
|
|
WILL_FIRE_RL_doTlbReq && v__h101631 == 1'd0 ;
|
|
assign pendValid_1_lat_0$whas =
|
|
MUX_pendValid_1_lat_0$wset_1__SEL_1 ||
|
|
MUX_pendValid_1_lat_0$wset_1__SEL_2 ;
|
|
assign pendValid_1_lat_1$whas =
|
|
WILL_FIRE_RL_doTlbReq && v__h101631 == 1'd1 ;
|
|
assign pendWait_0_lat_0$wget =
|
|
MUX_pendWait_0_dummy2_0$write_1__SEL_1 ?
|
|
MUX_pendWait_0_lat_0$wset_1__VAL_1 :
|
|
MUX_pendWait_0_lat_0$wset_1__VAL_2 ;
|
|
assign pendWait_0_lat_0$whas =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo95 ;
|
|
assign pendWait_1_lat_0$wget =
|
|
MUX_pendWait_1_dummy2_0$write_1__SEL_1 ?
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_1 :
|
|
MUX_pendWait_1_lat_0$wset_1__VAL_2 ;
|
|
assign pendWait_1_lat_0$whas =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo91 ;
|
|
assign memReqQ_enqReq_lat_0$wget =
|
|
MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1 ?
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_memReqQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign memReqQ_enqReq_lat_0$whas =
|
|
MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_1 ||
|
|
MUX_memReqQ_enqReq_dummy2_0$write_1__SEL_2 ;
|
|
assign respLdQ_enqReq_lat_0$wget = { 1'd1, toMem_respLd_enq_x } ;
|
|
assign respLdQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_doPageWalk && i__h135439 &&
|
|
(!pendWait_1_dummy2_0$Q_OUT || !pendWait_1_dummy2_1$Q_OUT ||
|
|
pendWait_1_rl[2:1] == 2'd0 ||
|
|
pendWait_1_rl[2:1] == 2'd1 ||
|
|
!pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1784 ||
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_respForO_ETC___d1797) ;
|
|
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1868 ||
|
|
WILL_FIRE_RL_doTlbReq ;
|
|
assign transCacheReqQ_enqP_lat_0$whas =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1569 ;
|
|
assign tlb4KB_m_pendIndex$wget =
|
|
{ tlb4KB_m_pendReq_dummy2_0$Q_OUT &&
|
|
tlb4KB_m_pendReq_dummy2_1$Q_OUT &&
|
|
tlb4KB_m_pendReq_rl[81],
|
|
tlb4KB_m_pendReq_rl[80] ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_pendReq_rl[7:0] } ;
|
|
|
|
// register dFlushReq
|
|
assign dFlushReq$D_IN = !WILL_FIRE_RL_doWaitFlush ;
|
|
assign dFlushReq$EN =
|
|
WILL_FIRE_RL_doWaitFlush || EN_toChildren_dTlbReqFlush_put ;
|
|
|
|
// register flushDoneQ_clearReq_rl
|
|
assign flushDoneQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushDoneQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_deqReq_rl
|
|
assign flushDoneQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushDoneQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_empty
|
|
assign flushDoneQ_empty$D_IN =
|
|
flushDoneQ_clearReq_dummy2_1$Q_OUT && flushDoneQ_clearReq_rl ||
|
|
NOT_flushDoneQ_enqReq_dummy2_2_read__36_51_OR__ETC___d461 ;
|
|
assign flushDoneQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_enqReq_rl
|
|
assign flushDoneQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushDoneQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushDoneQ_full
|
|
assign flushDoneQ_full$D_IN =
|
|
(!flushDoneQ_clearReq_dummy2_1$Q_OUT ||
|
|
!flushDoneQ_clearReq_rl) &&
|
|
flushDoneQ_enqReq_dummy2_2_read__36_AND_IF_flu_ETC___d448 ;
|
|
assign flushDoneQ_full$EN = 1'd1 ;
|
|
|
|
// register iFlushReq
|
|
assign iFlushReq$D_IN = !WILL_FIRE_RL_doWaitFlush ;
|
|
assign iFlushReq$EN =
|
|
WILL_FIRE_RL_doWaitFlush || EN_toChildren_iTlbReqFlush_put ;
|
|
|
|
// register memReqQ_clearReq_rl
|
|
assign memReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign memReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_data_0
|
|
assign memReqQ_data_0$D_IN =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[64:0] :
|
|
memReqQ_enqReq_rl[64:0] ;
|
|
assign memReqQ_data_0$EN =
|
|
memReqQ_enqP == 1'd0 &&
|
|
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
|
|
memReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 ;
|
|
|
|
// register memReqQ_data_1
|
|
assign memReqQ_data_1$D_IN =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[64:0] :
|
|
memReqQ_enqReq_rl[64:0] ;
|
|
assign memReqQ_data_1$EN =
|
|
memReqQ_enqP == 1'd1 &&
|
|
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
|
|
memReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 ;
|
|
|
|
// register memReqQ_deqP
|
|
assign memReqQ_deqP$D_IN =
|
|
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
|
|
_theResult_____2__h82166 ;
|
|
assign memReqQ_deqP$EN = 1'd1 ;
|
|
|
|
// register memReqQ_deqReq_rl
|
|
assign memReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign memReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_empty
|
|
assign memReqQ_empty$D_IN =
|
|
memReqQ_clearReq_dummy2_1$Q_OUT && memReqQ_clearReq_rl ||
|
|
IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705 &&
|
|
NOT_memReqQ_enqReq_dummy2_2_read__89_19_OR_IF__ETC___d723 ;
|
|
assign memReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register memReqQ_enqP
|
|
assign memReqQ_enqP$D_IN =
|
|
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
|
|
v__h81624 ;
|
|
assign memReqQ_enqP$EN = 1'd1 ;
|
|
|
|
// register memReqQ_enqReq_rl
|
|
assign memReqQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
|
|
assign memReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_full
|
|
assign memReqQ_full$D_IN =
|
|
NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 &&
|
|
IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705 &&
|
|
memReqQ_enqReq_dummy2_2_read__89_AND_IF_memReq_ETC___d715 ;
|
|
assign memReqQ_full$EN = 1'd1 ;
|
|
|
|
// register pendReq_0
|
|
assign pendReq_0$D_IN =
|
|
{ rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
|
|
vpn__h104314 } ;
|
|
assign pendReq_0$EN = pendValid_0_lat_1$whas ;
|
|
|
|
// register pendReq_1
|
|
assign pendReq_1$D_IN =
|
|
{ rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
|
|
vpn__h104314 } ;
|
|
assign pendReq_1$EN = pendValid_1_lat_1$whas ;
|
|
|
|
// register pendValid_0_rl
|
|
assign pendValid_0_rl$D_IN =
|
|
pendValid_0_lat_1$whas ||
|
|
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 ;
|
|
assign pendValid_0_rl$EN = 1'd1 ;
|
|
|
|
// register pendValid_1_rl
|
|
assign pendValid_1_rl$D_IN =
|
|
pendValid_1_lat_1$whas ||
|
|
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580 ;
|
|
assign pendValid_1_rl$EN = 1'd1 ;
|
|
|
|
// register pendWait_0_rl
|
|
assign pendWait_0_rl$D_IN =
|
|
(pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[2:1] == 2'd0 :
|
|
pendWait_0_rl[2:1] == 2'd0) ?
|
|
3'd0 :
|
|
((pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[2:1] == 2'd1 :
|
|
pendWait_0_rl[2:1] == 2'd1) ?
|
|
3'd2 :
|
|
{ 2'd2,
|
|
pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[0] :
|
|
pendWait_0_rl[0] }) ;
|
|
assign pendWait_0_rl$EN = 1'd1 ;
|
|
|
|
// register pendWait_1_rl
|
|
assign pendWait_1_rl$D_IN =
|
|
(pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[2:1] == 2'd0 :
|
|
pendWait_1_rl[2:1] == 2'd0) ?
|
|
3'd0 :
|
|
((pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[2:1] == 2'd1 :
|
|
pendWait_1_rl[2:1] == 2'd1) ?
|
|
3'd2 :
|
|
{ 2'd2,
|
|
pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[0] :
|
|
pendWait_1_rl[0] }) ;
|
|
assign pendWait_1_rl$EN = 1'd1 ;
|
|
|
|
// register pendWalkAddr_0
|
|
assign pendWalkAddr_0$D_IN =
|
|
MUX_pendWait_0_dummy2_0$write_1__SEL_1 ?
|
|
pteAddr__h132859 :
|
|
newPTEAddr__h136017 ;
|
|
assign pendWalkAddr_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h135081 == 1'd0 ;
|
|
|
|
// register pendWalkAddr_1
|
|
assign pendWalkAddr_1$D_IN =
|
|
MUX_pendWait_1_dummy2_0$write_1__SEL_1 ?
|
|
pteAddr__h132859 :
|
|
newPTEAddr__h136017 ;
|
|
assign pendWalkAddr_1$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h135081 == 1'd1 ;
|
|
|
|
// register pendWalkLevel_0
|
|
assign pendWalkLevel_0$D_IN =
|
|
MUX_pendWait_0_dummy2_0$write_1__SEL_1 ?
|
|
transCache$resp[45:44] :
|
|
newWalkLevel__h136015 ;
|
|
assign pendWalkLevel_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h135081 == 1'd0 ;
|
|
|
|
// register pendWalkLevel_1
|
|
assign pendWalkLevel_1$D_IN =
|
|
MUX_pendWait_1_dummy2_0$write_1__SEL_1 ?
|
|
transCache$resp[45:44] :
|
|
newWalkLevel__h136015 ;
|
|
assign pendWalkLevel_1$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && idx__h135081 == 1'd1 ;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_data_0
|
|
assign perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[3:0] :
|
|
perfReqQ_enqReq_rl[3:0] ;
|
|
assign perfReqQ_data_0$EN =
|
|
NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881 &&
|
|
perfReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841 ;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_empty
|
|
assign perfReqQ_empty$D_IN =
|
|
perfReqQ_clearReq_dummy2_1$Q_OUT && perfReqQ_clearReq_rl ||
|
|
NOT_perfReqQ_enqReq_dummy2_2_read__82_97_OR_IF_ETC___d902 ;
|
|
assign perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
assign perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
|
|
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_full
|
|
assign perfReqQ_full$D_IN =
|
|
NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881 &&
|
|
perfReqQ_enqReq_dummy2_2_read__82_AND_IF_perfR_ETC___d894 ;
|
|
assign perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register respForOtherReq
|
|
assign respForOtherReq$D_IN =
|
|
{ IF_NOT_pendWait_0_dummy2_0_read__585_586_OR_NO_ETC___d1787,
|
|
i__h135439 } ;
|
|
assign respForOtherReq$EN = WILL_FIRE_RL_doPageWalk ;
|
|
|
|
// register respLdQ_clearReq_rl
|
|
assign respLdQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign respLdQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register respLdQ_data_0
|
|
assign respLdQ_data_0$D_IN =
|
|
EN_toMem_respLd_enq ?
|
|
respLdQ_enqReq_lat_0$wget[64:0] :
|
|
respLdQ_enqReq_rl[64:0] ;
|
|
assign respLdQ_data_0$EN =
|
|
respLdQ_enqP == 1'd0 &&
|
|
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
|
|
respLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 ;
|
|
|
|
// register respLdQ_data_1
|
|
assign respLdQ_data_1$D_IN =
|
|
EN_toMem_respLd_enq ?
|
|
respLdQ_enqReq_lat_0$wget[64:0] :
|
|
respLdQ_enqReq_rl[64:0] ;
|
|
assign respLdQ_data_1$EN =
|
|
respLdQ_enqP == 1'd1 &&
|
|
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
|
|
respLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 ;
|
|
|
|
// register respLdQ_deqP
|
|
assign respLdQ_deqP$D_IN =
|
|
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
|
|
_theResult_____2__h89736 ;
|
|
assign respLdQ_deqP$EN = 1'd1 ;
|
|
|
|
// register respLdQ_deqReq_rl
|
|
assign respLdQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign respLdQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respLdQ_empty
|
|
assign respLdQ_empty$D_IN =
|
|
respLdQ_clearReq_dummy2_1$Q_OUT && respLdQ_clearReq_rl ||
|
|
IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802 &&
|
|
NOT_respLdQ_enqReq_dummy2_2_read__86_16_OR_IF__ETC___d820 ;
|
|
assign respLdQ_empty$EN = 1'd1 ;
|
|
|
|
// register respLdQ_enqP
|
|
assign respLdQ_enqP$D_IN =
|
|
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
|
|
v__h89194 ;
|
|
assign respLdQ_enqP$EN = 1'd1 ;
|
|
|
|
// register respLdQ_enqReq_rl
|
|
assign respLdQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
|
|
assign respLdQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respLdQ_full
|
|
assign respLdQ_full$D_IN =
|
|
NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 &&
|
|
IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802 &&
|
|
respLdQ_enqReq_dummy2_2_read__86_AND_IF_respLd_ETC___d812 ;
|
|
assign respLdQ_full$EN = 1'd1 ;
|
|
|
|
// register rqFromCQ_data_0_rl
|
|
assign rqFromCQ_data_0_rl$D_IN =
|
|
{ IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471,
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481,
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487 } ;
|
|
assign rqFromCQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register rqFromCQ_empty_rl
|
|
assign rqFromCQ_empty_rl$D_IN =
|
|
CAN_FIRE_RL_doTlbReq ||
|
|
!EN_toChildren_rqFromC_put && rqFromCQ_empty_rl ;
|
|
assign rqFromCQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register rqFromCQ_full_rl
|
|
assign rqFromCQ_full_rl$D_IN =
|
|
!CAN_FIRE_RL_doTlbReq &&
|
|
(EN_toChildren_rqFromC_put || rqFromCQ_full_rl) ;
|
|
assign rqFromCQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register rsToCQ_data_0_rl
|
|
assign rsToCQ_data_0_rl$D_IN =
|
|
{ IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534,
|
|
IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544 } ;
|
|
assign rsToCQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register rsToCQ_empty_rl
|
|
assign rsToCQ_empty_rl$D_IN =
|
|
EN_toChildren_rsToC_deq ||
|
|
(rsToCQ_empty_lat_0$whas ? 1'd0 : rsToCQ_empty_rl) ;
|
|
assign rsToCQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register rsToCQ_full_rl
|
|
assign rsToCQ_full_rl$D_IN =
|
|
!EN_toChildren_rsToC_deq &&
|
|
(rsToCQ_full_lat_0$whas ? 1'd1 : rsToCQ_full_rl) ;
|
|
assign rsToCQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_flushIdx
|
|
assign tlb4KB_m_flushIdx$D_IN =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ?
|
|
MUX_tlb4KB_m_flushIdx$write_1__VAL_1 :
|
|
8'd0 ;
|
|
assign tlb4KB_m_flushIdx$EN =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush || WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb4KB_m_pendReq_rl
|
|
assign tlb4KB_m_pendReq_rl$D_IN =
|
|
{ IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138 } ;
|
|
assign tlb4KB_m_pendReq_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_empty_rl
|
|
assign tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_repRam_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_repRam_rdReqQ_full_rl
|
|
assign tlb4KB_m_repRam_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_repRam_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_repRam_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_state
|
|
assign tlb4KB_m_state$D_IN = MUX_tlb4KB_m_state$write_1__SEL_1 ;
|
|
assign tlb4KB_m_state$EN =
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush && tlb4KB_m_flushIdx == 8'd255 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_0_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_1_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_2_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_empty_rl
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd0 :
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlb4KB_m_tlbRam_3_rdReqQ_full_rl
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
1'd1 :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_entryVec_0
|
|
assign tlbMG_m_entryVec_0$D_IN =
|
|
{ masked_vpn__h136483,
|
|
masked_ppn__h136484,
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[7:1],
|
|
walkLevel__h136014 } ;
|
|
assign tlbMG_m_entryVec_0$EN = MUX_tlbMG_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_1
|
|
assign tlbMG_m_entryVec_1$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_1$EN = MUX_tlbMG_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_2
|
|
assign tlbMG_m_entryVec_2$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_2$EN = MUX_tlbMG_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_3
|
|
assign tlbMG_m_entryVec_3$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_3$EN = MUX_tlbMG_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_4
|
|
assign tlbMG_m_entryVec_4$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_4$EN = MUX_tlbMG_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_5
|
|
assign tlbMG_m_entryVec_5$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_5$EN = MUX_tlbMG_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_6
|
|
assign tlbMG_m_entryVec_6$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_6$EN = MUX_tlbMG_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_entryVec_7
|
|
assign tlbMG_m_entryVec_7$D_IN = tlbMG_m_entryVec_0$D_IN ;
|
|
assign tlbMG_m_entryVec_7$EN = MUX_tlbMG_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register tlbMG_m_lruBit_rl
|
|
assign tlbMG_m_lruBit_rl$D_IN =
|
|
IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321 ;
|
|
assign tlbMG_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_randIdx
|
|
assign tlbMG_m_randIdx$D_IN = tlbMG_m_randIdx + 3'd1 ;
|
|
assign tlbMG_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_updRepIdx_rl
|
|
assign tlbMG_m_updRepIdx_rl$D_IN =
|
|
{ IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d332,
|
|
IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d342 } ;
|
|
assign tlbMG_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register tlbMG_m_validVec_0
|
|
assign tlbMG_m_validVec_0$D_IN = MUX_tlbMG_m_validVec_0$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_0$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_1
|
|
assign tlbMG_m_validVec_1$D_IN = MUX_tlbMG_m_validVec_1$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_1$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_2
|
|
assign tlbMG_m_validVec_2$D_IN = MUX_tlbMG_m_validVec_2$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_2$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd2 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_3
|
|
assign tlbMG_m_validVec_3$D_IN = MUX_tlbMG_m_validVec_3$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_3$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd3 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_4
|
|
assign tlbMG_m_validVec_4$D_IN = MUX_tlbMG_m_validVec_4$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_4$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd4 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_5
|
|
assign tlbMG_m_validVec_5$D_IN = MUX_tlbMG_m_validVec_5$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_5$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd5 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_6
|
|
assign tlbMG_m_validVec_6$D_IN = MUX_tlbMG_m_validVec_6$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_6$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd6 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbMG_m_validVec_7
|
|
assign tlbMG_m_validVec_7$D_IN = MUX_tlbMG_m_validVec_7$write_1__SEL_1 ;
|
|
assign tlbMG_m_validVec_7$EN =
|
|
WILL_FIRE_RL_doPageWalk && v__h143350 == 3'd7 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlbReqQ_data_0
|
|
assign tlbReqQ_data_0$D_IN = v__h101631 ;
|
|
assign tlbReqQ_data_0$EN = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// register tlbReqQ_empty_rl
|
|
assign tlbReqQ_empty_rl$D_IN =
|
|
!CAN_FIRE_RL_doTlbReq &&
|
|
(CAN_FIRE_RL_doTlbResp || tlbReqQ_empty_rl) ;
|
|
assign tlbReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register tlbReqQ_full_rl
|
|
assign tlbReqQ_full_rl$D_IN =
|
|
CAN_FIRE_RL_doTlbReq ||
|
|
!CAN_FIRE_RL_doTlbResp && tlbReqQ_full_rl ;
|
|
assign tlbReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register transCacheReqQ_data_0
|
|
assign transCacheReqQ_data_0$D_IN = tlbReqQ_data_0 ;
|
|
assign transCacheReqQ_data_0$EN = transCacheReqQ_enqP_lat_0$whas ;
|
|
|
|
// register transCacheReqQ_empty_rl
|
|
assign transCacheReqQ_empty_rl$D_IN =
|
|
!transCacheReqQ_enqP_lat_0$whas &&
|
|
(CAN_FIRE_RL_doTranslationCacheResp || transCacheReqQ_empty_rl) ;
|
|
assign transCacheReqQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register transCacheReqQ_full_rl
|
|
assign transCacheReqQ_full_rl$D_IN =
|
|
transCacheReqQ_enqP_lat_0$whas ||
|
|
!CAN_FIRE_RL_doTranslationCacheResp && transCacheReqQ_full_rl ;
|
|
assign transCacheReqQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register vm_info_D
|
|
assign vm_info_D$D_IN = updateVMInfo_vmD ;
|
|
assign vm_info_D$EN = EN_updateVMInfo ;
|
|
|
|
// register vm_info_I
|
|
assign vm_info_I$D_IN = updateVMInfo_vmI ;
|
|
assign vm_info_I$EN = EN_updateVMInfo ;
|
|
|
|
// register waitFlushDone
|
|
assign waitFlushDone$D_IN = !WILL_FIRE_RL_doWaitFlush ;
|
|
assign waitFlushDone$EN =
|
|
WILL_FIRE_RL_doWaitFlush || WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// submodule flushDoneQ_clearReq_dummy2_0
|
|
assign flushDoneQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign flushDoneQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule flushDoneQ_clearReq_dummy2_1
|
|
assign flushDoneQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign flushDoneQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule flushDoneQ_deqReq_dummy2_0
|
|
assign flushDoneQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign flushDoneQ_deqReq_dummy2_0$EN = EN_toChildren_flushDone_get ;
|
|
|
|
// submodule flushDoneQ_deqReq_dummy2_1
|
|
assign flushDoneQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign flushDoneQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule flushDoneQ_deqReq_dummy2_2
|
|
assign flushDoneQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign flushDoneQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule flushDoneQ_enqReq_dummy2_0
|
|
assign flushDoneQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign flushDoneQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_doWaitFlush ;
|
|
|
|
// submodule flushDoneQ_enqReq_dummy2_1
|
|
assign flushDoneQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign flushDoneQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule flushDoneQ_enqReq_dummy2_2
|
|
assign flushDoneQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign flushDoneQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule memReqQ_clearReq_dummy2_0
|
|
assign memReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign memReqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule memReqQ_clearReq_dummy2_1
|
|
assign memReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign memReqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule memReqQ_deqReq_dummy2_0
|
|
assign memReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign memReqQ_deqReq_dummy2_0$EN = EN_toMem_memReq_deq ;
|
|
|
|
// submodule memReqQ_deqReq_dummy2_1
|
|
assign memReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign memReqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule memReqQ_deqReq_dummy2_2
|
|
assign memReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign memReqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule memReqQ_enqReq_dummy2_0
|
|
assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign memReqQ_enqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
!IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639 ||
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 ;
|
|
|
|
// submodule memReqQ_enqReq_dummy2_1
|
|
assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign memReqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule memReqQ_enqReq_dummy2_2
|
|
assign memReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign memReqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule pendValid_0_dummy2_0
|
|
assign pendValid_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign pendValid_0_dummy2_0$EN =
|
|
WILL_FIRE_RL_doTlbResp && _dfoo13 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo101 ;
|
|
|
|
// submodule pendValid_0_dummy2_1
|
|
assign pendValid_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign pendValid_0_dummy2_1$EN = pendValid_0_lat_1$whas ;
|
|
|
|
// submodule pendValid_1_dummy2_0
|
|
assign pendValid_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign pendValid_1_dummy2_0$EN =
|
|
WILL_FIRE_RL_doTlbResp && _dfoo9 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo97 ;
|
|
|
|
// submodule pendValid_1_dummy2_1
|
|
assign pendValid_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign pendValid_1_dummy2_1$EN = pendValid_1_lat_1$whas ;
|
|
|
|
// submodule pendWait_0_dummy2_0
|
|
assign pendWait_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign pendWait_0_dummy2_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd0 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo93 ;
|
|
|
|
// submodule pendWait_0_dummy2_1
|
|
assign pendWait_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign pendWait_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule pendWait_1_dummy2_0
|
|
assign pendWait_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign pendWait_1_dummy2_0$EN =
|
|
WILL_FIRE_RL_doTranslationCacheResp &&
|
|
transCacheReqQ_data_0 == 1'd1 ||
|
|
WILL_FIRE_RL_doPageWalk && _dfoo89 ;
|
|
|
|
// submodule pendWait_1_dummy2_1
|
|
assign pendWait_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign pendWait_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_0
|
|
assign perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_clearReq_dummy2_1
|
|
assign perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_0
|
|
assign perfReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign perfReqQ_deqReq_dummy2_0$EN = EN_perf_resp ;
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_1
|
|
assign perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_deqReq_dummy2_2
|
|
assign perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_0
|
|
assign perfReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign perfReqQ_enqReq_dummy2_0$EN = EN_perf_req ;
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_1
|
|
assign perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule perfReqQ_enqReq_dummy2_2
|
|
assign perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule respLdQ_clearReq_dummy2_0
|
|
assign respLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign respLdQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule respLdQ_clearReq_dummy2_1
|
|
assign respLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign respLdQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule respLdQ_deqReq_dummy2_0
|
|
assign respLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign respLdQ_deqReq_dummy2_0$EN = respLdQ_deqReq_lat_0$whas ;
|
|
|
|
// submodule respLdQ_deqReq_dummy2_1
|
|
assign respLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign respLdQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule respLdQ_deqReq_dummy2_2
|
|
assign respLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign respLdQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule respLdQ_enqReq_dummy2_0
|
|
assign respLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign respLdQ_enqReq_dummy2_0$EN = EN_toMem_respLd_enq ;
|
|
|
|
// submodule respLdQ_enqReq_dummy2_1
|
|
assign respLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign respLdQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule respLdQ_enqReq_dummy2_2
|
|
assign respLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign respLdQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule rqFromCQ_data_0_dummy2_0
|
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assign rqFromCQ_data_0_dummy2_0$D_IN = 1'd1 ;
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assign rqFromCQ_data_0_dummy2_0$EN = EN_toChildren_rqFromC_put ;
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// submodule rqFromCQ_data_0_dummy2_1
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assign rqFromCQ_data_0_dummy2_1$D_IN = 1'b0 ;
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assign rqFromCQ_data_0_dummy2_1$EN = 1'b0 ;
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// submodule rqFromCQ_deqP_dummy2_0
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assign rqFromCQ_deqP_dummy2_0$D_IN = 1'd1 ;
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assign rqFromCQ_deqP_dummy2_0$EN = CAN_FIRE_RL_doTlbReq ;
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// submodule rqFromCQ_deqP_dummy2_1
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assign rqFromCQ_deqP_dummy2_1$D_IN = 1'b0 ;
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assign rqFromCQ_deqP_dummy2_1$EN = 1'b0 ;
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// submodule rqFromCQ_empty_dummy2_0
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assign rqFromCQ_empty_dummy2_0$D_IN = 1'd1 ;
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assign rqFromCQ_empty_dummy2_0$EN = EN_toChildren_rqFromC_put ;
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// submodule rqFromCQ_empty_dummy2_1
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assign rqFromCQ_empty_dummy2_1$D_IN = 1'd1 ;
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assign rqFromCQ_empty_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
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// submodule rqFromCQ_empty_dummy2_2
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assign rqFromCQ_empty_dummy2_2$D_IN = 1'b0 ;
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assign rqFromCQ_empty_dummy2_2$EN = 1'b0 ;
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// submodule rqFromCQ_enqP_dummy2_0
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assign rqFromCQ_enqP_dummy2_0$D_IN = 1'd1 ;
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assign rqFromCQ_enqP_dummy2_0$EN = EN_toChildren_rqFromC_put ;
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// submodule rqFromCQ_enqP_dummy2_1
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assign rqFromCQ_enqP_dummy2_1$D_IN = 1'b0 ;
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assign rqFromCQ_enqP_dummy2_1$EN = 1'b0 ;
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// submodule rqFromCQ_full_dummy2_0
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assign rqFromCQ_full_dummy2_0$D_IN = 1'd1 ;
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assign rqFromCQ_full_dummy2_0$EN = EN_toChildren_rqFromC_put ;
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// submodule rqFromCQ_full_dummy2_1
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assign rqFromCQ_full_dummy2_1$D_IN = 1'd1 ;
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assign rqFromCQ_full_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
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// submodule rqFromCQ_full_dummy2_2
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assign rqFromCQ_full_dummy2_2$D_IN = 1'b0 ;
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assign rqFromCQ_full_dummy2_2$EN = 1'b0 ;
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// submodule rsToCQ_data_0_dummy2_0
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assign rsToCQ_data_0_dummy2_0$D_IN = 1'd1 ;
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assign rsToCQ_data_0_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
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// submodule rsToCQ_data_0_dummy2_1
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assign rsToCQ_data_0_dummy2_1$D_IN = 1'b0 ;
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assign rsToCQ_data_0_dummy2_1$EN = 1'b0 ;
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// submodule rsToCQ_deqP_dummy2_0
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assign rsToCQ_deqP_dummy2_0$D_IN = 1'd1 ;
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assign rsToCQ_deqP_dummy2_0$EN = EN_toChildren_rsToC_deq ;
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// submodule rsToCQ_deqP_dummy2_1
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assign rsToCQ_deqP_dummy2_1$D_IN = 1'b0 ;
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assign rsToCQ_deqP_dummy2_1$EN = 1'b0 ;
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// submodule rsToCQ_empty_dummy2_0
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assign rsToCQ_empty_dummy2_0$D_IN = 1'd1 ;
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assign rsToCQ_empty_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
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// submodule rsToCQ_empty_dummy2_1
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assign rsToCQ_empty_dummy2_1$D_IN = 1'd1 ;
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assign rsToCQ_empty_dummy2_1$EN = EN_toChildren_rsToC_deq ;
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// submodule rsToCQ_empty_dummy2_2
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assign rsToCQ_empty_dummy2_2$D_IN = 1'b0 ;
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assign rsToCQ_empty_dummy2_2$EN = 1'b0 ;
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// submodule rsToCQ_enqP_dummy2_0
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assign rsToCQ_enqP_dummy2_0$D_IN = 1'd1 ;
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assign rsToCQ_enqP_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
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// submodule rsToCQ_enqP_dummy2_1
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assign rsToCQ_enqP_dummy2_1$D_IN = 1'b0 ;
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assign rsToCQ_enqP_dummy2_1$EN = 1'b0 ;
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// submodule rsToCQ_full_dummy2_0
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assign rsToCQ_full_dummy2_0$D_IN = 1'd1 ;
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assign rsToCQ_full_dummy2_0$EN = rsToCQ_data_0_lat_0$whas ;
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// submodule rsToCQ_full_dummy2_1
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assign rsToCQ_full_dummy2_1$D_IN = 1'd1 ;
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assign rsToCQ_full_dummy2_1$EN = EN_toChildren_rsToC_deq ;
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// submodule rsToCQ_full_dummy2_2
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assign rsToCQ_full_dummy2_2$D_IN = 1'b0 ;
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assign rsToCQ_full_dummy2_2$EN = 1'b0 ;
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// submodule tlb4KB_m_pendReq_dummy2_0
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assign tlb4KB_m_pendReq_dummy2_0$D_IN = 1'd1 ;
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assign tlb4KB_m_pendReq_dummy2_0$EN =
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MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
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// submodule tlb4KB_m_pendReq_dummy2_1
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assign tlb4KB_m_pendReq_dummy2_1$D_IN = 1'd1 ;
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assign tlb4KB_m_pendReq_dummy2_1$EN =
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tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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// submodule tlb4KB_m_repRam_bram
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always@(MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 or
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tlb4KB_m_pendReq_rl or
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WILL_FIRE_RL_tlb4KB_m_doFlush or
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|
tlb4KB_m_flushIdx or WILL_FIRE_RL_tlb4KB_m_doAddEntry)
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begin
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case (1'b1) // synopsys parallel_case
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MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1:
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tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_pendReq_rl[7:0];
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WILL_FIRE_RL_tlb4KB_m_doFlush:
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tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_flushIdx;
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WILL_FIRE_RL_tlb4KB_m_doAddEntry:
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tlb4KB_m_repRam_bram$ADDRA = tlb4KB_m_pendReq_rl[60:53];
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default: tlb4KB_m_repRam_bram$ADDRA =
|
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8'b10101010 /* unspecified value */ ;
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endcase
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end
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|
assign tlb4KB_m_repRam_bram$ADDRB =
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MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
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masked_vpn__h136483[7:0] :
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vpn__h104314[7:0] ;
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always@(MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1 or
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MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1 or
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WILL_FIRE_RL_tlb4KB_m_doFlush or
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WILL_FIRE_RL_tlb4KB_m_doAddEntry or
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MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3)
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begin
|
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case (1'b1) // synopsys parallel_case
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MUX_tlb4KB_m_repRam_bram$a_put_1__SEL_1:
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tlb4KB_m_repRam_bram$DIA = MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_1;
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WILL_FIRE_RL_tlb4KB_m_doFlush: tlb4KB_m_repRam_bram$DIA = 8'd228;
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WILL_FIRE_RL_tlb4KB_m_doAddEntry:
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tlb4KB_m_repRam_bram$DIA = MUX_tlb4KB_m_repRam_bram$a_put_3__VAL_3;
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default: tlb4KB_m_repRam_bram$DIA =
|
|
8'b10101010 /* unspecified value */ ;
|
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endcase
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end
|
|
assign tlb4KB_m_repRam_bram$DIB =
|
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MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
8'b10101010 /* unspecified value */ :
|
|
8'b10101010 /* unspecified value */ ;
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assign tlb4KB_m_repRam_bram$WEA = 1'd1 ;
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assign tlb4KB_m_repRam_bram$WEB = 1'd0 ;
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assign tlb4KB_m_repRam_bram$ENA =
|
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WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1548 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ||
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry ;
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assign tlb4KB_m_repRam_bram$ENB = tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0
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assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
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|
assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
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|
// submodule tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1
|
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assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
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assign tlb4KB_m_repRam_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
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// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_0
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assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
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assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
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|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_1
|
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assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_empty_dummy2_2
|
|
assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
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assign tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
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|
|
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// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0
|
|
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_0$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1
|
|
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_repRam_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
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|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_0
|
|
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_1
|
|
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_repRam_rdReqQ_full_dummy2_2
|
|
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_repRam_rdReqQ_full_dummy2_2$EN = 1'b0 ;
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|
|
|
// submodule tlb4KB_m_tlbRam_0_bram
|
|
assign tlb4KB_m_tlbRam_0_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_0_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
masked_vpn__h136483[7:0] :
|
|
vpn__h104314[7:0] ;
|
|
assign tlb4KB_m_tlbRam_0_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA ;
|
|
assign tlb4KB_m_tlbRam_0_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_0_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_0_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd0 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_0_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_0$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_bram
|
|
assign tlb4KB_m_tlbRam_1_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_1_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
masked_vpn__h136483[7:0] :
|
|
vpn__h104314[7:0] ;
|
|
assign tlb4KB_m_tlbRam_1_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_1_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA ;
|
|
assign tlb4KB_m_tlbRam_1_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_1_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_1_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd1 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_1_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
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|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
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|
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// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
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|
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// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_0$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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|
|
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// submodule tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
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|
assign tlb4KB_m_tlbRam_1_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
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// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0
|
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assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
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|
|
|
// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1
|
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assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
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|
|
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// submodule tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2
|
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assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
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|
assign tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$EN = 1'b0 ;
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|
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// submodule tlb4KB_m_tlbRam_2_bram
|
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assign tlb4KB_m_tlbRam_2_bram$ADDRA =
|
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MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_2_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
masked_vpn__h136483[7:0] :
|
|
vpn__h104314[7:0] ;
|
|
assign tlb4KB_m_tlbRam_2_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_2_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA ;
|
|
assign tlb4KB_m_tlbRam_2_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_2_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_2_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd2 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_2_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_0$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_bram
|
|
assign tlb4KB_m_tlbRam_3_bram$ADDRA =
|
|
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 ?
|
|
tlb4KB_m_pendReq_rl[60:53] :
|
|
tlb4KB_m_flushIdx ;
|
|
assign tlb4KB_m_tlbRam_3_bram$ADDRB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
masked_vpn__h136483[7:0] :
|
|
vpn__h104314[7:0] ;
|
|
assign tlb4KB_m_tlbRam_3_bram$DIA =
|
|
MUX_tlb4KB_m_tlbRam_3_bram$a_put_1__SEL_1 ?
|
|
MUX_tlb4KB_m_tlbRam_0_bram$a_put_3__VAL_1 :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA ;
|
|
assign tlb4KB_m_tlbRam_3_bram$DIB =
|
|
MUX_tlb4KB_m_pendReq_dummy2_1$write_1__SEL_1 ?
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
|
|
81'h0AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign tlb4KB_m_tlbRam_3_bram$WEA = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_bram$WEB = 1'd0 ;
|
|
assign tlb4KB_m_tlbRam_3_bram$ENA =
|
|
WILL_FIRE_RL_tlb4KB_m_doAddEntry &&
|
|
tlb4KB_m_repRam_bram$DOB[7:6] == 2'd3 &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 ||
|
|
WILL_FIRE_RL_tlb4KB_m_doFlush ;
|
|
assign tlb4KB_m_tlbRam_3_bram$ENB =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_0$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_0$EN =
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$EN =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlbMG_m_lruBit_dummy2_0
|
|
assign tlbMG_m_lruBit_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlbMG_m_lruBit_dummy2_0$EN =
|
|
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlbMG_m_lruBit_dummy2_1
|
|
assign tlbMG_m_lruBit_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlbMG_m_lruBit_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlbMG_m_updRepIdx_dummy2_0
|
|
assign tlbMG_m_updRepIdx_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlbMG_m_updRepIdx_dummy2_0$EN =
|
|
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule tlbMG_m_updRepIdx_dummy2_1
|
|
assign tlbMG_m_updRepIdx_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlbMG_m_updRepIdx_dummy2_1$EN = tlbMG_m_updRepIdx_lat_1$whas ;
|
|
|
|
// submodule tlbReqQ_deqP_dummy2_0
|
|
assign tlbReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlbReqQ_deqP_dummy2_0$EN = CAN_FIRE_RL_doTlbResp ;
|
|
|
|
// submodule tlbReqQ_deqP_dummy2_1
|
|
assign tlbReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlbReqQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlbReqQ_empty_dummy2_0
|
|
assign tlbReqQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlbReqQ_empty_dummy2_0$EN = CAN_FIRE_RL_doTlbResp ;
|
|
|
|
// submodule tlbReqQ_empty_dummy2_1
|
|
assign tlbReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlbReqQ_empty_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// submodule tlbReqQ_empty_dummy2_2
|
|
assign tlbReqQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlbReqQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule tlbReqQ_enqP_dummy2_0
|
|
assign tlbReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlbReqQ_enqP_dummy2_0$EN = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// submodule tlbReqQ_enqP_dummy2_1
|
|
assign tlbReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign tlbReqQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule tlbReqQ_full_dummy2_0
|
|
assign tlbReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign tlbReqQ_full_dummy2_0$EN = CAN_FIRE_RL_doTlbResp ;
|
|
|
|
// submodule tlbReqQ_full_dummy2_1
|
|
assign tlbReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign tlbReqQ_full_dummy2_1$EN = CAN_FIRE_RL_doTlbReq ;
|
|
|
|
// submodule tlbReqQ_full_dummy2_2
|
|
assign tlbReqQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign tlbReqQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule transCache
|
|
assign transCache$addEntry_level = walkLevel__h136014 ;
|
|
assign transCache$addEntry_ppn =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:10] ;
|
|
assign transCache$addEntry_vpn =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707 ;
|
|
assign transCache$req_vpn = vpn__h116705 ;
|
|
assign transCache$EN_req =
|
|
WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1569 ;
|
|
assign transCache$EN_deqResp = CAN_FIRE_RL_doTranslationCacheResp ;
|
|
assign transCache$EN_addEntry =
|
|
WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2] &&
|
|
walkLevel__h136014 != 2'd0 ;
|
|
assign transCache$EN_flush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// submodule transCacheReqQ_deqP_dummy2_0
|
|
assign transCacheReqQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign transCacheReqQ_deqP_dummy2_0$EN =
|
|
CAN_FIRE_RL_doTranslationCacheResp ;
|
|
|
|
// submodule transCacheReqQ_deqP_dummy2_1
|
|
assign transCacheReqQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign transCacheReqQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule transCacheReqQ_empty_dummy2_0
|
|
assign transCacheReqQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign transCacheReqQ_empty_dummy2_0$EN =
|
|
CAN_FIRE_RL_doTranslationCacheResp ;
|
|
|
|
// submodule transCacheReqQ_empty_dummy2_1
|
|
assign transCacheReqQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign transCacheReqQ_empty_dummy2_1$EN = transCacheReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule transCacheReqQ_empty_dummy2_2
|
|
assign transCacheReqQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign transCacheReqQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule transCacheReqQ_enqP_dummy2_0
|
|
assign transCacheReqQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign transCacheReqQ_enqP_dummy2_0$EN = transCacheReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule transCacheReqQ_enqP_dummy2_1
|
|
assign transCacheReqQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign transCacheReqQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule transCacheReqQ_full_dummy2_0
|
|
assign transCacheReqQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign transCacheReqQ_full_dummy2_0$EN =
|
|
CAN_FIRE_RL_doTranslationCacheResp ;
|
|
|
|
// submodule transCacheReqQ_full_dummy2_1
|
|
assign transCacheReqQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign transCacheReqQ_full_dummy2_1$EN = transCacheReqQ_enqP_lat_0$whas ;
|
|
|
|
// submodule transCacheReqQ_full_dummy2_2
|
|
assign transCacheReqQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign transCacheReqQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BI_ETC___d1347 =
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330 ?
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 :
|
|
(!transCacheReqQ_full_dummy2_1$Q_OUT ||
|
|
!transCacheReqQ_full_dummy2_2$Q_OUT ||
|
|
CAN_FIRE_RL_doTranslationCacheResp ||
|
|
!transCacheReqQ_full_rl) &&
|
|
transCache$RDY_req ;
|
|
assign IF_IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_ETC___d1522 =
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ?
|
|
{ SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457,
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 } :
|
|
{ SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1466,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1472,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1478,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1484,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1486,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1492,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1498,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1504,
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1510,
|
|
x__h121246 } ;
|
|
assign IF_IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_ETC___d1351 =
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086 ?
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 :
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1349 ;
|
|
assign IF_IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_ETC___d1766 =
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ?
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 :
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] ?
|
|
IF_NOT_SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_ETC___d1764 :
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096) ;
|
|
assign IF_IF_respForOtherReq_669_BIT_1_670_THEN_NOT_r_ETC___d1727 =
|
|
(IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1703 ||
|
|
pendWalkAddr_0 != newPTEAddr__h136017) ?
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1723 &&
|
|
pendWait_1_dummy2_0$Q_OUT &&
|
|
pendWait_1_dummy2_1$Q_OUT &&
|
|
pendWait_1_rl[2:1] == 2'd1 &&
|
|
pendWalkAddr_1_636_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1725 :
|
|
idx__h135081 ;
|
|
assign IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 =
|
|
(IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107 &&
|
|
tlbMG_m_validVec_0 &&
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) ?
|
|
!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107 :
|
|
!tlbMG_m_validVec_1 ||
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 ;
|
|
assign IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1213 =
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1185 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1210 ;
|
|
assign IF_NOT_SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_ETC___d1764 =
|
|
(!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) ?
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1730 :
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 &&
|
|
NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1762 ;
|
|
assign IF_NOT_pendWait_0_dummy2_0_read__585_586_OR_NO_ETC___d1787 =
|
|
i__h135439 ?
|
|
pendWait_1_dummy2_0$Q_OUT && pendWait_1_dummy2_1$Q_OUT &&
|
|
pendWait_1_rl[2:1] != 2'd0 &&
|
|
pendWait_1_rl[2:1] != 2'd1 &&
|
|
pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1784 &&
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1723 :
|
|
idx__h135081 ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1561 =
|
|
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1553 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h129824 &&
|
|
tlb4KB_m_repRam_bram$DOB[5:4] != way__h129824) ?
|
|
tlb4KB_m_repRam_bram$DOB[5:4] :
|
|
tlb4KB_m_repRam_bram$DOB[7:6] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d1562 =
|
|
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1553 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h129824) ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[5:4] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d282 =
|
|
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h36041 &&
|
|
tlb4KB_m_repRam_bram$DOB[5:4] != way__h36041) ?
|
|
tlb4KB_m_repRam_bram$DOB[5:4] :
|
|
tlb4KB_m_repRam_bram$DOB[7:6] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d283 =
|
|
(!tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 &&
|
|
tlb4KB_m_repRam_bram$DOB[3:2] != way__h36041) ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[5:4] ;
|
|
assign IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d286 =
|
|
{ IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d282,
|
|
IF_NOT_tlb4KB_m_repRam_bram_b_read__66_BITS_1__ETC___d283,
|
|
tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 ?
|
|
tlb4KB_m_repRam_bram$DOB[3:2] :
|
|
tlb4KB_m_repRam_bram$DOB[1:0],
|
|
way__h36041 } ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308) ?
|
|
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311 :
|
|
tlb4KB_m_tlbRam_0_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1329 =
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311)) ?
|
|
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1320 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1328 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1323 ?
|
|
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1324 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1329 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1332 =
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311)) ?
|
|
2'd2 :
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d263 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
|
|
tlb4KB_m_pendReq_rl[79:53] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) ?
|
|
tlb4KB_m_tlbRam_1_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231 &&
|
|
tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234 :
|
|
tlb4KB_m_tlbRam_0_bram$DOB[80] ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d264 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 ?
|
|
tlb4KB_m_tlbRam_2_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243 &&
|
|
tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d263 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d265 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 ?
|
|
tlb4KB_m_tlbRam_3_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254 &&
|
|
tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d264 ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d269 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 ?
|
|
2'd2 :
|
|
((!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
|
|
tlb4KB_m_pendReq_rl[79:53] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1348 =
|
|
(NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1315 ?
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 :
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1318) &&
|
|
IF_IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BI_ETC___d1347 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1148 ?
|
|
!tlbMG_m_validVec_2 ||
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1185 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1172 ?
|
|
!tlbMG_m_validVec_3 ||
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1210 =
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1188 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193)) ?
|
|
!tlbMG_m_validVec_4 ||
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11 :
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1188 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1236 =
|
|
((!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1213 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222) ?
|
|
!tlbMG_m_validVec_5 ||
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1213 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1239 =
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1185 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1210 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1236 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1263 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1250 ?
|
|
!tlbMG_m_validVec_6 ||
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_NOT_tlbR_ETC__q15 :
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1239 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1349 =
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1269 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302) ?
|
|
NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_304_OR_ETC___d1305 &&
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_ETC___d1348 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1296 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) ?
|
|
tlbMG_m_validVec_1 &&
|
|
IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144 :
|
|
tlbMG_m_validVec_0 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1297 =
|
|
((!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144)) ?
|
|
tlbMG_m_validVec_2 &&
|
|
IF_tlbMG_m_entryVec_2_151_BITS_1_TO_0_152_EQ_0_ETC___d1168 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1296 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1298 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 ?
|
|
tlbMG_m_validVec_3 &&
|
|
IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1297 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1299 =
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193)) ?
|
|
tlbMG_m_validVec_4 &&
|
|
IF_tlbMG_m_entryVec_4_200_BITS_1_TO_0_201_EQ_0_ETC___d1219 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1298 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1300 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 ?
|
|
tlbMG_m_validVec_5 &&
|
|
IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1299 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1301 =
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246)) ?
|
|
tlbMG_m_validVec_6 &&
|
|
IF_tlbMG_m_entryVec_6_253_BITS_1_TO_0_254_EQ_0_ETC___d1274 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1300 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277 ?
|
|
tlbMG_m_validVec_7 &&
|
|
IF_tlbMG_m_entryVec_7_279_BITS_1_TO_0_280_EQ_0_ETC___d1288 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1301 ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1371 =
|
|
((!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144)) ?
|
|
3'd2 :
|
|
((!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) ?
|
|
3'd1 :
|
|
3'd0) ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1373 =
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193)) ?
|
|
3'd4 :
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 ?
|
|
3'd3 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1371) ;
|
|
assign IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1375 =
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246)) ?
|
|
3'd6 :
|
|
(NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 ?
|
|
3'd5 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1373) ;
|
|
assign IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639 =
|
|
(NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 ||
|
|
!pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618) ?
|
|
!transCacheReqQ_data_0 && pendWait_1_dummy2_0$Q_OUT &&
|
|
pendWait_1_dummy2_1$Q_OUT &&
|
|
pendWait_1_rl[2:1] == 2'd1 &&
|
|
pendWalkAddr_1 == pteAddr__h132859 :
|
|
transCacheReqQ_data_0 ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086 =
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1079 ?
|
|
!vm_info_I[46] :
|
|
!vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 =
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1079 ?
|
|
vm_info_I[46] :
|
|
vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 =
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1679 ?
|
|
!vm_info_I[46] :
|
|
!vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1807 =
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
walkLevel__h136014 == 2'd0 ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2] ||
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 =
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1679 ?
|
|
vm_info_I[46] :
|
|
vm_info_D[46] ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 =
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2] &&
|
|
walkLevel__h136014 == 2'd0 ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1863 =
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
walkLevel__h136014 != 2'd0 &&
|
|
((walkLevel__h136014 == 2'd1) ?
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[18:10] !=
|
|
9'd0 :
|
|
walkLevel__h136014 != 2'd2 ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[27:10] !=
|
|
18'd0) ;
|
|
assign IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1868 =
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
walkLevel__h136014 == 2'd0 ;
|
|
assign IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1730 =
|
|
(walkLevel__h136014 == 2'd0) ?
|
|
NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 :
|
|
transCache$RDY_addEntry &&
|
|
(IF_IF_respForOtherReq_669_BIT_1_670_THEN_NOT_r_ETC___d1727 ||
|
|
!memReqQ_full) ;
|
|
assign IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1761 =
|
|
(walkLevel__h136014 == 2'd0) ?
|
|
tlb4KB_m_state &&
|
|
NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943 &&
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953 &&
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d1757 :
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_304_OR_ETC___d1305 ;
|
|
assign IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813 =
|
|
(walkLevel__h136014 == 2'd1) ?
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[18:10] ==
|
|
9'd0 :
|
|
walkLevel__h136014 == 2'd2 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[27:10] ==
|
|
18'd0 ;
|
|
assign IF_memReqQ_deqReq_dummy2_2_read__97_AND_IF_mem_ETC___d705 =
|
|
_theResult_____2__h82166 == v__h81624 ;
|
|
assign IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674 =
|
|
EN_toMem_memReq_deq || memReqQ_deqReq_rl ;
|
|
assign IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[65] :
|
|
memReqQ_enqReq_rl[65] ;
|
|
assign IF_pendValid_0_dummy2_1_read__29_AND_IF_pendVa_ETC___d1020 =
|
|
(pendValid_0_dummy2_1$Q_OUT &&
|
|
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573) ?
|
|
!pendValid_1_dummy2_1$Q_OUT ||
|
|
(pendValid_1_lat_0$whas ? !1'd0 : !pendValid_1_rl) :
|
|
!pendValid_0_dummy2_1$Q_OUT ||
|
|
(pendValid_0_lat_0$whas ? !1'd0 : !pendValid_0_rl) ;
|
|
assign IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 =
|
|
pendValid_0_lat_0$whas ? 1'd0 : pendValid_0_rl ;
|
|
assign IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580 =
|
|
pendValid_1_lat_0$whas ? 1'd0 : pendValid_1_rl ;
|
|
assign IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841 =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[4] :
|
|
perfReqQ_enqReq_rl[4] ;
|
|
assign IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1702 =
|
|
respForOtherReq[1] ? !respForOtherReq[0] : !def__h135309 ;
|
|
assign IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1703 =
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1702 ||
|
|
!pendWait_0_dummy2_0$Q_OUT ||
|
|
!pendWait_0_dummy2_1$Q_OUT ||
|
|
pendWait_0_rl[2:1] != 2'd1 ;
|
|
assign IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1723 =
|
|
respForOtherReq[1] ?
|
|
!respForOtherReq[0] :
|
|
SEL_ARR_NOT_respLdQ_data_0_672_BIT_0_673_719_N_ETC___d1722 ;
|
|
assign IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1850 =
|
|
(IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1703 ||
|
|
pendWalkAddr_0 != newPTEAddr__h136017) &&
|
|
(IF_respForOtherReq_669_BIT_1_670_THEN_respForO_ETC___d1797 ||
|
|
!pendWait_1_dummy2_0$Q_OUT ||
|
|
!pendWait_1_dummy2_1$Q_OUT ||
|
|
pendWait_1_rl[2:1] != 2'd1 ||
|
|
!pendWalkAddr_1_636_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1725) ;
|
|
assign IF_respForOtherReq_669_BIT_1_670_THEN_respForO_ETC___d1797 =
|
|
respForOtherReq[1] ?
|
|
respForOtherReq[0] :
|
|
!SEL_ARR_NOT_respLdQ_data_0_672_BIT_0_673_719_N_ETC___d1722 ;
|
|
assign IF_respLdQ_deqReq_dummy2_2_read__94_AND_IF_res_ETC___d802 =
|
|
_theResult_____2__h89736 == v__h89194 ;
|
|
assign IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771 =
|
|
respLdQ_deqReq_lat_0$whas || respLdQ_deqReq_rl ;
|
|
assign IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 =
|
|
EN_toMem_respLd_enq ?
|
|
respLdQ_enqReq_lat_0$wget[65] :
|
|
respLdQ_enqReq_rl[65] ;
|
|
assign IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d471 =
|
|
EN_toChildren_rqFromC_put ?
|
|
toChildren_rqFromC_put[29] :
|
|
rqFromCQ_data_0_rl[29] ;
|
|
assign IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d481 =
|
|
EN_toChildren_rqFromC_put ?
|
|
toChildren_rqFromC_put[28:27] :
|
|
rqFromCQ_data_0_rl[28:27] ;
|
|
assign IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487 =
|
|
EN_toChildren_rqFromC_put ?
|
|
toChildren_rqFromC_put[26:0] :
|
|
rqFromCQ_data_0_rl[26:0] ;
|
|
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d518 =
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[83] :
|
|
rsToCQ_data_0_rl[83] ;
|
|
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d528 =
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[82:81] :
|
|
rsToCQ_data_0_rl[82:81] ;
|
|
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d534 =
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[80] :
|
|
rsToCQ_data_0_rl[80] ;
|
|
assign IF_rsToCQ_data_0_lat_0_whas__13_THEN_rsToCQ_da_ETC___d544 =
|
|
rsToCQ_data_0_lat_0$whas ?
|
|
rsToCQ_data_0_lat_0$wget[79:0] :
|
|
rsToCQ_data_0_rl[79:0] ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
!tlb4KB_m_pendReq_lat_1$wget[80] :
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_pendReq_rl[80] ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d110 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[81] :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_pendReq_rl[81] ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[80] :
|
|
!MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 &&
|
|
tlb4KB_m_pendReq_rl[80] ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[26:0] :
|
|
(MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ?
|
|
27'b010101010101010101010101010 :
|
|
tlb4KB_m_pendReq_rl[26:0]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136 =
|
|
tlb4KB_m_tlbRam_0_rdReqQ_enqP_lat_0$whas ?
|
|
tlb4KB_m_pendReq_lat_1$wget[79:0] :
|
|
(MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ?
|
|
80'hAAAAAAAAAAAAAAAAAAAA :
|
|
tlb4KB_m_pendReq_rl[79:0]) ;
|
|
assign IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d138 =
|
|
{ IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d120,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_NOT_tl_ETC___d125 ?
|
|
{ 53'h0AAAAAAAAAAAAA,
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d130 } :
|
|
IF_tlb4KB_m_pendReq_lat_1_whas__01_THEN_tlb4KB_ETC___d136 } ;
|
|
assign IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121 =
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn16705_ETC__q4 ==
|
|
tlbMG_m_entryVec_0[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144 =
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn16705_ETC__q5 ==
|
|
tlbMG_m_entryVec_1[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_2_151_BITS_1_TO_0_152_EQ_0_ETC___d1168 =
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn16705_ETC__q8 ==
|
|
tlbMG_m_entryVec_2[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193 =
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn16705_ETC__q10 ==
|
|
tlbMG_m_entryVec_3[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_4_200_BITS_1_TO_0_201_EQ_0_ETC___d1219 =
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn16705_ETC__q12 ==
|
|
tlbMG_m_entryVec_4[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246 =
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn16705_ETC__q14 ==
|
|
tlbMG_m_entryVec_5[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_6_253_BITS_1_TO_0_254_EQ_0_ETC___d1274 =
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn16705_ETC__q16 ==
|
|
tlbMG_m_entryVec_6[79:53] ;
|
|
assign IF_tlbMG_m_entryVec_7_279_BITS_1_TO_0_280_EQ_0_ETC___d1288 =
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn16705_ETC__q17 ==
|
|
tlbMG_m_entryVec_7[79:53] ;
|
|
assign IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976 =
|
|
tlbMG_m_lruBit_dummy2_1$Q_OUT ?
|
|
~IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321 :
|
|
8'd255 ;
|
|
assign IF_tlbMG_m_lruBit_lat_0_whas__18_THEN_tlbMG_m__ETC___d321 =
|
|
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
|
|
upd__h144892 :
|
|
tlbMG_m_lruBit_rl ;
|
|
assign IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d332 =
|
|
tlbMG_m_updRepIdx_lat_1$whas ?
|
|
tlbMG_m_updRepIdx_lat_1$wget[3] :
|
|
!MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 &&
|
|
tlbMG_m_updRepIdx_rl[3] ;
|
|
assign IF_tlbMG_m_updRepIdx_lat_1_whas__23_THEN_tlbMG_ETC___d342 =
|
|
tlbMG_m_updRepIdx_lat_1$whas ?
|
|
tlbMG_m_updRepIdx_lat_1$wget[2:0] :
|
|
(MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ?
|
|
3'b010 :
|
|
tlbMG_m_updRepIdx_rl[2:0]) ;
|
|
assign IF_tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_ETC___d2023 =
|
|
(tlbMG_m_validVec_0 && tlbMG_m_validVec_1) ?
|
|
(tlbMG_m_validVec_2 ? 3'd3 : 3'd2) :
|
|
(tlbMG_m_validVec_0 ? 3'd1 : 3'd0) ;
|
|
assign IF_tlbMG_m_validVec_4_198_AND_tlbMG_m_validVec_ETC___d2020 =
|
|
(tlbMG_m_validVec_4 && tlbMG_m_validVec_5) ?
|
|
(tlbMG_m_validVec_6 ? 3'd7 : 3'd6) :
|
|
(tlbMG_m_validVec_4 ? 3'd5 : 3'd4) ;
|
|
assign IF_transCacheReqQ_data_0_583_AND_pendWait_0_du_ETC___d1629 =
|
|
(transCacheReqQ_data_0 && pendWait_0_dummy2_0$Q_OUT &&
|
|
pendWait_0_dummy2_1$Q_OUT &&
|
|
pendWait_0_rl[2:1] == 2'd1 &&
|
|
pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618) ?
|
|
IF_transCache_RDY_resp__571_AND_transCache_res_ETC___d1596 :
|
|
transCacheReqQ_data_0 || !pendWait_1_dummy2_0$Q_OUT ||
|
|
!pendWait_1_dummy2_1$Q_OUT ||
|
|
pendWait_1_rl[2:1] != 2'd1 ||
|
|
IF_transCache_RDY_resp__571_AND_transCache_res_ETC___d1596 ;
|
|
assign IF_transCache_RDY_resp__571_AND_transCache_res_ETC___d1596 =
|
|
(transCache$RDY_resp &&
|
|
transCache_resp__592_BITS_45_TO_44_593_ULT_2___d1594) ?
|
|
transCache$RDY_resp :
|
|
NOT_transCacheReqQ_empty_dummy2_0_read__573_57_ETC___d1582 ;
|
|
assign NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1762 =
|
|
walkLevel__h136014 != 2'd0 &&
|
|
((walkLevel__h136014 == 2'd1) ?
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[18:10] !=
|
|
9'd0 :
|
|
walkLevel__h136014 != 2'd2 ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[27:10] !=
|
|
18'd0) ||
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1761 ;
|
|
assign NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1878 =
|
|
walkLevel__h136014 != 2'd0 &&
|
|
masked_ppn__h136484 !=
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q18 ;
|
|
assign NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1891 =
|
|
walkLevel__h136014 != 2'd0 &&
|
|
masked_vpn__h136483 !=
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q19 ;
|
|
assign NOT_flushDoneQ_enqReq_dummy2_2_read__36_51_OR__ETC___d461 =
|
|
(!flushDoneQ_enqReq_dummy2_2$Q_OUT ||
|
|
!CAN_FIRE_RL_doWaitFlush && !flushDoneQ_enqReq_rl) &&
|
|
(flushDoneQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_toChildren_flushDone_get || flushDoneQ_deqReq_rl) ||
|
|
flushDoneQ_empty) ;
|
|
assign NOT_memReqQ_clearReq_dummy2_1_read__83_84_OR_I_ETC___d688 =
|
|
!memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ;
|
|
assign NOT_memReqQ_enqReq_dummy2_2_read__89_19_OR_IF__ETC___d723 =
|
|
(!memReqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(memReqQ_enqReq_lat_0$whas ?
|
|
!memReqQ_enqReq_lat_0$wget[65] :
|
|
!memReqQ_enqReq_rl[65])) &&
|
|
(memReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674 ||
|
|
memReqQ_empty) ;
|
|
assign NOT_perfReqQ_clearReq_dummy2_1_read__76_77_OR__ETC___d881 =
|
|
!perfReqQ_clearReq_dummy2_1$Q_OUT || !perfReqQ_clearReq_rl ;
|
|
assign NOT_perfReqQ_enqReq_dummy2_2_read__82_97_OR_IF_ETC___d902 =
|
|
(!perfReqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_perf_req ?
|
|
!perfReqQ_enqReq_lat_0$wget[4] :
|
|
!perfReqQ_enqReq_rl[4])) &&
|
|
(perfReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_perf_resp || perfReqQ_deqReq_rl) ||
|
|
perfReqQ_empty) ;
|
|
assign NOT_respLdQ_clearReq_dummy2_1_read__80_81_OR_I_ETC___d785 =
|
|
!respLdQ_clearReq_dummy2_1$Q_OUT || !respLdQ_clearReq_rl ;
|
|
assign NOT_respLdQ_enqReq_dummy2_2_read__86_16_OR_IF__ETC___d820 =
|
|
(!respLdQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_toMem_respLd_enq ?
|
|
!respLdQ_enqReq_lat_0$wget[65] :
|
|
!respLdQ_enqReq_rl[65])) &&
|
|
(respLdQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771 ||
|
|
respLdQ_empty) ;
|
|
assign NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927 =
|
|
!rqFromCQ_empty_dummy2_1$Q_OUT ||
|
|
!rqFromCQ_empty_dummy2_2$Q_OUT ||
|
|
EN_toChildren_rqFromC_put ||
|
|
!rqFromCQ_empty_rl ;
|
|
assign NOT_rsToCQ_full_dummy2_0_read__087_088_OR_NOT__ETC___d1096 =
|
|
!rsToCQ_full_dummy2_0$Q_OUT || !rsToCQ_full_dummy2_1$Q_OUT ||
|
|
!rsToCQ_full_dummy2_2$Q_OUT ||
|
|
!rsToCQ_full_rl ;
|
|
assign NOT_tlb4KB_m_pendReq_dummy2_1_read__42_08_OR_I_ETC___d943 =
|
|
!tlb4KB_m_pendReq_dummy2_1$Q_OUT ||
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_pendReq_rl[81] ;
|
|
assign NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205 =
|
|
!tlb4KB_m_repRam_rdReqQ_empty_dummy2_0$Q_OUT ||
|
|
!tlb4KB_m_repRam_rdReqQ_empty_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_repRam_rdReqQ_empty_dummy2_2$Q_OUT ||
|
|
!tlb4KB_m_repRam_rdReqQ_empty_rl ;
|
|
assign NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989 =
|
|
!tlb4KB_m_repRam_rdReqQ_full_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_repRam_rdReqQ_full_dummy2_2$Q_OUT ||
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_repRam_rdReqQ_full_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1323 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311) &&
|
|
(!tlb4KB_m_tlbRam_2_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1320) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 =
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] !=
|
|
tlb4KB_m_pendReq_rl[79:53] ||
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6] != tlb4KB_m_pendReq_rl[6]) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231 ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d238 &&
|
|
(!tlb4KB_m_tlbRam_2_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243 ||
|
|
!tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d307 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 &&
|
|
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254 ||
|
|
!tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1315 =
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 &&
|
|
(!tlb4KB_m_tlbRam_0_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308) &&
|
|
(!tlb4KB_m_tlbRam_1_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1318 =
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
|
|
(tlb4KB_m_tlbRam_0_bram$DOB[80] &&
|
|
tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308 ||
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175) ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d1357 =
|
|
NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 &&
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 &&
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 &&
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195 &&
|
|
NOT_tlb4KB_m_repRam_rdReqQ_empty_dummy2_0_read_ETC___d205 &&
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070 &&
|
|
IF_IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_ETC___d1351 ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0_re_ETC___d165 =
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_0$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_dummy2_2$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_empty_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1_rea_ETC___d953 =
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_full_dummy2_2$Q_OUT ||
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_tlbRam_0_rdReqQ_full_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0_re_ETC___d175 =
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_0$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_dummy2_2$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_empty_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d1757 =
|
|
NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962 &&
|
|
NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971 &&
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980 &&
|
|
NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989 &&
|
|
(!tlb4KB_m_pendIndex$wget[8] ||
|
|
tlb4KB_m_pendIndex$wget[7:0] != masked_vpn__h136483[7:0]) ;
|
|
assign NOT_tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1_rea_ETC___d962 =
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_full_dummy2_2$Q_OUT ||
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_tlbRam_1_rdReqQ_full_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0_re_ETC___d185 =
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_0$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_dummy2_2$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_empty_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1_rea_ETC___d971 =
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_full_dummy2_2$Q_OUT ||
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_tlbRam_2_rdReqQ_full_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0_re_ETC___d195 =
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_0$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_empty_dummy2_2$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_empty_rl ;
|
|
assign NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d1024 =
|
|
NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980 &&
|
|
NOT_tlb4KB_m_repRam_rdReqQ_full_dummy2_1_read__ETC___d989 &&
|
|
(!tlbReqQ_full_dummy2_1$Q_OUT || !tlbReqQ_full_dummy2_2$Q_OUT ||
|
|
CAN_FIRE_RL_doTlbResp ||
|
|
!tlbReqQ_full_rl) &&
|
|
(!tlb4KB_m_pendIndex$wget[8] ||
|
|
tlb4KB_m_pendIndex$wget[7:0] != vpn__h104314[7:0]) &&
|
|
IF_pendValid_0_dummy2_1_read__29_AND_IF_pendVa_ETC___d1020 ;
|
|
assign NOT_tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1_rea_ETC___d980 =
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_1$Q_OUT ||
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_full_dummy2_2$Q_OUT ||
|
|
MUX_tlb4KB_m_pendReq_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlb4KB_m_tlbRam_3_rdReqQ_full_rl ;
|
|
assign NOT_tlbMG_m_entryVec_0_099_BITS_79_TO_53_120_E_ETC___d1904 =
|
|
tlbMG_m_entryVec_0[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_0[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_0[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1912 =
|
|
tlbMG_m_entryVec_1[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_1[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_1[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1966 =
|
|
NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1912 &&
|
|
NOT_tlbMG_m_entryVec_2_151_BITS_79_TO_53_167_E_ETC___d1920 &&
|
|
NOT_tlbMG_m_entryVec_3_175_BITS_79_TO_53_192_E_ETC___d1928 &&
|
|
NOT_tlbMG_m_entryVec_4_200_BITS_79_TO_53_218_E_ETC___d1936 &&
|
|
NOT_tlbMG_m_entryVec_5_226_BITS_79_TO_53_245_E_ETC___d1944 &&
|
|
NOT_tlbMG_m_entryVec_6_253_BITS_79_TO_53_273_E_ETC___d1952 &&
|
|
NOT_tlbMG_m_entryVec_7_279_BITS_79_TO_53_287_E_ETC___d1960 ;
|
|
assign NOT_tlbMG_m_entryVec_2_151_BITS_79_TO_53_167_E_ETC___d1920 =
|
|
tlbMG_m_entryVec_2[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_2[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_2[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_3_175_BITS_79_TO_53_192_E_ETC___d1928 =
|
|
tlbMG_m_entryVec_3[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_3[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_3[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_4_200_BITS_79_TO_53_218_E_ETC___d1936 =
|
|
tlbMG_m_entryVec_4[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_4[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_4[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_5_226_BITS_79_TO_53_245_E_ETC___d1944 =
|
|
tlbMG_m_entryVec_5[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_5[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_5[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_6_253_BITS_79_TO_53_273_E_ETC___d1952 =
|
|
tlbMG_m_entryVec_6[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_6[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_6[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_entryVec_7_279_BITS_79_TO_53_287_E_ETC___d1960 =
|
|
tlbMG_m_entryVec_7[79:53] != masked_vpn__h136483 ||
|
|
tlbMG_m_entryVec_7[1:0] != walkLevel__h136014 ||
|
|
tlbMG_m_entryVec_7[6] !=
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[5] ;
|
|
assign NOT_tlbMG_m_updRepIdx_dummy2_1_read__50_304_OR_ETC___d1305 =
|
|
!tlbMG_m_updRepIdx_dummy2_1$Q_OUT ||
|
|
MUX_tlbMG_m_updRepIdx_dummy_1_0$wset_1__VAL_1 ||
|
|
!tlbMG_m_updRepIdx_rl[3] ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1148 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
(!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144) ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1172 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1188 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1185 ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1250 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1239 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246) ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG_m_e_ETC___d1269 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107) &&
|
|
IF_IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_E_ETC___d1136 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1161 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1185 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1210 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1236 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_IF_tlbMG__ETC___d1263 ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 =
|
|
(!tlbMG_m_validVec_0 ||
|
|
!IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1121) &&
|
|
(!tlbMG_m_validVec_1 ||
|
|
!IF_tlbMG_m_entryVec_1_126_BITS_1_TO_0_127_EQ_0_ETC___d1144) &&
|
|
(!tlbMG_m_validVec_2 ||
|
|
!IF_tlbMG_m_entryVec_2_151_BITS_1_TO_0_152_EQ_0_ETC___d1168) ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1171 &&
|
|
(!tlbMG_m_validVec_3 ||
|
|
!IF_tlbMG_m_entryVec_3_175_BITS_1_TO_0_176_EQ_0_ETC___d1193) &&
|
|
(!tlbMG_m_validVec_4 ||
|
|
!IF_tlbMG_m_entryVec_4_200_BITS_1_TO_0_201_EQ_0_ETC___d1219) ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1222 &&
|
|
(!tlbMG_m_validVec_5 ||
|
|
!IF_tlbMG_m_entryVec_5_226_BITS_1_TO_0_227_EQ_0_ETC___d1246) &&
|
|
(!tlbMG_m_validVec_6 ||
|
|
!IF_tlbMG_m_entryVec_6_253_BITS_1_TO_0_254_EQ_0_ETC___d1274) ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1546 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277 &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
!IF_tlbMG_m_entryVec_7_279_BITS_1_TO_0_280_EQ_0_ETC___d1288) &&
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330 &&
|
|
x__h121246 != 2'd0 ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1548 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277 &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
!IF_tlbMG_m_entryVec_7_279_BITS_1_TO_0_280_EQ_0_ETC___d1288) &&
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1330 ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1569 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277 &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
!IF_tlbMG_m_entryVec_7_279_BITS_1_TO_0_280_EQ_0_ETC___d1288) &&
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1323 &&
|
|
(!tlb4KB_m_tlbRam_3_bram$DOB[80] ||
|
|
!tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1324) ;
|
|
assign NOT_tlbMG_m_validVec_0_097_098_OR_NOT_tlbMG_m__ETC___d2017 =
|
|
!tlbMG_m_validVec_0 || !tlbMG_m_validVec_1 ||
|
|
!tlbMG_m_validVec_2 ||
|
|
!tlbMG_m_validVec_3 ||
|
|
!tlbMG_m_validVec_4 ||
|
|
!tlbMG_m_validVec_5 ||
|
|
!tlbMG_m_validVec_6 ||
|
|
!tlbMG_m_validVec_7 ;
|
|
assign NOT_tlbMG_m_validVec_1_124_125_OR_NOT_tlbMG_m__ETC___d2056 =
|
|
(!tlbMG_m_validVec_1 ||
|
|
NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1912) &&
|
|
(!tlbMG_m_validVec_2 ||
|
|
NOT_tlbMG_m_entryVec_2_151_BITS_79_TO_53_167_E_ETC___d1920) &&
|
|
NOT_tlbMG_m_validVec_3_173_174_OR_NOT_tlbMG_m__ETC___d2054 ;
|
|
assign NOT_tlbMG_m_validVec_3_173_174_OR_NOT_tlbMG_m__ETC___d2054 =
|
|
(!tlbMG_m_validVec_3 ||
|
|
NOT_tlbMG_m_entryVec_3_175_BITS_79_TO_53_192_E_ETC___d1928) &&
|
|
(!tlbMG_m_validVec_4 ||
|
|
NOT_tlbMG_m_entryVec_4_200_BITS_79_TO_53_218_E_ETC___d1936) &&
|
|
NOT_tlbMG_m_validVec_5_224_225_OR_NOT_tlbMG_m__ETC___d2052 ;
|
|
assign NOT_tlbMG_m_validVec_5_224_225_OR_NOT_tlbMG_m__ETC___d2052 =
|
|
(!tlbMG_m_validVec_5 ||
|
|
NOT_tlbMG_m_entryVec_5_226_BITS_79_TO_53_245_E_ETC___d1944) &&
|
|
(!tlbMG_m_validVec_6 ||
|
|
NOT_tlbMG_m_entryVec_6_253_BITS_79_TO_53_273_E_ETC___d1952) &&
|
|
(!tlbMG_m_validVec_7 ||
|
|
NOT_tlbMG_m_entryVec_7_279_BITS_79_TO_53_287_E_ETC___d1960) ;
|
|
assign NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070 =
|
|
!tlbReqQ_empty_dummy2_0$Q_OUT || !tlbReqQ_empty_dummy2_1$Q_OUT ||
|
|
!tlbReqQ_empty_dummy2_2$Q_OUT ||
|
|
!tlbReqQ_empty_rl ;
|
|
assign NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 =
|
|
!transCacheReqQ_data_0 || !pendWait_0_dummy2_0$Q_OUT ||
|
|
!pendWait_0_dummy2_1$Q_OUT ||
|
|
pendWait_0_rl[2:1] != 2'd1 ;
|
|
assign NOT_transCacheReqQ_empty_dummy2_0_read__573_57_ETC___d1582 =
|
|
!transCacheReqQ_empty_dummy2_0$Q_OUT ||
|
|
!transCacheReqQ_empty_dummy2_1$Q_OUT ||
|
|
!transCacheReqQ_empty_dummy2_2$Q_OUT ||
|
|
!transCacheReqQ_empty_rl ;
|
|
assign SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1816 =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
(walkLevel__h136014 == 2'd0 ||
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813) ;
|
|
assign SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842 =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2] &&
|
|
walkLevel__h136014 != 2'd0 &&
|
|
IF_IF_respForOtherReq_669_BIT_1_670_THEN_NOT_r_ETC___d1727 ;
|
|
assign SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] &&
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2] &&
|
|
walkLevel__h136014 != 2'd0 &&
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1850 ;
|
|
assign SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2009 =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813 &&
|
|
walkLevel__h136014 != 2'd0 &&
|
|
NOT_tlbMG_m_entryVec_0_099_BITS_79_TO_53_120_E_ETC___d1904 &&
|
|
NOT_tlbMG_m_entryVec_1_126_BITS_79_TO_53_143_E_ETC___d1966 &&
|
|
tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_1__ETC___d2004 ;
|
|
assign SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2061 =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813 &&
|
|
walkLevel__h136014 != 2'd0 &&
|
|
(!tlbMG_m_validVec_0 ||
|
|
NOT_tlbMG_m_entryVec_0_099_BITS_79_TO_53_120_E_ETC___d1904) &&
|
|
NOT_tlbMG_m_validVec_1_124_125_OR_NOT_tlbMG_m__ETC___d2056 ;
|
|
assign _dfoo101 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo45 ;
|
|
assign _dfoo103 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo45 ;
|
|
assign _dfoo13 =
|
|
tlbReqQ_data_0 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086 ||
|
|
tlbReqQ_data_0 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
(IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ||
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1548) ;
|
|
assign _dfoo41 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1863 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1816 ||
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0]) ;
|
|
assign _dfoo45 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1863 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1816 ||
|
|
!SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0]) ;
|
|
assign _dfoo65 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 ||
|
|
_dfoo41 ;
|
|
assign _dfoo67 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 ||
|
|
_dfoo41 ;
|
|
assign _dfoo68 =
|
|
(idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842) ?
|
|
{ 2'd2,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1703 ||
|
|
pendWalkAddr_0 != newPTEAddr__h136017 } :
|
|
((idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853) ?
|
|
3'd2 :
|
|
3'd0) ;
|
|
assign _dfoo69 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 ||
|
|
_dfoo45 ;
|
|
assign _dfoo71 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853 ||
|
|
_dfoo45 ;
|
|
assign _dfoo72 =
|
|
(idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1842) ?
|
|
{ 2'd2,
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1703 ||
|
|
pendWalkAddr_0 != newPTEAddr__h136017 } :
|
|
((idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1853) ?
|
|
3'd2 :
|
|
3'd0) ;
|
|
assign _dfoo89 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo65 ;
|
|
assign _dfoo9 =
|
|
tlbReqQ_data_0 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086 ||
|
|
tlbReqQ_data_0 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
(IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 ||
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1548) ;
|
|
assign _dfoo91 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo67 ;
|
|
assign _dfoo93 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo69 ;
|
|
assign _dfoo95 =
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd0 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo71 ;
|
|
assign _dfoo97 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo41 ;
|
|
assign _dfoo99 =
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1680 ||
|
|
idx__h135081 == 1'd1 &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1837 ||
|
|
_dfoo41 ;
|
|
assign _theResult_____2__h82166 =
|
|
(memReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_deqReq_lat_1_whas__68_THEN_memReqQ__ETC___d674) ?
|
|
next_deqP___1__h82485 :
|
|
memReqQ_deqP ;
|
|
assign _theResult_____2__h89736 =
|
|
(respLdQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_respLdQ_deqReq_lat_1_whas__65_THEN_respLdQ__ETC___d771) ?
|
|
next_deqP___1__h90055 :
|
|
respLdQ_deqP ;
|
|
assign addIdx__h146150 =
|
|
(!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[0] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[1] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[2] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[3]) ?
|
|
((!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[4] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[5]) ?
|
|
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[6] ?
|
|
3'd6 :
|
|
3'd7) :
|
|
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[4] ?
|
|
3'd4 :
|
|
3'd5)) :
|
|
((!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[0] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[1]) ?
|
|
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[2] ?
|
|
3'd2 :
|
|
3'd3) :
|
|
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[0] ?
|
|
3'd0 :
|
|
3'd1)) ;
|
|
assign addIdx__h147417 =
|
|
(tlbMG_m_validVec_0 && tlbMG_m_validVec_1 &&
|
|
tlbMG_m_validVec_2 &&
|
|
tlbMG_m_validVec_3) ?
|
|
IF_tlbMG_m_validVec_4_198_AND_tlbMG_m_validVec_ETC___d2020 :
|
|
IF_tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_ETC___d2023 ;
|
|
assign baseAddr__h132858 = { 8'd0, x__h133131 } ;
|
|
assign basePpn__h133127 =
|
|
transCache_resp__592_BITS_45_TO_44_593_ULT_2___d1594 ?
|
|
transCache$resp[43:0] :
|
|
rootPPN__h132857 ;
|
|
assign flushDoneQ_enqReq_dummy2_2_read__36_AND_IF_flu_ETC___d448 =
|
|
flushDoneQ_enqReq_dummy2_2$Q_OUT &&
|
|
(CAN_FIRE_RL_doWaitFlush || flushDoneQ_enqReq_rl) ||
|
|
(!flushDoneQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_toChildren_flushDone_get && !flushDoneQ_deqReq_rl) &&
|
|
flushDoneQ_full ;
|
|
assign i__h135439 =
|
|
!pendWait_0_dummy2_0$Q_OUT || !pendWait_0_dummy2_1$Q_OUT ||
|
|
pendWait_0_rl[2:1] == 2'd0 ||
|
|
pendWait_0_rl[2:1] == 2'd1 ||
|
|
pendWait_0_rl[0] != def__h135309 ||
|
|
IF_respForOtherReq_669_BIT_1_670_THEN_NOT_resp_ETC___d1702 ;
|
|
assign idx__h118141 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1277 ?
|
|
3'd7 :
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1375 ;
|
|
assign idx__h135081 =
|
|
respForOtherReq[1] ? respForOtherReq[0] : def__h135309 ;
|
|
assign memReqQ_enqReq_dummy2_2_read__89_AND_IF_memReq_ETC___d715 =
|
|
memReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648 ||
|
|
(!memReqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_toMem_memReq_deq && !memReqQ_deqReq_rl) &&
|
|
memReqQ_full ;
|
|
assign newPTBase__h136016 = { 8'd0, x__h136105 } ;
|
|
assign newPTEAddr__h136017 =
|
|
newPTBase__h136016 + { 52'd0, x__h136122, 3'd0 } ;
|
|
assign newWalkLevel__h136015 = walkLevel__h136014 - 2'd1 ;
|
|
assign next_deqP___1__h82485 = memReqQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h90055 = respLdQ_deqP + 1'd1 ;
|
|
assign pendValid_0_dummy2_0_read__28_AND_pendValid_0__ETC___d936 =
|
|
pendValid_0_dummy2_0$Q_OUT && pendValid_0_dummy2_1$Q_OUT &&
|
|
pendValid_0_rl ||
|
|
pendValid_1_dummy2_0$Q_OUT && pendValid_1_dummy2_1$Q_OUT &&
|
|
pendValid_1_rl ;
|
|
assign pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051 =
|
|
pendWait_0_dummy2_1$Q_OUT &&
|
|
(pendWait_0_lat_0$whas ?
|
|
pendWait_0_lat_0$wget[2:1] != 2'd0 :
|
|
pendWait_0_rl[2:1] != 2'd0) ;
|
|
assign pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056 =
|
|
pendWait_1_dummy2_1$Q_OUT &&
|
|
(pendWait_1_lat_0$whas ?
|
|
pendWait_1_lat_0$wget[2:1] != 2'd0 :
|
|
pendWait_1_rl[2:1] != 2'd0) ;
|
|
assign pendWait_1_rl_18_BIT_0_30_EQ_SEL_ARR_respLdQ_d_ETC___d1784 =
|
|
pendWait_1_rl[0] == def__h135309 ;
|
|
assign pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618 =
|
|
pendWalkAddr_0 == pteAddr__h132859 ;
|
|
assign pendWalkAddr_1_636_EQ_0_CONCAT_SEL_ARR_respLdQ_ETC___d1725 =
|
|
pendWalkAddr_1 == newPTEAddr__h136017 ;
|
|
assign perfReqQ_enqReq_dummy2_2_read__82_AND_IF_perfR_ETC___d894 =
|
|
perfReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_perfReqQ_enqReq_lat_1_whas__32_THEN_perfReq_ETC___d841 ||
|
|
(!perfReqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_perf_resp && !perfReqQ_deqReq_rl) &&
|
|
perfReqQ_full ;
|
|
assign pteAddr__h132859 = baseAddr__h132858 + { 52'd0, x__h133171, 3'd0 } ;
|
|
assign respLdQ_enqReq_dummy2_2_read__86_AND_IF_respLd_ETC___d812 =
|
|
respLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745 ||
|
|
(!respLdQ_deqReq_dummy2_2$Q_OUT ||
|
|
!respLdQ_deqReq_lat_0$whas && !respLdQ_deqReq_rl) &&
|
|
respLdQ_full ;
|
|
assign rootPPN__h132857 =
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3 ?
|
|
vm_info_I[43:0] :
|
|
vm_info_D[43:0] ;
|
|
assign tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d1553 =
|
|
tlb4KB_m_repRam_bram$DOB[1:0] == way__h129824 ;
|
|
assign tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d271 =
|
|
tlb4KB_m_repRam_bram$DOB[1:0] == way__h36041 ;
|
|
assign tlb4KB_m_repRam_bram_b_read__66_BITS_1_TO_0_67_ETC___d287 =
|
|
tlb4KB_m_repRam_bram$DOB[1:0] == tlb4KB_m_repRam_bram$DOB[7:6] ;
|
|
assign tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_79_TO_5_ETC___d1308 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d1311 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_1_bram_b_read__27_BITS_79_TO_5_ETC___d231 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
|
|
assign tlb4KB_m_tlbRam_1_bram_b_read__27_BIT_6_33_EQ__ETC___d234 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
|
|
assign tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d1320 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_2_bram_b_read__39_BITS_79_TO_5_ETC___d243 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
|
|
assign tlb4KB_m_tlbRam_2_bram_b_read__39_BIT_6_45_EQ__ETC___d246 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
|
|
assign tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d1324 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[26:0] ;
|
|
assign tlb4KB_m_tlbRam_3_bram_b_read__51_BITS_79_TO_5_ETC___d254 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[79:53] == tlb4KB_m_pendReq_rl[79:53] ;
|
|
assign tlb4KB_m_tlbRam_3_bram_b_read__51_BIT_6_55_EQ__ETC___d256 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[6] == tlb4KB_m_pendReq_rl[6] ;
|
|
assign tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_1__ETC___d1974 =
|
|
tlbMG_m_validVec_0 && tlbMG_m_validVec_1 && tlbMG_m_validVec_2 &&
|
|
tlbMG_m_validVec_3 &&
|
|
tlbMG_m_validVec_4 &&
|
|
tlbMG_m_validVec_5 &&
|
|
tlbMG_m_validVec_6 &&
|
|
tlbMG_m_validVec_7 ;
|
|
assign tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_1__ETC___d2004 =
|
|
tlbMG_m_validVec_0_097_AND_tlbMG_m_validVec_1__ETC___d1974 &&
|
|
!SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[0] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[1] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[2] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[3] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[4] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[5] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[6] &&
|
|
!IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[7] ;
|
|
assign transCache_RDY_deqResp__572_AND_NOT_transCache_ETC___d1644 =
|
|
transCache$RDY_deqResp &&
|
|
NOT_transCacheReqQ_empty_dummy2_0_read__573_57_ETC___d1582 &&
|
|
((NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 ||
|
|
IF_transCache_RDY_resp__571_AND_transCache_res_ETC___d1596) &&
|
|
IF_transCacheReqQ_data_0_583_AND_pendWait_0_du_ETC___d1629 &&
|
|
IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639 ||
|
|
!memReqQ_full) ;
|
|
assign transCache_resp__592_BITS_45_TO_44_593_ULT_2___d1594 =
|
|
transCache$resp[45:44] < 2'd2 ;
|
|
assign upd__h144892 =
|
|
WILL_FIRE_RL_tlbMG_m_doUpdateRep ?
|
|
MUX_tlbMG_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
8'd0 ;
|
|
assign v__h101631 =
|
|
pendValid_0_dummy2_1$Q_OUT &&
|
|
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 ;
|
|
assign v__h143350 =
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_tlbMG_m__ETC___d2017 ?
|
|
addIdx__h147417 :
|
|
v__h144607 ;
|
|
assign v__h144607 =
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 ?
|
|
tlbMG_m_randIdx :
|
|
v__h145083 ;
|
|
assign v__h145083 =
|
|
(IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[0] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[1] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[2] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[3] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[4] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[5] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[6] ||
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[7]) ?
|
|
addIdx__h146150 :
|
|
3'd0 ;
|
|
assign v__h81624 =
|
|
(memReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_enqReq_lat_1_whas__39_THEN_memReqQ__ETC___d648) ?
|
|
v__h81907 :
|
|
memReqQ_enqP ;
|
|
assign v__h81907 = memReqQ_enqP + 1'd1 ;
|
|
assign v__h89194 =
|
|
(respLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_respLdQ_enqReq_lat_1_whas__36_THEN_respLdQ__ETC___d745) ?
|
|
v__h89477 :
|
|
respLdQ_enqP ;
|
|
assign v__h89477 = respLdQ_enqP + 1'd1 ;
|
|
assign val__h41243 =
|
|
(tlbMG_m_lruBit_dummy2_0$Q_OUT &&
|
|
tlbMG_m_lruBit_dummy2_1$Q_OUT) ?
|
|
tlbMG_m_lruBit_rl :
|
|
8'd0 ;
|
|
assign val__h41244 = val__h41243 | x__h41318 ;
|
|
assign vpn__h104314 =
|
|
rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
IF_rqFromCQ_data_0_lat_0_whas__66_THEN_rqFromC_ETC___d487 :
|
|
27'd0 ;
|
|
assign w__h118766 = way__h129824 ;
|
|
assign way__h129824 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d1323 ?
|
|
2'd3 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d1332 ;
|
|
assign way__h36041 =
|
|
NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_80_1_ETC___d250 ?
|
|
2'd3 :
|
|
IF_NOT_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT_8_ETC___d269 ;
|
|
assign x__h133131 = { basePpn__h133127, 12'd0 } ;
|
|
assign x__h136105 =
|
|
{ SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:10],
|
|
12'd0 } ;
|
|
assign x__h41318 = 8'd1 << tlbMG_m_updRepIdx_rl[2:0] ;
|
|
always@(memReqQ_deqP or memReqQ_data_0 or memReqQ_data_1)
|
|
begin
|
|
case (memReqQ_deqP)
|
|
1'd0:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1 =
|
|
memReqQ_data_0[64:1];
|
|
1'd1:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BITS_64_TO__ETC__q1 =
|
|
memReqQ_data_1[64:1];
|
|
endcase
|
|
end
|
|
always@(memReqQ_deqP or memReqQ_data_0 or memReqQ_data_1)
|
|
begin
|
|
case (memReqQ_deqP)
|
|
1'd0:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 =
|
|
memReqQ_data_0[0];
|
|
1'd1:
|
|
CASE_memReqQ_deqP_0_memReqQ_data_0_BIT_0_1_mem_ETC__q2 =
|
|
memReqQ_data_1[0];
|
|
endcase
|
|
end
|
|
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
|
|
begin
|
|
case (respLdQ_deqP)
|
|
1'd0: def__h135309 = respLdQ_data_0[0];
|
|
1'd1: def__h135309 = respLdQ_data_1[0];
|
|
endcase
|
|
end
|
|
always@(idx__h135081 or pendWalkLevel_0 or pendWalkLevel_1)
|
|
begin
|
|
case (idx__h135081)
|
|
1'd0: walkLevel__h136014 = pendWalkLevel_0;
|
|
1'd1: walkLevel__h136014 = pendWalkLevel_1;
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0: vpn__h116705 = pendReq_0[26:0];
|
|
1'd1: vpn__h116705 = pendReq_1[26:0];
|
|
endcase
|
|
end
|
|
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (transCacheReqQ_data_0)
|
|
1'd0:
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3 =
|
|
!pendReq_0[29];
|
|
1'd1:
|
|
CASE_transCacheReqQ_data_0_0_NOT_pendReq_0_BIT_ETC__q3 =
|
|
!pendReq_1[29];
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0:
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1079 =
|
|
!pendReq_0[29];
|
|
1'd1:
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1079 =
|
|
!pendReq_1[29];
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_0 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_0[1:0])
|
|
2'd0, 2'd1:
|
|
IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: IF_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_EQ_0_ETC___d1107 =
|
|
tlbMG_m_entryVec_0[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_0 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn16705_ETC__q4 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn16705_ETC__q4 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn16705_ETC__q4 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_0_BITS_1_TO_0_0_vpn16705_ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_1 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn16705_ETC__q5 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn16705_ETC__q5 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn16705_ETC__q5 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_vpn16705_ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_1 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_1[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: CASE_tlbMG_m_entryVec_1_BITS_1_TO_0_0_NOT_tlbR_ETC__q6 =
|
|
tlbMG_m_entryVec_1[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_2 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_2[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_NOT_tlbR_ETC__q7 =
|
|
tlbMG_m_entryVec_2[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_2 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn16705_ETC__q8 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn16705_ETC__q8 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn16705_ETC__q8 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_2_BITS_1_TO_0_0_vpn16705_ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_3 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_3[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_NOT_tlbR_ETC__q9 =
|
|
tlbMG_m_entryVec_3[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_3 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn16705_ETC__q10 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn16705_ETC__q10 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn16705_ETC__q10 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_3_BITS_1_TO_0_0_vpn16705_ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_4 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_4[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_NOT_tlbR_ETC__q11 =
|
|
tlbMG_m_entryVec_4[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_4 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn16705_ETC__q12 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn16705_ETC__q12 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn16705_ETC__q12 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_4_BITS_1_TO_0_0_vpn16705_ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_5 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_5[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_NOT_tlbR_ETC__q13 =
|
|
tlbMG_m_entryVec_5[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_5 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn16705_ETC__q14 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn16705_ETC__q14 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn16705_ETC__q14 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_5_BITS_1_TO_0_0_vpn16705_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_6 or
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070)
|
|
begin
|
|
case (tlbMG_m_entryVec_6[1:0])
|
|
2'd0, 2'd1:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_NOT_tlbR_ETC__q15 =
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
default: CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_NOT_tlbR_ETC__q15 =
|
|
tlbMG_m_entryVec_6[1:0] != 2'd2 ||
|
|
NOT_tlbReqQ_empty_dummy2_0_read__061_062_OR_NO_ETC___d1070;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_6 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn16705_ETC__q16 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn16705_ETC__q16 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn16705_ETC__q16 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_6_BITS_1_TO_0_0_vpn16705_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_entryVec_7 or vpn__h116705)
|
|
begin
|
|
case (tlbMG_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn16705_ETC__q17 =
|
|
vpn__h116705;
|
|
2'd1:
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn16705_ETC__q17 =
|
|
{ vpn__h116705[26:9], 9'd0 };
|
|
2'd2:
|
|
CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn16705_ETC__q17 =
|
|
{ vpn__h116705[26:18], 18'd0 };
|
|
2'd3: CASE_tlbMG_m_entryVec_7_BITS_1_TO_0_0_vpn16705_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0: x__h121246 = tlb4KB_m_tlbRam_0_bram$DOB[1:0];
|
|
2'd1: x__h121246 = tlb4KB_m_tlbRam_1_bram$DOB[1:0];
|
|
2'd2: x__h121246 = tlb4KB_m_tlbRam_2_bram$DOB[1:0];
|
|
2'd3: x__h121246 = tlb4KB_m_tlbRam_3_bram$DOB[1:0];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_0[5];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_1[5];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_2[5];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_3[5];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_4[5];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_5[5];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_6[5];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_5_418_tlbMG_ETC___d1427 =
|
|
tlbMG_m_entryVec_7[5];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_0[8];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_1[8];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_2[8];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_3[8];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_4[8];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_5[8];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_6[8];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_8_388_tlbMG_ETC___d1397 =
|
|
tlbMG_m_entryVec_7[8];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1504 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[3];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1504 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[3];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1504 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[3];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1504 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[3];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_0[3];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_1[3];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_2[3];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_3[3];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_4[3];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_5[3];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_6[3];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_3_438_tlbMG_ETC___d1447 =
|
|
tlbMG_m_entryVec_7[3];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1492 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[5];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1492 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[5];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1492 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[5];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1492 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[5];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1484 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[7];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1484 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[7];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1484 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[7];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1484 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[7];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_0[7];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_1[7];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_2[7];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_3[7];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_4[7];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_5[7];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_6[7];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_7_398_tlbMG_ETC___d1407 =
|
|
tlbMG_m_entryVec_7[7];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1478 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[8];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1478 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[8];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1478 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[8];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1478 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[8];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1466 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[79:53];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1466 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[79:53];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1466 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[79:53];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1466 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[79:53];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_0[79:53];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_1[79:53];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_2[79:53];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_3[79:53];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_4[79:53];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_5[79:53];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_6[79:53];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_79_TO_53_1_ETC___d1377 =
|
|
tlbMG_m_entryVec_7[79:53];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_0[1:0];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_1[1:0];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_2[1:0];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_3[1:0];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_4[1:0];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_5[1:0];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_6[1:0];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 =
|
|
tlbMG_m_entryVec_7[1:0];
|
|
endcase
|
|
end
|
|
always@(transCacheReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (transCacheReqQ_data_0)
|
|
1'd0:
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610 =
|
|
pendReq_0[26:0];
|
|
1'd1:
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610 =
|
|
pendReq_1[26:0];
|
|
endcase
|
|
end
|
|
always@(transCache$resp or
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610)
|
|
begin
|
|
case (transCache$resp[45:44])
|
|
2'd0:
|
|
x__h133171 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610[8:0];
|
|
2'd1:
|
|
x__h133171 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610[17:9];
|
|
2'd2:
|
|
x__h133171 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1610[26:18];
|
|
2'd3: x__h133171 = 9'b010101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(idx__h135081 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (idx__h135081)
|
|
1'd0:
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1679 =
|
|
!pendReq_0[29];
|
|
1'd1:
|
|
SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NOT_p_ETC___d1679 =
|
|
!pendReq_1[29];
|
|
endcase
|
|
end
|
|
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
|
|
begin
|
|
case (respLdQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684 =
|
|
respLdQ_data_0[64:1];
|
|
1'd1:
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684 =
|
|
respLdQ_data_1[64:1];
|
|
endcase
|
|
end
|
|
always@(walkLevel__h136014 or
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684)
|
|
begin
|
|
case (walkLevel__h136014)
|
|
2'd0:
|
|
masked_ppn__h136484 =
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:10];
|
|
2'd1:
|
|
masked_ppn__h136484 =
|
|
{ SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:19],
|
|
9'd0 };
|
|
2'd2:
|
|
masked_ppn__h136484 =
|
|
{ SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:28],
|
|
18'd0 };
|
|
2'd3: masked_ppn__h136484 = 44'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h135081 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (idx__h135081)
|
|
1'd0:
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707 =
|
|
pendReq_0[26:0];
|
|
1'd1:
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707 =
|
|
pendReq_1[26:0];
|
|
endcase
|
|
end
|
|
always@(newWalkLevel__h136015 or
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707)
|
|
begin
|
|
case (newWalkLevel__h136015)
|
|
2'd0:
|
|
x__h136122 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[8:0];
|
|
2'd1:
|
|
x__h136122 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[17:9];
|
|
2'd2:
|
|
x__h136122 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[26:18];
|
|
2'd3: x__h136122 = 9'b010101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(walkLevel__h136014 or
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707)
|
|
begin
|
|
case (walkLevel__h136014)
|
|
2'd0:
|
|
masked_vpn__h136483 =
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707;
|
|
2'd1:
|
|
masked_vpn__h136483 =
|
|
{ SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[26:9],
|
|
9'd0 };
|
|
2'd2:
|
|
masked_vpn__h136483 =
|
|
{ SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[26:18],
|
|
18'd0 };
|
|
2'd3: masked_vpn__h136483 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(respLdQ_deqP or respLdQ_data_0 or respLdQ_data_1)
|
|
begin
|
|
case (respLdQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_respLdQ_data_0_672_BIT_0_673_719_N_ETC___d1722 =
|
|
!respLdQ_data_0[0];
|
|
1'd1:
|
|
SEL_ARR_NOT_respLdQ_data_0_672_BIT_0_673_719_N_ETC___d1722 =
|
|
!respLdQ_data_1[0];
|
|
endcase
|
|
end
|
|
always@(walkLevel__h136014 or
|
|
SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707)
|
|
begin
|
|
case (walkLevel__h136014)
|
|
2'd1:
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748 =
|
|
{ SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[26:9],
|
|
9'd0 };
|
|
2'd2:
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748 =
|
|
{ SEL_ARR_pendReq_0_071_BITS_26_TO_0_109_pendReq_ETC___d1707[26:18],
|
|
18'd0 };
|
|
default: IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748 =
|
|
27'd0;
|
|
endcase
|
|
end
|
|
always@(walkLevel__h136014 or
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684)
|
|
begin
|
|
case (walkLevel__h136014)
|
|
2'd1:
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824 =
|
|
{ SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:19],
|
|
9'd0 };
|
|
2'd2:
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824 =
|
|
{ SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[53:28],
|
|
18'd0 };
|
|
default: IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824 =
|
|
44'd0;
|
|
endcase
|
|
end
|
|
always@(walkLevel__h136014 or
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824)
|
|
begin
|
|
case (walkLevel__h136014)
|
|
2'd1:
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q18 =
|
|
{ IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824[43:9],
|
|
9'd0 };
|
|
2'd2:
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q18 =
|
|
{ IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1824[43:18],
|
|
18'd0 };
|
|
default: CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q18 =
|
|
44'd0;
|
|
endcase
|
|
end
|
|
always@(walkLevel__h136014 or
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748)
|
|
begin
|
|
case (walkLevel__h136014)
|
|
2'd1:
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q19 =
|
|
{ IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748[26:9],
|
|
9'd0 };
|
|
2'd2:
|
|
CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q19 =
|
|
{ IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1748[26:18],
|
|
18'd0 };
|
|
default: CASE_walkLevel36014_1_IF_SEL_ARR_pendWalkLevel_ETC__q19 =
|
|
27'd0;
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1510 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[2];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1510 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[2];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1510 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[2];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1510 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[2];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_0[2];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_1[2];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_2[2];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_3[2];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_4[2];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_5[2];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_6[2];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_2_448_tlbMG_ETC___d1457 =
|
|
tlbMG_m_entryVec_7[2];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_0[4];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_1[4];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_2[4];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_3[4];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_4[4];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_5[4];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_6[4];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_4_428_tlbMG_ETC___d1437 =
|
|
tlbMG_m_entryVec_7[4];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1498 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[4];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1498 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[4];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1498 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[4];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1498 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[4];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1486 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[6];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1486 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[6];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1486 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[6];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BIT__ETC___d1486 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[6];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_0[6];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_1[6];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_2[6];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_3[6];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_4[6];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_5[6];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_6[6];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BIT_6_408_tlbMG_ETC___d1417 =
|
|
tlbMG_m_entryVec_7[6];
|
|
endcase
|
|
end
|
|
always@(w__h118766 or
|
|
tlb4KB_m_tlbRam_0_bram$DOB or
|
|
tlb4KB_m_tlbRam_1_bram$DOB or
|
|
tlb4KB_m_tlbRam_2_bram$DOB or tlb4KB_m_tlbRam_3_bram$DOB)
|
|
begin
|
|
case (w__h118766)
|
|
2'd0:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1472 =
|
|
tlb4KB_m_tlbRam_0_bram$DOB[52:9];
|
|
2'd1:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1472 =
|
|
tlb4KB_m_tlbRam_1_bram$DOB[52:9];
|
|
2'd2:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1472 =
|
|
tlb4KB_m_tlbRam_2_bram$DOB[52:9];
|
|
2'd3:
|
|
SEL_ARR_tlb4KB_m_tlbRam_0_bram_b_read__14_BITS_ETC___d1472 =
|
|
tlb4KB_m_tlbRam_3_bram$DOB[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h118141 or
|
|
tlbMG_m_entryVec_0 or
|
|
tlbMG_m_entryVec_1 or
|
|
tlbMG_m_entryVec_2 or
|
|
tlbMG_m_entryVec_3 or
|
|
tlbMG_m_entryVec_4 or
|
|
tlbMG_m_entryVec_5 or tlbMG_m_entryVec_6 or tlbMG_m_entryVec_7)
|
|
begin
|
|
case (idx__h118141)
|
|
3'd0:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_0[52:9];
|
|
3'd1:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_1[52:9];
|
|
3'd2:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_2[52:9];
|
|
3'd3:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_3[52:9];
|
|
3'd4:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_4[52:9];
|
|
3'd5:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_5[52:9];
|
|
3'd6:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_6[52:9];
|
|
3'd7:
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_52_TO_9_37_ETC___d1387 =
|
|
tlbMG_m_entryVec_7[52:9];
|
|
endcase
|
|
end
|
|
always@(NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 or
|
|
pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618 or
|
|
pendValid_0_dummy2_0$Q_OUT or
|
|
pendValid_0_dummy2_1$Q_OUT or
|
|
pendValid_0_rl or
|
|
pendValid_1_dummy2_0$Q_OUT or
|
|
pendValid_1_dummy2_1$Q_OUT or pendValid_1_rl)
|
|
begin
|
|
case (NOT_transCacheReqQ_data_0_583_584_OR_NOT_pendW_ETC___d1591 ||
|
|
!pendWalkAddr_0_601_EQ_0_CONCAT_IF_transCache_r_ETC___d1618)
|
|
1'd0:
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1662 =
|
|
!pendValid_0_dummy2_0$Q_OUT || !pendValid_0_dummy2_1$Q_OUT ||
|
|
!pendValid_0_rl;
|
|
1'd1:
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1662 =
|
|
!pendValid_1_dummy2_0$Q_OUT || !pendValid_1_dummy2_1$Q_OUT ||
|
|
!pendValid_1_rl;
|
|
endcase
|
|
end
|
|
always@(i__h135439 or
|
|
pendValid_0_dummy2_0$Q_OUT or
|
|
pendValid_0_dummy2_1$Q_OUT or
|
|
pendValid_0_rl or
|
|
pendValid_1_dummy2_0$Q_OUT or
|
|
pendValid_1_dummy2_1$Q_OUT or pendValid_1_rl)
|
|
begin
|
|
case (i__h135439)
|
|
1'd0:
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1790 =
|
|
!pendValid_0_dummy2_0$Q_OUT || !pendValid_0_dummy2_1$Q_OUT ||
|
|
!pendValid_0_rl;
|
|
1'd1:
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1790 =
|
|
!pendValid_1_dummy2_0$Q_OUT || !pendValid_1_dummy2_1$Q_OUT ||
|
|
!pendValid_1_rl;
|
|
endcase
|
|
end
|
|
always@(transCacheReqQ_data_0 or
|
|
pendWait_0_dummy2_0$Q_OUT or
|
|
pendWait_0_dummy2_1$Q_OUT or
|
|
pendWait_0_rl or
|
|
pendWait_1_dummy2_0$Q_OUT or
|
|
pendWait_1_dummy2_1$Q_OUT or pendWait_1_rl)
|
|
begin
|
|
case (transCacheReqQ_data_0)
|
|
1'd0:
|
|
SEL_ARR_pendWait_0_dummy2_0_read__585_AND_pend_ETC___d1651 =
|
|
pendWait_0_dummy2_0$Q_OUT && pendWait_0_dummy2_1$Q_OUT &&
|
|
pendWait_0_rl[2:1] != 2'd0;
|
|
1'd1:
|
|
SEL_ARR_pendWait_0_dummy2_0_read__585_AND_pend_ETC___d1651 =
|
|
pendWait_1_dummy2_0$Q_OUT && pendWait_1_dummy2_1$Q_OUT &&
|
|
pendWait_1_rl[2:1] != 2'd0;
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0:
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q20 =
|
|
pendReq_0[28:27];
|
|
1'd1:
|
|
CASE_tlbReqQ_data_0_0_pendReq_0_BITS_28_TO_27__ETC__q20 =
|
|
pendReq_1[28:27];
|
|
endcase
|
|
end
|
|
always@(idx__h135081 or pendReq_0 or pendReq_1)
|
|
begin
|
|
case (idx__h135081)
|
|
1'd0:
|
|
CASE_idx35081_0_pendReq_0_BITS_28_TO_27_1_pend_ETC__q21 =
|
|
pendReq_0[28:27];
|
|
1'd1:
|
|
CASE_idx35081_0_pendReq_0_BITS_28_TO_27_1_pend_ETC__q21 =
|
|
pendReq_1[28:27];
|
|
endcase
|
|
end
|
|
always@(tlbMG_m_randIdx or
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976)
|
|
begin
|
|
case (tlbMG_m_randIdx)
|
|
3'd0:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[0];
|
|
3'd1:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[1];
|
|
3'd2:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[2];
|
|
3'd3:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[3];
|
|
3'd4:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[4];
|
|
3'd5:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[5];
|
|
3'd6:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[6];
|
|
3'd7:
|
|
SEL_ARR_IF_tlbMG_m_lruBit_dummy2_1_read__56_TH_ETC___d1986 =
|
|
IF_tlbMG_m_lruBit_dummy2_1_read__56_THEN_INV_I_ETC___d1976[7];
|
|
endcase
|
|
end
|
|
always@(v__h101631 or
|
|
pendValid_0_dummy2_1$Q_OUT or
|
|
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573 or
|
|
pendValid_1_dummy2_1$Q_OUT or
|
|
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580)
|
|
begin
|
|
case (v__h101631)
|
|
1'd0:
|
|
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046 =
|
|
pendValid_0_dummy2_1$Q_OUT &&
|
|
IF_pendValid_0_lat_0_whas__70_THEN_pendValid_0_ETC___d573;
|
|
1'd1:
|
|
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046 =
|
|
pendValid_1_dummy2_1$Q_OUT &&
|
|
IF_pendValid_1_lat_0_whas__77_THEN_pendValid_1_ETC___d580;
|
|
endcase
|
|
end
|
|
always@(tlbReqQ_data_0 or
|
|
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051 or
|
|
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056)
|
|
begin
|
|
case (tlbReqQ_data_0)
|
|
1'd0:
|
|
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q22 =
|
|
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051;
|
|
1'd1:
|
|
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q22 =
|
|
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056;
|
|
endcase
|
|
end
|
|
always@(v__h101631 or
|
|
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051 or
|
|
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056)
|
|
begin
|
|
case (v__h101631)
|
|
1'd0:
|
|
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q23 =
|
|
pendWait_0_dummy2_1_read__047_AND_IF_pendWait__ETC___d1051;
|
|
1'd1:
|
|
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q23 =
|
|
pendWait_1_dummy2_1_read__052_AND_IF_pendWait__ETC___d1056;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
dFlushReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushDoneQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushDoneQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
iFlushReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
memReqQ_data_1 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
memReqQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
memReqQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
|
|
memReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendWait_0_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
pendWait_1_rl <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respForOtherReq <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
respLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
respLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
respLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
respLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
|
|
respLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY 30'h2AAAAAAA;
|
|
rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsToCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY 84'hAAAAAAAAAAAAAAAAAAAAA;
|
|
rsToCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rsToCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_flushIdx <= `BSV_ASSIGNMENT_DELAY 8'd0;
|
|
tlb4KB_m_pendReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
82'h0AAAAAAAAAAAAAAAAAAAA;
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_repRam_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 8'd0;
|
|
tlbMG_m_randIdx <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
tlbMG_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
tlbMG_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbMG_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlbReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
tlbReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
transCacheReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
transCacheReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
transCacheReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
vm_info_D <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
vm_info_I <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
waitFlushDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (dFlushReq$EN) dFlushReq <= `BSV_ASSIGNMENT_DELAY dFlushReq$D_IN;
|
|
if (flushDoneQ_clearReq_rl$EN)
|
|
flushDoneQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushDoneQ_clearReq_rl$D_IN;
|
|
if (flushDoneQ_deqReq_rl$EN)
|
|
flushDoneQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushDoneQ_deqReq_rl$D_IN;
|
|
if (flushDoneQ_empty$EN)
|
|
flushDoneQ_empty <= `BSV_ASSIGNMENT_DELAY flushDoneQ_empty$D_IN;
|
|
if (flushDoneQ_enqReq_rl$EN)
|
|
flushDoneQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushDoneQ_enqReq_rl$D_IN;
|
|
if (flushDoneQ_full$EN)
|
|
flushDoneQ_full <= `BSV_ASSIGNMENT_DELAY flushDoneQ_full$D_IN;
|
|
if (iFlushReq$EN) iFlushReq <= `BSV_ASSIGNMENT_DELAY iFlushReq$D_IN;
|
|
if (memReqQ_clearReq_rl$EN)
|
|
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
memReqQ_clearReq_rl$D_IN;
|
|
if (memReqQ_data_0$EN)
|
|
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_0$D_IN;
|
|
if (memReqQ_data_1$EN)
|
|
memReqQ_data_1 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_1$D_IN;
|
|
if (memReqQ_deqP$EN)
|
|
memReqQ_deqP <= `BSV_ASSIGNMENT_DELAY memReqQ_deqP$D_IN;
|
|
if (memReqQ_deqReq_rl$EN)
|
|
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_deqReq_rl$D_IN;
|
|
if (memReqQ_empty$EN)
|
|
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY memReqQ_empty$D_IN;
|
|
if (memReqQ_enqP$EN)
|
|
memReqQ_enqP <= `BSV_ASSIGNMENT_DELAY memReqQ_enqP$D_IN;
|
|
if (memReqQ_enqReq_rl$EN)
|
|
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_enqReq_rl$D_IN;
|
|
if (memReqQ_full$EN)
|
|
memReqQ_full <= `BSV_ASSIGNMENT_DELAY memReqQ_full$D_IN;
|
|
if (pendValid_0_rl$EN)
|
|
pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY pendValid_0_rl$D_IN;
|
|
if (pendValid_1_rl$EN)
|
|
pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY pendValid_1_rl$D_IN;
|
|
if (pendWait_0_rl$EN)
|
|
pendWait_0_rl <= `BSV_ASSIGNMENT_DELAY pendWait_0_rl$D_IN;
|
|
if (pendWait_1_rl$EN)
|
|
pendWait_1_rl <= `BSV_ASSIGNMENT_DELAY pendWait_1_rl$D_IN;
|
|
if (perfReqQ_clearReq_rl$EN)
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
perfReqQ_clearReq_rl$D_IN;
|
|
if (perfReqQ_data_0$EN)
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
|
|
if (perfReqQ_deqReq_rl$EN)
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
|
|
if (perfReqQ_empty$EN)
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
|
|
if (perfReqQ_enqReq_rl$EN)
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
|
|
if (perfReqQ_full$EN)
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
|
|
if (respForOtherReq$EN)
|
|
respForOtherReq <= `BSV_ASSIGNMENT_DELAY respForOtherReq$D_IN;
|
|
if (respLdQ_clearReq_rl$EN)
|
|
respLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
respLdQ_clearReq_rl$D_IN;
|
|
if (respLdQ_data_0$EN)
|
|
respLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY respLdQ_data_0$D_IN;
|
|
if (respLdQ_data_1$EN)
|
|
respLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY respLdQ_data_1$D_IN;
|
|
if (respLdQ_deqP$EN)
|
|
respLdQ_deqP <= `BSV_ASSIGNMENT_DELAY respLdQ_deqP$D_IN;
|
|
if (respLdQ_deqReq_rl$EN)
|
|
respLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY respLdQ_deqReq_rl$D_IN;
|
|
if (respLdQ_empty$EN)
|
|
respLdQ_empty <= `BSV_ASSIGNMENT_DELAY respLdQ_empty$D_IN;
|
|
if (respLdQ_enqP$EN)
|
|
respLdQ_enqP <= `BSV_ASSIGNMENT_DELAY respLdQ_enqP$D_IN;
|
|
if (respLdQ_enqReq_rl$EN)
|
|
respLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY respLdQ_enqReq_rl$D_IN;
|
|
if (respLdQ_full$EN)
|
|
respLdQ_full <= `BSV_ASSIGNMENT_DELAY respLdQ_full$D_IN;
|
|
if (rqFromCQ_data_0_rl$EN)
|
|
rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_data_0_rl$D_IN;
|
|
if (rqFromCQ_empty_rl$EN)
|
|
rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_empty_rl$D_IN;
|
|
if (rqFromCQ_full_rl$EN)
|
|
rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY rqFromCQ_full_rl$D_IN;
|
|
if (rsToCQ_data_0_rl$EN)
|
|
rsToCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_data_0_rl$D_IN;
|
|
if (rsToCQ_empty_rl$EN)
|
|
rsToCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_empty_rl$D_IN;
|
|
if (rsToCQ_full_rl$EN)
|
|
rsToCQ_full_rl <= `BSV_ASSIGNMENT_DELAY rsToCQ_full_rl$D_IN;
|
|
if (tlb4KB_m_flushIdx$EN)
|
|
tlb4KB_m_flushIdx <= `BSV_ASSIGNMENT_DELAY tlb4KB_m_flushIdx$D_IN;
|
|
if (tlb4KB_m_pendReq_rl$EN)
|
|
tlb4KB_m_pendReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_pendReq_rl$D_IN;
|
|
if (tlb4KB_m_repRam_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_repRam_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_repRam_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_repRam_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_state$EN)
|
|
tlb4KB_m_state <= `BSV_ASSIGNMENT_DELAY tlb4KB_m_state$D_IN;
|
|
if (tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_0_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_1_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_2_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$EN)
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl$D_IN;
|
|
if (tlb4KB_m_tlbRam_3_rdReqQ_full_rl$EN)
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl$D_IN;
|
|
if (tlbMG_m_lruBit_rl$EN)
|
|
tlbMG_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY tlbMG_m_lruBit_rl$D_IN;
|
|
if (tlbMG_m_randIdx$EN)
|
|
tlbMG_m_randIdx <= `BSV_ASSIGNMENT_DELAY tlbMG_m_randIdx$D_IN;
|
|
if (tlbMG_m_updRepIdx_rl$EN)
|
|
tlbMG_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
tlbMG_m_updRepIdx_rl$D_IN;
|
|
if (tlbMG_m_validVec_0$EN)
|
|
tlbMG_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_0$D_IN;
|
|
if (tlbMG_m_validVec_1$EN)
|
|
tlbMG_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_1$D_IN;
|
|
if (tlbMG_m_validVec_2$EN)
|
|
tlbMG_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_2$D_IN;
|
|
if (tlbMG_m_validVec_3$EN)
|
|
tlbMG_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_3$D_IN;
|
|
if (tlbMG_m_validVec_4$EN)
|
|
tlbMG_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_4$D_IN;
|
|
if (tlbMG_m_validVec_5$EN)
|
|
tlbMG_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_5$D_IN;
|
|
if (tlbMG_m_validVec_6$EN)
|
|
tlbMG_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_6$D_IN;
|
|
if (tlbMG_m_validVec_7$EN)
|
|
tlbMG_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_validVec_7$D_IN;
|
|
if (tlbReqQ_data_0$EN)
|
|
tlbReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY tlbReqQ_data_0$D_IN;
|
|
if (tlbReqQ_empty_rl$EN)
|
|
tlbReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY tlbReqQ_empty_rl$D_IN;
|
|
if (tlbReqQ_full_rl$EN)
|
|
tlbReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY tlbReqQ_full_rl$D_IN;
|
|
if (transCacheReqQ_data_0$EN)
|
|
transCacheReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
transCacheReqQ_data_0$D_IN;
|
|
if (transCacheReqQ_empty_rl$EN)
|
|
transCacheReqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
transCacheReqQ_empty_rl$D_IN;
|
|
if (transCacheReqQ_full_rl$EN)
|
|
transCacheReqQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
transCacheReqQ_full_rl$D_IN;
|
|
if (vm_info_D$EN) vm_info_D <= `BSV_ASSIGNMENT_DELAY vm_info_D$D_IN;
|
|
if (vm_info_I$EN) vm_info_I <= `BSV_ASSIGNMENT_DELAY vm_info_I$D_IN;
|
|
if (waitFlushDone$EN)
|
|
waitFlushDone <= `BSV_ASSIGNMENT_DELAY waitFlushDone$D_IN;
|
|
end
|
|
if (pendReq_0$EN) pendReq_0 <= `BSV_ASSIGNMENT_DELAY pendReq_0$D_IN;
|
|
if (pendReq_1$EN) pendReq_1 <= `BSV_ASSIGNMENT_DELAY pendReq_1$D_IN;
|
|
if (pendWalkAddr_0$EN)
|
|
pendWalkAddr_0 <= `BSV_ASSIGNMENT_DELAY pendWalkAddr_0$D_IN;
|
|
if (pendWalkAddr_1$EN)
|
|
pendWalkAddr_1 <= `BSV_ASSIGNMENT_DELAY pendWalkAddr_1$D_IN;
|
|
if (pendWalkLevel_0$EN)
|
|
pendWalkLevel_0 <= `BSV_ASSIGNMENT_DELAY pendWalkLevel_0$D_IN;
|
|
if (pendWalkLevel_1$EN)
|
|
pendWalkLevel_1 <= `BSV_ASSIGNMENT_DELAY pendWalkLevel_1$D_IN;
|
|
if (tlbMG_m_entryVec_0$EN)
|
|
tlbMG_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_0$D_IN;
|
|
if (tlbMG_m_entryVec_1$EN)
|
|
tlbMG_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_1$D_IN;
|
|
if (tlbMG_m_entryVec_2$EN)
|
|
tlbMG_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_2$D_IN;
|
|
if (tlbMG_m_entryVec_3$EN)
|
|
tlbMG_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_3$D_IN;
|
|
if (tlbMG_m_entryVec_4$EN)
|
|
tlbMG_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_4$D_IN;
|
|
if (tlbMG_m_entryVec_5$EN)
|
|
tlbMG_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_5$D_IN;
|
|
if (tlbMG_m_entryVec_6$EN)
|
|
tlbMG_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_6$D_IN;
|
|
if (tlbMG_m_entryVec_7$EN)
|
|
tlbMG_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY tlbMG_m_entryVec_7$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
dFlushReq = 1'h0;
|
|
flushDoneQ_clearReq_rl = 1'h0;
|
|
flushDoneQ_deqReq_rl = 1'h0;
|
|
flushDoneQ_empty = 1'h0;
|
|
flushDoneQ_enqReq_rl = 1'h0;
|
|
flushDoneQ_full = 1'h0;
|
|
iFlushReq = 1'h0;
|
|
memReqQ_clearReq_rl = 1'h0;
|
|
memReqQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
|
|
memReqQ_data_1 = 65'h0AAAAAAAAAAAAAAAA;
|
|
memReqQ_deqP = 1'h0;
|
|
memReqQ_deqReq_rl = 1'h0;
|
|
memReqQ_empty = 1'h0;
|
|
memReqQ_enqP = 1'h0;
|
|
memReqQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
memReqQ_full = 1'h0;
|
|
pendReq_0 = 30'h2AAAAAAA;
|
|
pendReq_1 = 30'h2AAAAAAA;
|
|
pendValid_0_rl = 1'h0;
|
|
pendValid_1_rl = 1'h0;
|
|
pendWait_0_rl = 3'h2;
|
|
pendWait_1_rl = 3'h2;
|
|
pendWalkAddr_0 = 64'hAAAAAAAAAAAAAAAA;
|
|
pendWalkAddr_1 = 64'hAAAAAAAAAAAAAAAA;
|
|
pendWalkLevel_0 = 2'h2;
|
|
pendWalkLevel_1 = 2'h2;
|
|
perfReqQ_clearReq_rl = 1'h0;
|
|
perfReqQ_data_0 = 4'hA;
|
|
perfReqQ_deqReq_rl = 1'h0;
|
|
perfReqQ_empty = 1'h0;
|
|
perfReqQ_enqReq_rl = 5'h0A;
|
|
perfReqQ_full = 1'h0;
|
|
respForOtherReq = 2'h2;
|
|
respLdQ_clearReq_rl = 1'h0;
|
|
respLdQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
|
|
respLdQ_data_1 = 65'h0AAAAAAAAAAAAAAAA;
|
|
respLdQ_deqP = 1'h0;
|
|
respLdQ_deqReq_rl = 1'h0;
|
|
respLdQ_empty = 1'h0;
|
|
respLdQ_enqP = 1'h0;
|
|
respLdQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
respLdQ_full = 1'h0;
|
|
rqFromCQ_data_0_rl = 30'h2AAAAAAA;
|
|
rqFromCQ_empty_rl = 1'h0;
|
|
rqFromCQ_full_rl = 1'h0;
|
|
rsToCQ_data_0_rl = 84'hAAAAAAAAAAAAAAAAAAAAA;
|
|
rsToCQ_empty_rl = 1'h0;
|
|
rsToCQ_full_rl = 1'h0;
|
|
tlb4KB_m_flushIdx = 8'hAA;
|
|
tlb4KB_m_pendReq_rl = 82'h2AAAAAAAAAAAAAAAAAAAA;
|
|
tlb4KB_m_repRam_rdReqQ_empty_rl = 1'h0;
|
|
tlb4KB_m_repRam_rdReqQ_full_rl = 1'h0;
|
|
tlb4KB_m_state = 1'h0;
|
|
tlb4KB_m_tlbRam_0_rdReqQ_empty_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_0_rdReqQ_full_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_1_rdReqQ_empty_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_1_rdReqQ_full_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_2_rdReqQ_empty_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_2_rdReqQ_full_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_3_rdReqQ_empty_rl = 1'h0;
|
|
tlb4KB_m_tlbRam_3_rdReqQ_full_rl = 1'h0;
|
|
tlbMG_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlbMG_m_lruBit_rl = 8'hAA;
|
|
tlbMG_m_randIdx = 3'h2;
|
|
tlbMG_m_updRepIdx_rl = 4'hA;
|
|
tlbMG_m_validVec_0 = 1'h0;
|
|
tlbMG_m_validVec_1 = 1'h0;
|
|
tlbMG_m_validVec_2 = 1'h0;
|
|
tlbMG_m_validVec_3 = 1'h0;
|
|
tlbMG_m_validVec_4 = 1'h0;
|
|
tlbMG_m_validVec_5 = 1'h0;
|
|
tlbMG_m_validVec_6 = 1'h0;
|
|
tlbMG_m_validVec_7 = 1'h0;
|
|
tlbReqQ_data_0 = 1'h0;
|
|
tlbReqQ_empty_rl = 1'h0;
|
|
tlbReqQ_full_rl = 1'h0;
|
|
transCacheReqQ_data_0 = 1'h0;
|
|
transCacheReqQ_empty_rl = 1'h0;
|
|
transCacheReqQ_full_rl = 1'h0;
|
|
vm_info_D = 49'h0AAAAAAAAAAAA;
|
|
vm_info_I = 49'h0AAAAAAAAAAAA;
|
|
waitFlushDone = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doStartFlush &&
|
|
NOT_rqFromCQ_empty_dummy2_1_read__19_20_OR_NOT_ETC___d927)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doStartFlush &&
|
|
pendValid_0_dummy2_0_read__28_AND_pendValid_0__ETC___d936)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTranslationCacheResp &&
|
|
SEL_ARR_pendWait_0_dummy2_0_read__585_AND_pend_ETC___d1651)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTranslationCacheResp &&
|
|
IF_NOT_transCacheReqQ_data_0_583_584_OR_NOT_pe_ETC___d1639 &&
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1662)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbResp && iFlushReq && dFlushReq)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbResp &&
|
|
CASE_tlbReqQ_data_0_0_pendWait_0_dummy2_1_read_ETC__q22)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1086)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
IF_NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tl_ETC___d1302 &&
|
|
(SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 ==
|
|
2'd0 ||
|
|
SEL_ARR_tlbMG_m_entryVec_0_099_BITS_1_TO_0_100_ETC___d1462 ==
|
|
2'd3))
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbResp &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1368 &&
|
|
NOT_tlbMG_m_validVec_0_097_098_OR_NOT_IF_tlbMG_ETC___d1546)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doPageWalk && iFlushReq && dFlushReq)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doPageWalk &&
|
|
IF_NOT_pendWait_0_dummy2_0_read__585_586_OR_NO_ETC___d1787 &&
|
|
SEL_ARR_NOT_pendValid_0_dummy2_0_read__28_655__ETC___d1790)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813 &&
|
|
NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1878)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[0] &&
|
|
(SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[3] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[1] ||
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d1684[2]) &&
|
|
IF_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel_1_ETC___d1813 &&
|
|
NOT_SEL_ARR_pendWalkLevel_0_694_pendWalkLevel__ETC___d1891)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doPageWalk &&
|
|
IF_SEL_ARR_NOT_pendReq_0_071_BIT_29_072_073_NO_ETC___d1811 &&
|
|
SEL_ARR_respLdQ_data_0_672_BITS_64_TO_1_681_re_ETC___d2009)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbReq &&
|
|
SEL_ARR_pendValid_0_dummy2_1_read__29_AND_IF_p_ETC___d1046)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_doTlbReq &&
|
|
CASE_v01631_0_pendWait_0_dummy2_1_read__047_AN_ETC__q23)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkL2Tlb
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|
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