356 lines
9.6 KiB
Verilog
356 lines
9.6 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_req O 1
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// resp O 46 const
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// RDY_resp O 1
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// RDY_deqResp O 1
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// RDY_addEntry O 1 const
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// RDY_flush O 1 const
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// flush_done O 1 const
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// RDY_flush_done O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// req_vpn I 27 unused
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// addEntry_vpn I 27 unused
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// addEntry_level I 2 unused
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// addEntry_ppn I 44 unused
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// EN_req I 1
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// EN_deqResp I 1
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// EN_addEntry I 1 unused
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// EN_flush I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// EN_deqResp -> RDY_req
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkNullTransCache(CLK,
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RST_N,
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req_vpn,
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EN_req,
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RDY_req,
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resp,
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RDY_resp,
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EN_deqResp,
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RDY_deqResp,
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addEntry_vpn,
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addEntry_level,
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addEntry_ppn,
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EN_addEntry,
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RDY_addEntry,
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EN_flush,
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RDY_flush,
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flush_done,
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RDY_flush_done);
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input CLK;
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input RST_N;
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// action method req
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input [26 : 0] req_vpn;
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input EN_req;
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output RDY_req;
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// value method resp
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output [45 : 0] resp;
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output RDY_resp;
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// action method deqResp
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input EN_deqResp;
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output RDY_deqResp;
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// action method addEntry
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input [26 : 0] addEntry_vpn;
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input [1 : 0] addEntry_level;
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input [43 : 0] addEntry_ppn;
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input EN_addEntry;
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output RDY_addEntry;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// signals for module outputs
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wire [45 : 0] resp;
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wire RDY_addEntry,
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RDY_deqResp,
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RDY_flush,
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RDY_flush_done,
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RDY_req,
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RDY_resp,
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flush_done;
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// register reqQ_empty_rl
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reg reqQ_empty_rl;
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wire reqQ_empty_rl$D_IN, reqQ_empty_rl$EN;
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// register reqQ_full_rl
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reg reqQ_full_rl;
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wire reqQ_full_rl$D_IN, reqQ_full_rl$EN;
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// ports of submodule reqQ_deqP_dummy2_0
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wire reqQ_deqP_dummy2_0$D_IN, reqQ_deqP_dummy2_0$EN;
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// ports of submodule reqQ_deqP_dummy2_1
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wire reqQ_deqP_dummy2_1$D_IN, reqQ_deqP_dummy2_1$EN;
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// ports of submodule reqQ_empty_dummy2_0
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wire reqQ_empty_dummy2_0$D_IN,
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reqQ_empty_dummy2_0$EN,
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reqQ_empty_dummy2_0$Q_OUT;
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// ports of submodule reqQ_empty_dummy2_1
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wire reqQ_empty_dummy2_1$D_IN,
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reqQ_empty_dummy2_1$EN,
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reqQ_empty_dummy2_1$Q_OUT;
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// ports of submodule reqQ_empty_dummy2_2
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wire reqQ_empty_dummy2_2$D_IN,
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reqQ_empty_dummy2_2$EN,
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reqQ_empty_dummy2_2$Q_OUT;
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// ports of submodule reqQ_enqP_dummy2_0
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wire reqQ_enqP_dummy2_0$D_IN, reqQ_enqP_dummy2_0$EN;
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// ports of submodule reqQ_enqP_dummy2_1
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wire reqQ_enqP_dummy2_1$D_IN, reqQ_enqP_dummy2_1$EN;
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// ports of submodule reqQ_full_dummy2_0
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wire reqQ_full_dummy2_0$D_IN, reqQ_full_dummy2_0$EN;
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// ports of submodule reqQ_full_dummy2_1
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wire reqQ_full_dummy2_1$D_IN,
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reqQ_full_dummy2_1$EN,
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reqQ_full_dummy2_1$Q_OUT;
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// ports of submodule reqQ_full_dummy2_2
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wire reqQ_full_dummy2_2$D_IN,
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reqQ_full_dummy2_2$EN,
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reqQ_full_dummy2_2$Q_OUT;
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// rule scheduling signals
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wire CAN_FIRE_RL_reqQ_empty_canon,
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CAN_FIRE_RL_reqQ_full_canon,
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CAN_FIRE_addEntry,
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CAN_FIRE_deqResp,
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CAN_FIRE_flush,
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CAN_FIRE_req,
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WILL_FIRE_RL_reqQ_empty_canon,
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WILL_FIRE_RL_reqQ_full_canon,
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WILL_FIRE_addEntry,
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WILL_FIRE_deqResp,
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WILL_FIRE_flush,
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WILL_FIRE_req;
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// action method req
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assign RDY_req =
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!reqQ_full_dummy2_1$Q_OUT || !reqQ_full_dummy2_2$Q_OUT ||
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EN_deqResp ||
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!reqQ_full_rl ;
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assign CAN_FIRE_req =
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!reqQ_full_dummy2_1$Q_OUT || !reqQ_full_dummy2_2$Q_OUT ||
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EN_deqResp ||
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!reqQ_full_rl ;
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assign WILL_FIRE_req = EN_req ;
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// value method resp
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assign resp = 46'h2AAAAAAAAAAA ;
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assign RDY_resp =
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!reqQ_empty_dummy2_0$Q_OUT || !reqQ_empty_dummy2_1$Q_OUT ||
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!reqQ_empty_dummy2_2$Q_OUT ||
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!reqQ_empty_rl ;
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// action method deqResp
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assign RDY_deqResp = RDY_resp ;
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assign CAN_FIRE_deqResp = RDY_resp ;
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assign WILL_FIRE_deqResp = EN_deqResp ;
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// action method addEntry
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assign RDY_addEntry = 1'd1 ;
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assign CAN_FIRE_addEntry = 1'd1 ;
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assign WILL_FIRE_addEntry = EN_addEntry ;
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// action method flush
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assign RDY_flush = 1'd1 ;
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assign CAN_FIRE_flush = 1'd1 ;
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assign WILL_FIRE_flush = EN_flush ;
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// value method flush_done
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assign flush_done = 1'd1 ;
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assign RDY_flush_done = 1'd1 ;
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// submodule reqQ_deqP_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_deqP_dummy2_0(.CLK(CLK),
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.D_IN(reqQ_deqP_dummy2_0$D_IN),
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.EN(reqQ_deqP_dummy2_0$EN),
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.Q_OUT());
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// submodule reqQ_deqP_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_deqP_dummy2_1(.CLK(CLK),
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.D_IN(reqQ_deqP_dummy2_1$D_IN),
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.EN(reqQ_deqP_dummy2_1$EN),
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.Q_OUT());
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// submodule reqQ_empty_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_empty_dummy2_0(.CLK(CLK),
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.D_IN(reqQ_empty_dummy2_0$D_IN),
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.EN(reqQ_empty_dummy2_0$EN),
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.Q_OUT(reqQ_empty_dummy2_0$Q_OUT));
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// submodule reqQ_empty_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_empty_dummy2_1(.CLK(CLK),
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.D_IN(reqQ_empty_dummy2_1$D_IN),
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.EN(reqQ_empty_dummy2_1$EN),
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.Q_OUT(reqQ_empty_dummy2_1$Q_OUT));
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// submodule reqQ_empty_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_empty_dummy2_2(.CLK(CLK),
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.D_IN(reqQ_empty_dummy2_2$D_IN),
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.EN(reqQ_empty_dummy2_2$EN),
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.Q_OUT(reqQ_empty_dummy2_2$Q_OUT));
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// submodule reqQ_enqP_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_enqP_dummy2_0(.CLK(CLK),
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.D_IN(reqQ_enqP_dummy2_0$D_IN),
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.EN(reqQ_enqP_dummy2_0$EN),
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.Q_OUT());
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// submodule reqQ_enqP_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_enqP_dummy2_1(.CLK(CLK),
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.D_IN(reqQ_enqP_dummy2_1$D_IN),
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.EN(reqQ_enqP_dummy2_1$EN),
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.Q_OUT());
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// submodule reqQ_full_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_full_dummy2_0(.CLK(CLK),
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.D_IN(reqQ_full_dummy2_0$D_IN),
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.EN(reqQ_full_dummy2_0$EN),
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.Q_OUT());
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// submodule reqQ_full_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_full_dummy2_1(.CLK(CLK),
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.D_IN(reqQ_full_dummy2_1$D_IN),
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.EN(reqQ_full_dummy2_1$EN),
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.Q_OUT(reqQ_full_dummy2_1$Q_OUT));
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// submodule reqQ_full_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) reqQ_full_dummy2_2(.CLK(CLK),
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.D_IN(reqQ_full_dummy2_2$D_IN),
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.EN(reqQ_full_dummy2_2$EN),
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.Q_OUT(reqQ_full_dummy2_2$Q_OUT));
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// rule RL_reqQ_empty_canon
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assign CAN_FIRE_RL_reqQ_empty_canon = 1'd1 ;
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assign WILL_FIRE_RL_reqQ_empty_canon = 1'd1 ;
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// rule RL_reqQ_full_canon
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assign CAN_FIRE_RL_reqQ_full_canon = 1'd1 ;
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assign WILL_FIRE_RL_reqQ_full_canon = 1'd1 ;
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// register reqQ_empty_rl
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assign reqQ_empty_rl$D_IN = !EN_req && (EN_deqResp || reqQ_empty_rl) ;
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assign reqQ_empty_rl$EN = 1'd1 ;
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// register reqQ_full_rl
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assign reqQ_full_rl$D_IN = EN_req || !EN_deqResp && reqQ_full_rl ;
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assign reqQ_full_rl$EN = 1'd1 ;
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// submodule reqQ_deqP_dummy2_0
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assign reqQ_deqP_dummy2_0$D_IN = 1'd1 ;
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assign reqQ_deqP_dummy2_0$EN = EN_deqResp ;
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// submodule reqQ_deqP_dummy2_1
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assign reqQ_deqP_dummy2_1$D_IN = 1'b0 ;
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assign reqQ_deqP_dummy2_1$EN = 1'b0 ;
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// submodule reqQ_empty_dummy2_0
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assign reqQ_empty_dummy2_0$D_IN = 1'd1 ;
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assign reqQ_empty_dummy2_0$EN = EN_deqResp ;
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// submodule reqQ_empty_dummy2_1
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assign reqQ_empty_dummy2_1$D_IN = 1'd1 ;
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assign reqQ_empty_dummy2_1$EN = EN_req ;
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// submodule reqQ_empty_dummy2_2
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assign reqQ_empty_dummy2_2$D_IN = 1'b0 ;
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assign reqQ_empty_dummy2_2$EN = 1'b0 ;
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// submodule reqQ_enqP_dummy2_0
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assign reqQ_enqP_dummy2_0$D_IN = 1'd1 ;
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assign reqQ_enqP_dummy2_0$EN = EN_req ;
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// submodule reqQ_enqP_dummy2_1
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assign reqQ_enqP_dummy2_1$D_IN = 1'b0 ;
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assign reqQ_enqP_dummy2_1$EN = 1'b0 ;
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// submodule reqQ_full_dummy2_0
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assign reqQ_full_dummy2_0$D_IN = 1'd1 ;
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assign reqQ_full_dummy2_0$EN = EN_deqResp ;
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// submodule reqQ_full_dummy2_1
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assign reqQ_full_dummy2_1$D_IN = 1'd1 ;
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assign reqQ_full_dummy2_1$EN = EN_req ;
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// submodule reqQ_full_dummy2_2
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assign reqQ_full_dummy2_2$D_IN = 1'b0 ;
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assign reqQ_full_dummy2_2$EN = 1'b0 ;
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// handling of inlined registers
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always@(posedge CLK)
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begin
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if (RST_N == `BSV_RESET_VALUE)
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begin
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reqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
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reqQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
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end
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else
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begin
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if (reqQ_empty_rl$EN)
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reqQ_empty_rl <= `BSV_ASSIGNMENT_DELAY reqQ_empty_rl$D_IN;
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if (reqQ_full_rl$EN)
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reqQ_full_rl <= `BSV_ASSIGNMENT_DELAY reqQ_full_rl$D_IN;
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end
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end
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// synopsys translate_off
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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initial
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begin
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reqQ_empty_rl = 1'h0;
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reqQ_full_rl = 1'h0;
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end
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`endif // BSV_NO_INITIAL_BLOCKS
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// synopsys translate_on
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endmodule // mkNullTransCache
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