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Toooba/src_SSITH_P3_sim/Verilog_RTL/module_execFpuSimple.v
Niraj Sharma d8a3c3d754 Generated src_SSITH_P3_sim RTL
2020-02-06 17:14:59 +05:30

10890 lines
454 KiB
Verilog
Raw Blame History

//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// execFpuSimple O 69
// execFpuSimple_fpu_inst I 9
// execFpuSimple_rVal1 I 64
// execFpuSimple_rVal2 I 64
//
// Combinational paths from inputs to outputs:
// (execFpuSimple_fpu_inst,
// execFpuSimple_rVal1,
// execFpuSimple_rVal2) -> execFpuSimple
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_execFpuSimple(execFpuSimple_fpu_inst,
execFpuSimple_rVal1,
execFpuSimple_rVal2,
execFpuSimple);
// value method execFpuSimple
input [8 : 0] execFpuSimple_fpu_inst;
input [63 : 0] execFpuSimple_rVal1;
input [63 : 0] execFpuSimple_rVal2;
output [68 : 0] execFpuSimple;
// signals for module outputs
wire [68 : 0] execFpuSimple;
// remaining internal signals
reg [63 : 0] IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838;
reg [51 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_4503_ETC__q6,
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q24,
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q25,
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q26,
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q27,
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q28,
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q29,
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q36,
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q37,
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q38,
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q39,
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q66,
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q67,
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q68,
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q69,
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q48,
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q49,
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q50,
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q51,
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q82,
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q83,
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q84,
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q85,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1774,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1789,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2083,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2098,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890,
_theResult___fst_sfd__h176791;
reg [30 : 0] IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600;
reg [22 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_8388_ETC__q4,
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q148,
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q149,
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q113,
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q114,
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q150,
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q151,
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q131,
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q132,
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q154,
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q155,
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q133,
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q134,
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q111,
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q112,
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q156,
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q157,
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q109,
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q110,
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q107,
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q108,
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q121,
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q122,
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q123,
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q124,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4433,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4448,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4567,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4582;
reg [10 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_2046_ETC__q5,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q63,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q79,
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q18,
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q19,
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q20,
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q21,
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q22,
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q23,
CASE_guard43842_0b0_0_0b1_0_0b10_out_exp44461__ETC__q33,
CASE_guard43842_0b0_0_0b1_theResult___exp44458_ETC__q32,
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_th_ETC__q34,
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_x4_ETC__q35,
CASE_guard53233_0b0_0_0b1_0_0b10_out_exp53852__ETC__q61,
CASE_guard53233_0b0_0_0b1_theResult___exp53849_ETC__q62,
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_th_ETC__q64,
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_x5_ETC__q65,
CASE_guard64466_0b0_0_0b1_0_0b10_out_exp65085__ETC__q45,
CASE_guard64466_0b0_0_0b1_theResult___exp65082_ETC__q44,
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_th_ETC__q46,
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_x6_ETC__q47,
CASE_guard75172_0b0_0_0b1_0_0b10_out_exp75791__ETC__q77,
CASE_guard75172_0b0_0_0b1_theResult___exp75788_ETC__q78,
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_th_ETC__q80,
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_x7_ETC__q81,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1056,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1478,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1751,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2059,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812,
_theResult___fst_exp__h176790;
reg [7 : 0] CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_254__ETC__q3,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q145,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q76,
CASE_guard2759_0b0_0_0b1_0_0b10_out_exp3175_0b_ETC__q143,
CASE_guard2759_0b0_0_0b1_theResult___exp3172_0_ETC__q144,
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103,
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104,
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_theRe_ETC__q146,
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_x3300_ETC__q147,
CASE_guard3586_0b0_0_0b1_0_0b10_out_exp4002_0b_ETC__q128,
CASE_guard3586_0b0_0_0b1_theResult___exp3999_0_ETC__q127,
CASE_guard3886_0b0_0_0b1_0_0b10_out_exp4302_0b_ETC__q74,
CASE_guard3886_0b0_0_0b1_theResult___exp4299_0_ETC__q75,
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_theRe_ETC__q129,
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_x4128_ETC__q130,
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105,
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106,
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_theRe_ETC__q152,
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_x4427_ETC__q153,
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q101,
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q102,
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q100,
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q99,
CASE_guard6904_0b0_0_0b1_0_0b10_out_exp7320_0b_ETC__q118,
CASE_guard6904_0b0_0_0b1_theResult___exp7317_0_ETC__q117,
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_theRe_ETC__q119,
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_x7446_ETC__q120,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3993,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4154,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4409,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4543;
reg CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q7,
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q86,
CASE_guard08409_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52,
CASE_guard17717_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53,
CASE_guard26784_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54,
CASE_guard3017_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140,
CASE_guard3586_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135,
CASE_guard4113_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136,
CASE_guard4153_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139,
CASE_guard43842_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55,
CASE_guard44572_0b0_execFpuSimple_rVal1_BIT_31_ETC__q56,
CASE_guard5164_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138,
CASE_guard6427_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137,
CASE_guard64466_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57,
CASE_guard65196_0b0_execFpuSimple_rVal1_BIT_63_ETC__q58,
CASE_guard6904_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125,
CASE_guard7431_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1161,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1168,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1586,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1593,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3820,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3828,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3838,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3846,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4098,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4105,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4259,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4266,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d912,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d920,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d928,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690;
wire [117 : 0] int_val__h94496,
int_val__h94497,
shifted__h94529,
shifted_out_mask__h96389,
x__h94762,
x__h96634,
x__h96657,
y__h94716,
y__h94811;
wire [115 : 0] int_val_rnd__h94501;
wire [88 : 0] int_val__h5743,
int_val__h5744,
shifted__h5776,
shifted_out_mask__h5777,
x__h5981,
x__h5994,
x__h6017,
y__h5935,
y__h6030;
wire [86 : 0] int_val_rnd__h5748;
wire [63 : 0] IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693,
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711,
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4603,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d67,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d78,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178,
_theResult_____1_fst__h6973,
_theResult_____1_fst__h8160,
_theResult_____1_fst__h95645,
_theResult_____1_fst__h96888,
_theResult___fst__h5722,
_theResult___fst__h5738,
_theResult___fst__h5753,
_theResult___fst__h6455,
_theResult___fst__h6470,
_theResult___fst__h7052,
_theResult___fst__h7068,
_theResult___fst__h7083,
_theResult___fst__h7642,
_theResult___fst__h7657,
_theResult___fst__h94475,
_theResult___fst__h94491,
_theResult___fst__h94506,
_theResult___fst__h95099,
_theResult___fst__h95114,
_theResult___fst__h95724,
_theResult___fst__h95740,
_theResult___fst__h95755,
_theResult___fst__h96342,
_theResult___fst__h96357,
dst_bits__h251,
dst_bits__h256,
dst_bits__h261,
dst_bits__h266,
dst_bits__h85575,
dst_bits__h85580,
dst_bits__h85585,
dst_bits__h85590,
max_val__h7094,
max_val__h95766,
out__h5724,
out__h6395,
out__h6400,
out__h6457,
out__h6989,
out__h7054,
out__h7587,
out__h94477,
out__h95039,
out__h95044,
out__h95101,
out__h95661,
out__h95726,
out__h96287,
sfd___3__h164456,
sfd___3__h175162,
x__h219,
x__h224,
x__h4245,
x__h4413,
x__h4568,
x__h85553,
x__h85558;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_ETC__q88,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimpl_ETC__q13,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimpl_ETC__q94,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q16,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q9,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q90,
IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q97,
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436,
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334,
_theResult____h117707,
_theResult____h16417,
_theResult____h34143,
_theResult___snd__h116321,
_theResult___snd__h116323,
_theResult___snd__h116330,
_theResult___snd__h116336,
_theResult___snd__h116359,
_theResult___snd__h125954,
_theResult___snd__h125965,
_theResult___snd__h125967,
_theResult___snd__h125977,
_theResult___snd__h125983,
_theResult___snd__h126006,
_theResult___snd__h134720,
_theResult___snd__h134734,
_theResult___snd__h134740,
_theResult___snd__h134758,
_theResult___snd__h24537,
_theResult___snd__h24548,
_theResult___snd__h24550,
_theResult___snd__h24560,
_theResult___snd__h24566,
_theResult___snd__h24589,
_theResult___snd__h33163,
_theResult___snd__h33165,
_theResult___snd__h33172,
_theResult___snd__h33178,
_theResult___snd__h33201,
_theResult___snd__h42390,
_theResult___snd__h42401,
_theResult___snd__h42403,
_theResult___snd__h42413,
_theResult___snd__h42419,
_theResult___snd__h42442,
_theResult___snd__h51040,
_theResult___snd__h51054,
_theResult___snd__h51060,
_theResult___snd__h51078,
result__h118320,
result__h34756,
sfd__h8786,
sfd__h97512,
sfdin__h125937,
sfdin__h24520,
sfdin__h42373,
x__h118415,
x__h34851;
wire [54 : 0] sfd___3__h143832,
sfd___3__h153223,
sfd__h135831,
sfd__h145471;
wire [53 : 0] sfd__h116388,
sfd__h126035,
sfd__h134793,
sfd__h143859,
sfd__h144602,
sfd__h153250,
sfd__h153992,
sfd__h164483,
sfd__h165226,
sfd__h175189,
sfd__h175931,
value__h17039;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865,
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102,
_theResult___fst_sfd__h101298,
_theResult___fst_sfd__h117124,
_theResult___fst_sfd__h117127,
_theResult___fst_sfd__h126771,
_theResult___fst_sfd__h126774,
_theResult___fst_sfd__h135553,
_theResult___fst_sfd__h135556,
_theResult___fst_sfd__h135565,
_theResult___fst_sfd__h135571,
_theResult___fst_sfd__h135812,
_theResult___fst_sfd__h144556,
_theResult___fst_sfd__h145312,
_theResult___fst_sfd__h145315,
_theResult___fst_sfd__h145458,
_theResult___fst_sfd__h153946,
_theResult___fst_sfd__h154701,
_theResult___fst_sfd__h154704,
_theResult___fst_sfd__h154835,
_theResult___fst_sfd__h165180,
_theResult___fst_sfd__h165936,
_theResult___fst_sfd__h165939,
_theResult___fst_sfd__h166082,
_theResult___fst_sfd__h175885,
_theResult___fst_sfd__h176640,
_theResult___fst_sfd__h176643,
_theResult___fst_sfd__h176774,
_theResult___fst_sfd__h96998,
_theResult___fst_sfd__h97058,
_theResult___fst_sfd__h97118,
_theResult___sfd__h117026,
_theResult___sfd__h126673,
_theResult___sfd__h135455,
_theResult___sfd__h144459,
_theResult___sfd__h145215,
_theResult___sfd__h153850,
_theResult___sfd__h154605,
_theResult___sfd__h165083,
_theResult___sfd__h165839,
_theResult___sfd__h175789,
_theResult___sfd__h176544,
_theResult___snd_fst_sfd__h117130,
_theResult___snd_fst_sfd__h135559,
_theResult___snd_fst_sfd__h145318,
_theResult___snd_fst_sfd__h154707,
_theResult___snd_fst_sfd__h165942,
_theResult___snd_fst_sfd__h176646,
_theResult___snd_fst_sfd__h97466,
dst_sfd__h96995,
dst_sfd__h97055,
dst_sfd__h97115,
out___1_sfd__h97215,
out_sfd__h117029,
out_sfd__h126676,
out_sfd__h135458,
out_sfd__h144462,
out_sfd__h145218,
out_sfd__h153853,
out_sfd__h154608,
out_sfd__h165086,
out_sfd__h165842,
out_sfd__h175792,
out_sfd__h176547;
wire [31 : 0] IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2643,
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2656,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2644,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2657,
IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2655,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2642,
execFpuSimple_rVal1_BITS_31_TO_0__q158,
int_val_rnd4501_BITS_31_TO_0__q8,
int_val_rnd748_BITS_31_TO_0__q87,
max_val__h5764,
max_val__h94517,
sfd___3__h56894,
sfd___3__h62749,
val__h6394,
val__h95038,
value__h136414,
x__h4067,
x__h4081,
x__h8190;
wire [30 : 0] IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625,
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630;
wire [24 : 0] sfd__h24618,
sfd__h33230,
sfd__h42471,
sfd__h51113,
sfd__h56921,
sfd__h57461,
sfd__h62776,
sfd__h63315,
sfd__h73603,
sfd__h74143,
sfd__h83903,
sfd__h84442,
value__h101927;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733,
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586,
_theResult___fst_sfd__h16400,
_theResult___fst_sfd__h25151,
_theResult___fst_sfd__h25154,
_theResult___fst_sfd__h33763,
_theResult___fst_sfd__h33766,
_theResult___fst_sfd__h43004,
_theResult___fst_sfd__h43007,
_theResult___fst_sfd__h51670,
_theResult___fst_sfd__h51673,
_theResult___fst_sfd__h51682,
_theResult___fst_sfd__h51688,
_theResult___fst_sfd__h51971,
_theResult___fst_sfd__h57415,
_theResult___fst_sfd__h57968,
_theResult___fst_sfd__h57971,
_theResult___fst_sfd__h63269,
_theResult___fst_sfd__h63821,
_theResult___fst_sfd__h63824,
_theResult___fst_sfd__h74097,
_theResult___fst_sfd__h74650,
_theResult___fst_sfd__h74653,
_theResult___fst_sfd__h84396,
_theResult___fst_sfd__h84948,
_theResult___fst_sfd__h84951,
_theResult___sfd__h25053,
_theResult___sfd__h33665,
_theResult___sfd__h42906,
_theResult___sfd__h51572,
_theResult___sfd__h57318,
_theResult___sfd__h57871,
_theResult___sfd__h63173,
_theResult___sfd__h63725,
_theResult___sfd__h74000,
_theResult___sfd__h74553,
_theResult___sfd__h84300,
_theResult___sfd__h84852,
_theResult___snd_fst_sfd__h33769,
_theResult___snd_fst_sfd__h51676,
_theResult___snd_fst_sfd__h57974,
_theResult___snd_fst_sfd__h63827,
_theResult___snd_fst_sfd__h74656,
_theResult___snd_fst_sfd__h84954,
_theResult___snd_fst_sfd__h8740,
in1_sfd__h4124,
in2_sfd__h4199,
out_sfd__h25056,
out_sfd__h33668,
out_sfd__h42909,
out_sfd__h51575,
out_sfd__h57321,
out_sfd__h57874,
out_sfd__h63176,
out_sfd__h63728,
out_sfd__h74003,
out_sfd__h74556,
out_sfd__h84303,
out_sfd__h84855;
wire [16 : 0] _1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115,
amt_abs__h96387;
wire [12 : 0] _150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746,
amt_abs__h5775;
wire [11 : 0] IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898,
_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669,
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276,
_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979,
x__h118448,
x__h144587,
x__h153977,
x__h165211,
x__h175916,
x__h34884;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737,
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806,
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q15,
_theResult___exp__h117025,
_theResult___exp__h126672,
_theResult___exp__h135454,
_theResult___exp__h144458,
_theResult___exp__h145214,
_theResult___exp__h153849,
_theResult___exp__h154604,
_theResult___exp__h165082,
_theResult___exp__h165838,
_theResult___exp__h175788,
_theResult___exp__h176543,
_theResult___fst_exp__h101297,
_theResult___fst_exp__h116361,
_theResult___fst_exp__h116367,
_theResult___fst_exp__h116370,
_theResult___fst_exp__h117123,
_theResult___fst_exp__h117126,
_theResult___fst_exp__h125943,
_theResult___fst_exp__h126008,
_theResult___fst_exp__h126014,
_theResult___fst_exp__h126017,
_theResult___fst_exp__h126770,
_theResult___fst_exp__h126773,
_theResult___fst_exp__h134726,
_theResult___fst_exp__h134765,
_theResult___fst_exp__h134771,
_theResult___fst_exp__h134774,
_theResult___fst_exp__h135552,
_theResult___fst_exp__h135555,
_theResult___fst_exp__h135564,
_theResult___fst_exp__h135567,
_theResult___fst_exp__h135811,
_theResult___fst_exp__h144555,
_theResult___fst_exp__h145311,
_theResult___fst_exp__h145314,
_theResult___fst_exp__h145457,
_theResult___fst_exp__h153945,
_theResult___fst_exp__h154700,
_theResult___fst_exp__h154703,
_theResult___fst_exp__h154834,
_theResult___fst_exp__h165179,
_theResult___fst_exp__h165935,
_theResult___fst_exp__h165938,
_theResult___fst_exp__h166081,
_theResult___fst_exp__h175884,
_theResult___fst_exp__h176639,
_theResult___fst_exp__h176642,
_theResult___fst_exp__h176773,
_theResult___snd_fst_exp__h117129,
_theResult___snd_fst_exp__h135558,
_theResult___snd_fst_exp__h145317,
_theResult___snd_fst_exp__h145320,
_theResult___snd_fst_exp__h145323,
_theResult___snd_fst_exp__h154706,
_theResult___snd_fst_exp__h154709,
_theResult___snd_fst_exp__h154712,
_theResult___snd_fst_exp__h165941,
_theResult___snd_fst_exp__h165944,
_theResult___snd_fst_exp__h165947,
_theResult___snd_fst_exp__h176645,
_theResult___snd_fst_exp__h176648,
_theResult___snd_fst_exp__h176651,
din_inc___2_exp__h135590,
din_inc___2_exp__h135620,
din_inc___2_exp__h135644,
din_inc___2_exp__h145356,
din_inc___2_exp__h154742,
din_inc___2_exp__h165980,
din_inc___2_exp__h176681,
execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92,
out_exp__h117028,
out_exp__h126675,
out_exp__h135457,
out_exp__h144461,
out_exp__h145217,
out_exp__h153852,
out_exp__h154607,
out_exp__h165085,
out_exp__h165841,
out_exp__h175791,
out_exp__h176546;
wire [9 : 0] IF_execFpuSimple_rVal1_BITS_63_TO_32_EQ_0xFFFF_ETC__q2,
IF_execFpuSimple_rVal1_BIT_63_AND_execFpuSimpl_ETC__q1,
x__h4812,
x__h93191;
wire [8 : 0] IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464,
x__h57446,
x__h63300,
x__h74128,
x__h84427;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192,
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633,
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702,
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034,
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195,
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96,
_theResult___exp__h25052,
_theResult___exp__h33664,
_theResult___exp__h42905,
_theResult___exp__h51571,
_theResult___exp__h57317,
_theResult___exp__h57870,
_theResult___exp__h63172,
_theResult___exp__h63724,
_theResult___exp__h73999,
_theResult___exp__h74552,
_theResult___exp__h84299,
_theResult___exp__h84851,
_theResult___fst_exp__h16399,
_theResult___fst_exp__h24526,
_theResult___fst_exp__h24591,
_theResult___fst_exp__h24597,
_theResult___fst_exp__h24600,
_theResult___fst_exp__h25150,
_theResult___fst_exp__h25153,
_theResult___fst_exp__h33203,
_theResult___fst_exp__h33209,
_theResult___fst_exp__h33212,
_theResult___fst_exp__h33762,
_theResult___fst_exp__h33765,
_theResult___fst_exp__h42379,
_theResult___fst_exp__h42444,
_theResult___fst_exp__h42450,
_theResult___fst_exp__h42453,
_theResult___fst_exp__h43003,
_theResult___fst_exp__h43006,
_theResult___fst_exp__h51046,
_theResult___fst_exp__h51085,
_theResult___fst_exp__h51091,
_theResult___fst_exp__h51094,
_theResult___fst_exp__h51669,
_theResult___fst_exp__h51672,
_theResult___fst_exp__h51681,
_theResult___fst_exp__h51684,
_theResult___fst_exp__h51970,
_theResult___fst_exp__h57414,
_theResult___fst_exp__h57967,
_theResult___fst_exp__h57970,
_theResult___fst_exp__h63268,
_theResult___fst_exp__h63820,
_theResult___fst_exp__h63823,
_theResult___fst_exp__h74096,
_theResult___fst_exp__h74649,
_theResult___fst_exp__h74652,
_theResult___fst_exp__h84395,
_theResult___fst_exp__h84947,
_theResult___fst_exp__h84950,
_theResult___snd_fst_exp__h33768,
_theResult___snd_fst_exp__h51675,
_theResult___snd_fst_exp__h57973,
_theResult___snd_fst_exp__h57976,
_theResult___snd_fst_exp__h57979,
_theResult___snd_fst_exp__h63826,
_theResult___snd_fst_exp__h63829,
_theResult___snd_fst_exp__h63832,
_theResult___snd_fst_exp__h74655,
_theResult___snd_fst_exp__h74658,
_theResult___snd_fst_exp__h74661,
_theResult___snd_fst_exp__h84953,
_theResult___snd_fst_exp__h84956,
_theResult___snd_fst_exp__h84959,
din_inc___2_exp__h51703,
din_inc___2_exp__h51727,
din_inc___2_exp__h51757,
din_inc___2_exp__h51781,
din_inc___2_exp__h58012,
din_inc___2_exp__h63862,
din_inc___2_exp__h74694,
din_inc___2_exp__h84989,
execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q11,
in1_exp__h4123,
in2_exp__h4198,
out_exp__h25055,
out_exp__h33667,
out_exp__h42908,
out_exp__h51574,
out_exp__h57320,
out_exp__h57873,
out_exp__h63175,
out_exp__h63727,
out_exp__h74002,
out_exp__h74555,
out_exp__h84302,
out_exp__h84854;
wire [6 : 0] IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133,
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678,
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326;
wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638;
wire [1 : 0] IF_sfd___32749_BIT_7_THEN_2_ELSE_0__q142,
IF_sfd___32749_BIT_8_THEN_2_ELSE_0__q141,
IF_sfd___343832_BIT_1_THEN_2_ELSE_0__q31,
IF_sfd___343832_BIT_2_THEN_2_ELSE_0__q30,
IF_sfd___353223_BIT_1_THEN_2_ELSE_0__q60,
IF_sfd___353223_BIT_2_THEN_2_ELSE_0__q59,
IF_sfd___364456_BIT_10_THEN_2_ELSE_0__q43,
IF_sfd___364456_BIT_11_THEN_2_ELSE_0__q42,
IF_sfd___364456_BIT_39_THEN_2_ELSE_0__q41,
IF_sfd___364456_BIT_40_THEN_2_ELSE_0__q40,
IF_sfd___36894_BIT_7_THEN_2_ELSE_0__q116,
IF_sfd___36894_BIT_8_THEN_2_ELSE_0__q115,
IF_sfd___375162_BIT_10_THEN_2_ELSE_0__q73,
IF_sfd___375162_BIT_11_THEN_2_ELSE_0__q72,
IF_sfd___375162_BIT_39_THEN_2_ELSE_0__q71,
IF_sfd___375162_BIT_40_THEN_2_ELSE_0__q70,
IF_sfdin2373_BIT_33_THEN_2_ELSE_0__q95,
IF_sfdin25937_BIT_4_THEN_2_ELSE_0__q14,
IF_sfdin4520_BIT_33_THEN_2_ELSE_0__q89,
IF_theResult___snd1040_BIT_33_THEN_2_ELSE_0__q98,
IF_theResult___snd16321_BIT_4_THEN_2_ELSE_0__q10,
IF_theResult___snd3163_BIT_33_THEN_2_ELSE_0__q91,
IF_theResult___snd34720_BIT_4_THEN_2_ELSE_0__q17,
guard__h108409,
guard__h117717,
guard__h126784,
guard__h143842,
guard__h144572,
guard__h153233,
guard__h153962,
guard__h16427,
guard__h164466,
guard__h165196,
guard__h175172,
guard__h175901,
guard__h25164,
guard__h34153,
guard__h43017,
guard__h56904,
guard__h57431,
guard__h62759,
guard__h63285,
guard__h73586,
guard__h74113,
guard__h83886,
guard__h84412;
wire IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175,
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198,
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792,
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815,
IF_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1__ETC___d3831,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1171,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4108,
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4883,
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559,
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4892,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1596,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2567,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4269,
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4901,
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2576,
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4910,
IF_NOT_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_r_ETC___d1172,
IF_NOT_3970_MINUS_0_CONCAT_IF_execFpuSimple_rV_ETC___d914,
IF_NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_N_ETC___d4109,
IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2705,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2292,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2483,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2520,
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d931,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3849,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4713,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4812,
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4852,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1162,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1169,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1587,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1594,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d164,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d2781,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3821,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3829,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3839,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3847,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4099,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4106,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4260,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4267,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d913,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d921,
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d929,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2470,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2507,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4798,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4838,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d933,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d1621,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3851,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4698,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4715,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4814,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d4286,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2686,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2690,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667,
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NOT_execF_ETC___d2157,
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4707,
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4848,
NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935,
NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2685,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2708,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4680,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873,
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878,
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915,
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536,
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212,
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d1599,
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d4272,
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759,
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769,
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9_ETC___d2160,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546,
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_ex_ETC___d2139,
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322,
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878,
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899,
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d2069,
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d4553,
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_execFpu_ETC___d76,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430,
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328,
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257,
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4641,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4694,
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4808,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954,
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331,
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332,
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277,
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116,
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466,
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4_AND_ETC___d2281,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683,
execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052,
execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129,
execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134,
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192,
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198,
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127,
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126,
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2138,
execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2640,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2653,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2688,
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2707,
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418,
execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895,
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439,
execFpuSimple_rVal1_BIT_63_4_AND_NOT_execFpuSi_ETC___d65,
execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58,
execFpuSimple_rVal1_BIT_63_4_OR_NOT_execFpuSim_ETC___d2141,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828,
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913,
guard__h118315,
guard__h34751,
saturated_bit__h5778,
saturated_bit__h94531,
value_BIT_23___h109067,
x__h176800,
x__h176927,
x__h177049,
x__h4248,
x__h4416,
x__h4571;
// value method execFpuSimple
assign execFpuSimple =
execFpuSimple_fpu_inst[0] ?
{ IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270,
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4_AND_ETC___d2281,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2470,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2507,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 } :
{ IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4603,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690,
execFpuSimple_fpu_inst[8:4] == 5'd10 &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4698,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4798,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4838,
execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 } ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_ETC__q88 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135 ?
_theResult___snd__h24589 :
_theResult____h16417 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimpl_ETC__q13 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680 ?
_theResult___snd__h126006 :
_theResult____h117707 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimpl_ETC__q94 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576 ?
_theResult___snd__h42442 :
_theResult____h34143 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q16 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753 ?
_theResult___snd__h116359 :
_theResult___snd__h134758 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q9 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351 ?
_theResult___snd__h116359 :
57'd0 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q90 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257 ?
_theResult___snd__h33201 :
57'd0 ;
assign IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q97 =
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649 ?
_theResult___snd__h33201 :
_theResult___snd__h51078 ;
assign IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 =
int_val_rnd__h94501[31:0] <= max_val__h94517 ;
assign IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198 =
int_val_rnd__h94501[63:0] <= max_val__h95766 ;
assign IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792 =
int_val_rnd__h5748[31:0] <= max_val__h5764 ;
assign IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815 =
int_val_rnd__h5748[63:0] <= max_val__h7094 ;
assign IF_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1__ETC___d3831 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
((_theResult___fst_exp__h24526 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3821) :
((_theResult___fst_exp__h33212 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3829) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1171 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1162 :
((x__h144587[10:0] == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1169) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
guard__h143842 != 2'b0 :
x__h144587[10:0] != 11'd2047 && guard__h144572 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4108 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4099 :
((x__h57446[7:0] == 8'd255) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4106) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4883 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
guard__h56904 != 2'b0 :
x__h57446[7:0] != 8'd255 && guard__h57431 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 ?
guard__h153233 != 2'b0 :
x__h153977[10:0] != 11'd2047 && guard__h153962 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4892 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 ?
guard__h62759 != 2'b0 :
x__h63300[7:0] != 8'd255 && guard__h63285 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1596 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1587 :
((x__h165211[10:0] == 11'd2047) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1594) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2567 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
guard__h164466 != 2'b0 :
x__h165211[10:0] != 11'd2047 && guard__h165196 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4269 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4260 :
((x__h74128[7:0] == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4267) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4901 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
guard__h73586 != 2'b0 :
x__h74128[7:0] != 8'd255 && guard__h74113 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2576 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 ?
guard__h175172 != 2'b0 :
x__h175916[10:0] != 11'd2047 && guard__h175901 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4910 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 ?
guard__h83886 != 2'b0 :
x__h84427[7:0] != 8'd255 && guard__h84412 != 2'b0 ;
assign IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 =
(_theResult____h16417[56] ?
6'd0 :
(_theResult____h16417[55] ?
6'd1 :
(_theResult____h16417[54] ?
6'd2 :
(_theResult____h16417[53] ?
6'd3 :
(_theResult____h16417[52] ?
6'd4 :
(_theResult____h16417[51] ?
6'd5 :
(_theResult____h16417[50] ?
6'd6 :
(_theResult____h16417[49] ?
6'd7 :
(_theResult____h16417[48] ?
6'd8 :
(_theResult____h16417[47] ?
6'd9 :
(_theResult____h16417[46] ?
6'd10 :
(_theResult____h16417[45] ?
6'd11 :
(_theResult____h16417[44] ?
6'd12 :
(_theResult____h16417[43] ?
6'd13 :
(_theResult____h16417[42] ?
6'd14 :
(_theResult____h16417[41] ?
6'd15 :
(_theResult____h16417[40] ?
6'd16 :
(_theResult____h16417[39] ?
6'd17 :
(_theResult____h16417[38] ?
6'd18 :
(_theResult____h16417[37] ?
6'd19 :
(_theResult____h16417[36] ?
6'd20 :
(_theResult____h16417[35] ?
6'd21 :
(_theResult____h16417[34] ?
6'd22 :
(_theResult____h16417[33] ?
6'd23 :
(_theResult____h16417[32] ?
6'd24 :
(_theResult____h16417[31] ?
6'd25 :
(_theResult____h16417[30] ?
6'd26 :
(_theResult____h16417[29] ?
6'd27 :
(_theResult____h16417[28] ?
6'd28 :
(_theResult____h16417[27] ?
6'd29 :
(_theResult____h16417[26] ?
6'd30 :
(_theResult____h16417[25] ?
6'd31 :
(_theResult____h16417[24] ?
6'd32 :
(_theResult____h16417[23] ?
6'd33 :
(_theResult____h16417[22] ?
6'd34 :
(_theResult____h16417[21] ?
6'd35 :
(_theResult____h16417[20] ?
6'd36 :
(_theResult____h16417[19] ?
6'd37 :
(_theResult____h16417[18] ?
6'd38 :
(_theResult____h16417[17] ?
6'd39 :
(_theResult____h16417[16] ?
6'd40 :
(_theResult____h16417[15] ?
6'd41 :
(_theResult____h16417[14] ?
6'd42 :
(_theResult____h16417[13] ?
6'd43 :
(_theResult____h16417[12] ?
6'd44 :
(_theResult____h16417[11] ?
6'd45 :
(_theResult____h16417[10] ?
6'd46 :
(_theResult____h16417[9] ?
6'd47 :
(_theResult____h16417[8] ?
6'd48 :
(_theResult____h16417[7] ?
6'd49 :
(_theResult____h16417[6] ?
6'd50 :
(_theResult____h16417[5] ?
6'd51 :
(_theResult____h16417[4] ?
6'd52 :
(_theResult____h16417[3] ?
6'd53 :
(_theResult____h16417[2] ?
6'd54 :
(_theResult____h16417[1] ?
6'd55 :
(_theResult____h16417[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 =
(_theResult____h117707[56] ?
6'd0 :
(_theResult____h117707[55] ?
6'd1 :
(_theResult____h117707[54] ?
6'd2 :
(_theResult____h117707[53] ?
6'd3 :
(_theResult____h117707[52] ?
6'd4 :
(_theResult____h117707[51] ?
6'd5 :
(_theResult____h117707[50] ?
6'd6 :
(_theResult____h117707[49] ?
6'd7 :
(_theResult____h117707[48] ?
6'd8 :
(_theResult____h117707[47] ?
6'd9 :
(_theResult____h117707[46] ?
6'd10 :
(_theResult____h117707[45] ?
6'd11 :
(_theResult____h117707[44] ?
6'd12 :
(_theResult____h117707[43] ?
6'd13 :
(_theResult____h117707[42] ?
6'd14 :
(_theResult____h117707[41] ?
6'd15 :
(_theResult____h117707[40] ?
6'd16 :
(_theResult____h117707[39] ?
6'd17 :
(_theResult____h117707[38] ?
6'd18 :
(_theResult____h117707[37] ?
6'd19 :
(_theResult____h117707[36] ?
6'd20 :
(_theResult____h117707[35] ?
6'd21 :
(_theResult____h117707[34] ?
6'd22 :
(_theResult____h117707[33] ?
6'd23 :
(_theResult____h117707[32] ?
6'd24 :
(_theResult____h117707[31] ?
6'd25 :
(_theResult____h117707[30] ?
6'd26 :
(_theResult____h117707[29] ?
6'd27 :
(_theResult____h117707[28] ?
6'd28 :
(_theResult____h117707[27] ?
6'd29 :
(_theResult____h117707[26] ?
6'd30 :
(_theResult____h117707[25] ?
6'd31 :
(_theResult____h117707[24] ?
6'd32 :
(_theResult____h117707[23] ?
6'd33 :
(_theResult____h117707[22] ?
6'd34 :
(_theResult____h117707[21] ?
6'd35 :
(_theResult____h117707[20] ?
6'd36 :
(_theResult____h117707[19] ?
6'd37 :
(_theResult____h117707[18] ?
6'd38 :
(_theResult____h117707[17] ?
6'd39 :
(_theResult____h117707[16] ?
6'd40 :
(_theResult____h117707[15] ?
6'd41 :
(_theResult____h117707[14] ?
6'd42 :
(_theResult____h117707[13] ?
6'd43 :
(_theResult____h117707[12] ?
6'd44 :
(_theResult____h117707[11] ?
6'd45 :
(_theResult____h117707[10] ?
6'd46 :
(_theResult____h117707[9] ?
6'd47 :
(_theResult____h117707[8] ?
6'd48 :
(_theResult____h117707[7] ?
6'd49 :
(_theResult____h117707[6] ?
6'd50 :
(_theResult____h117707[5] ?
6'd51 :
(_theResult____h117707[4] ?
6'd52 :
(_theResult____h117707[3] ?
6'd53 :
(_theResult____h117707[2] ?
6'd54 :
(_theResult____h117707[1] ?
6'd55 :
(_theResult____h117707[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 =
(_theResult____h34143[56] ?
6'd0 :
(_theResult____h34143[55] ?
6'd1 :
(_theResult____h34143[54] ?
6'd2 :
(_theResult____h34143[53] ?
6'd3 :
(_theResult____h34143[52] ?
6'd4 :
(_theResult____h34143[51] ?
6'd5 :
(_theResult____h34143[50] ?
6'd6 :
(_theResult____h34143[49] ?
6'd7 :
(_theResult____h34143[48] ?
6'd8 :
(_theResult____h34143[47] ?
6'd9 :
(_theResult____h34143[46] ?
6'd10 :
(_theResult____h34143[45] ?
6'd11 :
(_theResult____h34143[44] ?
6'd12 :
(_theResult____h34143[43] ?
6'd13 :
(_theResult____h34143[42] ?
6'd14 :
(_theResult____h34143[41] ?
6'd15 :
(_theResult____h34143[40] ?
6'd16 :
(_theResult____h34143[39] ?
6'd17 :
(_theResult____h34143[38] ?
6'd18 :
(_theResult____h34143[37] ?
6'd19 :
(_theResult____h34143[36] ?
6'd20 :
(_theResult____h34143[35] ?
6'd21 :
(_theResult____h34143[34] ?
6'd22 :
(_theResult____h34143[33] ?
6'd23 :
(_theResult____h34143[32] ?
6'd24 :
(_theResult____h34143[31] ?
6'd25 :
(_theResult____h34143[30] ?
6'd26 :
(_theResult____h34143[29] ?
6'd27 :
(_theResult____h34143[28] ?
6'd28 :
(_theResult____h34143[27] ?
6'd29 :
(_theResult____h34143[26] ?
6'd30 :
(_theResult____h34143[25] ?
6'd31 :
(_theResult____h34143[24] ?
6'd32 :
(_theResult____h34143[23] ?
6'd33 :
(_theResult____h34143[22] ?
6'd34 :
(_theResult____h34143[21] ?
6'd35 :
(_theResult____h34143[20] ?
6'd36 :
(_theResult____h34143[19] ?
6'd37 :
(_theResult____h34143[18] ?
6'd38 :
(_theResult____h34143[17] ?
6'd39 :
(_theResult____h34143[16] ?
6'd40 :
(_theResult____h34143[15] ?
6'd41 :
(_theResult____h34143[14] ?
6'd42 :
(_theResult____h34143[13] ?
6'd43 :
(_theResult____h34143[12] ?
6'd44 :
(_theResult____h34143[11] ?
6'd45 :
(_theResult____h34143[10] ?
6'd46 :
(_theResult____h34143[9] ?
6'd47 :
(_theResult____h34143[8] ?
6'd48 :
(_theResult____h34143[7] ?
6'd49 :
(_theResult____h34143[6] ?
6'd50 :
(_theResult____h34143[5] ?
6'd51 :
(_theResult____h34143[4] ?
6'd52 :
(_theResult____h34143[3] ?
6'd53 :
(_theResult____h34143[2] ?
6'd54 :
(_theResult____h34143[1] ?
6'd55 :
(_theResult____h34143[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192 =
(guard__h16427 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h24526 :
_theResult___exp__h25052 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194 =
(guard__h16427 == 2'b0) ?
_theResult___fst_exp__h24526 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h25052 :
_theResult___fst_exp__h24526) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733 =
(guard__h16427 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfdin__h24520[56:34] :
_theResult___sfd__h25053 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735 =
(guard__h16427 == 2'b0) ?
sfdin__h24520[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h25053 :
sfdin__h24520[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737 =
(guard__h117717 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___fst_exp__h125943 :
_theResult___exp__h126672 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739 =
(guard__h117717 == 2'b0) ?
_theResult___fst_exp__h125943 :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h126672 :
_theResult___fst_exp__h125943) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865 =
(guard__h117717 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfdin__h125937[56:5] :
_theResult___sfd__h126673 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867 =
(guard__h117717 == 2'b0) ?
sfdin__h125937[56:5] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h126673 :
sfdin__h125937[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633 =
(guard__h34153 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h42379 :
_theResult___exp__h42905 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635 =
(guard__h34153 == 2'b0) ?
_theResult___fst_exp__h42379 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h42905 :
_theResult___fst_exp__h42379) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779 =
(guard__h34153 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfdin__h42373[56:34] :
_theResult___sfd__h42906 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781 =
(guard__h34153 == 2'b0) ?
sfdin__h42373[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h42906 :
sfdin__h42373[56:34]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407 =
(guard__h108409 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___fst_exp__h116370 :
_theResult___exp__h117025 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409 =
(guard__h108409 == 2'b0) ?
_theResult___fst_exp__h116370 :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h117025 :
_theResult___fst_exp__h116370) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806 =
(guard__h126784 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___fst_exp__h134774 :
_theResult___exp__h135454 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808 =
(guard__h126784 == 2'b0) ?
_theResult___fst_exp__h134774 :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h135454 :
_theResult___fst_exp__h134774) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838 =
(guard__h108409 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___snd__h116321[56:5] :
_theResult___sfd__h117026 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840 =
(guard__h108409 == 2'b0) ?
_theResult___snd__h116321[56:5] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h117026 :
_theResult___snd__h116321[56:5]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884 =
(guard__h126784 == 2'b0 || execFpuSimple_rVal1[31]) ?
_theResult___snd__h134720[56:5] :
_theResult___sfd__h135455 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886 =
(guard__h126784 == 2'b0) ?
_theResult___snd__h134720[56:5] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h135455 :
_theResult___snd__h134720[56:5]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309 =
(guard__h25164 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h33212 :
_theResult___exp__h33664 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311 =
(guard__h25164 == 2'b0) ?
_theResult___fst_exp__h33212 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h33664 :
_theResult___fst_exp__h33212) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702 =
(guard__h43017 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___fst_exp__h51094 :
_theResult___exp__h51571 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704 =
(guard__h43017 == 2'b0) ?
_theResult___fst_exp__h51094 :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h51571 :
_theResult___fst_exp__h51094) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752 =
(guard__h25164 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___snd__h33163[56:34] :
_theResult___sfd__h33665 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754 =
(guard__h25164 == 2'b0) ?
_theResult___snd__h33163[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h33665 :
_theResult___snd__h33163[56:34]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798 =
(guard__h43017 == 2'b0 || execFpuSimple_rVal1[63]) ?
_theResult___snd__h51040[56:34] :
_theResult___sfd__h51572 ;
assign IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800 =
(guard__h43017 == 2'b0) ?
_theResult___snd__h51040[56:34] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h51572 :
_theResult___snd__h51040[56:34]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053 =
(guard__h143842 == 2'b0) ?
11'd0 :
(execFpuSimple_rVal1[31] ? _theResult___exp__h144458 : 11'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097 =
(guard__h144572 == 2'b0 || execFpuSimple_rVal1[31]) ?
x__h144587[10:0] :
_theResult___exp__h145214 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099 =
(guard__h144572 == 2'b0) ?
x__h144587[10:0] :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h145214 :
x__h144587[10:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124 =
(guard__h143842 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h143832[54:3] :
_theResult___sfd__h144459 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126 =
(guard__h143842 == 2'b0) ?
sfd___3__h143832[54:3] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h144459 :
sfd___3__h143832[54:3]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142 =
(guard__h144572 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h143832[53:2] :
_theResult___sfd__h145215 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144 =
(guard__h144572 == 2'b0) ?
sfd___3__h143832[53:2] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h145215 :
sfd___3__h143832[53:2]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990 =
(guard__h56904 == 2'b0) ?
8'd0 :
(execFpuSimple_rVal1[31] ? _theResult___exp__h57317 : 8'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034 =
(guard__h57431 == 2'b0 || execFpuSimple_rVal1[31]) ?
x__h57446[7:0] :
_theResult___exp__h57870 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036 =
(guard__h57431 == 2'b0) ?
x__h57446[7:0] :
(execFpuSimple_rVal1[31] ?
_theResult___exp__h57870 :
x__h57446[7:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062 =
(guard__h56904 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h56894[31:9] :
_theResult___sfd__h57318 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064 =
(guard__h56904 == 2'b0) ?
sfd___3__h56894[31:9] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h57318 :
sfd___3__h56894[31:9]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080 =
(guard__h57431 == 2'b0 || execFpuSimple_rVal1[31]) ?
sfd___3__h56894[30:8] :
_theResult___sfd__h57871 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082 =
(guard__h57431 == 2'b0) ?
sfd___3__h56894[30:8] :
(execFpuSimple_rVal1[31] ?
_theResult___sfd__h57871 :
sfd___3__h56894[30:8]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475 =
(guard__h164466 == 2'b0) ?
11'd0 :
(execFpuSimple_rVal1[63] ? _theResult___exp__h165082 : 11'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519 =
(guard__h165196 == 2'b0 || execFpuSimple_rVal1[63]) ?
x__h165211[10:0] :
_theResult___exp__h165838 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521 =
(guard__h165196 == 2'b0) ?
x__h165211[10:0] :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h165838 :
x__h165211[10:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547 =
(guard__h164466 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164456[63:12] :
_theResult___sfd__h165083 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549 =
(guard__h164466 == 2'b0) ?
sfd___3__h164456[63:12] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h165083 :
sfd___3__h164456[63:12]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565 =
(guard__h165196 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164456[62:11] :
_theResult___sfd__h165839 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567 =
(guard__h165196 == 2'b0) ?
sfd___3__h164456[62:11] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h165839 :
sfd___3__h164456[62:11]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151 =
(guard__h73586 == 2'b0) ?
8'd0 :
(execFpuSimple_rVal1[63] ? _theResult___exp__h73999 : 8'd0) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195 =
(guard__h74113 == 2'b0 || execFpuSimple_rVal1[63]) ?
x__h74128[7:0] :
_theResult___exp__h74552 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197 =
(guard__h74113 == 2'b0) ?
x__h74128[7:0] :
(execFpuSimple_rVal1[63] ?
_theResult___exp__h74552 :
x__h74128[7:0]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223 =
(guard__h73586 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164456[63:41] :
_theResult___sfd__h74000 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225 =
(guard__h73586 == 2'b0) ?
sfd___3__h164456[63:41] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h74000 :
sfd___3__h164456[63:41]) ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241 =
(guard__h74113 == 2'b0 || execFpuSimple_rVal1[63]) ?
sfd___3__h164456[62:40] :
_theResult___sfd__h74553 ;
assign IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243 =
(guard__h74113 == 2'b0) ?
sfd___3__h164456[62:40] :
(execFpuSimple_rVal1[63] ?
_theResult___sfd__h74553 :
sfd___3__h164456[62:40]) ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2643 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
x__h4081 :
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2642 ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2656 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
x__h4081 :
IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2655 ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
64'd0 :
x__h4245 ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
64'd0 :
x__h4413 ;
assign IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
64'd0 :
x__h4568 ;
assign IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011 =
value__h136414[31] ?
6'd0 :
(value__h136414[30] ?
6'd1 :
(value__h136414[29] ?
6'd2 :
(value__h136414[28] ?
6'd3 :
(value__h136414[27] ?
6'd4 :
(value__h136414[26] ?
6'd5 :
(value__h136414[25] ?
6'd6 :
(value__h136414[24] ?
6'd7 :
(value__h136414[23] ?
6'd8 :
(value__h136414[22] ?
6'd9 :
(value__h136414[21] ?
6'd10 :
(value__h136414[20] ?
6'd11 :
(value__h136414[19] ?
6'd12 :
(value__h136414[18] ?
6'd13 :
(value__h136414[17] ?
6'd14 :
(value__h136414[16] ?
6'd15 :
(value__h136414[15] ?
6'd16 :
(value__h136414[14] ?
6'd17 :
(value__h136414[13] ?
6'd18 :
(value__h136414[12] ?
6'd19 :
(value__h136414[11] ?
6'd20 :
(value__h136414[10] ?
6'd21 :
(value__h136414[9] ?
6'd22 :
(value__h136414[8] ?
6'd23 :
(value__h136414[7] ?
6'd24 :
(value__h136414[6] ?
6'd25 :
(value__h136414[5] ?
6'd26 :
(value__h136414[4] ?
6'd27 :
(value__h136414[3] ?
6'd28 :
(value__h136414[2] ?
6'd29 :
(value__h136414[1] ?
6'd30 :
(value__h136414[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949 =
value__h136414[31] ?
6'd0 :
(value__h136414[30] ?
6'd1 :
(value__h136414[29] ?
6'd2 :
(value__h136414[28] ?
6'd3 :
(value__h136414[27] ?
6'd4 :
(value__h136414[26] ?
6'd5 :
(value__h136414[25] ?
6'd6 :
(value__h136414[24] ?
6'd7 :
(value__h136414[23] ?
6'd8 :
(value__h136414[22] ?
6'd9 :
(value__h136414[21] ?
6'd10 :
(value__h136414[20] ?
6'd11 :
(value__h136414[19] ?
6'd12 :
(value__h136414[18] ?
6'd13 :
(value__h136414[17] ?
6'd14 :
(value__h136414[16] ?
6'd15 :
(value__h136414[15] ?
6'd16 :
(value__h136414[14] ?
6'd17 :
(value__h136414[13] ?
6'd18 :
(value__h136414[12] ?
6'd19 :
(value__h136414[11] ?
6'd20 :
(value__h136414[10] ?
6'd21 :
(value__h136414[9] ?
6'd22 :
(value__h136414[8] ?
6'd23 :
(value__h136414[7] ?
6'd24 :
(value__h136414[6] ?
6'd25 :
(value__h136414[5] ?
6'd26 :
(value__h136414[4] ?
6'd27 :
(value__h136414[3] ?
6'd28 :
(value__h136414[2] ?
6'd29 :
(value__h136414[1] ?
6'd30 :
(value__h136414[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 =
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ?
7'd0 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ?
7'd1 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ?
7'd2 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ?
7'd3 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ?
7'd4 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ?
7'd5 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ?
7'd6 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ?
7'd7 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ?
7'd8 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ?
7'd9 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ?
7'd10 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ?
7'd11 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ?
7'd12 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ?
7'd13 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ?
7'd14 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ?
7'd15 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ?
7'd16 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ?
7'd17 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ?
7'd18 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ?
7'd19 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ?
7'd20 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ?
7'd21 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ?
7'd22 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ?
7'd23 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ?
7'd24 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ?
7'd25 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ?
7'd26 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ?
7'd27 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ?
7'd28 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ?
7'd29 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ?
7'd30 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ?
7'd31 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ?
7'd32 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ?
7'd33 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ?
7'd34 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ?
7'd35 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ?
7'd36 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ?
7'd37 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ?
7'd38 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ?
7'd39 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ?
7'd40 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ?
7'd41 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ?
7'd42 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ?
7'd43 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ?
7'd44 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ?
7'd45 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ?
7'd46 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ?
7'd47 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ?
7'd48 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ?
7'd49 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ?
7'd50 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ?
7'd51 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ?
7'd52 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ?
7'd53 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ?
7'd54 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ?
7'd55 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ?
7'd56 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ?
7'd57 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ?
7'd58 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ?
7'd59 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ?
7'd60 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ?
7'd61 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ?
7'd62 :
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2644 =
(in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
x__h4067 :
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2643 ;
assign IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2657 =
(in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0) ?
x__h4067 :
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2656 ;
assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_r_ETC___d1172 =
(!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016) ?
execFpuSimple_rVal1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1171 ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_execFpuSimple_rV_ETC___d914 =
(!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ||
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ||
_theResult___fst_exp__h116370 == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d913 ;
assign IF_NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_N_ETC___d4109 =
(!value__h136414[31] &&
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954) ?
execFpuSimple_rVal1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4108 ;
assign IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2655 =
((execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31] ||
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2653) ?
x__h4067 :
x__h4081 ;
assign IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2705 =
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) ?
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 &&
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677 :
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 &&
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2292 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[2] :
_theResult___fst_exp__h135555 == 11'd2047 &&
_theResult___fst_sfd__h135556 == 52'd0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2483 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[1] :
_theResult___fst_exp__h134774 == 11'd0 &&
guard__h126784 != 2'b0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2520 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[0] :
_theResult___fst_exp__h134774 != 11'd2047 &&
guard__h126784 != 2'b0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752 =
((SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q15[10],
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q15 }) -
12'd3074 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d931 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
((_theResult___fst_exp__h125943 == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d921) :
((_theResult___fst_exp__h134774 == 11'd2047) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d929) ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648 =
((SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96[7],
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96 }) -
9'd386 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3849 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
((_theResult___fst_exp__h42379 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3839) :
((_theResult___fst_exp__h51094 == 8'd255) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3847) ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4713 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[2] :
_theResult___fst_exp__h51672 == 8'd255 &&
_theResult___fst_sfd__h51673 == 23'd0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4812 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[1] :
_theResult___fst_exp__h51094 == 8'd0 && guard__h43017 != 2'b0 ;
assign IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4852 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[0] :
_theResult___fst_exp__h51094 != 8'd255 &&
guard__h43017 != 2'b0 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1162 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard43842_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1161 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1169 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard44572_0b0_execFpuSimple_rVal1_BIT_31_ETC__q56 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1168 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1587 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard64466_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1586 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d1594 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard65196_0b0_execFpuSimple_rVal1_BIT_63_ETC__q58 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1593 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d164 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
int_val__h94497[1:0] == 2'b11 ||
int_val__h94497[1:0] == 2'b10 && int_val__h94497[2] :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q7 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d2781 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
int_val__h5744[1:0] == 2'b11 ||
int_val__h5744[1:0] == 2'b10 && int_val__h5744[2] :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q86 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3821 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard6427_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3820 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3829 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard5164_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3828 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3839 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4153_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3838 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d3847 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3017_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3846 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4099 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard6904_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4098 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4106 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard7431_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4105 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4260 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3586_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4259 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d4267 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4113_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4266 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d913 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard08409_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d912 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d921 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard17717_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d920 ;
assign IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d929 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard26784_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d928 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2470 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2507 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4798 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4715 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4838 =
(execFpuSimple_fpu_inst[8:4] == 5'd10) ?
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4814 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601 =
(execFpuSimple_fpu_inst[8:4] == 5'd15) ?
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 !=
11'd2047 ||
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 ==
52'd0) &&
execFpuSimple_rVal1[31:0] != 32'd0 &&
IF_NOT_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_r_ETC___d1172 :
execFpuSimple_fpu_inst[8:4] == 5'd17 &&
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d1599 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274 =
(execFpuSimple_fpu_inst[8:4] == 5'd15) ?
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 !=
8'd255 ||
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 ==
23'd0) &&
execFpuSimple_rVal1[31:0] != 32'd0 &&
IF_NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_N_ETC___d4109 :
execFpuSimple_fpu_inst[8:4] == 5'd17 &&
NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d4272 ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2186 =
(execFpuSimple_fpu_inst[8:4] == 5'd8 ||
execFpuSimple_fpu_inst[8:4] == 5'd9 ||
execFpuSimple_fpu_inst[8:4] == 5'd22 ||
execFpuSimple_fpu_inst[8:4] == 5'd23 ||
execFpuSimple_fpu_inst[8:4] == 5'd24 ||
execFpuSimple_fpu_inst[8:4] == 5'd11 ||
execFpuSimple_fpu_inst[8:4] == 5'd12 ||
execFpuSimple_fpu_inst[8:4] == 5'd13 ||
execFpuSimple_fpu_inst[8:4] == 5'd14) ?
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 :
{ execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607,
_theResult___fst_exp__h176790,
_theResult___fst_sfd__h176791 } ;
assign IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4603 =
(execFpuSimple_fpu_inst[8:4] == 5'd8 ||
execFpuSimple_fpu_inst[8:4] == 5'd9 ||
execFpuSimple_fpu_inst[8:4] == 5'd19 ||
execFpuSimple_fpu_inst[8:4] == 5'd20 ||
execFpuSimple_fpu_inst[8:4] == 5'd21 ||
execFpuSimple_fpu_inst[8:4] == 5'd22 ||
execFpuSimple_fpu_inst[8:4] == 5'd23 ||
execFpuSimple_fpu_inst[8:4] == 5'd24 ||
execFpuSimple_fpu_inst[8:4] == 5'd11 ||
execFpuSimple_fpu_inst[8:4] == 5'd12 ||
execFpuSimple_fpu_inst[8:4] == 5'd13 ||
execFpuSimple_fpu_inst[8:4] == 5'd14) ?
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 :
{ 32'hFFFFFFFF, x__h8190 } ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 &&
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[4] :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 &&
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[4] ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 &&
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[3] :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 &&
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235[3] ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2294 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ||
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[2] :
!SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ||
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2292 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2485 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 &&
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ||
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[1]) :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 &&
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2483 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ||
!_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 &&
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218[0] :
!SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ||
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d2520 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 =
((execFpuSimple_rVal1[30:23] == 8'd0) ?
(execFpuSimple_rVal1[22] ?
6'd2 :
(execFpuSimple_rVal1[21] ?
6'd3 :
(execFpuSimple_rVal1[20] ?
6'd4 :
(execFpuSimple_rVal1[19] ?
6'd5 :
(execFpuSimple_rVal1[18] ?
6'd6 :
(execFpuSimple_rVal1[17] ?
6'd7 :
(execFpuSimple_rVal1[16] ?
6'd8 :
(execFpuSimple_rVal1[15] ?
6'd9 :
(execFpuSimple_rVal1[14] ?
6'd10 :
(execFpuSimple_rVal1[13] ?
6'd11 :
(execFpuSimple_rVal1[12] ?
6'd12 :
(execFpuSimple_rVal1[11] ?
6'd13 :
(execFpuSimple_rVal1[10] ?
6'd14 :
(execFpuSimple_rVal1[9] ?
6'd15 :
(execFpuSimple_rVal1[8] ?
6'd16 :
(execFpuSimple_rVal1[7] ?
6'd17 :
(execFpuSimple_rVal1[6] ?
6'd18 :
(execFpuSimple_rVal1[5] ?
6'd19 :
(execFpuSimple_rVal1[4] ?
6'd20 :
(execFpuSimple_rVal1[3] ?
6'd21 :
(execFpuSimple_rVal1[2] ?
6'd22 :
(execFpuSimple_rVal1[1] ?
6'd23 :
(execFpuSimple_rVal1[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d933 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_execFpuSimple_rV_ETC___d914 :
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ?
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d931 :
execFpuSimple_rVal1[31]) ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d1621 =
((execFpuSimple_rVal1[30:23] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h135567) ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 !=
52'd0 ||
execFpuSimple_rVal1[30:23] == 8'd255 ;
assign IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 =
(execFpuSimple_rVal1[30:23] == 8'd255 &&
execFpuSimple_rVal1[22:0] != 23'd0) ?
_theResult___snd_fst_sfd__h97466 :
_theResult___fst_sfd__h135571 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 =
(execFpuSimple_rVal1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h145323 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016) ?
52'd0 :
_theResult___snd_fst_sfd__h145318 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 =
(execFpuSimple_rVal1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h154712 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 ||
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671) ?
52'd0 :
_theResult___snd_fst_sfd__h154707 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!value__h136414[31] &&
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915) ?
8'd0 :
_theResult___snd_fst_exp__h57979 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 =
execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052 ?
23'd0 :
_theResult___snd_fst_sfd__h57974 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!execFpuSimple_rVal1[31] &&
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878) ?
8'd0 :
_theResult___snd_fst_exp__h63832 ;
assign IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 =
(execFpuSimple_rVal1[31:0] == 32'd0 ||
!execFpuSimple_rVal1[31] &&
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 ||
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331) ?
23'd0 :
_theResult___snd_fst_sfd__h63827 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 =
((execFpuSimple_rVal1[62:52] == 11'd0) ?
(execFpuSimple_rVal1[51] ?
6'd2 :
(execFpuSimple_rVal1[50] ?
6'd3 :
(execFpuSimple_rVal1[49] ?
6'd4 :
(execFpuSimple_rVal1[48] ?
6'd5 :
(execFpuSimple_rVal1[47] ?
6'd6 :
(execFpuSimple_rVal1[46] ?
6'd7 :
(execFpuSimple_rVal1[45] ?
6'd8 :
(execFpuSimple_rVal1[44] ?
6'd9 :
(execFpuSimple_rVal1[43] ?
6'd10 :
(execFpuSimple_rVal1[42] ?
6'd11 :
(execFpuSimple_rVal1[41] ?
6'd12 :
(execFpuSimple_rVal1[40] ?
6'd13 :
(execFpuSimple_rVal1[39] ?
6'd14 :
(execFpuSimple_rVal1[38] ?
6'd15 :
(execFpuSimple_rVal1[37] ?
6'd16 :
(execFpuSimple_rVal1[36] ?
6'd17 :
(execFpuSimple_rVal1[35] ?
6'd18 :
(execFpuSimple_rVal1[34] ?
6'd19 :
(execFpuSimple_rVal1[33] ?
6'd20 :
(execFpuSimple_rVal1[32] ?
6'd21 :
(execFpuSimple_rVal1[31] ?
6'd22 :
(execFpuSimple_rVal1[30] ?
6'd23 :
(execFpuSimple_rVal1[29] ?
6'd24 :
(execFpuSimple_rVal1[28] ?
6'd25 :
(execFpuSimple_rVal1[27] ?
6'd26 :
(execFpuSimple_rVal1[26] ?
6'd27 :
(execFpuSimple_rVal1[25] ?
6'd28 :
(execFpuSimple_rVal1[24] ?
6'd29 :
(execFpuSimple_rVal1[23] ?
6'd30 :
(execFpuSimple_rVal1[22] ?
6'd31 :
(execFpuSimple_rVal1[21] ?
6'd32 :
(execFpuSimple_rVal1[20] ?
6'd33 :
(execFpuSimple_rVal1[19] ?
6'd34 :
(execFpuSimple_rVal1[18] ?
6'd35 :
(execFpuSimple_rVal1[17] ?
6'd36 :
(execFpuSimple_rVal1[16] ?
6'd37 :
(execFpuSimple_rVal1[15] ?
6'd38 :
(execFpuSimple_rVal1[14] ?
6'd39 :
(execFpuSimple_rVal1[13] ?
6'd40 :
(execFpuSimple_rVal1[12] ?
6'd41 :
(execFpuSimple_rVal1[11] ?
6'd42 :
(execFpuSimple_rVal1[10] ?
6'd43 :
(execFpuSimple_rVal1[9] ?
6'd44 :
(execFpuSimple_rVal1[8] ?
6'd45 :
(execFpuSimple_rVal1[7] ?
6'd46 :
(execFpuSimple_rVal1[6] ?
6'd47 :
(execFpuSimple_rVal1[5] ?
6'd48 :
(execFpuSimple_rVal1[4] ?
6'd49 :
(execFpuSimple_rVal1[3] ?
6'd50 :
(execFpuSimple_rVal1[2] ?
6'd51 :
(execFpuSimple_rVal1[1] ?
6'd52 :
(execFpuSimple_rVal1[0] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3851 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ?
IF_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1__ETC___d3831 :
execFpuSimple_rVal1[63]) :
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ?
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3849 :
execFpuSimple_rVal1[63]) ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4641 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 &&
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[4] ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4698 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4694 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 &&
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655[3] ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4715 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4707 :
!SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ||
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4713 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4814 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4808 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 &&
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4812 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4848 :
!SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ||
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d4852 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
_theResult___snd_fst_sfd__h8740 :
_theResult___fst_sfd__h51688 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d4286 =
((execFpuSimple_rVal1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h51684) ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 !=
23'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d67 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
execFpuSimple_rVal2 :
(execFpuSimple_rVal1_BIT_63_4_AND_NOT_execFpuSi_ETC___d65 ?
execFpuSimple_rVal1 :
execFpuSimple_rVal2) ;
assign IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d78 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
execFpuSimple_rVal2 :
(NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_execFpu_ETC___d76 ?
execFpuSimple_rVal1 :
execFpuSimple_rVal2) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal1[30:0] :
31'h7FC00000 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2642 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
(execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) ||
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2640) ?
x__h4067 :
x__h4081 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 =
in1_exp__h4123 < in2_exp__h4198 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 =
in1_exp__h4123 == in2_exp__h4198 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677 =
in1_sfd__h4124 < in2_sfd__h4199 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 =
in1_exp__h4123 <= in2_exp__h4198 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682 =
in1_sfd__h4124 <= in2_sfd__h4199 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2686 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682) &&
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2690 =
in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0 &&
in2_exp__h4198 == 8'd0 &&
in2_sfd__h4199 == 23'd0 ||
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31] ||
execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31]) &&
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2688 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804 =
in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0 ||
int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
!in1_sfd__h4124[22] ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0 &&
!in2_sfd__h4199[22] ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 == 8'd255 && in2_sfd__h4199 != 23'd0 ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748[86:32] != 55'd0 ||
!IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748[86:64] != 23'd0 ||
!IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815) ;
assign IF_execFpuSimple_rVal1_BITS_63_TO_32_EQ_0xFFFF_ETC__q2 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 == 8'd255 &&
in1_sfd__h4124 == 23'd0) ?
10'd1 :
10'd0 ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666 =
execFpuSimple_rVal1[31] ?
6'd0 :
(execFpuSimple_rVal1[30] ?
6'd1 :
(execFpuSimple_rVal1[29] ?
6'd2 :
(execFpuSimple_rVal1[28] ?
6'd3 :
(execFpuSimple_rVal1[27] ?
6'd4 :
(execFpuSimple_rVal1[26] ?
6'd5 :
(execFpuSimple_rVal1[25] ?
6'd6 :
(execFpuSimple_rVal1[24] ?
6'd7 :
(execFpuSimple_rVal1[23] ?
6'd8 :
(execFpuSimple_rVal1[22] ?
6'd9 :
(execFpuSimple_rVal1[21] ?
6'd10 :
(execFpuSimple_rVal1[20] ?
6'd11 :
(execFpuSimple_rVal1[19] ?
6'd12 :
(execFpuSimple_rVal1[18] ?
6'd13 :
(execFpuSimple_rVal1[17] ?
6'd14 :
(execFpuSimple_rVal1[16] ?
6'd15 :
(execFpuSimple_rVal1[15] ?
6'd16 :
(execFpuSimple_rVal1[14] ?
6'd17 :
(execFpuSimple_rVal1[13] ?
6'd18 :
(execFpuSimple_rVal1[12] ?
6'd19 :
(execFpuSimple_rVal1[11] ?
6'd20 :
(execFpuSimple_rVal1[10] ?
6'd21 :
(execFpuSimple_rVal1[9] ?
6'd22 :
(execFpuSimple_rVal1[8] ?
6'd23 :
(execFpuSimple_rVal1[7] ?
6'd24 :
(execFpuSimple_rVal1[6] ?
6'd25 :
(execFpuSimple_rVal1[5] ?
6'd26 :
(execFpuSimple_rVal1[4] ?
6'd27 :
(execFpuSimple_rVal1[3] ?
6'd28 :
(execFpuSimple_rVal1[2] ?
6'd29 :
(execFpuSimple_rVal1[1] ?
6'd30 :
(execFpuSimple_rVal1[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326 =
execFpuSimple_rVal1[31] ?
6'd0 :
(execFpuSimple_rVal1[30] ?
6'd1 :
(execFpuSimple_rVal1[29] ?
6'd2 :
(execFpuSimple_rVal1[28] ?
6'd3 :
(execFpuSimple_rVal1[27] ?
6'd4 :
(execFpuSimple_rVal1[26] ?
6'd5 :
(execFpuSimple_rVal1[25] ?
6'd6 :
(execFpuSimple_rVal1[24] ?
6'd7 :
(execFpuSimple_rVal1[23] ?
6'd8 :
(execFpuSimple_rVal1[22] ?
6'd9 :
(execFpuSimple_rVal1[21] ?
6'd10 :
(execFpuSimple_rVal1[20] ?
6'd11 :
(execFpuSimple_rVal1[19] ?
6'd12 :
(execFpuSimple_rVal1[18] ?
6'd13 :
(execFpuSimple_rVal1[17] ?
6'd14 :
(execFpuSimple_rVal1[16] ?
6'd15 :
(execFpuSimple_rVal1[15] ?
6'd16 :
(execFpuSimple_rVal1[14] ?
6'd17 :
(execFpuSimple_rVal1[13] ?
6'd18 :
(execFpuSimple_rVal1[12] ?
6'd19 :
(execFpuSimple_rVal1[11] ?
6'd20 :
(execFpuSimple_rVal1[10] ?
6'd21 :
(execFpuSimple_rVal1[9] ?
6'd22 :
(execFpuSimple_rVal1[8] ?
6'd23 :
(execFpuSimple_rVal1[7] ?
6'd24 :
(execFpuSimple_rVal1[6] ?
6'd25 :
(execFpuSimple_rVal1[5] ?
6'd26 :
(execFpuSimple_rVal1[4] ?
6'd27 :
(execFpuSimple_rVal1[3] ?
6'd28 :
(execFpuSimple_rVal1[2] ?
6'd29 :
(execFpuSimple_rVal1[1] ?
6'd30 :
(execFpuSimple_rVal1[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748 =
value__h136414[30] || value__h136414[29] || value__h136414[28] ||
value__h136414[27] ||
value__h136414[26] ||
value__h136414[25] ||
value__h136414[24] ||
value__h136414[23] ||
value__h136414[22] ||
value__h136414[21] ||
value__h136414[20] ||
value__h136414[19] ||
value__h136414[18] ||
value__h136414[17] ||
value__h136414[16] ||
value__h136414[15] ||
value__h136414[14] ||
value__h136414[13] ||
value__h136414[12] ||
value__h136414[11] ||
value__h136414[10] ||
value__h136414[9] ||
value__h136414[8] ||
value__h136414[7] ||
value__h136414[6] ||
value__h136414[5] ||
value__h136414[4] ||
value__h136414[3] ||
value__h136414[2] ||
value__h136414[1] ||
value__h136414[0] ;
assign IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886 =
(value__h136414[31] ||
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748) &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 &&
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4883 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 =
execFpuSimple_rVal1[63] ?
7'd0 :
(execFpuSimple_rVal1[62] ?
7'd1 :
(execFpuSimple_rVal1[61] ?
7'd2 :
(execFpuSimple_rVal1[60] ?
7'd3 :
(execFpuSimple_rVal1[59] ?
7'd4 :
(execFpuSimple_rVal1[58] ?
7'd5 :
(execFpuSimple_rVal1[57] ?
7'd6 :
(execFpuSimple_rVal1[56] ?
7'd7 :
(execFpuSimple_rVal1[55] ?
7'd8 :
(execFpuSimple_rVal1[54] ?
7'd9 :
(execFpuSimple_rVal1[53] ?
7'd10 :
(execFpuSimple_rVal1[52] ?
7'd11 :
(execFpuSimple_rVal1[51] ?
7'd12 :
(execFpuSimple_rVal1[50] ?
7'd13 :
(execFpuSimple_rVal1[49] ?
7'd14 :
(execFpuSimple_rVal1[48] ?
7'd15 :
(execFpuSimple_rVal1[47] ?
7'd16 :
(execFpuSimple_rVal1[46] ?
7'd17 :
(execFpuSimple_rVal1[45] ?
7'd18 :
(execFpuSimple_rVal1[44] ?
7'd19 :
(execFpuSimple_rVal1[43] ?
7'd20 :
(execFpuSimple_rVal1[42] ?
7'd21 :
(execFpuSimple_rVal1[41] ?
7'd22 :
(execFpuSimple_rVal1[40] ?
7'd23 :
(execFpuSimple_rVal1[39] ?
7'd24 :
(execFpuSimple_rVal1[38] ?
7'd25 :
(execFpuSimple_rVal1[37] ?
7'd26 :
(execFpuSimple_rVal1[36] ?
7'd27 :
(execFpuSimple_rVal1[35] ?
7'd28 :
(execFpuSimple_rVal1[34] ?
7'd29 :
(execFpuSimple_rVal1[33] ?
7'd30 :
(execFpuSimple_rVal1[32] ?
7'd31 :
(execFpuSimple_rVal1[31] ?
7'd32 :
(execFpuSimple_rVal1[30] ?
7'd33 :
(execFpuSimple_rVal1[29] ?
7'd34 :
(execFpuSimple_rVal1[28] ?
7'd35 :
(execFpuSimple_rVal1[27] ?
7'd36 :
(execFpuSimple_rVal1[26] ?
7'd37 :
(execFpuSimple_rVal1[25] ?
7'd38 :
(execFpuSimple_rVal1[24] ?
7'd39 :
(execFpuSimple_rVal1[23] ?
7'd40 :
(execFpuSimple_rVal1[22] ?
7'd41 :
(execFpuSimple_rVal1[21] ?
7'd42 :
(execFpuSimple_rVal1[20] ?
7'd43 :
(execFpuSimple_rVal1[19] ?
7'd44 :
(execFpuSimple_rVal1[18] ?
7'd45 :
(execFpuSimple_rVal1[17] ?
7'd46 :
(execFpuSimple_rVal1[16] ?
7'd47 :
(execFpuSimple_rVal1[15] ?
7'd48 :
(execFpuSimple_rVal1[14] ?
7'd49 :
(execFpuSimple_rVal1[13] ?
7'd50 :
(execFpuSimple_rVal1[12] ?
7'd51 :
(execFpuSimple_rVal1[11] ?
7'd52 :
(execFpuSimple_rVal1[10] ?
7'd53 :
(execFpuSimple_rVal1[9] ?
7'd54 :
(execFpuSimple_rVal1[8] ?
7'd55 :
(execFpuSimple_rVal1[7] ?
7'd56 :
(execFpuSimple_rVal1[6] ?
7'd57 :
(execFpuSimple_rVal1[5] ?
7'd58 :
(execFpuSimple_rVal1[4] ?
7'd59 :
(execFpuSimple_rVal1[3] ?
7'd60 :
(execFpuSimple_rVal1[2] ?
7'd61 :
(execFpuSimple_rVal1[1] ?
7'd62 :
(execFpuSimple_rVal1[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178 =
execFpuSimple_rVal1[63] ?
-execFpuSimple_rVal1 :
execFpuSimple_rVal1 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 &&
_theResult___fst_exp__h165938 == 11'd2047 &&
_theResult___fst_sfd__h165939 == 52'd0) ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 &&
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2567 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 &&
_theResult___fst_exp__h74652 == 8'd255 &&
_theResult___fst_sfd__h74653 == 23'd0) ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904 =
(IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] ||
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) &&
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 &&
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 &&
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4901 ;
assign IF_execFpuSimple_rVal1_BIT_63_4_THEN_NOT_execF_ETC___d2157 =
execFpuSimple_rVal1[63] ?
!execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 ||
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 &&
!execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129 :
execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 ||
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 &&
execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134 ;
assign IF_execFpuSimple_rVal1_BIT_63_AND_execFpuSimpl_ETC__q1 =
(execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
10'd1 :
10'd0 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 =
(execFpuSimple_rVal1 == 64'd0 ||
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) ?
11'd0 :
_theResult___snd_fst_exp__h165947 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536) ?
52'd0 :
_theResult___snd_fst_sfd__h165942 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 =
(execFpuSimple_rVal1 == 64'd0 ||
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0]) ?
8'd0 :
_theResult___snd_fst_exp__h74661 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212) ?
23'd0 :
_theResult___snd_fst_sfd__h74656 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 =
(execFpuSimple_rVal1 == 64'd0 ||
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
11'd0 :
_theResult___snd_fst_exp__h176651 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d2069) ?
52'd0 :
_theResult___snd_fst_sfd__h176646 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549 =
(execFpuSimple_rVal1 == 64'd0 ||
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
8'd0 :
_theResult___snd_fst_exp__h84959 ;
assign IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586 =
(execFpuSimple_rVal1 == 64'd0 ||
NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d4553) ?
23'd0 :
_theResult___snd_fst_sfd__h84954 ;
assign IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630 =
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal2[30:0] :
31'h7FC00000 ;
assign IF_sfd___32749_BIT_7_THEN_2_ELSE_0__q142 =
sfd___3__h62749[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___32749_BIT_8_THEN_2_ELSE_0__q141 =
sfd___3__h62749[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___343832_BIT_1_THEN_2_ELSE_0__q31 =
sfd___3__h143832[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___343832_BIT_2_THEN_2_ELSE_0__q30 =
sfd___3__h143832[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___353223_BIT_1_THEN_2_ELSE_0__q60 =
sfd___3__h153223[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___353223_BIT_2_THEN_2_ELSE_0__q59 =
sfd___3__h153223[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___364456_BIT_10_THEN_2_ELSE_0__q43 =
sfd___3__h164456[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___364456_BIT_11_THEN_2_ELSE_0__q42 =
sfd___3__h164456[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___364456_BIT_39_THEN_2_ELSE_0__q41 =
sfd___3__h164456[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___364456_BIT_40_THEN_2_ELSE_0__q40 =
sfd___3__h164456[40] ? 2'd2 : 2'd0 ;
assign IF_sfd___36894_BIT_7_THEN_2_ELSE_0__q116 =
sfd___3__h56894[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___36894_BIT_8_THEN_2_ELSE_0__q115 =
sfd___3__h56894[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___375162_BIT_10_THEN_2_ELSE_0__q73 =
sfd___3__h175162[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___375162_BIT_11_THEN_2_ELSE_0__q72 =
sfd___3__h175162[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___375162_BIT_39_THEN_2_ELSE_0__q71 =
sfd___3__h175162[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___375162_BIT_40_THEN_2_ELSE_0__q70 =
sfd___3__h175162[40] ? 2'd2 : 2'd0 ;
assign IF_sfdin2373_BIT_33_THEN_2_ELSE_0__q95 =
sfdin__h42373[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin25937_BIT_4_THEN_2_ELSE_0__q14 =
sfdin__h125937[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin4520_BIT_33_THEN_2_ELSE_0__q89 =
sfdin__h24520[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd1040_BIT_33_THEN_2_ELSE_0__q98 =
_theResult___snd__h51040[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd16321_BIT_4_THEN_2_ELSE_0__q10 =
_theResult___snd__h116321[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd3163_BIT_33_THEN_2_ELSE_0__q91 =
_theResult___snd__h33163[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd34720_BIT_4_THEN_2_ELSE_0__q17 =
_theResult___snd__h134720[4] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4707 =
!_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ||
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[2] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_ETC___d4848 =
!_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ||
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[0] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[0]) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935 =
(((execFpuSimple_rVal1[30:23] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h135567) !=
11'd2047 ||
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 ==
52'd0) &&
((execFpuSimple_rVal1[30:23] == 8'd255 &&
execFpuSimple_rVal1[22:0] != 23'd0 ||
(execFpuSimple_rVal1[30:23] == 8'd255 ||
execFpuSimple_rVal1[30:23] == 8'd0) &&
execFpuSimple_rVal1[22:0] == 23'd0) ?
execFpuSimple_rVal1[31] :
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d933) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853 =
(((execFpuSimple_rVal1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h51684) !=
8'd255 ||
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 ==
23'd0) &&
((execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
(execFpuSimple_rVal1[62:52] == 11'd2047 ||
execFpuSimple_rVal1[62:52] == 11'd0) &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
execFpuSimple_rVal1[63] :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3851) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2685 =
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2673 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2677) &&
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2681 &&
(!IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2675 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2682) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2708 =
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0 ||
in2_exp__h4198 != 8'd0 ||
in2_sfd__h4199 != 23'd0) &&
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2707 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670 =
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
int_val_rnd__h5748[86:32] != 55'd0) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4680 =
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
int_val_rnd__h5748[86:64] != 23'd0) ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
int_val_rnd__h5748[86:32] == 55'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 == 87'd0 ||
execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
int_val_rnd__h5748[86:32] == 55'd0 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
int_val_rnd__h5748[86:64] == 23'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 != 23'd0) &&
(int_val_rnd__h5748 == 87'd0 ||
execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
int_val_rnd__h5748[86:64] == 23'd0 &&
(in1_exp__h4123 != 8'd0 || in1_sfd__h4124 != 23'd0) &&
int_val__h5744[1:0] != 2'd0 ;
assign NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915 =
!value__h136414[30] && !value__h136414[29] &&
!value__h136414[28] &&
!value__h136414[27] &&
!value__h136414[26] &&
!value__h136414[25] &&
!value__h136414[24] &&
!value__h136414[23] &&
!value__h136414[22] &&
!value__h136414[21] &&
!value__h136414[20] &&
!value__h136414[19] &&
!value__h136414[18] &&
!value__h136414[17] &&
!value__h136414[16] &&
!value__h136414[15] &&
!value__h136414[14] &&
!value__h136414[13] &&
!value__h136414[12] &&
!value__h136414[11] &&
!value__h136414[10] &&
!value__h136414[9] &&
!value__h136414[8] &&
!value__h136414[7] &&
!value__h136414[6] &&
!value__h136414[5] &&
!value__h136414[4] &&
!value__h136414[3] &&
!value__h136414[2] &&
!value__h136414[1] &&
!value__h136414[0] ;
assign NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536 =
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0] ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 ||
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 ;
assign NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212 =
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[63] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[62] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[61] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[60] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[59] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[58] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[57] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[56] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[55] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[54] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[53] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[52] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[51] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[50] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[49] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[48] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[47] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[46] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[45] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[44] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[43] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[42] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[41] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[40] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[39] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[38] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[37] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[36] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[35] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[34] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[33] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[32] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[31] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[30] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[29] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[28] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[27] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[26] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[25] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[24] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[23] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[22] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[21] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[20] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[19] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[18] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[17] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[16] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[15] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[14] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[13] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[12] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[11] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[10] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[9] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[8] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[7] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[6] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[5] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[4] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[3] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[2] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[1] &&
!IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178[0] ||
!_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 ||
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 ;
assign NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d1599 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 !=
11'd2047 ||
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 ==
52'd0) &&
execFpuSimple_rVal1 != 64'd0 &&
(NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d1536 ?
execFpuSimple_rVal1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d1596) ;
assign NOT_IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF__ETC___d4272 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 !=
8'd255 ||
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 ==
23'd0) &&
execFpuSimple_rVal1 != 64'd0 &&
(NOT_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_e_ETC___d4212 ?
execFpuSimple_rVal1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d4269) ;
assign NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(value__h136414[31] ||
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748) &&
(!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 &&
_theResult___fst_exp__h57970 == 8'd255 &&
_theResult___fst_sfd__h57971 == 23'd0) ;
assign NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418) &&
(!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 &&
_theResult___fst_exp__h63823 == 8'd255 &&
_theResult___fst_sfd__h63824 == 23'd0) ;
assign NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(value__h136414[31] ||
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4748) &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9_ETC___d2160 =
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] != 11'd0 ||
execFpuSimple_rVal2[51:0] != 52'd0) &&
(execFpuSimple_rVal1[63] && !execFpuSimple_rVal2[63] ||
(execFpuSimple_rVal1[63] || !execFpuSimple_rVal2[63]) &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NOT_execF_ETC___d2157) ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val_rnd__h94501[115:32] == 84'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94497[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94501 == 116'd0 || !execFpuSimple_rVal1[63]) &&
int_val_rnd__h94501[115:32] == 84'd0 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94497[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val_rnd__h94501[115:64] == 52'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94497[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94501 == 116'd0 || !execFpuSimple_rVal1[63]) &&
int_val_rnd__h94501[115:64] == 52'd0 &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
int_val__h94497[1:0] != 2'd0 ;
assign NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_ex_ETC___d2139 =
!execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
!execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134) &&
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129) ;
assign NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 =
!execFpuSimple_rVal1[21] && !execFpuSimple_rVal1[20] &&
!execFpuSimple_rVal1[19] &&
!execFpuSimple_rVal1[18] &&
!execFpuSimple_rVal1[17] &&
!execFpuSimple_rVal1[16] &&
!execFpuSimple_rVal1[15] &&
!execFpuSimple_rVal1[14] &&
!execFpuSimple_rVal1[13] &&
!execFpuSimple_rVal1[12] &&
!execFpuSimple_rVal1[11] &&
!execFpuSimple_rVal1[10] &&
!execFpuSimple_rVal1[9] &&
!execFpuSimple_rVal1[8] &&
!execFpuSimple_rVal1[7] &&
!execFpuSimple_rVal1[6] &&
!execFpuSimple_rVal1[5] &&
!execFpuSimple_rVal1[4] &&
!execFpuSimple_rVal1[3] &&
!execFpuSimple_rVal1[2] &&
!execFpuSimple_rVal1[1] &&
!execFpuSimple_rVal1[0] ;
assign NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878 =
!execFpuSimple_rVal1[30] && !execFpuSimple_rVal1[29] &&
!execFpuSimple_rVal1[28] &&
!execFpuSimple_rVal1[27] &&
!execFpuSimple_rVal1[26] &&
!execFpuSimple_rVal1[25] &&
!execFpuSimple_rVal1[24] &&
!execFpuSimple_rVal1[23] &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 ;
assign NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 =
!execFpuSimple_rVal1[51] && !execFpuSimple_rVal1[50] &&
!execFpuSimple_rVal1[49] &&
!execFpuSimple_rVal1[48] &&
!execFpuSimple_rVal1[47] &&
!execFpuSimple_rVal1[46] &&
!execFpuSimple_rVal1[45] &&
!execFpuSimple_rVal1[44] &&
!execFpuSimple_rVal1[43] &&
!execFpuSimple_rVal1[42] &&
!execFpuSimple_rVal1[41] &&
!execFpuSimple_rVal1[40] &&
!execFpuSimple_rVal1[39] &&
!execFpuSimple_rVal1[38] &&
!execFpuSimple_rVal1[37] &&
!execFpuSimple_rVal1[36] &&
!execFpuSimple_rVal1[35] &&
!execFpuSimple_rVal1[34] &&
!execFpuSimple_rVal1[33] &&
!execFpuSimple_rVal1[32] &&
!execFpuSimple_rVal1[31] &&
NOT_execFpuSimple_rVal1_BIT_30_627_863_AND_NOT_ETC___d1878 ;
assign NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d2069 =
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 ||
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 ;
assign NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_NOT_exe_ETC___d4553 =
!execFpuSimple_rVal1[63] && !execFpuSimple_rVal1[62] &&
!execFpuSimple_rVal1[61] &&
!execFpuSimple_rVal1[60] &&
!execFpuSimple_rVal1[59] &&
!execFpuSimple_rVal1[58] &&
!execFpuSimple_rVal1[57] &&
!execFpuSimple_rVal1[56] &&
!execFpuSimple_rVal1[55] &&
!execFpuSimple_rVal1[54] &&
!execFpuSimple_rVal1[53] &&
!execFpuSimple_rVal1[52] &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 ||
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 ;
assign NOT_execFpuSimple_rVal1_BIT_63_4_0_AND_execFpu_ETC___d76 =
!execFpuSimple_rVal1[63] && execFpuSimple_rVal2[63] ||
execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58 &&
!(execFpuSimple_rVal1[63] ^
execFpuSimple_rVal1[62:0] <= execFpuSimple_rVal2[62:0]) ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 =
{ {4{execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q11[7]}},
execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q11 } ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 =
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 ^
12'h800) <=
12'd3071 ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 =
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 ^
12'h800) <
12'd1026 ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 +
12'd1023 ;
assign SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q15 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12[10:0] -
11'd1023 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 =
{ execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92[10],
execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92 } ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 =
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 ^
12'h800) <=
12'd2175 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 =
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 ^
12'h800) <
12'd1922 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 +
12'd127 ;
assign SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q96 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626 =
{ 3'd0,
_theResult___fst_exp__h24526 == 8'd0 &&
(sfdin__h24520[56:34] == 23'd0 || guard__h16427 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h25153 == 8'd255 &&
_theResult___fst_sfd__h25154 == 23'd0,
1'd0,
_theResult___fst_exp__h24526 != 8'd255 &&
guard__h16427 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d2235 =
{ 3'd0,
_theResult___fst_exp__h125943 == 11'd0 &&
(sfdin__h125937[56:5] == 52'd0 || guard__h117717 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h126773 == 11'd2047 &&
_theResult___fst_sfd__h126774 == 52'd0,
1'd0,
_theResult___fst_exp__h125943 != 11'd2047 &&
guard__h117717 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d4655 =
{ 3'd0,
_theResult___fst_exp__h42379 == 8'd0 &&
(sfdin__h42373[56:34] == 23'd0 || guard__h34153 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h43006 == 8'd255 &&
_theResult___fst_sfd__h43007 == 23'd0,
1'd0,
_theResult___fst_exp__h42379 != 8'd255 &&
guard__h34153 != 2'b0 } ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d2218 =
{ 3'd0,
_theResult___fst_exp__h116370 == 11'd0 &&
guard__h108409 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h117126 == 11'd2047 &&
_theResult___fst_sfd__h117127 == 52'd0,
1'd0,
_theResult___fst_exp__h116370 != 11'd2047 &&
guard__h108409 != 2'b0 } ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351 =
({ 6'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753 =
({ 6'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ^
12'h800) <=
(IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752 ^
12'h800) ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257 =
({ 3'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649 =
({ 3'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ^
9'h100) <=
(IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648 ^
9'h100) ;
assign _0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638 =
{ 3'd0,
_theResult___fst_exp__h33212 == 8'd0 && guard__h25164 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h33765 == 8'd255 &&
_theResult___fst_sfd__h33766 == 23'd0,
1'd0,
_theResult___fst_exp__h33212 != 8'd255 &&
guard__h25164 != 2'b0 } ;
assign _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436 =
sfd__h97512 >>
_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 ;
assign _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334 =
sfd__h8786 >>
_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 ;
assign _1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115 =
17'd1075 - { 6'd0, execFpuSimple_rVal1[62:52] } ;
assign _150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746 =
13'd150 - { 5'd0, in1_exp__h4123 } ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898 =
12'd3074 -
{ 6'd0,
execFpuSimple_rVal1[51] ?
6'd0 :
(execFpuSimple_rVal1[50] ?
6'd1 :
(execFpuSimple_rVal1[49] ?
6'd2 :
(execFpuSimple_rVal1[48] ?
6'd3 :
(execFpuSimple_rVal1[47] ?
6'd4 :
(execFpuSimple_rVal1[46] ?
6'd5 :
(execFpuSimple_rVal1[45] ?
6'd6 :
(execFpuSimple_rVal1[44] ?
6'd7 :
(execFpuSimple_rVal1[43] ?
6'd8 :
(execFpuSimple_rVal1[42] ?
6'd9 :
(execFpuSimple_rVal1[41] ?
6'd10 :
(execFpuSimple_rVal1[40] ?
6'd11 :
(execFpuSimple_rVal1[39] ?
6'd12 :
(execFpuSimple_rVal1[38] ?
6'd13 :
(execFpuSimple_rVal1[37] ?
6'd14 :
(execFpuSimple_rVal1[36] ?
6'd15 :
(execFpuSimple_rVal1[35] ?
6'd16 :
(execFpuSimple_rVal1[34] ?
6'd17 :
(execFpuSimple_rVal1[33] ?
6'd18 :
(execFpuSimple_rVal1[32] ?
6'd19 :
(execFpuSimple_rVal1[31] ?
6'd20 :
(execFpuSimple_rVal1[30] ?
6'd21 :
(execFpuSimple_rVal1[29] ?
6'd22 :
(execFpuSimple_rVal1[28] ?
6'd23 :
(execFpuSimple_rVal1[27] ?
6'd24 :
(execFpuSimple_rVal1[26] ?
6'd25 :
(execFpuSimple_rVal1[25] ?
6'd26 :
(execFpuSimple_rVal1[24] ?
6'd27 :
(execFpuSimple_rVal1[23] ?
6'd28 :
(execFpuSimple_rVal1[22] ?
6'd29 :
(execFpuSimple_rVal1[21] ?
6'd30 :
(execFpuSimple_rVal1[20] ?
6'd31 :
(execFpuSimple_rVal1[19] ?
6'd32 :
(execFpuSimple_rVal1[18] ?
6'd33 :
(execFpuSimple_rVal1[17] ?
6'd34 :
(execFpuSimple_rVal1[16] ?
6'd35 :
(execFpuSimple_rVal1[15] ?
6'd36 :
(execFpuSimple_rVal1[14] ?
6'd37 :
(execFpuSimple_rVal1[13] ?
6'd38 :
(execFpuSimple_rVal1[12] ?
6'd39 :
(execFpuSimple_rVal1[11] ?
6'd40 :
(execFpuSimple_rVal1[10] ?
6'd41 :
(execFpuSimple_rVal1[9] ?
6'd42 :
(execFpuSimple_rVal1[8] ?
6'd43 :
(execFpuSimple_rVal1[7] ?
6'd44 :
(execFpuSimple_rVal1[6] ?
6'd45 :
(execFpuSimple_rVal1[5] ?
6'd46 :
(execFpuSimple_rVal1[4] ?
6'd47 :
(execFpuSimple_rVal1[3] ?
6'd48 :
(execFpuSimple_rVal1[2] ?
6'd49 :
(execFpuSimple_rVal1[1] ?
6'd50 :
(execFpuSimple_rVal1[0] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 =
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 =
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2898 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4641 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 &&
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[4] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[4]) ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4694 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 &&
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[3] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[3]) ;
assign _3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d4808 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 &&
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d4626[1] :
_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d4638[1]) ;
assign _3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 =
12'd3074 -
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d429 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 =
(12'd32 -
{ 6'd0,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 =
(9'd32 -
{ 3'd0,
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 =
(_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 =
(12'd32 -
{ 6'd0,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 =
(9'd32 -
{ 3'd0,
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 =
(_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 ^
9'h100) <
9'd130 ;
assign _3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276 =
12'd3970 -
{ 7'd0,
execFpuSimple_rVal1[22] ?
5'd0 :
(execFpuSimple_rVal1[21] ?
5'd1 :
(execFpuSimple_rVal1[20] ?
5'd2 :
(execFpuSimple_rVal1[19] ?
5'd3 :
(execFpuSimple_rVal1[18] ?
5'd4 :
(execFpuSimple_rVal1[17] ?
5'd5 :
(execFpuSimple_rVal1[16] ?
5'd6 :
(execFpuSimple_rVal1[15] ?
5'd7 :
(execFpuSimple_rVal1[14] ?
5'd8 :
(execFpuSimple_rVal1[13] ?
5'd9 :
(execFpuSimple_rVal1[12] ?
5'd10 :
(execFpuSimple_rVal1[11] ?
5'd11 :
(execFpuSimple_rVal1[10] ?
5'd12 :
(execFpuSimple_rVal1[9] ?
5'd13 :
(execFpuSimple_rVal1[8] ?
5'd14 :
(execFpuSimple_rVal1[7] ?
5'd15 :
(execFpuSimple_rVal1[6] ?
5'd16 :
(execFpuSimple_rVal1[5] ?
5'd17 :
(execFpuSimple_rVal1[4] ?
5'd18 :
(execFpuSimple_rVal1[3] ?
5'd19 :
(execFpuSimple_rVal1[2] ?
5'd20 :
(execFpuSimple_rVal1[1] ?
5'd21 :
(execFpuSimple_rVal1[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 =
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 =
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d276 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 =
12'd3970 -
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3327 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 =
(12'd64 -
{ 5'd0,
IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 =
(9'd64 -
{ 2'd0,
IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 =
(_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 ^
9'h100) <
9'd130 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 =
(12'd64 -
{ 5'd0,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 =
(9'd64 -
{ 2'd0,
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 =
(_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 ^
9'h100) <
9'd130 ;
assign _theResult_____1_fst__h6973 =
(int_val_rnd__h5748[86:32] == 55'd0) ?
out__h6989 :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult_____1_fst__h8160 =
(int_val_rnd__h5748[86:64] == 23'd0) ?
int_val_rnd__h5748[63:0] :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult_____1_fst__h95645 =
(int_val_rnd__h94501[115:32] == 84'd0) ?
out__h95661 :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult_____1_fst__h96888 =
(int_val_rnd__h94501[115:64] == 52'd0) ?
int_val_rnd__h94501[63:0] :
64'hFFFFFFFFFFFFFFFF ;
assign _theResult____h117707 =
((_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 ^
12'h800) <
12'd2105) ?
result__h118320 :
((value__h101927 == 25'd0) ? sfd__h97512 : 57'd1) ;
assign _theResult____h16417 =
(value__h17039 == 54'd0) ? sfd__h8786 : 57'd1 ;
assign _theResult____h34143 =
((_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 ^
12'h800) <
12'd2105) ?
result__h34756 :
_theResult____h16417 ;
assign _theResult___exp__h117025 =
sfd__h116388[53] ?
((_theResult___fst_exp__h116370 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h135590) :
((_theResult___fst_exp__h116370 == 11'd0 &&
sfd__h116388[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h116370) ;
assign _theResult___exp__h126672 =
sfd__h126035[53] ?
((_theResult___fst_exp__h125943 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h135620) :
((_theResult___fst_exp__h125943 == 11'd0 &&
sfd__h126035[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h125943) ;
assign _theResult___exp__h135454 =
sfd__h134793[53] ?
((_theResult___fst_exp__h134774 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h135644) :
((_theResult___fst_exp__h134774 == 11'd0 &&
sfd__h134793[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h134774) ;
assign _theResult___exp__h144458 =
(sfd__h143859[53] || sfd__h143859[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h145214 =
sfd__h144602[53] ?
((x__h144587[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h145356) :
((x__h144587[10:0] == 11'd0 && sfd__h144602[53:52] == 2'b01) ?
11'd1 :
x__h144587[10:0]) ;
assign _theResult___exp__h153849 =
(sfd__h153250[53] || sfd__h153250[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h154604 =
sfd__h153992[53] ?
((x__h153977[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h154742) :
((x__h153977[10:0] == 11'd0 && sfd__h153992[53:52] == 2'b01) ?
11'd1 :
x__h153977[10:0]) ;
assign _theResult___exp__h165082 =
(sfd__h164483[53] || sfd__h164483[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h165838 =
sfd__h165226[53] ?
((x__h165211[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h165980) :
((x__h165211[10:0] == 11'd0 && sfd__h165226[53:52] == 2'b01) ?
11'd1 :
x__h165211[10:0]) ;
assign _theResult___exp__h175788 =
(sfd__h175189[53] || sfd__h175189[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h176543 =
sfd__h175931[53] ?
((x__h175916[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h176681) :
((x__h175916[10:0] == 11'd0 && sfd__h175931[53:52] == 2'b01) ?
11'd1 :
x__h175916[10:0]) ;
assign _theResult___exp__h25052 =
sfd__h24618[24] ?
((_theResult___fst_exp__h24526 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51703) :
((_theResult___fst_exp__h24526 == 8'd0 &&
sfd__h24618[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h24526) ;
assign _theResult___exp__h33664 =
sfd__h33230[24] ?
((_theResult___fst_exp__h33212 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51727) :
((_theResult___fst_exp__h33212 == 8'd0 &&
sfd__h33230[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h33212) ;
assign _theResult___exp__h42905 =
sfd__h42471[24] ?
((_theResult___fst_exp__h42379 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51757) :
((_theResult___fst_exp__h42379 == 8'd0 &&
sfd__h42471[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h42379) ;
assign _theResult___exp__h51571 =
sfd__h51113[24] ?
((_theResult___fst_exp__h51094 == 8'd254) ?
8'd255 :
din_inc___2_exp__h51781) :
((_theResult___fst_exp__h51094 == 8'd0 &&
sfd__h51113[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h51094) ;
assign _theResult___exp__h57317 =
(sfd__h56921[24] || sfd__h56921[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h57870 =
sfd__h57461[24] ?
((x__h57446[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h58012) :
((x__h57446[7:0] == 8'd0 && sfd__h57461[24:23] == 2'b01) ?
8'd1 :
x__h57446[7:0]) ;
assign _theResult___exp__h63172 =
(sfd__h62776[24] || sfd__h62776[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h63724 =
sfd__h63315[24] ?
((x__h63300[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h63862) :
((x__h63300[7:0] == 8'd0 && sfd__h63315[24:23] == 2'b01) ?
8'd1 :
x__h63300[7:0]) ;
assign _theResult___exp__h73999 =
(sfd__h73603[24] || sfd__h73603[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h74552 =
sfd__h74143[24] ?
((x__h74128[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h74694) :
((x__h74128[7:0] == 8'd0 && sfd__h74143[24:23] == 2'b01) ?
8'd1 :
x__h74128[7:0]) ;
assign _theResult___exp__h84299 =
(sfd__h83903[24] || sfd__h83903[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h84851 =
sfd__h84442[24] ?
((x__h84427[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h84989) :
((x__h84427[7:0] == 8'd0 && sfd__h84442[24:23] == 2'b01) ?
8'd1 :
x__h84427[7:0]) ;
assign _theResult___fst__h5722 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h5724 :
_theResult___fst__h5738 ;
assign _theResult___fst__h5738 =
(in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0) ?
64'd0 :
_theResult___fst__h5753 ;
assign _theResult___fst__h5753 =
(int_val_rnd__h5748[86:32] == 55'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2792) ?
out__h6395 :
out__h6400 ;
assign _theResult___fst__h6455 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h6457 :
_theResult___fst__h6470 ;
assign _theResult___fst__h6470 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804 ?
64'd0 :
_theResult_____1_fst__h6973 ;
assign _theResult___fst__h7052 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h7054 :
_theResult___fst__h7068 ;
assign _theResult___fst__h7068 =
(in1_exp__h4123 == 8'd0 && in1_sfd__h4124 == 23'd0) ?
64'd0 :
_theResult___fst__h7083 ;
assign _theResult___fst__h7083 =
(int_val_rnd__h5748[86:64] == 23'd0 &&
IF_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_B_ETC___d2815) ?
out__h7587 :
max_val__h7094 ;
assign _theResult___fst__h7642 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0) ?
out__h6457 :
_theResult___fst__h7657 ;
assign _theResult___fst__h7657 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2804 ?
64'd0 :
_theResult_____1_fst__h8160 ;
assign _theResult___fst__h94475 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h94477 :
_theResult___fst__h94491 ;
assign _theResult___fst__h94491 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
64'd0 :
_theResult___fst__h94506 ;
assign _theResult___fst__h94506 =
(int_val_rnd__h94501[115:32] == 84'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175) ?
out__h95039 :
out__h95044 ;
assign _theResult___fst__h95099 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h95101 :
_theResult___fst__h95114 ;
assign _theResult___fst__h95114 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
64'd0 :
_theResult_____1_fst__h95645 ;
assign _theResult___fst__h95724 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h95726 :
_theResult___fst__h95740 ;
assign _theResult___fst__h95740 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
64'd0 :
_theResult___fst__h95755 ;
assign _theResult___fst__h95755 =
(int_val_rnd__h94501[115:64] == 52'd0 &&
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198) ?
out__h96287 :
max_val__h95766 ;
assign _theResult___fst__h96342 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
out__h95101 :
_theResult___fst__h96357 ;
assign _theResult___fst__h96357 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
64'd0 :
_theResult_____1_fst__h96888 ;
assign _theResult___fst_exp__h101297 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3) ?
11'd2047 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_2046_ETC__q5 ;
assign _theResult___fst_exp__h116361 =
11'd897 -
{ 5'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ;
assign _theResult___fst_exp__h116367 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d351) ?
11'd0 :
_theResult___fst_exp__h116361 ;
assign _theResult___fst_exp__h116370 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___fst_exp__h116367 :
11'd897 ;
assign _theResult___fst_exp__h117123 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q19 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413 ;
assign _theResult___fst_exp__h117126 =
(_theResult___fst_exp__h116370 == 11'd2047) ?
_theResult___fst_exp__h116370 :
_theResult___fst_exp__h117123 ;
assign _theResult___fst_exp__h125943 =
_theResult____h117707[56] ?
11'd2 :
_theResult___fst_exp__h126017 ;
assign _theResult___fst_exp__h126008 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 } ;
assign _theResult___fst_exp__h126014 =
(!_theResult____h117707[56] && !_theResult____h117707[55] &&
!_theResult____h117707[54] &&
!_theResult____h117707[53] &&
!_theResult____h117707[52] &&
!_theResult____h117707[51] &&
!_theResult____h117707[50] &&
!_theResult____h117707[49] &&
!_theResult____h117707[48] &&
!_theResult____h117707[47] &&
!_theResult____h117707[46] &&
!_theResult____h117707[45] &&
!_theResult____h117707[44] &&
!_theResult____h117707[43] &&
!_theResult____h117707[42] &&
!_theResult____h117707[41] &&
!_theResult____h117707[40] &&
!_theResult____h117707[39] &&
!_theResult____h117707[38] &&
!_theResult____h117707[37] &&
!_theResult____h117707[36] &&
!_theResult____h117707[35] &&
!_theResult____h117707[34] &&
!_theResult____h117707[33] &&
!_theResult____h117707[32] &&
!_theResult____h117707[31] &&
!_theResult____h117707[30] &&
!_theResult____h117707[29] &&
!_theResult____h117707[28] &&
!_theResult____h117707[27] &&
!_theResult____h117707[26] &&
!_theResult____h117707[25] &&
!_theResult____h117707[24] &&
!_theResult____h117707[23] &&
!_theResult____h117707[22] &&
!_theResult____h117707[21] &&
!_theResult____h117707[20] &&
!_theResult____h117707[19] &&
!_theResult____h117707[18] &&
!_theResult____h117707[17] &&
!_theResult____h117707[16] &&
!_theResult____h117707[15] &&
!_theResult____h117707[14] &&
!_theResult____h117707[13] &&
!_theResult____h117707[12] &&
!_theResult____h117707[11] &&
!_theResult____h117707[10] &&
!_theResult____h117707[9] &&
!_theResult____h117707[8] &&
!_theResult____h117707[7] &&
!_theResult____h117707[6] &&
!_theResult____h117707[5] &&
!_theResult____h117707[4] &&
!_theResult____h117707[3] &&
!_theResult____h117707[2] &&
!_theResult____h117707[1] &&
!_theResult____h117707[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimple_r_ETC___d680) ?
11'd0 :
_theResult___fst_exp__h126008 ;
assign _theResult___fst_exp__h126017 =
(!_theResult____h117707[56] && _theResult____h117707[55]) ?
11'd1 :
_theResult___fst_exp__h126014 ;
assign _theResult___fst_exp__h126770 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q21 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743 ;
assign _theResult___fst_exp__h126773 =
(_theResult___fst_exp__h125943 == 11'd2047) ?
_theResult___fst_exp__h125943 :
_theResult___fst_exp__h126770 ;
assign _theResult___fst_exp__h134726 =
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12[10:0] ==
11'd0) ?
11'd1 :
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12[10:0] ;
assign _theResult___fst_exp__h134765 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC__q12[10:0] -
{ 5'd0,
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 } ;
assign _theResult___fst_exp__h134771 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO_23__ETC___d753) ?
11'd0 :
_theResult___fst_exp__h134765 ;
assign _theResult___fst_exp__h134774 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___fst_exp__h134771 :
_theResult___fst_exp__h134726 ;
assign _theResult___fst_exp__h135552 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q23 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812 ;
assign _theResult___fst_exp__h135555 =
(_theResult___fst_exp__h134774 == 11'd2047) ?
_theResult___fst_exp__h134774 :
_theResult___fst_exp__h135552 ;
assign _theResult___fst_exp__h135564 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ?
_theResult___snd_fst_exp__h117129 :
_theResult___fst_exp__h101297) :
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ?
_theResult___snd_fst_exp__h135558 :
_theResult___fst_exp__h101297) ;
assign _theResult___fst_exp__h135567 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
execFpuSimple_rVal1[22:0] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h135564 ;
assign _theResult___fst_exp__h135811 =
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d1621 ?
11'd2047 :
_theResult___fst_exp__h135567 ;
assign _theResult___fst_exp__h144555 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard43842_0b0_0_0b1_0_0b10_out_exp44461__ETC__q33 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1056 ;
assign _theResult___fst_exp__h145311 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_x4_ETC__q35 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103 ;
assign _theResult___fst_exp__h145314 =
(x__h144587[10:0] == 11'd2047) ?
x__h144587[10:0] :
_theResult___fst_exp__h145311 ;
assign _theResult___fst_exp__h145457 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 ;
assign _theResult___fst_exp__h153945 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard53233_0b0_0_0b1_0_0b10_out_exp53852__ETC__q61 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q63 ;
assign _theResult___fst_exp__h154700 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_x5_ETC__q65 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1751 ;
assign _theResult___fst_exp__h154703 =
(x__h153977[10:0] == 11'd2047) ?
x__h153977[10:0] :
_theResult___fst_exp__h154700 ;
assign _theResult___fst_exp__h154834 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 ;
assign _theResult___fst_exp__h16399 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3) ?
8'd255 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_254__ETC__q3 ;
assign _theResult___fst_exp__h165179 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard64466_0b0_0_0b1_0_0b10_out_exp65085__ETC__q45 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1478 ;
assign _theResult___fst_exp__h165935 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_x6_ETC__q47 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525 ;
assign _theResult___fst_exp__h165938 =
(x__h165211[10:0] == 11'd2047) ?
x__h165211[10:0] :
_theResult___fst_exp__h165935 ;
assign _theResult___fst_exp__h166081 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 ;
assign _theResult___fst_exp__h175884 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard75172_0b0_0_0b1_0_0b10_out_exp75791__ETC__q77 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q79 ;
assign _theResult___fst_exp__h176639 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_x7_ETC__q81 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2059 ;
assign _theResult___fst_exp__h176642 =
(x__h175916[10:0] == 11'd2047) ?
x__h175916[10:0] :
_theResult___fst_exp__h176639 ;
assign _theResult___fst_exp__h176773 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 !=
52'd0) ?
11'd2047 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 ;
assign _theResult___fst_exp__h24526 =
_theResult____h16417[56] ? 8'd2 : _theResult___fst_exp__h24600 ;
assign _theResult___fst_exp__h24591 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 } ;
assign _theResult___fst_exp__h24597 =
(!_theResult____h16417[56] && !_theResult____h16417[55] &&
!_theResult____h16417[54] &&
!_theResult____h16417[53] &&
!_theResult____h16417[52] &&
!_theResult____h16417[51] &&
!_theResult____h16417[50] &&
!_theResult____h16417[49] &&
!_theResult____h16417[48] &&
!_theResult____h16417[47] &&
!_theResult____h16417[46] &&
!_theResult____h16417[45] &&
!_theResult____h16417[44] &&
!_theResult____h16417[43] &&
!_theResult____h16417[42] &&
!_theResult____h16417[41] &&
!_theResult____h16417[40] &&
!_theResult____h16417[39] &&
!_theResult____h16417[38] &&
!_theResult____h16417[37] &&
!_theResult____h16417[36] &&
!_theResult____h16417[35] &&
!_theResult____h16417[34] &&
!_theResult____h16417[33] &&
!_theResult____h16417[32] &&
!_theResult____h16417[31] &&
!_theResult____h16417[30] &&
!_theResult____h16417[29] &&
!_theResult____h16417[28] &&
!_theResult____h16417[27] &&
!_theResult____h16417[26] &&
!_theResult____h16417[25] &&
!_theResult____h16417[24] &&
!_theResult____h16417[23] &&
!_theResult____h16417[22] &&
!_theResult____h16417[21] &&
!_theResult____h16417[20] &&
!_theResult____h16417[19] &&
!_theResult____h16417[18] &&
!_theResult____h16417[17] &&
!_theResult____h16417[16] &&
!_theResult____h16417[15] &&
!_theResult____h16417[14] &&
!_theResult____h16417[13] &&
!_theResult____h16417[12] &&
!_theResult____h16417[11] &&
!_theResult____h16417[10] &&
!_theResult____h16417[9] &&
!_theResult____h16417[8] &&
!_theResult____h16417[7] &&
!_theResult____h16417[6] &&
!_theResult____h16417[5] &&
!_theResult____h16417[4] &&
!_theResult____h16417[3] &&
!_theResult____h16417[2] &&
!_theResult____h16417[1] &&
!_theResult____h16417[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rV_ETC___d3135) ?
8'd0 :
_theResult___fst_exp__h24591 ;
assign _theResult___fst_exp__h24600 =
(!_theResult____h16417[56] && _theResult____h16417[55]) ?
8'd1 :
_theResult___fst_exp__h24597 ;
assign _theResult___fst_exp__h25150 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q100 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198 ;
assign _theResult___fst_exp__h25153 =
(_theResult___fst_exp__h24526 == 8'd255) ?
_theResult___fst_exp__h24526 :
_theResult___fst_exp__h25150 ;
assign _theResult___fst_exp__h33203 =
8'd129 -
{ 2'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ;
assign _theResult___fst_exp__h33209 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3257) ?
8'd0 :
_theResult___fst_exp__h33203 ;
assign _theResult___fst_exp__h33212 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___fst_exp__h33209 :
8'd129 ;
assign _theResult___fst_exp__h33762 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q102 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315 ;
assign _theResult___fst_exp__h33765 =
(_theResult___fst_exp__h33212 == 8'd255) ?
_theResult___fst_exp__h33212 :
_theResult___fst_exp__h33762 ;
assign _theResult___fst_exp__h42379 =
_theResult____h34143[56] ? 8'd2 : _theResult___fst_exp__h42453 ;
assign _theResult___fst_exp__h42444 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 } ;
assign _theResult___fst_exp__h42450 =
(!_theResult____h34143[56] && !_theResult____h34143[55] &&
!_theResult____h34143[54] &&
!_theResult____h34143[53] &&
!_theResult____h34143[52] &&
!_theResult____h34143[51] &&
!_theResult____h34143[50] &&
!_theResult____h34143[49] &&
!_theResult____h34143[48] &&
!_theResult____h34143[47] &&
!_theResult____h34143[46] &&
!_theResult____h34143[45] &&
!_theResult____h34143[44] &&
!_theResult____h34143[43] &&
!_theResult____h34143[42] &&
!_theResult____h34143[41] &&
!_theResult____h34143[40] &&
!_theResult____h34143[39] &&
!_theResult____h34143[38] &&
!_theResult____h34143[37] &&
!_theResult____h34143[36] &&
!_theResult____h34143[35] &&
!_theResult____h34143[34] &&
!_theResult____h34143[33] &&
!_theResult____h34143[32] &&
!_theResult____h34143[31] &&
!_theResult____h34143[30] &&
!_theResult____h34143[29] &&
!_theResult____h34143[28] &&
!_theResult____h34143[27] &&
!_theResult____h34143[26] &&
!_theResult____h34143[25] &&
!_theResult____h34143[24] &&
!_theResult____h34143[23] &&
!_theResult____h34143[22] &&
!_theResult____h34143[21] &&
!_theResult____h34143[20] &&
!_theResult____h34143[19] &&
!_theResult____h34143[18] &&
!_theResult____h34143[17] &&
!_theResult____h34143[16] &&
!_theResult____h34143[15] &&
!_theResult____h34143[14] &&
!_theResult____h34143[13] &&
!_theResult____h34143[12] &&
!_theResult____h34143[11] &&
!_theResult____h34143[10] &&
!_theResult____h34143[9] &&
!_theResult____h34143[8] &&
!_theResult____h34143[7] &&
!_theResult____h34143[6] &&
!_theResult____h34143[5] &&
!_theResult____h34143[4] &&
!_theResult____h34143[3] &&
!_theResult____h34143[2] &&
!_theResult____h34143[1] &&
!_theResult____h34143[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimple_r_ETC___d3576) ?
8'd0 :
_theResult___fst_exp__h42444 ;
assign _theResult___fst_exp__h42453 =
(!_theResult____h34143[56] && _theResult____h34143[55]) ?
8'd1 :
_theResult___fst_exp__h42450 ;
assign _theResult___fst_exp__h43003 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 ;
assign _theResult___fst_exp__h43006 =
(_theResult___fst_exp__h42379 == 8'd255) ?
_theResult___fst_exp__h42379 :
_theResult___fst_exp__h43003 ;
assign _theResult___fst_exp__h51046 =
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] ==
8'd0) ?
8'd1 :
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] ;
assign _theResult___fst_exp__h51085 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC__q93[7:0] -
{ 2'd0,
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 } ;
assign _theResult___fst_exp__h51091 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899 ||
!_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO_52__ETC___d3649) ?
8'd0 :
_theResult___fst_exp__h51085 ;
assign _theResult___fst_exp__h51094 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___fst_exp__h51091 :
_theResult___fst_exp__h51046 ;
assign _theResult___fst_exp__h51669 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 ;
assign _theResult___fst_exp__h51672 =
(_theResult___fst_exp__h51094 == 8'd255) ?
_theResult___fst_exp__h51094 :
_theResult___fst_exp__h51669 ;
assign _theResult___fst_exp__h51681 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ?
_theResult___snd_fst_exp__h33768 :
_theResult___fst_exp__h16399) :
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ?
_theResult___snd_fst_exp__h51675 :
_theResult___fst_exp__h16399) ;
assign _theResult___fst_exp__h51684 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h51681 ;
assign _theResult___fst_exp__h51970 =
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d4286 ?
8'd255 :
_theResult___fst_exp__h51684 ;
assign _theResult___fst_exp__h57414 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard6904_0b0_0_0b1_0_0b10_out_exp7320_0b_ETC__q118 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3993 ;
assign _theResult___fst_exp__h57967 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_x7446_ETC__q120 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040 ;
assign _theResult___fst_exp__h57970 =
(x__h57446[7:0] == 8'd255) ?
x__h57446[7:0] :
_theResult___fst_exp__h57967 ;
assign _theResult___fst_exp__h63268 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard2759_0b0_0_0b1_0_0b10_out_exp3175_0b_ETC__q143 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q145 ;
assign _theResult___fst_exp__h63820 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_x3300_ETC__q147 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4409 ;
assign _theResult___fst_exp__h63823 =
(x__h63300[7:0] == 8'd255) ?
x__h63300[7:0] :
_theResult___fst_exp__h63820 ;
assign _theResult___fst_exp__h74096 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3586_0b0_0_0b1_0_0b10_out_exp4002_0b_ETC__q128 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4154 ;
assign _theResult___fst_exp__h74649 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_x4128_ETC__q130 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201 ;
assign _theResult___fst_exp__h74652 =
(x__h74128[7:0] == 8'd255) ?
x__h74128[7:0] :
_theResult___fst_exp__h74649 ;
assign _theResult___fst_exp__h84395 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3886_0b0_0_0b1_0_0b10_out_exp4302_0b_ETC__q74 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q76 ;
assign _theResult___fst_exp__h84947 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_x4427_ETC__q153 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4543 ;
assign _theResult___fst_exp__h84950 =
(x__h84427[7:0] == 8'd255) ?
x__h84427[7:0] :
_theResult___fst_exp__h84947 ;
assign _theResult___fst_sfd__h101298 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3) ?
52'd0 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_4503_ETC__q6 ;
assign _theResult___fst_sfd__h117124 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q25 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844 ;
assign _theResult___fst_sfd__h117127 =
(_theResult___fst_exp__h116370 == 11'd2047) ?
_theResult___snd__h116321[56:5] :
_theResult___fst_sfd__h117124 ;
assign _theResult___fst_sfd__h126771 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q27 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871 ;
assign _theResult___fst_sfd__h126774 =
(_theResult___fst_exp__h125943 == 11'd2047) ?
sfdin__h125937[56:5] :
_theResult___fst_sfd__h126771 ;
assign _theResult___fst_sfd__h135553 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q29 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890 ;
assign _theResult___fst_sfd__h135556 =
(_theResult___fst_exp__h134774 == 11'd2047) ?
_theResult___snd__h134720[56:5] :
_theResult___fst_sfd__h135553 ;
assign _theResult___fst_sfd__h135565 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d277 ?
_theResult___snd_fst_sfd__h117130 :
_theResult___fst_sfd__h101298) :
(SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d430 ?
_theResult___snd_fst_sfd__h135559 :
_theResult___fst_sfd__h101298) ;
assign _theResult___fst_sfd__h135571 =
((execFpuSimple_rVal1[30:23] == 8'd255 ||
execFpuSimple_rVal1[30:23] == 8'd0) &&
execFpuSimple_rVal1[22:0] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h135565 ;
assign _theResult___fst_sfd__h135812 =
(((execFpuSimple_rVal1[30:23] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h135567) ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_255_ETC___d897 ;
assign _theResult___fst_sfd__h144556 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q37 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130 ;
assign _theResult___fst_sfd__h145312 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q39 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148 ;
assign _theResult___fst_sfd__h145315 =
(x__h144587[10:0] == 11'd2047) ?
sfd___3__h143832[53:2] :
_theResult___fst_sfd__h145312 ;
assign _theResult___fst_sfd__h145458 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1109 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1152 ;
assign _theResult___fst_sfd__h153946 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q67 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1774 ;
assign _theResult___fst_sfd__h154701 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q69 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1789 ;
assign _theResult___fst_sfd__h154704 =
(x__h153977[10:0] == 11'd2047) ?
sfd___3__h153223[53:2] :
_theResult___fst_sfd__h154701 ;
assign _theResult___fst_sfd__h154835 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1757 ==
11'd2047 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d1793 ;
assign _theResult___fst_sfd__h16400 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3) ?
23'd0 :
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_8388_ETC__q4 ;
assign _theResult___fst_sfd__h165180 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q49 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553 ;
assign _theResult___fst_sfd__h165936 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q51 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571 ;
assign _theResult___fst_sfd__h165939 =
(x__h165211[10:0] == 11'd2047) ?
sfd___3__h164456[62:11] :
_theResult___fst_sfd__h165936 ;
assign _theResult___fst_sfd__h166082 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1531 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d1575 ;
assign _theResult___fst_sfd__h175885 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q83 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2083 ;
assign _theResult___fst_sfd__h176640 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q85 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2098 ;
assign _theResult___fst_sfd__h176643 =
(x__h175916[10:0] == 11'd2047) ?
sfd___3__h175162[62:11] :
_theResult___fst_sfd__h176640 ;
assign _theResult___fst_sfd__h176774 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2065 ==
11'd2047 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 !=
52'd0) ?
52'h8000000000000 :
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d2102 ;
assign _theResult___fst_sfd__h25151 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q108 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739 ;
assign _theResult___fst_sfd__h25154 =
(_theResult___fst_exp__h24526 == 8'd255) ?
sfdin__h24520[56:34] :
_theResult___fst_sfd__h25151 ;
assign _theResult___fst_sfd__h33763 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q110 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758 ;
assign _theResult___fst_sfd__h33766 =
(_theResult___fst_exp__h33212 == 8'd255) ?
_theResult___snd__h33163[56:34] :
_theResult___fst_sfd__h33763 ;
assign _theResult___fst_sfd__h43004 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q112 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785 ;
assign _theResult___fst_sfd__h43007 =
(_theResult___fst_exp__h42379 == 8'd255) ?
sfdin__h42373[56:34] :
_theResult___fst_sfd__h43004 ;
assign _theResult___fst_sfd__h51670 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q114 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804 ;
assign _theResult___fst_sfd__h51673 =
(_theResult___fst_exp__h51094 == 8'd255) ?
_theResult___snd__h51040[56:34] :
_theResult___fst_sfd__h51670 ;
assign _theResult___fst_sfd__h51682 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2899 ?
_theResult___snd_fst_sfd__h33769 :
_theResult___fst_sfd__h16400) :
(SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3328 ?
_theResult___snd_fst_sfd__h51676 :
_theResult___fst_sfd__h16400) ;
assign _theResult___fst_sfd__h51688 =
((execFpuSimple_rVal1[62:52] == 11'd2047 ||
execFpuSimple_rVal1[62:52] == 11'd0) &&
execFpuSimple_rVal1[51:0] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h51682 ;
assign _theResult___fst_sfd__h51971 =
(((execFpuSimple_rVal1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h51684) ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 !=
23'd0) ?
23'd4194304 :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d3811 ;
assign _theResult___fst_sfd__h57415 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q122 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068 ;
assign _theResult___fst_sfd__h57968 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q124 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086 ;
assign _theResult___fst_sfd__h57971 =
(x__h57446[7:0] == 8'd255) ?
sfd___3__h56894[30:8] :
_theResult___fst_sfd__h57968 ;
assign _theResult___fst_sfd__h63269 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q149 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4433 ;
assign _theResult___fst_sfd__h63821 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q151 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4448 ;
assign _theResult___fst_sfd__h63824 =
(x__h63300[7:0] == 8'd255) ?
sfd___3__h62749[30:8] :
_theResult___fst_sfd__h63821 ;
assign _theResult___fst_sfd__h74097 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q132 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229 ;
assign _theResult___fst_sfd__h74650 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q134 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247 ;
assign _theResult___fst_sfd__h74653 =
(x__h74128[7:0] == 8'd255) ?
sfd___3__h164456[62:40] :
_theResult___fst_sfd__h74650 ;
assign _theResult___fst_sfd__h84396 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q155 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4567 ;
assign _theResult___fst_sfd__h84948 =
(execFpuSimple_fpu_inst[3:1] != 3'd1 &&
execFpuSimple_fpu_inst[3:1] != 3'd2 &&
execFpuSimple_fpu_inst[3:1] != 3'd3 &&
execFpuSimple_fpu_inst[3:1] != 3'd4) ?
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q157 :
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4582 ;
assign _theResult___fst_sfd__h84951 =
(x__h84427[7:0] == 8'd255) ?
sfd___3__h175162[62:40] :
_theResult___fst_sfd__h84948 ;
assign _theResult___fst_sfd__h96998 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
52'd0 :
dst_sfd__h96995 ;
assign _theResult___fst_sfd__h97058 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
52'd0 :
dst_sfd__h97055 ;
assign _theResult___fst_sfd__h97118 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
52'd0 :
dst_sfd__h97115 ;
assign _theResult___sfd__h117026 =
sfd__h116388[53] ?
((_theResult___fst_exp__h116370 == 11'd2046) ?
52'd0 :
sfd__h116388[52:1]) :
sfd__h116388[51:0] ;
assign _theResult___sfd__h126673 =
sfd__h126035[53] ?
((_theResult___fst_exp__h125943 == 11'd2046) ?
52'd0 :
sfd__h126035[52:1]) :
sfd__h126035[51:0] ;
assign _theResult___sfd__h135455 =
sfd__h134793[53] ?
((_theResult___fst_exp__h134774 == 11'd2046) ?
52'd0 :
sfd__h134793[52:1]) :
sfd__h134793[51:0] ;
assign _theResult___sfd__h144459 =
sfd__h143859[53] ? sfd__h143859[52:1] : sfd__h143859[51:0] ;
assign _theResult___sfd__h145215 =
sfd__h144602[53] ?
((x__h144587[10:0] == 11'd2046) ? 52'd0 : sfd__h144602[52:1]) :
sfd__h144602[51:0] ;
assign _theResult___sfd__h153850 =
sfd__h153250[53] ? sfd__h153250[52:1] : sfd__h153250[51:0] ;
assign _theResult___sfd__h154605 =
sfd__h153992[53] ?
((x__h153977[10:0] == 11'd2046) ? 52'd0 : sfd__h153992[52:1]) :
sfd__h153992[51:0] ;
assign _theResult___sfd__h165083 =
sfd__h164483[53] ? sfd__h164483[52:1] : sfd__h164483[51:0] ;
assign _theResult___sfd__h165839 =
sfd__h165226[53] ?
((x__h165211[10:0] == 11'd2046) ? 52'd0 : sfd__h165226[52:1]) :
sfd__h165226[51:0] ;
assign _theResult___sfd__h175789 =
sfd__h175189[53] ? sfd__h175189[52:1] : sfd__h175189[51:0] ;
assign _theResult___sfd__h176544 =
sfd__h175931[53] ?
((x__h175916[10:0] == 11'd2046) ? 52'd0 : sfd__h175931[52:1]) :
sfd__h175931[51:0] ;
assign _theResult___sfd__h25053 =
sfd__h24618[24] ?
((_theResult___fst_exp__h24526 == 8'd254) ?
23'd0 :
sfd__h24618[23:1]) :
sfd__h24618[22:0] ;
assign _theResult___sfd__h33665 =
sfd__h33230[24] ?
((_theResult___fst_exp__h33212 == 8'd254) ?
23'd0 :
sfd__h33230[23:1]) :
sfd__h33230[22:0] ;
assign _theResult___sfd__h42906 =
sfd__h42471[24] ?
((_theResult___fst_exp__h42379 == 8'd254) ?
23'd0 :
sfd__h42471[23:1]) :
sfd__h42471[22:0] ;
assign _theResult___sfd__h51572 =
sfd__h51113[24] ?
((_theResult___fst_exp__h51094 == 8'd254) ?
23'd0 :
sfd__h51113[23:1]) :
sfd__h51113[22:0] ;
assign _theResult___sfd__h57318 =
sfd__h56921[24] ? sfd__h56921[23:1] : sfd__h56921[22:0] ;
assign _theResult___sfd__h57871 =
sfd__h57461[24] ?
((x__h57446[7:0] == 8'd254) ? 23'd0 : sfd__h57461[23:1]) :
sfd__h57461[22:0] ;
assign _theResult___sfd__h63173 =
sfd__h62776[24] ? sfd__h62776[23:1] : sfd__h62776[22:0] ;
assign _theResult___sfd__h63725 =
sfd__h63315[24] ?
((x__h63300[7:0] == 8'd254) ? 23'd0 : sfd__h63315[23:1]) :
sfd__h63315[22:0] ;
assign _theResult___sfd__h74000 =
sfd__h73603[24] ? sfd__h73603[23:1] : sfd__h73603[22:0] ;
assign _theResult___sfd__h74553 =
sfd__h74143[24] ?
((x__h74128[7:0] == 8'd254) ? 23'd0 : sfd__h74143[23:1]) :
sfd__h74143[22:0] ;
assign _theResult___sfd__h84300 =
sfd__h83903[24] ? sfd__h83903[23:1] : sfd__h83903[22:0] ;
assign _theResult___sfd__h84852 =
sfd__h84442[24] ?
((x__h84427[7:0] == 8'd254) ? 23'd0 : sfd__h84442[23:1]) :
sfd__h84442[22:0] ;
assign _theResult___snd__h116321 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___snd__h116330 :
_theResult___snd__h116323 ;
assign _theResult___snd__h116323 = { execFpuSimple_rVal1[22:0], 34'd0 } ;
assign _theResult___snd__h116330 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322) ?
sfd__h97512 :
_theResult___snd__h116336 ;
assign _theResult___snd__h116336 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q9[54:0],
2'd0 } ;
assign _theResult___snd__h116359 =
sfd__h97512 <<
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d349 ;
assign _theResult___snd__h125954 = { _theResult____h117707[55:0], 1'd0 } ;
assign _theResult___snd__h125965 =
(!_theResult____h117707[56] && _theResult____h117707[55]) ?
_theResult___snd__h125967 :
_theResult___snd__h125977 ;
assign _theResult___snd__h125967 = { _theResult____h117707[54:0], 2'd0 } ;
assign _theResult___snd__h125977 =
(!_theResult____h117707[56] && !_theResult____h117707[55] &&
!_theResult____h117707[54] &&
!_theResult____h117707[53] &&
!_theResult____h117707[52] &&
!_theResult____h117707[51] &&
!_theResult____h117707[50] &&
!_theResult____h117707[49] &&
!_theResult____h117707[48] &&
!_theResult____h117707[47] &&
!_theResult____h117707[46] &&
!_theResult____h117707[45] &&
!_theResult____h117707[44] &&
!_theResult____h117707[43] &&
!_theResult____h117707[42] &&
!_theResult____h117707[41] &&
!_theResult____h117707[40] &&
!_theResult____h117707[39] &&
!_theResult____h117707[38] &&
!_theResult____h117707[37] &&
!_theResult____h117707[36] &&
!_theResult____h117707[35] &&
!_theResult____h117707[34] &&
!_theResult____h117707[33] &&
!_theResult____h117707[32] &&
!_theResult____h117707[31] &&
!_theResult____h117707[30] &&
!_theResult____h117707[29] &&
!_theResult____h117707[28] &&
!_theResult____h117707[27] &&
!_theResult____h117707[26] &&
!_theResult____h117707[25] &&
!_theResult____h117707[24] &&
!_theResult____h117707[23] &&
!_theResult____h117707[22] &&
!_theResult____h117707[21] &&
!_theResult____h117707[20] &&
!_theResult____h117707[19] &&
!_theResult____h117707[18] &&
!_theResult____h117707[17] &&
!_theResult____h117707[16] &&
!_theResult____h117707[15] &&
!_theResult____h117707[14] &&
!_theResult____h117707[13] &&
!_theResult____h117707[12] &&
!_theResult____h117707[11] &&
!_theResult____h117707[10] &&
!_theResult____h117707[9] &&
!_theResult____h117707[8] &&
!_theResult____h117707[7] &&
!_theResult____h117707[6] &&
!_theResult____h117707[5] &&
!_theResult____h117707[4] &&
!_theResult____h117707[3] &&
!_theResult____h117707[2] &&
!_theResult____h117707[1] &&
!_theResult____h117707[0]) ?
_theResult____h117707 :
_theResult___snd__h125983 ;
assign _theResult___snd__h125983 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_execFpuSimpl_ETC__q13[54:0],
2'd0 } ;
assign _theResult___snd__h126006 =
_theResult____h117707 <<
IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d678 ;
assign _theResult___snd__h134720 =
(execFpuSimple_rVal1[30:23] == 8'd0) ?
_theResult___snd__h134734 :
_theResult___snd__h116323 ;
assign _theResult___snd__h134734 =
(execFpuSimple_rVal1[30:23] == 8'd0 &&
!execFpuSimple_rVal1[22] &&
NOT_execFpuSimple_rVal1_BIT_21_30_80_AND_NOT_e_ETC___d322) ?
sfd__h97512 :
_theResult___snd__h134740 ;
assign _theResult___snd__h134740 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_30_TO__ETC__q16[54:0],
2'd0 } ;
assign _theResult___snd__h134758 =
sfd__h97512 <<
IF_SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_M_ETC___d752 ;
assign _theResult___snd__h24537 = { _theResult____h16417[55:0], 1'd0 } ;
assign _theResult___snd__h24548 =
(!_theResult____h16417[56] && _theResult____h16417[55]) ?
_theResult___snd__h24550 :
_theResult___snd__h24560 ;
assign _theResult___snd__h24550 = { _theResult____h16417[54:0], 2'd0 } ;
assign _theResult___snd__h24560 =
(!_theResult____h16417[56] && !_theResult____h16417[55] &&
!_theResult____h16417[54] &&
!_theResult____h16417[53] &&
!_theResult____h16417[52] &&
!_theResult____h16417[51] &&
!_theResult____h16417[50] &&
!_theResult____h16417[49] &&
!_theResult____h16417[48] &&
!_theResult____h16417[47] &&
!_theResult____h16417[46] &&
!_theResult____h16417[45] &&
!_theResult____h16417[44] &&
!_theResult____h16417[43] &&
!_theResult____h16417[42] &&
!_theResult____h16417[41] &&
!_theResult____h16417[40] &&
!_theResult____h16417[39] &&
!_theResult____h16417[38] &&
!_theResult____h16417[37] &&
!_theResult____h16417[36] &&
!_theResult____h16417[35] &&
!_theResult____h16417[34] &&
!_theResult____h16417[33] &&
!_theResult____h16417[32] &&
!_theResult____h16417[31] &&
!_theResult____h16417[30] &&
!_theResult____h16417[29] &&
!_theResult____h16417[28] &&
!_theResult____h16417[27] &&
!_theResult____h16417[26] &&
!_theResult____h16417[25] &&
!_theResult____h16417[24] &&
!_theResult____h16417[23] &&
!_theResult____h16417[22] &&
!_theResult____h16417[21] &&
!_theResult____h16417[20] &&
!_theResult____h16417[19] &&
!_theResult____h16417[18] &&
!_theResult____h16417[17] &&
!_theResult____h16417[16] &&
!_theResult____h16417[15] &&
!_theResult____h16417[14] &&
!_theResult____h16417[13] &&
!_theResult____h16417[12] &&
!_theResult____h16417[11] &&
!_theResult____h16417[10] &&
!_theResult____h16417[9] &&
!_theResult____h16417[8] &&
!_theResult____h16417[7] &&
!_theResult____h16417[6] &&
!_theResult____h16417[5] &&
!_theResult____h16417[4] &&
!_theResult____h16417[3] &&
!_theResult____h16417[2] &&
!_theResult____h16417[1] &&
!_theResult____h16417[0]) ?
_theResult____h16417 :
_theResult___snd__h24566 ;
assign _theResult___snd__h24566 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_execFpuSimple_ETC__q88[54:0],
2'd0 } ;
assign _theResult___snd__h24589 =
_theResult____h16417 <<
IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS__ETC___d3133 ;
assign _theResult___snd__h33163 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___snd__h33172 :
_theResult___snd__h33165 ;
assign _theResult___snd__h33165 = { execFpuSimple_rVal1[51:0], 5'd0 } ;
assign _theResult___snd__h33172 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
sfd__h8786 :
_theResult___snd__h33178 ;
assign _theResult___snd__h33178 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q90[54:0],
2'd0 } ;
assign _theResult___snd__h33201 =
sfd__h8786 <<
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d3255 ;
assign _theResult___snd__h42390 = { _theResult____h34143[55:0], 1'd0 } ;
assign _theResult___snd__h42401 =
(!_theResult____h34143[56] && _theResult____h34143[55]) ?
_theResult___snd__h42403 :
_theResult___snd__h42413 ;
assign _theResult___snd__h42403 = { _theResult____h34143[54:0], 2'd0 } ;
assign _theResult___snd__h42413 =
(!_theResult____h34143[56] && !_theResult____h34143[55] &&
!_theResult____h34143[54] &&
!_theResult____h34143[53] &&
!_theResult____h34143[52] &&
!_theResult____h34143[51] &&
!_theResult____h34143[50] &&
!_theResult____h34143[49] &&
!_theResult____h34143[48] &&
!_theResult____h34143[47] &&
!_theResult____h34143[46] &&
!_theResult____h34143[45] &&
!_theResult____h34143[44] &&
!_theResult____h34143[43] &&
!_theResult____h34143[42] &&
!_theResult____h34143[41] &&
!_theResult____h34143[40] &&
!_theResult____h34143[39] &&
!_theResult____h34143[38] &&
!_theResult____h34143[37] &&
!_theResult____h34143[36] &&
!_theResult____h34143[35] &&
!_theResult____h34143[34] &&
!_theResult____h34143[33] &&
!_theResult____h34143[32] &&
!_theResult____h34143[31] &&
!_theResult____h34143[30] &&
!_theResult____h34143[29] &&
!_theResult____h34143[28] &&
!_theResult____h34143[27] &&
!_theResult____h34143[26] &&
!_theResult____h34143[25] &&
!_theResult____h34143[24] &&
!_theResult____h34143[23] &&
!_theResult____h34143[22] &&
!_theResult____h34143[21] &&
!_theResult____h34143[20] &&
!_theResult____h34143[19] &&
!_theResult____h34143[18] &&
!_theResult____h34143[17] &&
!_theResult____h34143[16] &&
!_theResult____h34143[15] &&
!_theResult____h34143[14] &&
!_theResult____h34143[13] &&
!_theResult____h34143[12] &&
!_theResult____h34143[11] &&
!_theResult____h34143[10] &&
!_theResult____h34143[9] &&
!_theResult____h34143[8] &&
!_theResult____h34143[7] &&
!_theResult____h34143[6] &&
!_theResult____h34143[5] &&
!_theResult____h34143[4] &&
!_theResult____h34143[3] &&
!_theResult____h34143[2] &&
!_theResult____h34143[1] &&
!_theResult____h34143[0]) ?
_theResult____h34143 :
_theResult___snd__h42419 ;
assign _theResult___snd__h42419 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_execFpuSimpl_ETC__q94[54:0],
2'd0 } ;
assign _theResult___snd__h42442 =
_theResult____h34143 <<
IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_ETC___d3574 ;
assign _theResult___snd__h51040 =
(execFpuSimple_rVal1[62:52] == 11'd0) ?
_theResult___snd__h51054 :
_theResult___snd__h33165 ;
assign _theResult___snd__h51054 =
(execFpuSimple_rVal1[62:52] == 11'd0 &&
NOT_execFpuSimple_rVal1_BIT_51_1_3_AND_NOT_exe_ETC___d1899) ?
sfd__h8786 :
_theResult___snd__h51060 ;
assign _theResult___snd__h51060 =
{ IF_0_CONCAT_IF_execFpuSimple_rVal1_BITS_62_TO__ETC__q97[54:0],
2'd0 } ;
assign _theResult___snd__h51078 =
sfd__h8786 <<
IF_SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MI_ETC___d3648 ;
assign _theResult___snd_fst_exp__h117129 =
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ?
11'd0 :
_theResult___fst_exp__h117126 ;
assign _theResult___snd_fst_exp__h135558 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_theResult___fst_exp__h126773 :
_theResult___fst_exp__h135555 ;
assign _theResult___snd_fst_exp__h145317 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
_theResult___fst_exp__h144555 :
_theResult___fst_exp__h145314 ;
assign _theResult___snd_fst_exp__h145320 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 ?
11'd0 :
_theResult___snd_fst_exp__h145317 ;
assign _theResult___snd_fst_exp__h145323 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ?
_theResult___snd_fst_exp__h145320 :
11'd2047 ;
assign _theResult___snd_fst_exp__h154706 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 ?
_theResult___fst_exp__h153945 :
_theResult___fst_exp__h154703 ;
assign _theResult___snd_fst_exp__h154709 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 ?
11'd0 :
_theResult___snd_fst_exp__h154706 ;
assign _theResult___snd_fst_exp__h154712 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 ?
_theResult___snd_fst_exp__h154709 :
11'd2047 ;
assign _theResult___snd_fst_exp__h165941 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
_theResult___fst_exp__h165179 :
_theResult___fst_exp__h165938 ;
assign _theResult___snd_fst_exp__h165944 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1439 ?
11'd0 :
_theResult___snd_fst_exp__h165941 ;
assign _theResult___snd_fst_exp__h165947 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1438 ?
_theResult___snd_fst_exp__h165944 :
11'd2047 ;
assign _theResult___snd_fst_exp__h176645 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 ?
_theResult___fst_exp__h175884 :
_theResult___fst_exp__h176642 ;
assign _theResult___snd_fst_exp__h176648 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 ?
11'd0 :
_theResult___snd_fst_exp__h176645 ;
assign _theResult___snd_fst_exp__h176651 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 ?
_theResult___snd_fst_exp__h176648 :
11'd2047 ;
assign _theResult___snd_fst_exp__h33768 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_theResult___fst_exp__h25153 :
_theResult___fst_exp__h33765 ;
assign _theResult___snd_fst_exp__h51675 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_theResult___fst_exp__h43006 :
_theResult___fst_exp__h51672 ;
assign _theResult___snd_fst_exp__h57973 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
_theResult___fst_exp__h57414 :
_theResult___fst_exp__h57970 ;
assign _theResult___snd_fst_exp__h57976 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 ?
8'd0 :
_theResult___snd_fst_exp__h57973 ;
assign _theResult___snd_fst_exp__h57979 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ?
_theResult___snd_fst_exp__h57976 :
8'd255 ;
assign _theResult___snd_fst_exp__h63826 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 ?
_theResult___fst_exp__h63268 :
_theResult___fst_exp__h63823 ;
assign _theResult___snd_fst_exp__h63829 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 ?
8'd0 :
_theResult___snd_fst_exp__h63826 ;
assign _theResult___snd_fst_exp__h63832 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 ?
_theResult___snd_fst_exp__h63829 :
8'd255 ;
assign _theResult___snd_fst_exp__h74655 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
_theResult___fst_exp__h74096 :
_theResult___fst_exp__h74652 ;
assign _theResult___snd_fst_exp__h74658 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4116 ?
8'd0 :
_theResult___snd_fst_exp__h74655 ;
assign _theResult___snd_fst_exp__h74661 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4115 ?
_theResult___snd_fst_exp__h74658 :
8'd255 ;
assign _theResult___snd_fst_exp__h84953 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 ?
_theResult___fst_exp__h84395 :
_theResult___fst_exp__h84950 ;
assign _theResult___snd_fst_exp__h84956 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 ?
8'd0 :
_theResult___snd_fst_exp__h84953 ;
assign _theResult___snd_fst_exp__h84959 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 ?
_theResult___snd_fst_exp__h84956 :
8'd255 ;
assign _theResult___snd_fst_sfd__h117130 =
_3970_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d278 ?
52'd0 :
_theResult___fst_sfd__h117127 ;
assign _theResult___snd_fst_sfd__h135559 =
SEXT_execFpuSimple_rVal1_BITS_30_TO_23_23_MINU_ETC___d431 ?
_theResult___fst_sfd__h126774 :
_theResult___fst_sfd__h135556 ;
assign _theResult___snd_fst_sfd__h145318 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 ?
_theResult___fst_sfd__h144556 :
_theResult___fst_sfd__h145315 ;
assign _theResult___snd_fst_sfd__h154707 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 ?
_theResult___fst_sfd__h153946 :
_theResult___fst_sfd__h154704 ;
assign _theResult___snd_fst_sfd__h165942 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1440 ?
_theResult___fst_sfd__h165180 :
_theResult___fst_sfd__h165939 ;
assign _theResult___snd_fst_sfd__h176646 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 ?
_theResult___fst_sfd__h175885 :
_theResult___fst_sfd__h176643 ;
assign _theResult___snd_fst_sfd__h33769 =
_3074_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_ETC___d2900 ?
_theResult___fst_sfd__h25154 :
_theResult___fst_sfd__h33766 ;
assign _theResult___snd_fst_sfd__h51676 =
SEXT_execFpuSimple_rVal1_BITS_62_TO_52_1_MINUS_ETC___d3329 ?
_theResult___fst_sfd__h43007 :
_theResult___fst_sfd__h51673 ;
assign _theResult___snd_fst_sfd__h57974 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3955 ?
_theResult___fst_sfd__h57415 :
_theResult___fst_sfd__h57971 ;
assign _theResult___snd_fst_sfd__h63827 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4332 ?
_theResult___fst_sfd__h63269 :
_theResult___fst_sfd__h63824 ;
assign _theResult___snd_fst_sfd__h74656 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4117 ?
_theResult___fst_sfd__h74097 :
_theResult___fst_sfd__h74653 ;
assign _theResult___snd_fst_sfd__h84954 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 ?
_theResult___fst_sfd__h84396 :
_theResult___fst_sfd__h84951 ;
assign _theResult___snd_fst_sfd__h8740 =
(execFpuSimple_rVal1[51:29] == 23'd0) ?
23'd2097152 :
execFpuSimple_rVal1[51:29] ;
assign _theResult___snd_fst_sfd__h97466 =
(execFpuSimple_rVal1[22:0] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h97215 ;
assign amt_abs__h5775 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
~_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746 +
13'd1 :
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746 ;
assign amt_abs__h96387 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
~_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115 +
17'd1 :
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115 ;
assign din_inc___2_exp__h135590 = _theResult___fst_exp__h116370 + 11'd1 ;
assign din_inc___2_exp__h135620 = _theResult___fst_exp__h125943 + 11'd1 ;
assign din_inc___2_exp__h135644 = _theResult___fst_exp__h134774 + 11'd1 ;
assign din_inc___2_exp__h145356 = x__h144587[10:0] + 11'd1 ;
assign din_inc___2_exp__h154742 = x__h153977[10:0] + 11'd1 ;
assign din_inc___2_exp__h165980 = x__h165211[10:0] + 11'd1 ;
assign din_inc___2_exp__h176681 = x__h175916[10:0] + 11'd1 ;
assign din_inc___2_exp__h51703 = _theResult___fst_exp__h24526 + 8'd1 ;
assign din_inc___2_exp__h51727 = _theResult___fst_exp__h33212 + 8'd1 ;
assign din_inc___2_exp__h51757 = _theResult___fst_exp__h42379 + 8'd1 ;
assign din_inc___2_exp__h51781 = _theResult___fst_exp__h51094 + 8'd1 ;
assign din_inc___2_exp__h58012 = x__h57446[7:0] + 8'd1 ;
assign din_inc___2_exp__h63862 = x__h63300[7:0] + 8'd1 ;
assign din_inc___2_exp__h74694 = x__h74128[7:0] + 8'd1 ;
assign din_inc___2_exp__h84989 = x__h84427[7:0] + 8'd1 ;
assign dst_bits__h251 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'h000000007FFFFFFF :
_theResult___fst__h5722 ;
assign dst_bits__h256 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h6455 ;
assign dst_bits__h261 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'h7FFFFFFFFFFFFFFF :
_theResult___fst__h7052 ;
assign dst_bits__h266 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h7642 ;
assign dst_bits__h85575 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'h000000007FFFFFFF :
_theResult___fst__h94475 ;
assign dst_bits__h85580 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h95099 ;
assign dst_bits__h85585 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'h7FFFFFFFFFFFFFFF :
_theResult___fst__h95724 ;
assign dst_bits__h85590 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
_theResult___fst__h96342 ;
assign dst_sfd__h96995 = { 51'd0, x__h176800 } ;
assign dst_sfd__h97055 = { 51'd0, x__h176927 } ;
assign dst_sfd__h97115 = { 51'd0, x__h177049 } ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4_AND_ETC___d2281 =
execFpuSimple_fpu_inst[8:4] == 5'd10 &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 || execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2277 ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263 =
execFpuSimple_fpu_inst[8:4] == 5'd14 &&
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63] ||
int_val_rnd__h94501[115:64] != 52'd0)) ;
assign execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683 =
execFpuSimple_fpu_inst[8:4] == 5'd14 &&
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4680) ;
assign execFpuSimple_rVal1_BITS_30_TO_23_MINUS_127__q11 =
execFpuSimple_rVal1[30:23] - 8'd127 ;
assign execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_OR_ETC___d4052 =
execFpuSimple_rVal1[31:0] == 32'd0 ||
!value__h136414[31] &&
NOT_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG__ETC___d3915 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3953 ||
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3954 ;
assign execFpuSimple_rVal1_BITS_31_TO_0__q158 = execFpuSimple_rVal1[31:0] ;
assign execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129 =
execFpuSimple_rVal1[51:0] <= execFpuSimple_rVal2[51:0] ;
assign execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134 =
execFpuSimple_rVal1[51:0] < execFpuSimple_rVal2[51:0] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
!execFpuSimple_rVal1[51] ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0 &&
!execFpuSimple_rVal2[51] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0 ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 =
execFpuSimple_rVal1[62:52] == execFpuSimple_rVal2[62:52] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 =
execFpuSimple_rVal1[62:52] <= execFpuSimple_rVal2[62:52] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2138 =
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2126 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
execFpuSimple_rVal1_BITS_51_TO_0_3_ULE_execFpu_ETC___d2129) &&
!execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 &&
(!execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_execFpu_ETC___d2127 ||
!execFpuSimple_rVal1_BITS_51_TO_0_3_ULT_execFpu_ETC___d2134) ;
assign execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_execFp_ETC___d2132 =
execFpuSimple_rVal1[62:52] < execFpuSimple_rVal2[62:52] ;
assign execFpuSimple_rVal1_BITS_62_TO_52_MINUS_1023__q92 =
execFpuSimple_rVal1[62:52] - 11'd1023 ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ==
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31]) ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2640 =
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636 &&
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ^
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 <
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630 ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2653 =
execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2636 &&
!((execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ^
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 <=
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630) ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2688 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) &&
((execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) ?
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2685 :
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2686) ;
assign execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0xFFF_ETC___d2707 =
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
(execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) ||
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] ||
execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31]) &&
IF_NOT_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2705 ;
assign execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418 =
execFpuSimple_rVal1[30] || execFpuSimple_rVal1[29] ||
execFpuSimple_rVal1[28] ||
execFpuSimple_rVal1[27] ||
execFpuSimple_rVal1[26] ||
execFpuSimple_rVal1[25] ||
execFpuSimple_rVal1[24] ||
execFpuSimple_rVal1[23] ||
execFpuSimple_rVal1[22] ||
execFpuSimple_rVal1[21] ||
execFpuSimple_rVal1[20] ||
execFpuSimple_rVal1[19] ||
execFpuSimple_rVal1[18] ||
execFpuSimple_rVal1[17] ||
execFpuSimple_rVal1[16] ||
execFpuSimple_rVal1[15] ||
execFpuSimple_rVal1[14] ||
execFpuSimple_rVal1[13] ||
execFpuSimple_rVal1[12] ||
execFpuSimple_rVal1[11] ||
execFpuSimple_rVal1[10] ||
execFpuSimple_rVal1[9] ||
execFpuSimple_rVal1[8] ||
execFpuSimple_rVal1[7] ||
execFpuSimple_rVal1[6] ||
execFpuSimple_rVal1[5] ||
execFpuSimple_rVal1[4] ||
execFpuSimple_rVal1[3] ||
execFpuSimple_rVal1[2] ||
execFpuSimple_rVal1[1] ||
execFpuSimple_rVal1[0] ;
assign execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895 =
(execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418) &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 &&
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4892 ;
assign execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439 =
execFpuSimple_rVal1[51] || execFpuSimple_rVal1[50] ||
execFpuSimple_rVal1[49] ||
execFpuSimple_rVal1[48] ||
execFpuSimple_rVal1[47] ||
execFpuSimple_rVal1[46] ||
execFpuSimple_rVal1[45] ||
execFpuSimple_rVal1[44] ||
execFpuSimple_rVal1[43] ||
execFpuSimple_rVal1[42] ||
execFpuSimple_rVal1[41] ||
execFpuSimple_rVal1[40] ||
execFpuSimple_rVal1[39] ||
execFpuSimple_rVal1[38] ||
execFpuSimple_rVal1[37] ||
execFpuSimple_rVal1[36] ||
execFpuSimple_rVal1[35] ||
execFpuSimple_rVal1[34] ||
execFpuSimple_rVal1[33] ||
execFpuSimple_rVal1[32] ||
execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418 ;
assign execFpuSimple_rVal1_BIT_63_4_AND_NOT_execFpuSi_ETC___d65 =
execFpuSimple_rVal1[63] && !execFpuSimple_rVal2[63] ||
execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58 &&
execFpuSimple_rVal1[63] ^
execFpuSimple_rVal1[62:0] < execFpuSimple_rVal2[62:0] ;
assign execFpuSimple_rVal1_BIT_63_4_EQ_execFpuSimple__ETC___d58 =
execFpuSimple_rVal1[63] == execFpuSimple_rVal2[63] ;
assign execFpuSimple_rVal1_BIT_63_4_OR_NOT_execFpuSim_ETC___d2141 =
(execFpuSimple_rVal1[63] || !execFpuSimple_rVal2[63]) &&
(execFpuSimple_rVal1[63] ?
execFpuSimple_rVal1_BITS_62_TO_52_1_ULE_execFp_ETC___d2138 :
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_ULT_ex_ETC___d2139) ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
(!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1982 &&
_theResult___fst_exp__h176642 == 11'd2047 &&
_theResult___fst_sfd__h176643 == 52'd0) ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1980 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1981 &&
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2576 ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
(!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 ||
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4467 &&
_theResult___fst_exp__h84950 == 8'd255 &&
_theResult___fst_sfd__h84951 == 23'd0) ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 ;
assign execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913 =
(execFpuSimple_rVal1[63] || execFpuSimple_rVal1[62] ||
execFpuSimple_rVal1[61] ||
execFpuSimple_rVal1[60] ||
execFpuSimple_rVal1[59] ||
execFpuSimple_rVal1[58] ||
execFpuSimple_rVal1[57] ||
execFpuSimple_rVal1[56] ||
execFpuSimple_rVal1[55] ||
execFpuSimple_rVal1[54] ||
execFpuSimple_rVal1[53] ||
execFpuSimple_rVal1[52] ||
execFpuSimple_rVal1_BIT_51_1_OR_execFpuSimple__ETC___d2439) &&
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4465 &&
!_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4466 &&
IF_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d4910 ;
assign guard__h108409 =
{ IF_theResult___snd16321_BIT_4_THEN_2_ELSE_0__q10[1],
{ _theResult___snd__h116321[3:0], 52'd0 } != 56'd0 } ;
assign guard__h117717 =
{ IF_sfdin25937_BIT_4_THEN_2_ELSE_0__q14[1],
{ sfdin__h125937[3:0], 52'd0 } != 56'd0 } ;
assign guard__h118315 = x__h118415 != 57'd0 ;
assign guard__h126784 =
{ IF_theResult___snd34720_BIT_4_THEN_2_ELSE_0__q17[1],
{ _theResult___snd__h134720[3:0], 52'd0 } != 56'd0 } ;
assign guard__h143842 =
{ IF_sfd___343832_BIT_2_THEN_2_ELSE_0__q30[1],
{ sfd___3__h143832[1:0], 52'd0 } != 54'd0 } ;
assign guard__h144572 =
{ IF_sfd___343832_BIT_1_THEN_2_ELSE_0__q31[1],
{ sfd___3__h143832[0], 53'd0 } != 54'd0 } ;
assign guard__h153233 =
{ IF_sfd___353223_BIT_2_THEN_2_ELSE_0__q59[1],
{ sfd___3__h153223[1:0], 52'd0 } != 54'd0 } ;
assign guard__h153962 =
{ IF_sfd___353223_BIT_1_THEN_2_ELSE_0__q60[1],
{ sfd___3__h153223[0], 53'd0 } != 54'd0 } ;
assign guard__h16427 =
{ IF_sfdin4520_BIT_33_THEN_2_ELSE_0__q89[1],
{ sfdin__h24520[32:0], 23'd0 } != 56'd0 } ;
assign guard__h164466 =
{ IF_sfd___364456_BIT_11_THEN_2_ELSE_0__q42[1],
{ sfd___3__h164456[10:0], 52'd0 } != 63'd0 } ;
assign guard__h165196 =
{ IF_sfd___364456_BIT_10_THEN_2_ELSE_0__q43[1],
{ sfd___3__h164456[9:0], 53'd0 } != 63'd0 } ;
assign guard__h175172 =
{ IF_sfd___375162_BIT_11_THEN_2_ELSE_0__q72[1],
{ sfd___3__h175162[10:0], 52'd0 } != 63'd0 } ;
assign guard__h175901 =
{ IF_sfd___375162_BIT_10_THEN_2_ELSE_0__q73[1],
{ sfd___3__h175162[9:0], 53'd0 } != 63'd0 } ;
assign guard__h25164 =
{ IF_theResult___snd3163_BIT_33_THEN_2_ELSE_0__q91[1],
{ _theResult___snd__h33163[32:0], 23'd0 } != 56'd0 } ;
assign guard__h34153 =
{ IF_sfdin2373_BIT_33_THEN_2_ELSE_0__q95[1],
{ sfdin__h42373[32:0], 23'd0 } != 56'd0 } ;
assign guard__h34751 = x__h34851 != 57'd0 ;
assign guard__h43017 =
{ IF_theResult___snd1040_BIT_33_THEN_2_ELSE_0__q98[1],
{ _theResult___snd__h51040[32:0], 23'd0 } != 56'd0 } ;
assign guard__h56904 =
{ IF_sfd___36894_BIT_8_THEN_2_ELSE_0__q115[1],
{ sfd___3__h56894[7:0], 23'd0 } != 31'd0 } ;
assign guard__h57431 =
{ IF_sfd___36894_BIT_7_THEN_2_ELSE_0__q116[1],
{ sfd___3__h56894[6:0], 24'd0 } != 31'd0 } ;
assign guard__h62759 =
{ IF_sfd___32749_BIT_8_THEN_2_ELSE_0__q141[1],
{ sfd___3__h62749[7:0], 23'd0 } != 31'd0 } ;
assign guard__h63285 =
{ IF_sfd___32749_BIT_7_THEN_2_ELSE_0__q142[1],
{ sfd___3__h62749[6:0], 24'd0 } != 31'd0 } ;
assign guard__h73586 =
{ IF_sfd___364456_BIT_40_THEN_2_ELSE_0__q40[1],
{ sfd___3__h164456[39:0], 23'd0 } != 63'd0 } ;
assign guard__h74113 =
{ IF_sfd___364456_BIT_39_THEN_2_ELSE_0__q41[1],
{ sfd___3__h164456[38:0], 24'd0 } != 63'd0 } ;
assign guard__h83886 =
{ IF_sfd___375162_BIT_40_THEN_2_ELSE_0__q70[1],
{ sfd___3__h175162[39:0], 23'd0 } != 63'd0 } ;
assign guard__h84412 =
{ IF_sfd___375162_BIT_39_THEN_2_ELSE_0__q71[1],
{ sfd___3__h175162[38:0], 24'd0 } != 63'd0 } ;
assign in1_exp__h4123 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal1[30:23] :
8'd255 ;
assign in1_sfd__h4124 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal1[22:0] :
23'd4194304 ;
assign in2_exp__h4198 =
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal2[30:23] :
8'd255 ;
assign in2_sfd__h4199 =
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF) ?
execFpuSimple_rVal2[22:0] :
23'd4194304 ;
assign int_val__h5743 =
{ 64'b0000000000000000000000000000000000000000000000000000000000000001,
in1_sfd__h4124,
2'b0 } ;
assign int_val__h5744 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
shifted__h5776 | y__h5935 :
shifted__h5776 | y__h6030 ;
assign int_val__h94496 =
{ 64'b0000000000000000000000000000000000000000000000000000000000000001,
execFpuSimple_rVal1[51:0],
2'b0 } ;
assign int_val__h94497 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
shifted__h94529 | y__h94716 :
shifted__h94529 | y__h94811 ;
assign int_val_rnd4501_BITS_31_TO_0__q8 = int_val_rnd__h94501[31:0] ;
assign int_val_rnd748_BITS_31_TO_0__q87 = int_val_rnd__h5748[31:0] ;
assign int_val_rnd__h5748 =
int_val__h5744[88:2] +
((int_val__h5744[1:0] != 2'd0 &&
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d2781) ?
87'd1 :
87'd0) ;
assign int_val_rnd__h94501 =
int_val__h94497[117:2] +
((int_val__h94497[1:0] != 2'd0 &&
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_0__ETC___d164) ?
116'd1 :
116'd0) ;
assign max_val__h5764 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign max_val__h7094 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign max_val__h94517 =
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign max_val__h95766 =
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign out___1_sfd__h97215 = { execFpuSimple_rVal1[22:0], 29'd0 } ;
assign out__h5724 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'hFFFFFFFF80000000 :
64'h000000007FFFFFFF ;
assign out__h6395 = { {32{val__h6394[31]}}, val__h6394 } ;
assign out__h6400 = { {32{max_val__h5764[31]}}, max_val__h5764 } ;
assign out__h6457 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'd0 :
64'hFFFFFFFFFFFFFFFF ;
assign out__h6989 =
{ {32{int_val_rnd748_BITS_31_TO_0__q87[31]}},
int_val_rnd748_BITS_31_TO_0__q87 } ;
assign out__h7054 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign out__h7587 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
~int_val_rnd__h5748[63:0] + 64'd1 :
int_val_rnd__h5748[63:0] ;
assign out__h94477 =
execFpuSimple_rVal1[63] ?
64'hFFFFFFFF80000000 :
64'h000000007FFFFFFF ;
assign out__h95039 = { {32{val__h95038[31]}}, val__h95038 } ;
assign out__h95044 = { {32{max_val__h94517[31]}}, max_val__h94517 } ;
assign out__h95101 =
execFpuSimple_rVal1[63] ? 64'd0 : 64'hFFFFFFFFFFFFFFFF ;
assign out__h95661 =
{ {32{int_val_rnd4501_BITS_31_TO_0__q8[31]}},
int_val_rnd4501_BITS_31_TO_0__q8 } ;
assign out__h95726 =
execFpuSimple_rVal1[63] ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign out__h96287 =
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
~int_val_rnd__h94501[63:0] + 64'd1 :
int_val_rnd__h94501[63:0] ;
assign out_exp__h117028 =
_theResult___snd__h116321[5] ?
_theResult___exp__h117025 :
_theResult___fst_exp__h116370 ;
assign out_exp__h126675 =
sfdin__h125937[5] ?
_theResult___exp__h126672 :
_theResult___fst_exp__h125943 ;
assign out_exp__h135457 =
_theResult___snd__h134720[5] ?
_theResult___exp__h135454 :
_theResult___fst_exp__h134774 ;
assign out_exp__h144461 =
sfd___3__h143832[3] ? _theResult___exp__h144458 : 11'd0 ;
assign out_exp__h145217 =
sfd___3__h143832[2] ?
_theResult___exp__h145214 :
x__h144587[10:0] ;
assign out_exp__h153852 =
sfd___3__h153223[3] ? _theResult___exp__h153849 : 11'd0 ;
assign out_exp__h154607 =
sfd___3__h153223[2] ?
_theResult___exp__h154604 :
x__h153977[10:0] ;
assign out_exp__h165085 =
sfd___3__h164456[12] ? _theResult___exp__h165082 : 11'd0 ;
assign out_exp__h165841 =
sfd___3__h164456[11] ?
_theResult___exp__h165838 :
x__h165211[10:0] ;
assign out_exp__h175791 =
sfd___3__h175162[12] ? _theResult___exp__h175788 : 11'd0 ;
assign out_exp__h176546 =
sfd___3__h175162[11] ?
_theResult___exp__h176543 :
x__h175916[10:0] ;
assign out_exp__h25055 =
sfdin__h24520[34] ?
_theResult___exp__h25052 :
_theResult___fst_exp__h24526 ;
assign out_exp__h33667 =
_theResult___snd__h33163[34] ?
_theResult___exp__h33664 :
_theResult___fst_exp__h33212 ;
assign out_exp__h42908 =
sfdin__h42373[34] ?
_theResult___exp__h42905 :
_theResult___fst_exp__h42379 ;
assign out_exp__h51574 =
_theResult___snd__h51040[34] ?
_theResult___exp__h51571 :
_theResult___fst_exp__h51094 ;
assign out_exp__h57320 =
sfd___3__h56894[9] ? _theResult___exp__h57317 : 8'd0 ;
assign out_exp__h57873 =
sfd___3__h56894[8] ? _theResult___exp__h57870 : x__h57446[7:0] ;
assign out_exp__h63175 =
sfd___3__h62749[9] ? _theResult___exp__h63172 : 8'd0 ;
assign out_exp__h63727 =
sfd___3__h62749[8] ? _theResult___exp__h63724 : x__h63300[7:0] ;
assign out_exp__h74002 =
sfd___3__h164456[41] ? _theResult___exp__h73999 : 8'd0 ;
assign out_exp__h74555 =
sfd___3__h164456[40] ?
_theResult___exp__h74552 :
x__h74128[7:0] ;
assign out_exp__h84302 =
sfd___3__h175162[41] ? _theResult___exp__h84299 : 8'd0 ;
assign out_exp__h84854 =
sfd___3__h175162[40] ?
_theResult___exp__h84851 :
x__h84427[7:0] ;
assign out_sfd__h117029 =
_theResult___snd__h116321[5] ?
_theResult___sfd__h117026 :
_theResult___snd__h116321[56:5] ;
assign out_sfd__h126676 =
sfdin__h125937[5] ?
_theResult___sfd__h126673 :
sfdin__h125937[56:5] ;
assign out_sfd__h135458 =
_theResult___snd__h134720[5] ?
_theResult___sfd__h135455 :
_theResult___snd__h134720[56:5] ;
assign out_sfd__h144462 =
sfd___3__h143832[3] ?
_theResult___sfd__h144459 :
sfd___3__h143832[54:3] ;
assign out_sfd__h145218 =
sfd___3__h143832[2] ?
_theResult___sfd__h145215 :
sfd___3__h143832[53:2] ;
assign out_sfd__h153853 =
sfd___3__h153223[3] ?
_theResult___sfd__h153850 :
sfd___3__h153223[54:3] ;
assign out_sfd__h154608 =
sfd___3__h153223[2] ?
_theResult___sfd__h154605 :
sfd___3__h153223[53:2] ;
assign out_sfd__h165086 =
sfd___3__h164456[12] ?
_theResult___sfd__h165083 :
sfd___3__h164456[63:12] ;
assign out_sfd__h165842 =
sfd___3__h164456[11] ?
_theResult___sfd__h165839 :
sfd___3__h164456[62:11] ;
assign out_sfd__h175792 =
sfd___3__h175162[12] ?
_theResult___sfd__h175789 :
sfd___3__h175162[63:12] ;
assign out_sfd__h176547 =
sfd___3__h175162[11] ?
_theResult___sfd__h176544 :
sfd___3__h175162[62:11] ;
assign out_sfd__h25056 =
sfdin__h24520[34] ?
_theResult___sfd__h25053 :
sfdin__h24520[56:34] ;
assign out_sfd__h33668 =
_theResult___snd__h33163[34] ?
_theResult___sfd__h33665 :
_theResult___snd__h33163[56:34] ;
assign out_sfd__h42909 =
sfdin__h42373[34] ?
_theResult___sfd__h42906 :
sfdin__h42373[56:34] ;
assign out_sfd__h51575 =
_theResult___snd__h51040[34] ?
_theResult___sfd__h51572 :
_theResult___snd__h51040[56:34] ;
assign out_sfd__h57321 =
sfd___3__h56894[9] ?
_theResult___sfd__h57318 :
sfd___3__h56894[31:9] ;
assign out_sfd__h57874 =
sfd___3__h56894[8] ?
_theResult___sfd__h57871 :
sfd___3__h56894[30:8] ;
assign out_sfd__h63176 =
sfd___3__h62749[9] ?
_theResult___sfd__h63173 :
sfd___3__h62749[31:9] ;
assign out_sfd__h63728 =
sfd___3__h62749[8] ?
_theResult___sfd__h63725 :
sfd___3__h62749[30:8] ;
assign out_sfd__h74003 =
sfd___3__h164456[41] ?
_theResult___sfd__h74000 :
sfd___3__h164456[63:41] ;
assign out_sfd__h74556 =
sfd___3__h164456[40] ?
_theResult___sfd__h74553 :
sfd___3__h164456[62:40] ;
assign out_sfd__h84303 =
sfd___3__h175162[41] ?
_theResult___sfd__h84300 :
sfd___3__h175162[63:41] ;
assign out_sfd__h84855 =
sfd___3__h175162[40] ?
_theResult___sfd__h84852 :
sfd___3__h175162[62:40] ;
assign result__h118320 =
{ _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436[56:1],
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_30_TO__ETC___d436[0] |
guard__h118315 } ;
assign result__h34756 =
{ _0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334[56:1],
_0b0_CONCAT_NOT_execFpuSimple_rVal1_BITS_62_TO__ETC___d3334[0] |
guard__h34751 } ;
assign saturated_bit__h5778 = x__h5981 != 89'd0 ;
assign saturated_bit__h94531 = x__h94762 != 118'd0 ;
assign sfd___3__h143832 =
sfd__h135831 <<
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d1011 ;
assign sfd___3__h153223 =
sfd__h145471 <<
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d1666 ;
assign sfd___3__h164456 =
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d1178 <<
IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ex_ETC___d1434 ;
assign sfd___3__h175162 =
execFpuSimple_rVal1 <<
IF_execFpuSimple_rVal1_BIT_63_4_THEN_0_ELSE_IF_ETC___d1976 ;
assign sfd___3__h56894 =
value__h136414 <<
IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_e_ETC___d3949 ;
assign sfd___3__h62749 =
execFpuSimple_rVal1[31:0] <<
IF_execFpuSimple_rVal1_BIT_31_05_THEN_0_ELSE_I_ETC___d4326 ;
assign sfd__h116388 =
{ 1'b0,
_theResult___fst_exp__h116370 != 11'd0,
_theResult___snd__h116321[56:5] } +
54'd1 ;
assign sfd__h126035 =
{ 1'b0,
_theResult___fst_exp__h125943 != 11'd0,
sfdin__h125937[56:5] } +
54'd1 ;
assign sfd__h134793 =
{ 1'b0,
_theResult___fst_exp__h134774 != 11'd0,
_theResult___snd__h134720[56:5] } +
54'd1 ;
assign sfd__h135831 = { value__h136414, 23'd0 } ;
assign sfd__h143859 = { 2'd0, sfd___3__h143832[54:3] } + 54'd1 ;
assign sfd__h144602 =
{ 1'b0, x__h144587[10:0] != 11'd0, sfd___3__h143832[53:2] } +
54'd1 ;
assign sfd__h145471 = { execFpuSimple_rVal1[31:0], 23'd0 } ;
assign sfd__h153250 = { 2'd0, sfd___3__h153223[54:3] } + 54'd1 ;
assign sfd__h153992 =
{ 1'b0, x__h153977[10:0] != 11'd0, sfd___3__h153223[53:2] } +
54'd1 ;
assign sfd__h164483 = { 2'd0, sfd___3__h164456[63:12] } + 54'd1 ;
assign sfd__h165226 =
{ 1'b0, x__h165211[10:0] != 11'd0, sfd___3__h164456[62:11] } +
54'd1 ;
assign sfd__h175189 = { 2'd0, sfd___3__h175162[63:12] } + 54'd1 ;
assign sfd__h175931 =
{ 1'b0, x__h175916[10:0] != 11'd0, sfd___3__h175162[62:11] } +
54'd1 ;
assign sfd__h24618 =
{ 1'b0,
_theResult___fst_exp__h24526 != 8'd0,
sfdin__h24520[56:34] } +
25'd1 ;
assign sfd__h33230 =
{ 1'b0,
_theResult___fst_exp__h33212 != 8'd0,
_theResult___snd__h33163[56:34] } +
25'd1 ;
assign sfd__h42471 =
{ 1'b0,
_theResult___fst_exp__h42379 != 8'd0,
sfdin__h42373[56:34] } +
25'd1 ;
assign sfd__h51113 =
{ 1'b0,
_theResult___fst_exp__h51094 != 8'd0,
_theResult___snd__h51040[56:34] } +
25'd1 ;
assign sfd__h56921 = { 2'd0, sfd___3__h56894[31:9] } + 25'd1 ;
assign sfd__h57461 =
{ 1'b0, x__h57446[7:0] != 8'd0, sfd___3__h56894[30:8] } + 25'd1 ;
assign sfd__h62776 = { 2'd0, sfd___3__h62749[31:9] } + 25'd1 ;
assign sfd__h63315 =
{ 1'b0, x__h63300[7:0] != 8'd0, sfd___3__h62749[30:8] } + 25'd1 ;
assign sfd__h73603 = { 2'd0, sfd___3__h164456[63:41] } + 25'd1 ;
assign sfd__h74143 =
{ 1'b0, x__h74128[7:0] != 8'd0, sfd___3__h164456[62:40] } +
25'd1 ;
assign sfd__h83903 = { 2'd0, sfd___3__h175162[63:41] } + 25'd1 ;
assign sfd__h84442 =
{ 1'b0, x__h84427[7:0] != 8'd0, sfd___3__h175162[62:40] } +
25'd1 ;
assign sfd__h8786 = { value__h17039, 3'd0 } ;
assign sfd__h97512 = { value__h101927, 32'd0 } ;
assign sfdin__h125937 =
_theResult____h117707[56] ?
_theResult___snd__h125954 :
_theResult___snd__h125965 ;
assign sfdin__h24520 =
_theResult____h16417[56] ?
_theResult___snd__h24537 :
_theResult___snd__h24548 ;
assign sfdin__h42373 =
_theResult____h34143[56] ?
_theResult___snd__h42390 :
_theResult___snd__h42401 ;
assign shifted__h5776 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
int_val__h5743 << amt_abs__h5775 :
int_val__h5743 >> amt_abs__h5775 ;
assign shifted__h94529 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
int_val__h94496 << amt_abs__h96387 :
int_val__h94496 >> amt_abs__h96387 ;
assign shifted_out_mask__h5777 =
_150_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BITS_ETC___d2746[12] ?
~x__h5994 :
~x__h6017 ;
assign shifted_out_mask__h96389 =
_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BITS_6_ETC___d115[16] ?
~x__h96634 :
~x__h96657 ;
assign val__h6394 =
(int_val_rnd__h5748 != 87'd0 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ?
~int_val_rnd__h5748[31:0] + 32'd1 :
int_val_rnd__h5748[31:0] ;
assign val__h95038 =
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63]) ?
~int_val_rnd__h94501[31:0] + 32'd1 :
int_val_rnd__h94501[31:0] ;
assign value_BIT_23___h109067 = execFpuSimple_rVal1[30:23] != 8'd0 ;
assign value__h101927 =
{ 1'b0, value_BIT_23___h109067, execFpuSimple_rVal1[22:0] } ;
assign value__h136414 =
execFpuSimple_rVal1[31] ?
-execFpuSimple_rVal1[31:0] :
execFpuSimple_rVal1[31:0] ;
assign value__h17039 =
{ 1'b0,
execFpuSimple_rVal1[62:52] != 11'd0,
execFpuSimple_rVal1[51:0] } ;
assign x__h118415 = sfd__h97512 << x__h118448 ;
assign x__h118448 =
12'd57 -
_3074_MINUS_SEXT_execFpuSimple_rVal1_BITS_30_TO_ETC___d432 ;
assign x__h144587 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1014 +
12'd1023 ;
assign x__h153977 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1669 +
12'd1023 ;
assign x__h165211 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1437 +
12'd1023 ;
assign x__h175916 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d1979 +
12'd1023 ;
assign x__h176800 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal2[62:52] != 11'd2047 ||
execFpuSimple_rVal2[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0 &&
execFpuSimple_rVal2[62:52] == 11'd0 &&
execFpuSimple_rVal2[51:0] == 52'd0 ||
(!execFpuSimple_rVal1[63] || execFpuSimple_rVal2[63]) &&
execFpuSimple_rVal1_BIT_63_4_OR_NOT_execFpuSim_ETC___d2141) ;
assign x__h176927 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal2[62:52] != 11'd2047 ||
execFpuSimple_rVal2[51:0] == 52'd0) &&
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9_ETC___d2160 ;
assign x__h177049 = x__h176927 || x__h176800 ;
assign x__h219 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
in2_exp__h4198 == 8'd255 &&
in2_sfd__h4199 != 23'd0) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2644 } ;
assign x__h224 =
(in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
in2_exp__h4198 == 8'd255 &&
in2_sfd__h4199 != 23'd0) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_ETC___d2657 } ;
assign x__h34851 = sfd__h8786 << x__h34884 ;
assign x__h34884 =
12'd57 -
_3970_MINUS_SEXT_execFpuSimple_rVal1_BITS_62_TO_ETC___d3330 ;
assign x__h4067 =
{ execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31],
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 } ;
assign x__h4081 =
{ execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31],
IF_execFpuSimple_rVal2_BITS_63_TO_32_612_EQ_0x_ETC___d2630 } ;
assign x__h4245 = { 63'd0, x__h4248 } ;
assign x__h4248 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in2_exp__h4198 != 8'd255 || in2_sfd__h4199 == 23'd0) &&
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2690 ;
assign x__h4413 = { 63'd0, x__h4416 } ;
assign x__h4416 =
(in1_exp__h4123 != 8'd255 || in1_sfd__h4124 == 23'd0) &&
(in2_exp__h4198 != 8'd255 || in2_sfd__h4199 == 23'd0) &&
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d2708 ;
assign x__h4568 = { 63'd0, x__h4571 } ;
assign x__h4571 = x__h4416 || x__h4248 ;
assign x__h4812 =
{ in1_exp__h4123 == 8'd255 && in1_sfd__h4124[22],
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 &&
!in1_sfd__h4124[22],
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 == 8'd255 &&
in1_sfd__h4124 == 23'd0,
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 != 8'd255 &&
in1_exp__h4123 != 8'd0,
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 != 23'd0,
(execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31]) &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 == 23'd0,
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 == 23'd0,
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 == 8'd0 &&
in1_sfd__h4124 != 23'd0,
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31] &&
in1_exp__h4123 != 8'd255 &&
in1_exp__h4123 != 8'd0,
IF_execFpuSimple_rVal1_BITS_63_TO_32_EQ_0xFFFF_ETC__q2[0] } ;
assign x__h57446 =
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d3952 +
9'd127 ;
assign x__h5981 = int_val__h5743 & shifted_out_mask__h5777 ;
assign x__h5994 = 89'h1FFFFFFFFFFFFFFFFFFFFFF >> amt_abs__h5775 ;
assign x__h6017 = 89'h1FFFFFFFFFFFFFFFFFFFFFF << amt_abs__h5775 ;
assign x__h63300 =
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4329 +
9'd127 ;
assign x__h74128 =
_64_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d4114 +
9'd127 ;
assign x__h8190 =
{ execFpuSimple_fpu_inst[8:4] != 5'd8 &&
execFpuSimple_fpu_inst[8:4] != 5'd9 &&
execFpuSimple_fpu_inst[8:4] != 5'd19 &&
execFpuSimple_fpu_inst[8:4] != 5'd20 &&
execFpuSimple_fpu_inst[8:4] != 5'd21 &&
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280,
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 } ;
assign x__h84427 =
_64_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_6_ETC___d4464 +
9'd127 ;
assign x__h85553 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
64'h7FF8000000000000 :
((execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
execFpuSimple_rVal1 :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d67) ;
assign x__h85558 =
(execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
64'h7FF8000000000000 :
((execFpuSimple_rVal2[62:52] == 11'd2047 &&
execFpuSimple_rVal2[51:0] != 52'd0) ?
execFpuSimple_rVal1 :
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_ETC___d78) ;
assign x__h93191 =
{ execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51],
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 &&
!execFpuSimple_rVal1[51],
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0,
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] != 11'd2047 &&
execFpuSimple_rVal1[62:52] != 11'd0,
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] != 52'd0,
!execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0,
execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] == 52'd0,
execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] == 11'd0 &&
execFpuSimple_rVal1[51:0] != 52'd0,
execFpuSimple_rVal1[63] &&
execFpuSimple_rVal1[62:52] != 11'd2047 &&
execFpuSimple_rVal1[62:52] != 11'd0,
IF_execFpuSimple_rVal1_BIT_63_AND_execFpuSimpl_ETC__q1[0] } ;
assign x__h94762 = int_val__h94496 & shifted_out_mask__h96389 ;
assign x__h96634 = 118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF >> amt_abs__h96387 ;
assign x__h96657 = 118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF << amt_abs__h96387 ;
assign y__h5935 = { saturated_bit__h5778, 88'd0 } ;
assign y__h6030 = { 88'd0, saturated_bit__h5778 } ;
assign y__h94716 = { saturated_bit__h94531, 117'd0 } ;
assign y__h94811 = { 117'd0, saturated_bit__h94531 } ;
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_254__ETC__q3 = 8'd254;
3'd2:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_254__ETC__q3 =
execFpuSimple_rVal1[63] ? 8'd255 : 8'd254;
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_254__ETC__q3 =
execFpuSimple_rVal1[63] ? 8'd254 : 8'd255;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_254__ETC__q3 = 8'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_8388_ETC__q4 =
23'd8388607;
3'd2:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_8388_ETC__q4 =
execFpuSimple_rVal1[63] ? 23'd0 : 23'd8388607;
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_8388_ETC__q4 =
execFpuSimple_rVal1[63] ? 23'd8388607 : 23'd0;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_8388_ETC__q4 = 23'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_2046_ETC__q5 = 11'd2046;
3'd2:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_2046_ETC__q5 =
execFpuSimple_rVal1[31] ? 11'd2047 : 11'd2046;
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_2046_ETC__q5 =
execFpuSimple_rVal1[31] ? 11'd2046 : 11'd2047;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_2046_ETC__q5 = 11'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_4503_ETC__q6 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_4503_ETC__q6 =
execFpuSimple_rVal1[31] ? 52'd0 : 52'hFFFFFFFFFFFFF;
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_4503_ETC__q6 =
execFpuSimple_rVal1[31] ? 52'hFFFFFFFFFFFFF : 52'd0;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_1_4503_ETC__q6 = 52'd0;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or int_val__h94497)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q7 =
!execFpuSimple_rVal1[63];
3'd4:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q7 =
int_val__h94497[1];
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q7 =
execFpuSimple_fpu_inst[3:1] == 3'd2 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h108409 or
_theResult___fst_exp__h116370 or _theResult___exp__h117025)
begin
case (guard__h108409)
2'b0:
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q18 =
_theResult___fst_exp__h116370;
2'b01, 2'b10, 2'b11:
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q18 =
_theResult___exp__h117025;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h116370 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407 or
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q18)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413 =
_theResult___fst_exp__h116370;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d409;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d407;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413 =
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q18;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d413 =
11'd0;
endcase
end
always@(guard__h108409 or
_theResult___fst_exp__h116370 or
out_exp__h117028 or _theResult___exp__h117025)
begin
case (guard__h108409)
2'b0, 2'b01:
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q19 =
_theResult___fst_exp__h116370;
2'b10:
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q19 =
out_exp__h117028;
2'b11:
CASE_guard08409_0b0_theResult___fst_exp16370_0_ETC__q19 =
_theResult___exp__h117025;
endcase
end
always@(guard__h117717 or
_theResult___fst_exp__h125943 or _theResult___exp__h126672)
begin
case (guard__h117717)
2'b0:
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q20 =
_theResult___fst_exp__h125943;
2'b01, 2'b10, 2'b11:
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q20 =
_theResult___exp__h126672;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h125943 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737 or
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q20)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743 =
_theResult___fst_exp__h125943;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d739;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d737;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743 =
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q20;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d743 =
11'd0;
endcase
end
always@(guard__h117717 or
_theResult___fst_exp__h125943 or
out_exp__h126675 or _theResult___exp__h126672)
begin
case (guard__h117717)
2'b0, 2'b01:
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q21 =
_theResult___fst_exp__h125943;
2'b10:
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q21 =
out_exp__h126675;
2'b11:
CASE_guard17717_0b0_theResult___fst_exp25943_0_ETC__q21 =
_theResult___exp__h126672;
endcase
end
always@(guard__h126784 or
_theResult___fst_exp__h134774 or _theResult___exp__h135454)
begin
case (guard__h126784)
2'b0:
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q22 =
_theResult___fst_exp__h134774;
2'b01, 2'b10, 2'b11:
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q22 =
_theResult___exp__h135454;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h134774 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806 or
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q22)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812 =
_theResult___fst_exp__h134774;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d808;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d806;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812 =
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q22;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d812 =
11'd0;
endcase
end
always@(guard__h126784 or
_theResult___fst_exp__h134774 or
out_exp__h135457 or _theResult___exp__h135454)
begin
case (guard__h126784)
2'b0, 2'b01:
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q23 =
_theResult___fst_exp__h134774;
2'b10:
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q23 =
out_exp__h135457;
2'b11:
CASE_guard26784_0b0_theResult___fst_exp34774_0_ETC__q23 =
_theResult___exp__h135454;
endcase
end
always@(guard__h108409 or
_theResult___snd__h116321 or _theResult___sfd__h117026)
begin
case (guard__h108409)
2'b0:
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q24 =
_theResult___snd__h116321[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q24 =
_theResult___sfd__h117026;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h116321 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838 or
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q24)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844 =
_theResult___snd__h116321[56:5];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d840;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d838;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844 =
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q24;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d844 =
52'd0;
endcase
end
always@(guard__h108409 or
_theResult___snd__h116321 or
out_sfd__h117029 or _theResult___sfd__h117026)
begin
case (guard__h108409)
2'b0, 2'b01:
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q25 =
_theResult___snd__h116321[56:5];
2'b10:
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q25 =
out_sfd__h117029;
2'b11:
CASE_guard08409_0b0_theResult___snd16321_BITS__ETC__q25 =
_theResult___sfd__h117026;
endcase
end
always@(guard__h117717 or sfdin__h125937 or _theResult___sfd__h126673)
begin
case (guard__h117717)
2'b0:
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q26 =
sfdin__h125937[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q26 =
_theResult___sfd__h126673;
endcase
end
always@(execFpuSimple_fpu_inst or
sfdin__h125937 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867 or
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865 or
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q26)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871 =
sfdin__h125937[56:5];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d867;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871 =
IF_IF_IF_IF_3074_MINUS_SEXT_execFpuSimple_rVal_ETC___d865;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871 =
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q26;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d871 =
52'd0;
endcase
end
always@(guard__h117717 or
sfdin__h125937 or out_sfd__h126676 or _theResult___sfd__h126673)
begin
case (guard__h117717)
2'b0, 2'b01:
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q27 =
sfdin__h125937[56:5];
2'b10:
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q27 =
out_sfd__h126676;
2'b11:
CASE_guard17717_0b0_sfdin25937_BITS_56_TO_5_0b_ETC__q27 =
_theResult___sfd__h126673;
endcase
end
always@(guard__h126784 or
_theResult___snd__h134720 or _theResult___sfd__h135455)
begin
case (guard__h126784)
2'b0:
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q28 =
_theResult___snd__h134720[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q28 =
_theResult___sfd__h135455;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h134720 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886 or
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884 or
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q28)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890 =
_theResult___snd__h134720[56:5];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d886;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890 =
IF_IF_IF_execFpuSimple_rVal1_BITS_30_TO_23_23__ETC___d884;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890 =
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q28;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d890 =
52'd0;
endcase
end
always@(guard__h126784 or
_theResult___snd__h134720 or
out_sfd__h135458 or _theResult___sfd__h135455)
begin
case (guard__h126784)
2'b0, 2'b01:
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q29 =
_theResult___snd__h134720[56:5];
2'b10:
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q29 =
out_sfd__h135458;
2'b11:
CASE_guard26784_0b0_theResult___snd34720_BITS__ETC__q29 =
_theResult___sfd__h135455;
endcase
end
always@(guard__h143842 or _theResult___exp__h144458)
begin
case (guard__h143842)
2'b0: CASE_guard43842_0b0_0_0b1_theResult___exp44458_ETC__q32 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard43842_0b0_0_0b1_theResult___exp44458_ETC__q32 =
_theResult___exp__h144458;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053 or
guard__h143842 or
execFpuSimple_rVal1 or
_theResult___exp__h144458 or
CASE_guard43842_0b0_0_0b1_theResult___exp44458_ETC__q32)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1056 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1053;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1056 =
(guard__h143842 == 2'b0 || execFpuSimple_rVal1[31]) ?
11'd0 :
_theResult___exp__h144458;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1056 =
CASE_guard43842_0b0_0_0b1_theResult___exp44458_ETC__q32;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1056 =
11'd0;
endcase
end
always@(guard__h143842 or out_exp__h144461 or _theResult___exp__h144458)
begin
case (guard__h143842)
2'b0, 2'b01:
CASE_guard43842_0b0_0_0b1_0_0b10_out_exp44461__ETC__q33 = 11'd0;
2'b10:
CASE_guard43842_0b0_0_0b1_0_0b10_out_exp44461__ETC__q33 =
out_exp__h144461;
2'b11:
CASE_guard43842_0b0_0_0b1_0_0b10_out_exp44461__ETC__q33 =
_theResult___exp__h144458;
endcase
end
always@(guard__h144572 or x__h144587 or _theResult___exp__h145214)
begin
case (guard__h144572)
2'b0:
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_th_ETC__q34 =
x__h144587[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_th_ETC__q34 =
_theResult___exp__h145214;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h144587 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097 or
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_th_ETC__q34)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103 =
x__h144587[10:0];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1099;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1097;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103 =
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_th_ETC__q34;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1103 =
11'd0;
endcase
end
always@(guard__h144572 or
x__h144587 or out_exp__h145217 or _theResult___exp__h145214)
begin
case (guard__h144572)
2'b0, 2'b01:
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_x4_ETC__q35 =
x__h144587[10:0];
2'b10:
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_x4_ETC__q35 =
out_exp__h145217;
2'b11:
CASE_guard44572_0b0_x44587_BITS_10_TO_0_0b1_x4_ETC__q35 =
_theResult___exp__h145214;
endcase
end
always@(guard__h143842 or sfd___3__h143832 or _theResult___sfd__h144459)
begin
case (guard__h143842)
2'b0:
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q36 =
sfd___3__h143832[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q36 =
_theResult___sfd__h144459;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h143832 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124 or
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q36)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130 =
sfd___3__h143832[54:3];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1126;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1124;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130 =
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q36;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1130 =
52'd0;
endcase
end
always@(guard__h143842 or
sfd___3__h143832 or out_sfd__h144462 or _theResult___sfd__h144459)
begin
case (guard__h143842)
2'b0, 2'b01:
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q37 =
sfd___3__h143832[54:3];
2'b10:
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q37 =
out_sfd__h144462;
2'b11:
CASE_guard43842_0b0_sfd___343832_BITS_54_TO_3__ETC__q37 =
_theResult___sfd__h144459;
endcase
end
always@(guard__h144572 or sfd___3__h143832 or _theResult___sfd__h145215)
begin
case (guard__h144572)
2'b0:
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q38 =
sfd___3__h143832[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q38 =
_theResult___sfd__h145215;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h143832 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142 or
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q38)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148 =
sfd___3__h143832[53:2];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1144;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d1142;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148 =
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q38;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1148 =
52'd0;
endcase
end
always@(guard__h144572 or
sfd___3__h143832 or out_sfd__h145218 or _theResult___sfd__h145215)
begin
case (guard__h144572)
2'b0, 2'b01:
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q39 =
sfd___3__h143832[53:2];
2'b10:
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q39 =
out_sfd__h145218;
2'b11:
CASE_guard44572_0b0_sfd___343832_BITS_53_TO_2__ETC__q39 =
_theResult___sfd__h145215;
endcase
end
always@(guard__h164466 or _theResult___exp__h165082)
begin
case (guard__h164466)
2'b0: CASE_guard64466_0b0_0_0b1_theResult___exp65082_ETC__q44 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard64466_0b0_0_0b1_theResult___exp65082_ETC__q44 =
_theResult___exp__h165082;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475 or
guard__h164466 or
execFpuSimple_rVal1 or
_theResult___exp__h165082 or
CASE_guard64466_0b0_0_0b1_theResult___exp65082_ETC__q44)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1478 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1475;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1478 =
(guard__h164466 == 2'b0 || execFpuSimple_rVal1[63]) ?
11'd0 :
_theResult___exp__h165082;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1478 =
CASE_guard64466_0b0_0_0b1_theResult___exp65082_ETC__q44;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1478 =
11'd0;
endcase
end
always@(guard__h164466 or out_exp__h165085 or _theResult___exp__h165082)
begin
case (guard__h164466)
2'b0, 2'b01:
CASE_guard64466_0b0_0_0b1_0_0b10_out_exp65085__ETC__q45 = 11'd0;
2'b10:
CASE_guard64466_0b0_0_0b1_0_0b10_out_exp65085__ETC__q45 =
out_exp__h165085;
2'b11:
CASE_guard64466_0b0_0_0b1_0_0b10_out_exp65085__ETC__q45 =
_theResult___exp__h165082;
endcase
end
always@(guard__h165196 or x__h165211 or _theResult___exp__h165838)
begin
case (guard__h165196)
2'b0:
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_th_ETC__q46 =
x__h165211[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_th_ETC__q46 =
_theResult___exp__h165838;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h165211 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519 or
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_th_ETC__q46)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525 =
x__h165211[10:0];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1521;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1519;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525 =
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_th_ETC__q46;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1525 =
11'd0;
endcase
end
always@(guard__h165196 or
x__h165211 or out_exp__h165841 or _theResult___exp__h165838)
begin
case (guard__h165196)
2'b0, 2'b01:
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_x6_ETC__q47 =
x__h165211[10:0];
2'b10:
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_x6_ETC__q47 =
out_exp__h165841;
2'b11:
CASE_guard65196_0b0_x65211_BITS_10_TO_0_0b1_x6_ETC__q47 =
_theResult___exp__h165838;
endcase
end
always@(guard__h164466 or sfd___3__h164456 or _theResult___sfd__h165083)
begin
case (guard__h164466)
2'b0:
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q48 =
sfd___3__h164456[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q48 =
_theResult___sfd__h165083;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164456 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547 or
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q48)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553 =
sfd___3__h164456[63:12];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1549;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1547;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553 =
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q48;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1553 =
52'd0;
endcase
end
always@(guard__h164466 or
sfd___3__h164456 or out_sfd__h165086 or _theResult___sfd__h165083)
begin
case (guard__h164466)
2'b0, 2'b01:
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q49 =
sfd___3__h164456[63:12];
2'b10:
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q49 =
out_sfd__h165086;
2'b11:
CASE_guard64466_0b0_sfd___364456_BITS_63_TO_12_ETC__q49 =
_theResult___sfd__h165083;
endcase
end
always@(guard__h165196 or sfd___3__h164456 or _theResult___sfd__h165839)
begin
case (guard__h165196)
2'b0:
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q50 =
sfd___3__h164456[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q50 =
_theResult___sfd__h165839;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164456 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565 or
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q50)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571 =
sfd___3__h164456[62:11];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1567;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d1565;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571 =
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q50;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1571 =
52'd0;
endcase
end
always@(guard__h165196 or
sfd___3__h164456 or out_sfd__h165842 or _theResult___sfd__h165839)
begin
case (guard__h165196)
2'b0, 2'b01:
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q51 =
sfd___3__h164456[62:11];
2'b10:
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q51 =
out_sfd__h165842;
2'b11:
CASE_guard65196_0b0_sfd___364456_BITS_62_TO_11_ETC__q51 =
_theResult___sfd__h165839;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h108409)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d912 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d912 =
(guard__h108409 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h108409 == 2'b01 || guard__h108409 == 2'b10 ||
guard__h108409 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d912 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h108409 or execFpuSimple_rVal1)
begin
case (guard__h108409)
2'b0, 2'b01, 2'b10:
CASE_guard08409_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard08409_0b0_execFpuSimple_rVal1_BIT_31_ETC__q52 =
guard__h108409 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h117717)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d920 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d920 =
(guard__h117717 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h117717 == 2'b01 || guard__h117717 == 2'b10 ||
guard__h117717 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d920 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h117717 or execFpuSimple_rVal1)
begin
case (guard__h117717)
2'b0, 2'b01, 2'b10:
CASE_guard17717_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard17717_0b0_execFpuSimple_rVal1_BIT_31_ETC__q53 =
guard__h117717 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h126784)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d928 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d928 =
(guard__h126784 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h126784 == 2'b01 || guard__h126784 == 2'b10 ||
guard__h126784 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d928 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h126784 or execFpuSimple_rVal1)
begin
case (guard__h126784)
2'b0, 2'b01, 2'b10:
CASE_guard26784_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard26784_0b0_execFpuSimple_rVal1_BIT_31_ETC__q54 =
guard__h126784 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h143842)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1161 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1161 =
(guard__h143842 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h143842 == 2'b01 || guard__h143842 == 2'b10 ||
guard__h143842 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1161 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h143842 or execFpuSimple_rVal1)
begin
case (guard__h143842)
2'b0, 2'b01, 2'b10:
CASE_guard43842_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard43842_0b0_execFpuSimple_rVal1_BIT_31_ETC__q55 =
guard__h143842 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h144572)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1168 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1168 =
(guard__h144572 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h144572 == 2'b01 || guard__h144572 == 2'b10 ||
guard__h144572 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1168 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h144572 or execFpuSimple_rVal1)
begin
case (guard__h144572)
2'b0, 2'b01, 2'b10:
CASE_guard44572_0b0_execFpuSimple_rVal1_BIT_31_ETC__q56 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard44572_0b0_execFpuSimple_rVal1_BIT_31_ETC__q56 =
guard__h144572 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h164466)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1586 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1586 =
(guard__h164466 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h164466 == 2'b01 || guard__h164466 == 2'b10 ||
guard__h164466 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1586 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h164466 or execFpuSimple_rVal1)
begin
case (guard__h164466)
2'b0, 2'b01, 2'b10:
CASE_guard64466_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard64466_0b0_execFpuSimple_rVal1_BIT_63_ETC__q57 =
guard__h164466 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h165196)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1593 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1593 =
(guard__h165196 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h165196 == 2'b01 || guard__h165196 == 2'b10 ||
guard__h165196 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1593 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h165196 or execFpuSimple_rVal1)
begin
case (guard__h165196)
2'b0, 2'b01, 2'b10:
CASE_guard65196_0b0_execFpuSimple_rVal1_BIT_63_ETC__q58 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard65196_0b0_execFpuSimple_rVal1_BIT_63_ETC__q58 =
guard__h165196 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or
NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935 or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601 or
execFpuSimple_rVal2 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
execFpuSimple_rVal2[63];
5'd6:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
!execFpuSimple_rVal2[63];
5'd7:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
execFpuSimple_rVal1[63] ^ execFpuSimple_rVal2[63];
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d1607 =
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
((execFpuSimple_fpu_inst[8:4] == 5'd10) ?
NOT_IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_ETC___d935 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d1601);
endcase
end
always@(guard__h153233 or out_exp__h153852 or _theResult___exp__h153849)
begin
case (guard__h153233)
2'b0, 2'b01:
CASE_guard53233_0b0_0_0b1_0_0b10_out_exp53852__ETC__q61 = 11'd0;
2'b10:
CASE_guard53233_0b0_0_0b1_0_0b10_out_exp53852__ETC__q61 =
out_exp__h153852;
2'b11:
CASE_guard53233_0b0_0_0b1_0_0b10_out_exp53852__ETC__q61 =
_theResult___exp__h153849;
endcase
end
always@(guard__h153233 or _theResult___exp__h153849)
begin
case (guard__h153233)
2'b0: CASE_guard53233_0b0_0_0b1_theResult___exp53849_ETC__q62 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard53233_0b0_0_0b1_theResult___exp53849_ETC__q62 =
_theResult___exp__h153849;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h153233 or
_theResult___exp__h153849 or
CASE_guard53233_0b0_0_0b1_theResult___exp53849_ETC__q62)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q63 =
(guard__h153233 == 2'b0) ? 11'd0 : _theResult___exp__h153849;
3'd4:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q63 =
CASE_guard53233_0b0_0_0b1_theResult___exp53849_ETC__q62;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q63 =
11'd0;
endcase
end
always@(guard__h153962 or x__h153977 or _theResult___exp__h154604)
begin
case (guard__h153962)
2'b0:
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_th_ETC__q64 =
x__h153977[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_th_ETC__q64 =
_theResult___exp__h154604;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h153977 or
guard__h153962 or
_theResult___exp__h154604 or
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_th_ETC__q64)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1751 =
x__h153977[10:0];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1751 =
(guard__h153962 == 2'b0) ?
x__h153977[10:0] :
_theResult___exp__h154604;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1751 =
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_th_ETC__q64;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1751 =
11'd0;
endcase
end
always@(guard__h153962 or
x__h153977 or out_exp__h154607 or _theResult___exp__h154604)
begin
case (guard__h153962)
2'b0, 2'b01:
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_x5_ETC__q65 =
x__h153977[10:0];
2'b10:
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_x5_ETC__q65 =
out_exp__h154607;
2'b11:
CASE_guard53962_0b0_x53977_BITS_10_TO_0_0b1_x5_ETC__q65 =
_theResult___exp__h154604;
endcase
end
always@(guard__h153233 or sfd___3__h153223 or _theResult___sfd__h153850)
begin
case (guard__h153233)
2'b0:
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q66 =
sfd___3__h153223[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q66 =
_theResult___sfd__h153850;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h153223 or
guard__h153233 or
_theResult___sfd__h153850 or
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q66)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1774 =
sfd___3__h153223[54:3];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1774 =
(guard__h153233 == 2'b0) ?
sfd___3__h153223[54:3] :
_theResult___sfd__h153850;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1774 =
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q66;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1774 =
52'd0;
endcase
end
always@(guard__h153233 or
sfd___3__h153223 or out_sfd__h153853 or _theResult___sfd__h153850)
begin
case (guard__h153233)
2'b0, 2'b01:
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q67 =
sfd___3__h153223[54:3];
2'b10:
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q67 =
out_sfd__h153853;
2'b11:
CASE_guard53233_0b0_sfd___353223_BITS_54_TO_3__ETC__q67 =
_theResult___sfd__h153850;
endcase
end
always@(guard__h153962 or sfd___3__h153223 or _theResult___sfd__h154605)
begin
case (guard__h153962)
2'b0:
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q68 =
sfd___3__h153223[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q68 =
_theResult___sfd__h154605;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h153223 or
guard__h153962 or
_theResult___sfd__h154605 or
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q68)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1789 =
sfd___3__h153223[53:2];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1789 =
(guard__h153962 == 2'b0) ?
sfd___3__h153223[53:2] :
_theResult___sfd__h154605;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1789 =
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q68;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d1789 =
52'd0;
endcase
end
always@(guard__h153962 or
sfd___3__h153223 or out_sfd__h154608 or _theResult___sfd__h154605)
begin
case (guard__h153962)
2'b0, 2'b01:
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q69 =
sfd___3__h153223[53:2];
2'b10:
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q69 =
out_sfd__h154608;
2'b11:
CASE_guard53962_0b0_sfd___353223_BITS_53_TO_2__ETC__q69 =
_theResult___sfd__h154605;
endcase
end
always@(guard__h83886 or out_exp__h84302 or _theResult___exp__h84299)
begin
case (guard__h83886)
2'b0, 2'b01:
CASE_guard3886_0b0_0_0b1_0_0b10_out_exp4302_0b_ETC__q74 = 8'd0;
2'b10:
CASE_guard3886_0b0_0_0b1_0_0b10_out_exp4302_0b_ETC__q74 =
out_exp__h84302;
2'b11:
CASE_guard3886_0b0_0_0b1_0_0b10_out_exp4302_0b_ETC__q74 =
_theResult___exp__h84299;
endcase
end
always@(guard__h83886 or _theResult___exp__h84299)
begin
case (guard__h83886)
2'b0: CASE_guard3886_0b0_0_0b1_theResult___exp4299_0_ETC__q75 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard3886_0b0_0_0b1_theResult___exp4299_0_ETC__q75 =
_theResult___exp__h84299;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h83886 or
_theResult___exp__h84299 or
CASE_guard3886_0b0_0_0b1_theResult___exp4299_0_ETC__q75)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q76 =
(guard__h83886 == 2'b0) ? 8'd0 : _theResult___exp__h84299;
3'd4:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q76 =
CASE_guard3886_0b0_0_0b1_theResult___exp4299_0_ETC__q75;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q76 = 8'd0;
endcase
end
always@(guard__h175172 or out_exp__h175791 or _theResult___exp__h175788)
begin
case (guard__h175172)
2'b0, 2'b01:
CASE_guard75172_0b0_0_0b1_0_0b10_out_exp75791__ETC__q77 = 11'd0;
2'b10:
CASE_guard75172_0b0_0_0b1_0_0b10_out_exp75791__ETC__q77 =
out_exp__h175791;
2'b11:
CASE_guard75172_0b0_0_0b1_0_0b10_out_exp75791__ETC__q77 =
_theResult___exp__h175788;
endcase
end
always@(guard__h175172 or _theResult___exp__h175788)
begin
case (guard__h175172)
2'b0: CASE_guard75172_0b0_0_0b1_theResult___exp75788_ETC__q78 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard75172_0b0_0_0b1_theResult___exp75788_ETC__q78 =
_theResult___exp__h175788;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h175172 or
_theResult___exp__h175788 or
CASE_guard75172_0b0_0_0b1_theResult___exp75788_ETC__q78)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q79 =
(guard__h175172 == 2'b0) ? 11'd0 : _theResult___exp__h175788;
3'd4:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q79 =
CASE_guard75172_0b0_0_0b1_theResult___exp75788_ETC__q78;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q79 =
11'd0;
endcase
end
always@(guard__h175901 or x__h175916 or _theResult___exp__h176543)
begin
case (guard__h175901)
2'b0:
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_th_ETC__q80 =
x__h175916[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_th_ETC__q80 =
_theResult___exp__h176543;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h175916 or
guard__h175901 or
_theResult___exp__h176543 or
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_th_ETC__q80)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2059 =
x__h175916[10:0];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2059 =
(guard__h175901 == 2'b0) ?
x__h175916[10:0] :
_theResult___exp__h176543;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2059 =
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_th_ETC__q80;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2059 =
11'd0;
endcase
end
always@(guard__h175901 or
x__h175916 or out_exp__h176546 or _theResult___exp__h176543)
begin
case (guard__h175901)
2'b0, 2'b01:
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_x7_ETC__q81 =
x__h175916[10:0];
2'b10:
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_x7_ETC__q81 =
out_exp__h176546;
2'b11:
CASE_guard75901_0b0_x75916_BITS_10_TO_0_0b1_x7_ETC__q81 =
_theResult___exp__h176543;
endcase
end
always@(guard__h175172 or sfd___3__h175162 or _theResult___sfd__h175789)
begin
case (guard__h175172)
2'b0:
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q82 =
sfd___3__h175162[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q82 =
_theResult___sfd__h175789;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175162 or
guard__h175172 or
_theResult___sfd__h175789 or
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q82)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2083 =
sfd___3__h175162[63:12];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2083 =
(guard__h175172 == 2'b0) ?
sfd___3__h175162[63:12] :
_theResult___sfd__h175789;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2083 =
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q82;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2083 =
52'd0;
endcase
end
always@(guard__h175172 or
sfd___3__h175162 or out_sfd__h175792 or _theResult___sfd__h175789)
begin
case (guard__h175172)
2'b0, 2'b01:
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q83 =
sfd___3__h175162[63:12];
2'b10:
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q83 =
out_sfd__h175792;
2'b11:
CASE_guard75172_0b0_sfd___375162_BITS_63_TO_12_ETC__q83 =
_theResult___sfd__h175789;
endcase
end
always@(guard__h175901 or sfd___3__h175162 or _theResult___sfd__h176544)
begin
case (guard__h175901)
2'b0:
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q84 =
sfd___3__h175162[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q84 =
_theResult___sfd__h176544;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175162 or
guard__h175901 or
_theResult___sfd__h176544 or
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q84)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2098 =
sfd___3__h175162[62:11];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2098 =
(guard__h175901 == 2'b0) ?
sfd___3__h175162[62:11] :
_theResult___sfd__h176544;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2098 =
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q84;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d2098 =
52'd0;
endcase
end
always@(guard__h175901 or
sfd___3__h175162 or out_sfd__h176547 or _theResult___sfd__h176544)
begin
case (guard__h175901)
2'b0, 2'b01:
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q85 =
sfd___3__h175162[62:11];
2'b10:
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q85 =
out_sfd__h176547;
2'b11:
CASE_guard75901_0b0_sfd___375162_BITS_62_TO_11_ETC__q85 =
_theResult___sfd__h176544;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
_theResult___fst_exp__h135811 or
_theResult___fst_exp__h145457 or
_theResult___fst_exp__h154834 or
_theResult___fst_exp__h166081 or _theResult___fst_exp__h176773)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5, 5'd6, 5'd7:
_theResult___fst_exp__h176790 = execFpuSimple_rVal1[62:52];
5'd8,
5'd9,
5'd11,
5'd12,
5'd13,
5'd14,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24:
_theResult___fst_exp__h176790 = 11'd0;
5'd10: _theResult___fst_exp__h176790 = _theResult___fst_exp__h135811;
5'd15: _theResult___fst_exp__h176790 = _theResult___fst_exp__h145457;
5'd16: _theResult___fst_exp__h176790 = _theResult___fst_exp__h154834;
5'd17: _theResult___fst_exp__h176790 = _theResult___fst_exp__h166081;
5'd18: _theResult___fst_exp__h176790 = _theResult___fst_exp__h176773;
default: _theResult___fst_exp__h176790 = 11'd0;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
_theResult___fst_sfd__h135812 or
_theResult___fst_sfd__h145458 or
_theResult___fst_sfd__h154835 or
_theResult___fst_sfd__h166082 or
_theResult___fst_sfd__h176774 or
_theResult___fst_sfd__h96998 or
_theResult___fst_sfd__h97058 or _theResult___fst_sfd__h97118)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5, 5'd6, 5'd7:
_theResult___fst_sfd__h176791 = execFpuSimple_rVal1[51:0];
5'd8, 5'd9, 5'd11, 5'd12, 5'd13, 5'd14, 5'd22, 5'd23, 5'd24:
_theResult___fst_sfd__h176791 = 52'd0;
5'd10: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h135812;
5'd15: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h145458;
5'd16: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h154835;
5'd17: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h166082;
5'd18: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h176774;
5'd19: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h96998;
5'd20: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h97058;
5'd21: _theResult___fst_sfd__h176791 = _theResult___fst_sfd__h97118;
default: _theResult___fst_sfd__h176791 = 52'd0;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 or
_theResult___fst_exp__h145314 or
_theResult___fst_sfd__h145315 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 or
_theResult___fst_exp__h154703 or
_theResult___fst_sfd__h154704 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 ||
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1017 &&
_theResult___fst_exp__h145314 == 11'd2047 &&
_theResult___fst_sfd__h145315 == 52'd0);
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 ||
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1672 &&
_theResult___fst_exp__h154703 == 11'd2047 &&
_theResult___fst_sfd__h154704 == 52'd0);
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2387;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2465 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2460;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263 or
execFpuSimple_rVal1 or
value_BIT_23___h109067 or
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239 or
int_val_rnd__h94501 or
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175 or
IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2239;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94501[115:32] != 84'd0 ||
!IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d175);
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94501 != 116'd0 && execFpuSimple_rVal1[63] ||
int_val_rnd__h94501[115:32] != 84'd0);
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] != 52'd0 ||
execFpuSimple_rVal1[62:52] == 11'd2047 &&
execFpuSimple_rVal1[51:0] == 52'd0 ||
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(int_val_rnd__h94501[115:64] != 52'd0 ||
!IF_1075_MINUS_0_CONCAT_execFpuSimple_rVal1_BIT_ETC___d198);
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 =
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d2263;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2494;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d2502 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2497;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579 or
value_BIT_23___h109067 or
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541 or
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 or
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 or
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 or
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] == 23'd0) &&
(execFpuSimple_rVal1[30:23] != 8'd255 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
(value_BIT_23___h109067 ||
execFpuSimple_rVal1[22:0] != 23'd0) &&
IF_execFpuSimple_rVal1_BITS_30_TO_23_23_EQ_0_2_ETC___d2522;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2531;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2537;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2541;
5'd14:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
NOT_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_204_ETC___d2546;
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1015 &&
!_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_BI_ETC___d1016 &&
IF_32_MINUS_0_CONCAT_IF_IF_execFpuSimple_rVal1_ETC___d2551;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1670 &&
!_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d1671 &&
IF_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BI_ETC___d2559;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d2570;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2589 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d2579;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or int_val__h5744)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q86 =
execFpuSimple_rVal1[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal1[31];
3'd4:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q86 =
int_val__h5744[1];
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_NOT__ETC__q86 =
execFpuSimple_fpu_inst[3:1] == 3'd2 &&
execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h16427 or
_theResult___fst_exp__h24526 or _theResult___exp__h25052)
begin
case (guard__h16427)
2'b0:
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q99 =
_theResult___fst_exp__h24526;
2'b01, 2'b10, 2'b11:
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q99 =
_theResult___exp__h25052;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h24526 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192 or
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q99)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198 =
_theResult___fst_exp__h24526;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3194;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3192;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198 =
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q99;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3198 =
8'd0;
endcase
end
always@(guard__h16427 or
_theResult___fst_exp__h24526 or
out_exp__h25055 or _theResult___exp__h25052)
begin
case (guard__h16427)
2'b0, 2'b01:
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q100 =
_theResult___fst_exp__h24526;
2'b10:
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q100 =
out_exp__h25055;
2'b11:
CASE_guard6427_0b0_theResult___fst_exp4526_0b1_ETC__q100 =
_theResult___exp__h25052;
endcase
end
always@(guard__h25164 or
_theResult___fst_exp__h33212 or _theResult___exp__h33664)
begin
case (guard__h25164)
2'b0:
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q101 =
_theResult___fst_exp__h33212;
2'b01, 2'b10, 2'b11:
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q101 =
_theResult___exp__h33664;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h33212 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309 or
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q101)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315 =
_theResult___fst_exp__h33212;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3311;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3309;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315 =
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q101;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3315 =
8'd0;
endcase
end
always@(guard__h25164 or
_theResult___fst_exp__h33212 or
out_exp__h33667 or _theResult___exp__h33664)
begin
case (guard__h25164)
2'b0, 2'b01:
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q102 =
_theResult___fst_exp__h33212;
2'b10:
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q102 =
out_exp__h33667;
2'b11:
CASE_guard5164_0b0_theResult___fst_exp3212_0b1_ETC__q102 =
_theResult___exp__h33664;
endcase
end
always@(guard__h43017 or
_theResult___fst_exp__h51094 or _theResult___exp__h51571)
begin
case (guard__h43017)
2'b0:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103 =
_theResult___fst_exp__h51094;
2'b01, 2'b10, 2'b11:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103 =
_theResult___exp__h51571;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h51094 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702 or
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
_theResult___fst_exp__h51094;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3704;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3702;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q103;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3708 =
8'd0;
endcase
end
always@(guard__h43017 or
_theResult___fst_exp__h51094 or
out_exp__h51574 or _theResult___exp__h51571)
begin
case (guard__h43017)
2'b0, 2'b01:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 =
_theResult___fst_exp__h51094;
2'b10:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 =
out_exp__h51574;
2'b11:
CASE_guard3017_0b0_theResult___fst_exp1094_0b1_ETC__q104 =
_theResult___exp__h51571;
endcase
end
always@(guard__h34153 or
_theResult___fst_exp__h42379 or _theResult___exp__h42905)
begin
case (guard__h34153)
2'b0:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105 =
_theResult___fst_exp__h42379;
2'b01, 2'b10, 2'b11:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105 =
_theResult___exp__h42905;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___fst_exp__h42379 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633 or
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
_theResult___fst_exp__h42379;
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3635;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3633;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q105;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3639 =
8'd0;
endcase
end
always@(guard__h34153 or
_theResult___fst_exp__h42379 or
out_exp__h42908 or _theResult___exp__h42905)
begin
case (guard__h34153)
2'b0, 2'b01:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 =
_theResult___fst_exp__h42379;
2'b10:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 =
out_exp__h42908;
2'b11:
CASE_guard4153_0b0_theResult___fst_exp2379_0b1_ETC__q106 =
_theResult___exp__h42905;
endcase
end
always@(guard__h16427 or sfdin__h24520 or _theResult___sfd__h25053)
begin
case (guard__h16427)
2'b0:
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q107 =
sfdin__h24520[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q107 =
_theResult___sfd__h25053;
endcase
end
always@(execFpuSimple_fpu_inst or
sfdin__h24520 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735 or
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733 or
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q107)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739 =
sfdin__h24520[56:34];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3735;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739 =
IF_IF_IF_IF_0b0_CONCAT_NOT_execFpuSimple_rVal1_ETC___d3733;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739 =
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q107;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3739 =
23'd0;
endcase
end
always@(guard__h16427 or
sfdin__h24520 or out_sfd__h25056 or _theResult___sfd__h25053)
begin
case (guard__h16427)
2'b0, 2'b01:
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q108 =
sfdin__h24520[56:34];
2'b10:
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q108 =
out_sfd__h25056;
2'b11:
CASE_guard6427_0b0_sfdin4520_BITS_56_TO_34_0b1_ETC__q108 =
_theResult___sfd__h25053;
endcase
end
always@(guard__h25164 or
_theResult___snd__h33163 or _theResult___sfd__h33665)
begin
case (guard__h25164)
2'b0:
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q109 =
_theResult___snd__h33163[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q109 =
_theResult___sfd__h33665;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h33163 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752 or
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q109)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758 =
_theResult___snd__h33163[56:34];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3754;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3752;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758 =
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q109;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3758 =
23'd0;
endcase
end
always@(guard__h25164 or
_theResult___snd__h33163 or
out_sfd__h33668 or _theResult___sfd__h33665)
begin
case (guard__h25164)
2'b0, 2'b01:
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q110 =
_theResult___snd__h33163[56:34];
2'b10:
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q110 =
out_sfd__h33668;
2'b11:
CASE_guard5164_0b0_theResult___snd3163_BITS_56_ETC__q110 =
_theResult___sfd__h33665;
endcase
end
always@(guard__h34153 or sfdin__h42373 or _theResult___sfd__h42906)
begin
case (guard__h34153)
2'b0:
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q111 =
sfdin__h42373[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q111 =
_theResult___sfd__h42906;
endcase
end
always@(execFpuSimple_fpu_inst or
sfdin__h42373 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781 or
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779 or
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q111)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785 =
sfdin__h42373[56:34];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3781;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785 =
IF_IF_IF_IF_3970_MINUS_SEXT_execFpuSimple_rVal_ETC___d3779;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785 =
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q111;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3785 =
23'd0;
endcase
end
always@(guard__h34153 or
sfdin__h42373 or out_sfd__h42909 or _theResult___sfd__h42906)
begin
case (guard__h34153)
2'b0, 2'b01:
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q112 =
sfdin__h42373[56:34];
2'b10:
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q112 =
out_sfd__h42909;
2'b11:
CASE_guard4153_0b0_sfdin2373_BITS_56_TO_34_0b1_ETC__q112 =
_theResult___sfd__h42906;
endcase
end
always@(guard__h43017 or
_theResult___snd__h51040 or _theResult___sfd__h51572)
begin
case (guard__h43017)
2'b0:
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q113 =
_theResult___snd__h51040[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q113 =
_theResult___sfd__h51572;
endcase
end
always@(execFpuSimple_fpu_inst or
_theResult___snd__h51040 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800 or
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798 or
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q113)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804 =
_theResult___snd__h51040[56:34];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3800;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804 =
IF_IF_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_E_ETC___d3798;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804 =
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q113;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3804 =
23'd0;
endcase
end
always@(guard__h43017 or
_theResult___snd__h51040 or
out_sfd__h51575 or _theResult___sfd__h51572)
begin
case (guard__h43017)
2'b0, 2'b01:
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q114 =
_theResult___snd__h51040[56:34];
2'b10:
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q114 =
out_sfd__h51575;
2'b11:
CASE_guard3017_0b0_theResult___snd1040_BITS_56_ETC__q114 =
_theResult___sfd__h51572;
endcase
end
always@(guard__h56904 or _theResult___exp__h57317)
begin
case (guard__h56904)
2'b0: CASE_guard6904_0b0_0_0b1_theResult___exp7317_0_ETC__q117 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard6904_0b0_0_0b1_theResult___exp7317_0_ETC__q117 =
_theResult___exp__h57317;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990 or
guard__h56904 or
execFpuSimple_rVal1 or
_theResult___exp__h57317 or
CASE_guard6904_0b0_0_0b1_theResult___exp7317_0_ETC__q117)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3993 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d3990;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3993 =
(guard__h56904 == 2'b0 || execFpuSimple_rVal1[31]) ?
8'd0 :
_theResult___exp__h57317;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3993 =
CASE_guard6904_0b0_0_0b1_theResult___exp7317_0_ETC__q117;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3993 =
8'd0;
endcase
end
always@(guard__h56904 or out_exp__h57320 or _theResult___exp__h57317)
begin
case (guard__h56904)
2'b0, 2'b01:
CASE_guard6904_0b0_0_0b1_0_0b10_out_exp7320_0b_ETC__q118 = 8'd0;
2'b10:
CASE_guard6904_0b0_0_0b1_0_0b10_out_exp7320_0b_ETC__q118 =
out_exp__h57320;
2'b11:
CASE_guard6904_0b0_0_0b1_0_0b10_out_exp7320_0b_ETC__q118 =
_theResult___exp__h57317;
endcase
end
always@(guard__h57431 or x__h57446 or _theResult___exp__h57870)
begin
case (guard__h57431)
2'b0:
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_theRe_ETC__q119 =
x__h57446[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_theRe_ETC__q119 =
_theResult___exp__h57870;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h57446 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034 or
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_theRe_ETC__q119)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040 =
x__h57446[7:0];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4036;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4034;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040 =
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_theRe_ETC__q119;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4040 =
8'd0;
endcase
end
always@(guard__h57431 or
x__h57446 or out_exp__h57873 or _theResult___exp__h57870)
begin
case (guard__h57431)
2'b0, 2'b01:
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_x7446_ETC__q120 =
x__h57446[7:0];
2'b10:
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_x7446_ETC__q120 =
out_exp__h57873;
2'b11:
CASE_guard7431_0b0_x7446_BITS_7_TO_0_0b1_x7446_ETC__q120 =
_theResult___exp__h57870;
endcase
end
always@(guard__h56904 or sfd___3__h56894 or _theResult___sfd__h57318)
begin
case (guard__h56904)
2'b0:
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q121 =
sfd___3__h56894[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q121 =
_theResult___sfd__h57318;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h56894 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062 or
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q121)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068 =
sfd___3__h56894[31:9];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4064;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4062;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068 =
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q121;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4068 =
23'd0;
endcase
end
always@(guard__h56904 or
sfd___3__h56894 or out_sfd__h57321 or _theResult___sfd__h57318)
begin
case (guard__h56904)
2'b0, 2'b01:
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q122 =
sfd___3__h56894[31:9];
2'b10:
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q122 =
out_sfd__h57321;
2'b11:
CASE_guard6904_0b0_sfd___36894_BITS_31_TO_9_0b_ETC__q122 =
_theResult___sfd__h57318;
endcase
end
always@(guard__h57431 or sfd___3__h56894 or _theResult___sfd__h57871)
begin
case (guard__h57431)
2'b0:
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q123 =
sfd___3__h56894[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q123 =
_theResult___sfd__h57871;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h56894 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082 or
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080 or
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q123)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086 =
sfd___3__h56894[30:8];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4082;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086 =
IF_IF_IF_execFpuSimple_rVal1_BIT_31_05_THEN_NE_ETC___d4080;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086 =
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q123;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4086 =
23'd0;
endcase
end
always@(guard__h57431 or
sfd___3__h56894 or out_sfd__h57874 or _theResult___sfd__h57871)
begin
case (guard__h57431)
2'b0, 2'b01:
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q124 =
sfd___3__h56894[30:8];
2'b10:
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q124 =
out_sfd__h57874;
2'b11:
CASE_guard7431_0b0_sfd___36894_BITS_30_TO_8_0b_ETC__q124 =
_theResult___sfd__h57871;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h56904)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4098 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4098 =
(guard__h56904 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h56904 == 2'b01 || guard__h56904 == 2'b10 ||
guard__h56904 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4098 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h56904 or execFpuSimple_rVal1)
begin
case (guard__h56904)
2'b0, 2'b01, 2'b10:
CASE_guard6904_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard6904_0b0_execFpuSimple_rVal1_BIT_31__ETC__q125 =
guard__h56904 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h57431)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4105 =
execFpuSimple_rVal1[31];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4105 =
(guard__h57431 == 2'b0) ?
execFpuSimple_rVal1[31] :
(guard__h57431 == 2'b01 || guard__h57431 == 2'b10 ||
guard__h57431 == 2'b11) &&
execFpuSimple_rVal1[31];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4105 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[31];
endcase
end
always@(guard__h57431 or execFpuSimple_rVal1)
begin
case (guard__h57431)
2'b0, 2'b01, 2'b10:
CASE_guard7431_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126 =
execFpuSimple_rVal1[31];
2'd3:
CASE_guard7431_0b0_execFpuSimple_rVal1_BIT_31__ETC__q126 =
guard__h57431 == 2'b11 && execFpuSimple_rVal1[31];
endcase
end
always@(guard__h73586 or _theResult___exp__h73999)
begin
case (guard__h73586)
2'b0: CASE_guard3586_0b0_0_0b1_theResult___exp3999_0_ETC__q127 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard3586_0b0_0_0b1_theResult___exp3999_0_ETC__q127 =
_theResult___exp__h73999;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151 or
guard__h73586 or
execFpuSimple_rVal1 or
_theResult___exp__h73999 or
CASE_guard3586_0b0_0_0b1_theResult___exp3999_0_ETC__q127)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4154 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4151;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4154 =
(guard__h73586 == 2'b0 || execFpuSimple_rVal1[63]) ?
8'd0 :
_theResult___exp__h73999;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4154 =
CASE_guard3586_0b0_0_0b1_theResult___exp3999_0_ETC__q127;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4154 =
8'd0;
endcase
end
always@(guard__h73586 or out_exp__h74002 or _theResult___exp__h73999)
begin
case (guard__h73586)
2'b0, 2'b01:
CASE_guard3586_0b0_0_0b1_0_0b10_out_exp4002_0b_ETC__q128 = 8'd0;
2'b10:
CASE_guard3586_0b0_0_0b1_0_0b10_out_exp4002_0b_ETC__q128 =
out_exp__h74002;
2'b11:
CASE_guard3586_0b0_0_0b1_0_0b10_out_exp4002_0b_ETC__q128 =
_theResult___exp__h73999;
endcase
end
always@(guard__h74113 or x__h74128 or _theResult___exp__h74552)
begin
case (guard__h74113)
2'b0:
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_theRe_ETC__q129 =
x__h74128[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_theRe_ETC__q129 =
_theResult___exp__h74552;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h74128 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195 or
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_theRe_ETC__q129)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201 =
x__h74128[7:0];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4197;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4195;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201 =
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_theRe_ETC__q129;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4201 =
8'd0;
endcase
end
always@(guard__h74113 or
x__h74128 or out_exp__h74555 or _theResult___exp__h74552)
begin
case (guard__h74113)
2'b0, 2'b01:
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_x4128_ETC__q130 =
x__h74128[7:0];
2'b10:
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_x4128_ETC__q130 =
out_exp__h74555;
2'b11:
CASE_guard4113_0b0_x4128_BITS_7_TO_0_0b1_x4128_ETC__q130 =
_theResult___exp__h74552;
endcase
end
always@(guard__h73586 or sfd___3__h164456 or _theResult___sfd__h74000)
begin
case (guard__h73586)
2'b0:
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q131 =
sfd___3__h164456[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q131 =
_theResult___sfd__h74000;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164456 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223 or
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q131)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229 =
sfd___3__h164456[63:41];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4225;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4223;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229 =
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q131;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4229 =
23'd0;
endcase
end
always@(guard__h73586 or
sfd___3__h164456 or out_sfd__h74003 or _theResult___sfd__h74000)
begin
case (guard__h73586)
2'b0, 2'b01:
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q132 =
sfd___3__h164456[63:41];
2'b10:
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q132 =
out_sfd__h74003;
2'b11:
CASE_guard3586_0b0_sfd___364456_BITS_63_TO_41__ETC__q132 =
_theResult___sfd__h74000;
endcase
end
always@(guard__h74113 or sfd___3__h164456 or _theResult___sfd__h74553)
begin
case (guard__h74113)
2'b0:
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q133 =
sfd___3__h164456[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q133 =
_theResult___sfd__h74553;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h164456 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243 or
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241 or
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q133)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247 =
sfd___3__h164456[62:40];
3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4243;
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247 =
IF_IF_IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_ETC___d4241;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247 =
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q133;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4247 =
23'd0;
endcase
end
always@(guard__h74113 or
sfd___3__h164456 or out_sfd__h74556 or _theResult___sfd__h74553)
begin
case (guard__h74113)
2'b0, 2'b01:
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q134 =
sfd___3__h164456[62:40];
2'b10:
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q134 =
out_sfd__h74556;
2'b11:
CASE_guard4113_0b0_sfd___364456_BITS_62_TO_40__ETC__q134 =
_theResult___sfd__h74553;
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h73586)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4259 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4259 =
(guard__h73586 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h73586 == 2'b01 || guard__h73586 == 2'b10 ||
guard__h73586 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4259 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h73586 or execFpuSimple_rVal1)
begin
case (guard__h73586)
2'b0, 2'b01, 2'b10:
CASE_guard3586_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard3586_0b0_execFpuSimple_rVal1_BIT_63__ETC__q135 =
guard__h73586 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h74113)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4266 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4266 =
(guard__h74113 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h74113 == 2'b01 || guard__h74113 == 2'b10 ||
guard__h74113 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4266 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h74113 or execFpuSimple_rVal1)
begin
case (guard__h74113)
2'b0, 2'b01, 2'b10:
CASE_guard4113_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard4113_0b0_execFpuSimple_rVal1_BIT_63__ETC__q136 =
guard__h74113 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h16427)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3820 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3820 =
(guard__h16427 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h16427 == 2'b01 || guard__h16427 == 2'b10 ||
guard__h16427 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3820 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h16427 or execFpuSimple_rVal1)
begin
case (guard__h16427)
2'b0, 2'b01, 2'b10:
CASE_guard6427_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard6427_0b0_execFpuSimple_rVal1_BIT_63__ETC__q137 =
guard__h16427 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h25164)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3828 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3828 =
(guard__h25164 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h25164 == 2'b01 || guard__h25164 == 2'b10 ||
guard__h25164 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3828 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h25164 or execFpuSimple_rVal1)
begin
case (guard__h25164)
2'b0, 2'b01, 2'b10:
CASE_guard5164_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard5164_0b0_execFpuSimple_rVal1_BIT_63__ETC__q138 =
guard__h25164 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h34153)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3838 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3838 =
(guard__h34153 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h34153 == 2'b01 || guard__h34153 == 2'b10 ||
guard__h34153 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3838 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h34153 or execFpuSimple_rVal1)
begin
case (guard__h34153)
2'b0, 2'b01, 2'b10:
CASE_guard4153_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard4153_0b0_execFpuSimple_rVal1_BIT_63__ETC__q139 =
guard__h34153 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(execFpuSimple_fpu_inst or execFpuSimple_rVal1 or guard__h43017)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd2, 3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3846 =
execFpuSimple_rVal1[63];
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3846 =
(guard__h43017 == 2'b0) ?
execFpuSimple_rVal1[63] :
(guard__h43017 == 2'b01 || guard__h43017 == 2'b10 ||
guard__h43017 == 2'b11) &&
execFpuSimple_rVal1[63];
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d3846 =
execFpuSimple_fpu_inst[3:1] == 3'd1 &&
execFpuSimple_rVal1[63];
endcase
end
always@(guard__h43017 or execFpuSimple_rVal1)
begin
case (guard__h43017)
2'b0, 2'b01, 2'b10:
CASE_guard3017_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140 =
execFpuSimple_rVal1[63];
2'd3:
CASE_guard3017_0b0_execFpuSimple_rVal1_BIT_63__ETC__q140 =
guard__h43017 == 2'b11 && execFpuSimple_rVal1[63];
endcase
end
always@(guard__h62759 or out_exp__h63175 or _theResult___exp__h63172)
begin
case (guard__h62759)
2'b0, 2'b01:
CASE_guard2759_0b0_0_0b1_0_0b10_out_exp3175_0b_ETC__q143 = 8'd0;
2'b10:
CASE_guard2759_0b0_0_0b1_0_0b10_out_exp3175_0b_ETC__q143 =
out_exp__h63175;
2'b11:
CASE_guard2759_0b0_0_0b1_0_0b10_out_exp3175_0b_ETC__q143 =
_theResult___exp__h63172;
endcase
end
always@(guard__h62759 or _theResult___exp__h63172)
begin
case (guard__h62759)
2'b0: CASE_guard2759_0b0_0_0b1_theResult___exp3172_0_ETC__q144 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard2759_0b0_0_0b1_theResult___exp3172_0_ETC__q144 =
_theResult___exp__h63172;
endcase
end
always@(execFpuSimple_fpu_inst or
guard__h62759 or
_theResult___exp__h63172 or
CASE_guard2759_0b0_0_0b1_theResult___exp3172_0_ETC__q144)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd3:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q145 =
(guard__h62759 == 2'b0) ? 8'd0 : _theResult___exp__h63172;
3'd4:
CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q145 =
CASE_guard2759_0b0_0_0b1_theResult___exp3172_0_ETC__q144;
default: CASE_execFpuSimple_fpu_inst_BITS_3_TO_1_3_IF_g_ETC__q145 =
8'd0;
endcase
end
always@(guard__h63285 or x__h63300 or _theResult___exp__h63724)
begin
case (guard__h63285)
2'b0:
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_theRe_ETC__q146 =
x__h63300[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_theRe_ETC__q146 =
_theResult___exp__h63724;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h63300 or
guard__h63285 or
_theResult___exp__h63724 or
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_theRe_ETC__q146)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4409 =
x__h63300[7:0];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4409 =
(guard__h63285 == 2'b0) ?
x__h63300[7:0] :
_theResult___exp__h63724;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4409 =
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_theRe_ETC__q146;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4409 =
8'd0;
endcase
end
always@(guard__h63285 or
x__h63300 or out_exp__h63727 or _theResult___exp__h63724)
begin
case (guard__h63285)
2'b0, 2'b01:
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_x3300_ETC__q147 =
x__h63300[7:0];
2'b10:
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_x3300_ETC__q147 =
out_exp__h63727;
2'b11:
CASE_guard3285_0b0_x3300_BITS_7_TO_0_0b1_x3300_ETC__q147 =
_theResult___exp__h63724;
endcase
end
always@(guard__h62759 or sfd___3__h62749 or _theResult___sfd__h63173)
begin
case (guard__h62759)
2'b0:
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q148 =
sfd___3__h62749[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q148 =
_theResult___sfd__h63173;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h62749 or
guard__h62759 or
_theResult___sfd__h63173 or
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q148)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4433 =
sfd___3__h62749[31:9];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4433 =
(guard__h62759 == 2'b0) ?
sfd___3__h62749[31:9] :
_theResult___sfd__h63173;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4433 =
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q148;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4433 =
23'd0;
endcase
end
always@(guard__h62759 or
sfd___3__h62749 or out_sfd__h63176 or _theResult___sfd__h63173)
begin
case (guard__h62759)
2'b0, 2'b01:
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q149 =
sfd___3__h62749[31:9];
2'b10:
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q149 =
out_sfd__h63176;
2'b11:
CASE_guard2759_0b0_sfd___32749_BITS_31_TO_9_0b_ETC__q149 =
_theResult___sfd__h63173;
endcase
end
always@(guard__h63285 or sfd___3__h62749 or _theResult___sfd__h63725)
begin
case (guard__h63285)
2'b0:
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q150 =
sfd___3__h62749[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q150 =
_theResult___sfd__h63725;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h62749 or
guard__h63285 or
_theResult___sfd__h63725 or
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q150)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4448 =
sfd___3__h62749[30:8];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4448 =
(guard__h63285 == 2'b0) ?
sfd___3__h62749[30:8] :
_theResult___sfd__h63725;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4448 =
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q150;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4448 =
23'd0;
endcase
end
always@(guard__h63285 or
sfd___3__h62749 or out_sfd__h63728 or _theResult___sfd__h63725)
begin
case (guard__h63285)
2'b0, 2'b01:
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q151 =
sfd___3__h62749[30:8];
2'b10:
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q151 =
out_sfd__h63728;
2'b11:
CASE_guard3285_0b0_sfd___32749_BITS_30_TO_8_0b_ETC__q151 =
_theResult___sfd__h63725;
endcase
end
always@(guard__h84412 or x__h84427 or _theResult___exp__h84851)
begin
case (guard__h84412)
2'b0:
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_theRe_ETC__q152 =
x__h84427[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_theRe_ETC__q152 =
_theResult___exp__h84851;
endcase
end
always@(execFpuSimple_fpu_inst or
x__h84427 or
guard__h84412 or
_theResult___exp__h84851 or
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_theRe_ETC__q152)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4543 =
x__h84427[7:0];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4543 =
(guard__h84412 == 2'b0) ?
x__h84427[7:0] :
_theResult___exp__h84851;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4543 =
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_theRe_ETC__q152;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4543 =
8'd0;
endcase
end
always@(guard__h84412 or
x__h84427 or out_exp__h84854 or _theResult___exp__h84851)
begin
case (guard__h84412)
2'b0, 2'b01:
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_x4427_ETC__q153 =
x__h84427[7:0];
2'b10:
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_x4427_ETC__q153 =
out_exp__h84854;
2'b11:
CASE_guard4412_0b0_x4427_BITS_7_TO_0_0b1_x4427_ETC__q153 =
_theResult___exp__h84851;
endcase
end
always@(guard__h83886 or sfd___3__h175162 or _theResult___sfd__h84300)
begin
case (guard__h83886)
2'b0:
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q154 =
sfd___3__h175162[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q154 =
_theResult___sfd__h84300;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175162 or
guard__h83886 or
_theResult___sfd__h84300 or
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q154)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4567 =
sfd___3__h175162[63:41];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4567 =
(guard__h83886 == 2'b0) ?
sfd___3__h175162[63:41] :
_theResult___sfd__h84300;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4567 =
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q154;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4567 =
23'd0;
endcase
end
always@(guard__h83886 or
sfd___3__h175162 or out_sfd__h84303 or _theResult___sfd__h84300)
begin
case (guard__h83886)
2'b0, 2'b01:
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q155 =
sfd___3__h175162[63:41];
2'b10:
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q155 =
out_sfd__h84303;
2'b11:
CASE_guard3886_0b0_sfd___375162_BITS_63_TO_41__ETC__q155 =
_theResult___sfd__h84300;
endcase
end
always@(guard__h84412 or sfd___3__h175162 or _theResult___sfd__h84852)
begin
case (guard__h84412)
2'b0:
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q156 =
sfd___3__h175162[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q156 =
_theResult___sfd__h84852;
endcase
end
always@(execFpuSimple_fpu_inst or
sfd___3__h175162 or
guard__h84412 or
_theResult___sfd__h84852 or
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q156)
begin
case (execFpuSimple_fpu_inst[3:1])
3'd1, 3'd2:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4582 =
sfd___3__h175162[62:40];
3'd3:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4582 =
(guard__h84412 == 2'b0) ?
sfd___3__h175162[62:40] :
_theResult___sfd__h84852;
3'd4:
IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4582 =
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q156;
default: IF_execFpuSimple_fpu_inst_BITS_3_TO_1_41_EQ_4__ETC___d4582 =
23'd0;
endcase
end
always@(guard__h84412 or
sfd___3__h175162 or out_sfd__h84855 or _theResult___sfd__h84852)
begin
case (guard__h84412)
2'b0, 2'b01:
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q157 =
sfd___3__h175162[62:40];
2'b10:
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q157 =
out_sfd__h84855;
2'b11:
CASE_guard4412_0b0_sfd___375162_BITS_62_TO_40__ETC__q157 =
_theResult___sfd__h84852;
endcase
end
always@(execFpuSimple_fpu_inst or
NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853 or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274 or
execFpuSimple_rVal2 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31];
5'd6:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
execFpuSimple_rVal2[63:32] != 32'hFFFFFFFF ||
!execFpuSimple_rVal2[31];
5'd7:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
(execFpuSimple_rVal1[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal1[31]) ^
(execFpuSimple_rVal2[63:32] == 32'hFFFFFFFF &&
execFpuSimple_rVal2[31]);
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_5_4_T_ETC___d4280 =
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
((execFpuSimple_fpu_inst[8:4] == 5'd10) ?
NOT_IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ__ETC___d3853 :
execFpuSimple_fpu_inst[8:4] != 5'd11 &&
execFpuSimple_fpu_inst[8:4] != 5'd12 &&
execFpuSimple_fpu_inst[8:4] != 5'd13 &&
execFpuSimple_fpu_inst[8:4] != 5'd14 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4274);
endcase
end
always@(execFpuSimple_fpu_inst or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625 or
_theResult___fst_exp__h51970 or
_theResult___fst_sfd__h51971 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415 or
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549 or
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd5, 5'd6, 5'd7:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d2625;
5'd8,
5'd9,
5'd11,
5'd12,
5'd13,
5'd14,
5'd19,
5'd20,
5'd21,
5'd22,
5'd23,
5'd24:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 = 31'd0;
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
{ _theResult___fst_exp__h51970, _theResult___fst_sfd__h51971 };
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046 ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4046,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4090 };
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415 ==
8'd255 &&
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4415,
IF_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_45_ETC___d4452 };
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207 ==
8'd255 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4207,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_IF_exec_ETC___d4251 };
5'd18:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
(IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549 ==
8'd255 &&
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586 !=
23'd0) ?
31'h7FC00000 :
{ IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4549,
IF_execFpuSimple_rVal1_EQ_0_176_OR_NOT_execFpu_ETC___d4586 };
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4600 =
31'd0;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683 or
execFpuSimple_rVal1 or
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659 or
in1_exp__h4123 or
in1_sfd__h4124 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4659;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4667;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 == 23'd0 ||
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4670;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
in1_exp__h4123 == 8'd255 && in1_sfd__h4124 != 23'd0 ||
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4677;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 =
execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_14_9_AND_ETC___d4683;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788 or
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759 or
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4759;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4769;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4778;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4793 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4788;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828 or
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820 or
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 or
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
NOT_execFpuSimple_rVal1_BITS_31_TO_0_44_EQ_0_4_ETC___d4820;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
(execFpuSimple_rVal1[31] ||
execFpuSimple_rVal1_BIT_30_627_OR_execFpuSimpl_ETC___d2418) &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4330 &&
_32_MINUS_0_CONCAT_IF_execFpuSimple_rVal1_BIT_3_ETC___d4331;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4825;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_15_43_ETC___d4833 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4828;
endcase
end
always@(execFpuSimple_fpu_inst or
execFpuSimple_rVal1 or
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913 or
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873 or
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878 or
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886 or
execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895 or
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd10:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] == 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd2047 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
(execFpuSimple_rVal1[62:52] != 11'd0 ||
execFpuSimple_rVal1[51:0] != 52'd0) &&
IF_execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_0_9__ETC___d4854;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4863;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4869;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4873;
5'd14:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
NOT_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_E_ETC___d4878;
5'd15:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
IF_execFpuSimple_rVal1_BIT_31_05_THEN_NEG_exec_ETC___d4886;
5'd16:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_rVal1[31:0] != 32'd0 &&
execFpuSimple_rVal1_BIT_31_05_OR_execFpuSimple_ETC___d4895;
5'd17:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_rVal1 != 64'd0 &&
IF_execFpuSimple_rVal1_BIT_63_4_THEN_NEG_execF_ETC___d4904;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4923 =
execFpuSimple_fpu_inst[8:4] == 5'd18 &&
execFpuSimple_rVal1 != 64'd0 &&
execFpuSimple_rVal1_BIT_63_4_OR_execFpuSimple__ETC___d4913;
endcase
end
always@(execFpuSimple_fpu_inst or
dst_bits__h266 or
x__h219 or
x__h224 or
dst_bits__h251 or
dst_bits__h256 or
dst_bits__h261 or
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693 or
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711 or
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714 or
x__h4812 or
execFpuSimple_rVal1_BITS_31_TO_0__q158 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
x__h219;
5'd9:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
x__h224;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h251;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h256;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h261;
5'd19:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2693;
5'd20:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2711;
5'd21:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
IF_IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_ETC___d2714;
5'd22:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
{ 54'd0, x__h4812 };
5'd23:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
{ {32{execFpuSimple_rVal1_BITS_31_TO_0__q158[31]}},
execFpuSimple_rVal1_BITS_31_TO_0__q158 };
5'd24:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
{ 32'hFFFFFFFF, execFpuSimple_rVal1[31:0] };
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d2838 =
dst_bits__h266;
endcase
end
always@(execFpuSimple_fpu_inst or
dst_bits__h85590 or
x__h85553 or
x__h85558 or
dst_bits__h85575 or
dst_bits__h85580 or
dst_bits__h85585 or x__h93191 or execFpuSimple_rVal1)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
x__h85553;
5'd9:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
x__h85558;
5'd11:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85575;
5'd12:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85580;
5'd13:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85585;
5'd22:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
{ 54'd0, x__h93191 };
5'd23, 5'd24:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
execFpuSimple_rVal1;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_THE_ETC___d217 =
dst_bits__h85590;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607 or
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8, 5'd9, 5'd19:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4607;
5'd20, 5'd21:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690 =
IF_execFpuSimple_rVal1_BITS_63_TO_32_604_EQ_0x_ETC___d4612;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d4690 =
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d4687;
endcase
end
always@(execFpuSimple_fpu_inst or
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267 or
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192 or
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198)
begin
case (execFpuSimple_fpu_inst[8:4])
5'd8, 5'd9, 5'd19:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270 =
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2192;
5'd20, 5'd21:
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270 =
execFpuSimple_rVal1_BITS_62_TO_52_1_EQ_2047_2__ETC___d2198;
default: IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_8_OR__ETC___d2270 =
execFpuSimple_fpu_inst[8:4] != 5'd22 &&
execFpuSimple_fpu_inst[8:4] != 5'd5 &&
execFpuSimple_fpu_inst[8:4] != 5'd6 &&
execFpuSimple_fpu_inst[8:4] != 5'd7 &&
execFpuSimple_fpu_inst[8:4] != 5'd23 &&
execFpuSimple_fpu_inst[8:4] != 5'd24 &&
IF_execFpuSimple_fpu_inst_BITS_8_TO_4_EQ_10_4__ETC___d2267;
endcase
end
endmodule // module_execFpuSimple
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