83829590dd
Now able to run multiple ISA tests in a single simulation run connected to remote debugger DSharp, using either hart_reset or ndm_reset between tests to bring the system back into reset state. All Debug Module commands working: - dm_reset, hart_reset, ndm_reset - break (set breakpoint) - step - continue (until breakpoint of 'halt' command) - halt - read/write GPR, FPR, CSR, memory - elf_load
323 lines
11 KiB
Plaintext
323 lines
11 KiB
Plaintext
// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved
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package AXI4_Deburster;
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// ================================================================
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// This package defines a AXI4-slave-to-AXI4-slave conversion module.
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// The parameter interface is an AXI4-slave that carries no burst transactions.
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// The output interface is an AXI4-slave that carries burst transactions.
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// ================================================================
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// Bluespec library imports
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import Vector :: *;
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import FIFOF :: *;
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import SpecialFIFOs :: *;
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import ConfigReg :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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// ================================================================
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// Project imports
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import Semi_FIFOF :: *;
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import AXI4_Types :: *;
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// ================================================================
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// The interface for the fabric module
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interface AXI4_Deburster_IFC #(numeric type wd_id,
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numeric type wd_addr,
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numeric type wd_data,
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numeric type wd_user);
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method Action reset;
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// From master
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interface AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user) from_master;
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// To slave
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interface AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user) to_slave;
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endinterface
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// ================================================================
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// The Deburster module
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// The function parameter is an address-decode function, which
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// returns (True, slave-port-num) if address is mapped to slave-port-num
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// (False, ?) if address is unmapped to any slave port
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module mkAXI4_Deburster (AXI4_Deburster_IFC #(wd_id, wd_addr, wd_data, wd_user))
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provisos (Add #(a__, 8, wd_addr));
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// 0 quiet; 1: display start of burst; 2: display all traffic
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Integer cfg_verbosity = 0;
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Reg #(Bool) rg_reset <- mkReg (True);
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// Transactor facing master
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AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user)
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xactor_from_master <- mkAXI4_Slave_Xactor;
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// Transactor facing slave
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AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user)
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xactor_to_slave <- mkAXI4_Master_Xactor;
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// On a write-transaction, this register is the W-channel burst beat count
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// (0 => start of burst)
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Reg #(AXI4_Len) rg_w_beat_count <- mkReg (0);
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// On a write-transaction, records awlen for slave
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// Size of FIFO should cover slave latency
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FIFOF #(AXI4_Len) f_w_awlen <- mkSizedFIFOF (4);
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// On a write-transaction, this register is the B-channel burst beat count
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// which is the number of individual (non-burst) responses from the
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// slave to be combined into a single burst response to the master.
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// (0 => ready for next burst)
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Reg #(AXI4_Len) rg_b_beat_count <- mkReg (0);
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// On a burst write-transaction, all the individual slave responses
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// may not have the same 'resp' on the B channel. This register
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// remembers the first 'non-okay' resp (if any), to be returned to
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// the master in the burst response.
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Reg #(AXI4_Resp) rg_b_resp <- mkReg (axi4_resp_okay);
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// On a read-transaction, records arlen for slave
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// Size of FIFO should cover slave latency
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FIFOF #(AXI4_Len) f_r_arlen <- mkSizedFIFOF (4);
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// On a read-transaction, this register is the AR-channel burst beat count
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// (0 => start of next burst)
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Reg #(AXI4_Len) rg_ar_beat_count <- mkReg (0);
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// On a read-transaction, this register is the R-channel burst beat count
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// (0 => ready for next burst)
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Reg #(AXI4_Len) rg_r_beat_count <- mkReg (0);
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// ----------------------------------------------------------------
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// Compute address for beat
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function Bit #(wd_addr) fv_addr_for_beat (Bit #(wd_addr) start_addr,
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AXI4_Size axsize,
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AXI4_Burst axburst,
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AXI4_Len beat_count);
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Bit #(wd_addr) addr = start_addr;
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if (axburst == axburst_incr)
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addr = start_addr + (zeroExtend (beat_count) << pack (axsize));
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else if (axburst == axburst_wrap)
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addr = start_addr; // TODO: fixup
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return addr;
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endfunction
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// ----------------------------------------------------------------
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// RESET
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rule rl_reset (rg_reset);
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$display ("%0d: %m::AXI4_Deburster.rl_reset", cur_cycle);
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xactor_from_master.reset;
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xactor_to_slave.reset;
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f_w_awlen.clear;
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rg_w_beat_count <= 0;
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rg_b_beat_count <= 0;
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rg_b_resp <= axi4_resp_okay;
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f_r_arlen.clear;
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rg_ar_beat_count <= 0;
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rg_r_beat_count <= 0;
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rg_reset <= False;
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endrule
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// ----------------------------------------------------------------
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// BEHAVIOR
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// ----------------
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// Wr requests (AW and W channels)
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rule rl_wr_xaction_master_to_slave;
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AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) a_in = xactor_from_master.o_wr_addr.first;
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AXI4_Wr_Data #(wd_data, wd_user) d_in = xactor_from_master.o_wr_data.first;
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// Construct output AW item
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let a_out = a_in;
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a_out.awaddr = fv_addr_for_beat (a_in.awaddr, a_in.awsize, a_in.awburst, rg_w_beat_count);
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a_out.awlen = 0;
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a_out.awburst = axburst_fixed; // Not necessary when awlen=1, but slave may be finicky
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// Set WLAST to true since this is always last beat of outgoing xaction (awlen=1)
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let d_out = d_in;
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d_out.wlast = True;
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// Send to slave
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xactor_to_slave.i_wr_addr.enq (a_out);
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xactor_to_slave.i_wr_data.enq (d_out);
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xactor_from_master.o_wr_data.deq;
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// Remember burst length so that individual responses from slave
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// can be combined into a single burst response to the master.
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if (rg_w_beat_count == 0)
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f_w_awlen.enq (a_in.awlen);
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if (rg_w_beat_count < a_in.awlen)
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rg_w_beat_count <= rg_w_beat_count + 1;
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else begin
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// Last beat of incoming burst; done with AW item
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xactor_from_master.o_wr_addr.deq;
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rg_w_beat_count <= 0;
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// Simulation-only assertion-check (no action, just display assertion failure)
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// Last incoming beat must have WLAST = 1
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if (! d_in.wlast) begin
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$display ("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s", cur_cycle);
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$display (" WLAST not set on last data beat (awlen = %0d)", a_in.awlen);
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$display (" ", fshow (d_in));
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end
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end
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// Debugging
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s, beat %0d",
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cur_cycle, rg_w_beat_count);
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if (rg_w_beat_count == 0)
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$display (" a_in : ", fshow (a_in));
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if ((rg_w_beat_count == 0) || (cfg_verbosity > 1)) begin
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$display (" d_in : ", fshow (d_in));
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$display (" a_out: ", fshow (a_out));
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$display (" d_out: ", fshow (d_out));
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end
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end
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endrule: rl_wr_xaction_master_to_slave
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// ----------------
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// Wr responses (B channel): consume responses from slave until the
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// last response for a burst, then respond to master. Remember if
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// any of them was not an 'okay' response.
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rule rl_wr_resp_slave_to_master;
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AXI4_Wr_Resp #(wd_id, wd_user) b_in <- pop_o (xactor_to_slave.o_wr_resp);
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if (rg_b_beat_count < f_w_awlen.first) begin
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// Remember first non-okay response (if any) of a burst in rg_b_resp
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if ((rg_b_resp == axi4_resp_okay) && (b_in.bresp != axi4_resp_okay))
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rg_b_resp <= b_in.bresp;
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// not last beat of burst
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rg_b_beat_count <= rg_b_beat_count + 1;
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if (cfg_verbosity > 1) begin
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$display ("%0d: %m::AXI4_Deburster.rl_wr_resp_slave_to_master: m <- s, beat %0d",
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cur_cycle, rg_b_beat_count);
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$display (" Consuming and discarding beat %0d", rg_b_beat_count);
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$display (" ", fshow (b_in));
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end
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end
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else begin
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// Last beat of burst
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let b_out = b_in;
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if (rg_b_resp != axi4_resp_okay)
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b_out.bresp = rg_b_resp;
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xactor_from_master.i_wr_resp.enq (b_out);
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f_w_awlen.deq;
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// Get ready for next burst
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rg_b_beat_count <= 0;
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rg_b_resp <= axi4_resp_okay;
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if (cfg_verbosity > 1) begin
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$display ("%0d: %m::AXI4_Deburster.rl_wr_resp_slave_to_master: m <- s, beat %0d",
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cur_cycle, rg_b_beat_count);
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$display (" b_in: ", fshow (b_in));
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$display (" b_out: ", fshow (b_out));
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end
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end
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endrule
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// ----------------
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// Rd requests (AR channel)
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rule rl_rd_xaction_master_to_slave;
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AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a_in = xactor_from_master.o_rd_addr.first;
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// Compute forwarded request for each beat, and send
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let a_out = a_in;
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a_out.araddr = fv_addr_for_beat (a_in.araddr, a_in.arsize, a_in.arburst, rg_ar_beat_count);
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a_out.arlen = 0;
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a_out.arburst = axburst_fixed; // Not necessary when arlen=1, but slave may be finicky
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xactor_to_slave.i_rd_addr.enq (a_out);
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// On first beat, set up the response count
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if (rg_ar_beat_count == 0)
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f_r_arlen.enq (a_in.arlen);
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if (rg_ar_beat_count < a_in.arlen)
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rg_ar_beat_count <= rg_ar_beat_count + 1;
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else begin
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// Last beat sent; done with AR item
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xactor_from_master.o_rd_addr.deq;
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rg_ar_beat_count <= 0;
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end
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// Debugging
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m::AXI4_Deburster.rl_rd_xaction_master_to_slave: m -> s, beat %0d",
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cur_cycle, rg_ar_beat_count);
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if (rg_ar_beat_count == 0)
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$display (" a_in: ", fshow (a_in));
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if ((rg_ar_beat_count == 0) || (cfg_verbosity > 1))
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$display (" a_out: ", fshow (a_out));
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end
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endrule: rl_rd_xaction_master_to_slave
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// ----------------
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// Rd responses
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rule rl_rd_resp_slave_to_master;
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AXI4_Rd_Data #(wd_id, wd_data, wd_user) r_in <- pop_o (xactor_to_slave.o_rd_data);
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let arlen = f_r_arlen.first;
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let r_out = r_in;
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if (rg_r_beat_count < arlen) begin
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// not last beat of burst
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r_out.rlast = False;
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rg_r_beat_count <= rg_r_beat_count + 1;
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end
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else begin
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// Last beat of burst
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rg_r_beat_count <= 0;
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r_out.rlast = True; // should be set already, but override if not
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f_r_arlen.deq;
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end
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xactor_from_master.i_rd_data.enq (r_out);
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// Debugging
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m::AXI4_Deburster.rl_rd_resp_slave_to_master: m <- s, beat %0d",
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cur_cycle, rg_r_beat_count);
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if ((rg_r_beat_count == 0) || (cfg_verbosity > 1)) begin
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$display (" r_in: ", fshow (r_in));
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$display (" r_out: ", fshow (r_out));
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end
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end
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endrule: rl_rd_resp_slave_to_master
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// ----------------------------------------------------------------
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// INTERFACE
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method Action reset () if (! rg_reset);
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rg_reset <= True;
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endmethod
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interface from_master = xactor_from_master.axi_side;
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interface to_slave = xactor_to_slave .axi_side;
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endmodule
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// ================================================================
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endpackage: AXI4_Deburster
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