83829590dd
Now able to run multiple ISA tests in a single simulation run connected to remote debugger DSharp, using either hart_reset or ndm_reset between tests to bring the system back into reset state. All Debug Module commands working: - dm_reset, hart_reset, ndm_reset - break (set breakpoint) - step - continue (until breakpoint of 'halt' command) - halt - read/write GPR, FPR, CSR, memory - elf_load
675 lines
25 KiB
Plaintext
675 lines
25 KiB
Plaintext
// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
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package Mem_Controller;
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// ================================================================
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// This module is a slave on the interconnect Fabric.
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//
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// On the back side of the Mem_Controller is a ``raw'' memory
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// interface, a simple, wide, R/W interface,
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// which is connected to real memory in hardware (BRAM, DRAM, ...)
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// and to a model thereof in simulation.
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//
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// The raw mem interface data width is typically one or two cache lines.
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// Note: raw mem write requests are 'fire and forget'; there is no ack
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// ----------------
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// This slave IP can be attached to fabrics with 32b- or 64b-wide data channels.
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// (NOTE: this is the width of the fabric, which can be chosen
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// independently of the native width of a CPU master on the
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// fabric (such as RV32/RV64 for a RISC-V CPU).
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// When attached to 32b-wide fabric, 64-bit locations must be
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// read/written in two 32b transaction, once for the lower 32b and
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// once for the upper 32b.
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// When fabric data is 64b wide, fabric addresses must be 8B-aligned
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// - Reads always return 64b data
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// - Write data should be 64b wide with an 8b byte-strobe indicating
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// which bytes are to be written. Strobes should be for aligned
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// 1B, 2B, 4B or 8B chunks.
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// When fabric data is 32b wide, fabric addresses must be 4B-aligned
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// - Reads always return 32b data
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// - Write data should be 32b wide with a 4b byte-strobe indicating
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// which bytes are to be written. Strobes should for aligned
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// 1B, 2B, or 4B chunks.
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// Some of the 'truncate()'s and 'zeroExtend()'s below are no-ops but
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// necessary to satisfy type-checking.
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// ================================================================
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export
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Bits_per_Raw_Mem_Addr,
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Raw_Mem_Addr,
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Bits_per_Raw_Mem_Word,
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Raw_Mem_Word,
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Mem_Controller_IFC (..),
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mkMem_Controller,
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status_mem_controller_terminated;
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// ================================================================
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// BSV library imports
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import Vector :: *;
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import FIFOF :: *;
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import SpecialFIFOs :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Memory :: *;
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import ConfigReg :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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import Semi_FIFOF :: *;
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import ByteLane :: *;
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// ================================================================
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// Project imports
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import Fabric_Defs :: *;
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import SoC_Map :: *;
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import AXI4_Types :: *;
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// ================================================================
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// Raw mem data width: 256 (bits/ 32 x Byte/ 8 x Word32/ 4 x Word64)
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// Raw mem address width: 64 (arbitrarily chosen generously large)
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typedef 256 Bits_per_Raw_Mem_Word;
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typedef Bit #(Bits_per_Raw_Mem_Word) Raw_Mem_Word;
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typedef 64 Bits_per_Raw_Mem_Addr;
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typedef Bit #(Bits_per_Raw_Mem_Addr) Raw_Mem_Addr;
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// ----------------
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// Views of raw mem word as bytes, word32s and word64s
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// Example values on the right based on 256b raw mem data width
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typedef TDiv #(Bits_per_Raw_Mem_Word, 8) Bytes_per_Raw_Mem_Word; // 32 bytes
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Integer bytes_per_raw_mem_word = valueOf (Bytes_per_Raw_Mem_Word);
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// # of addr lsbs to index a byte in a Raw_Mem_Word
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typedef TLog #(Bytes_per_Raw_Mem_Word) Bits_per_Byte_in_Raw_Mem_Word; // 5
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Integer bits_per_byte_in_raw_mem_word = valueOf (Bits_per_Byte_in_Raw_Mem_Word);
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Integer hi_byte_in_raw_mem_word = bits_per_byte_in_raw_mem_word - 1; // 4
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typedef TDiv #(Bits_per_Raw_Mem_Word, 32) Word32s_per_Raw_Mem_Word; // 8 x 32b words
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Integer word32s_per_raw_mem_word = valueOf (Word32s_per_Raw_Mem_Word);
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// # of addr lsbs to index a Word32 in a Raw_Mem_Word seen as a vector of Word32s
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typedef TLog #(Word32s_per_Raw_Mem_Word) Bits_per_Word32_in_Raw_Mem_Word; // 3
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// Type of index of a Word32 in a Raw_Mem_Word seen as a vector of Word32s
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typedef Bit #(Bits_per_Word32_in_Raw_Mem_Word) Word32_in_Raw_Mem_Word;
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typedef TDiv #(Bits_per_Raw_Mem_Word, 64) Word64s_per_Raw_Mem_Word; // 4 x 64b words
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Integer word64s_per_raw_mem_word = valueOf (Word64s_per_Raw_Mem_Word);
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// # of addr lsbs to index a Word64 in a Raw_Mem_Word seen as a vector of Word64s
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typedef TLog #(Word64s_per_Raw_Mem_Word) Bits_per_Word64_in_Raw_Mem_Word; // 2
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// Type of index of a Word64 in a Raw_Mem_Word seen as a vector of Word64s
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typedef Bit #(Bits_per_Word64_in_Raw_Mem_Word) Word64_in_Raw_Mem_Word;
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typedef TDiv #(Bytes_per_Raw_Mem_Word, Bytes_per_Fabric_Data) Fabric_Data_per_Raw_Mem_Word;
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// Index of bit that selects a fabric data word in an address
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`ifdef FABRIC32
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Integer lo_fabric_data = 2;
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`endif
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`ifdef FABRIC64
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Integer lo_fabric_data = 3;
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`endif
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// ================================================================
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function Bool fn_addr_is_aligned (Fabric_Addr addr, AXI4_Size size);
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Bool is_aligned = ( (size == axsize_1)
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|| ((size == axsize_2) && (addr [0] == 1'h0))
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|| ((size == axsize_4) && (addr [1:0] == 2'h0))
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|| ((size == axsize_8) && (addr [2:0] == 3'h0))
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|| ((size == axsize_16) && (addr [3:0] == 4'h0))
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|| ((size == axsize_32) && (addr [4:0] == 5'h0))
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|| ((size == axsize_64) && (addr [5:0] == 6'h0))
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|| ((size == axsize_128) && (addr [6:0] == 7'h0)));
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return is_aligned;
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endfunction
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function Bool fn_addr_is_in_range (Fabric_Addr addr_base, Fabric_Addr addr, Fabric_Addr addr_lim);
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// Note: 'in_range' is redundant if the fabric only delivers
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// relevant addresses to this module so this is just a bit of
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// defensive programming.
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return ((addr_base <= addr) && (addr < addr_lim));
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endfunction
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function Bool fn_addr_is_ok (Fabric_Addr addr_base, Fabric_Addr addr, Fabric_Addr addr_lim, AXI4_Size size);
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return ( fn_addr_is_aligned (addr, size)
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&& fn_addr_is_in_range (addr_base, addr, addr_lim));
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endfunction
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// Compute raw mem addr that holds a given fabric addr
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function Raw_Mem_Addr fn_addr_to_raw_mem_addr (Fabric_Addr addr);
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Fabric_Addr a1 = addr >> log2 (bytes_per_raw_mem_word);
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return extend (a1);
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endfunction
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// Compute # of raw mem words from base to lim fabric addrs
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function Raw_Mem_Addr fn_raw_mem_words_per_mem (Fabric_Addr base, Fabric_Addr lim);
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return fn_addr_to_raw_mem_addr (lim - base);
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endfunction
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// ================================================================
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// Local constants and types
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// Module state
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typedef enum {STATE_POWER_ON_RESET,
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`ifdef INCLUDE_INITIAL_MEMZERO
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STATE_ZEROING_MEM, // while zero-ing out memory
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`endif
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STATE_RESET_RELOAD_CACHE, // on reset, start reload on reset
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STATE_RELOADING, // while reloading the raw-mem word cache
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STATE_READY // while handling requests
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} State
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deriving (Bits, Eq, FShow);
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// ================================================================
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// Catch-all status
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Integer status_mem_controller_terminated = 1;
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// ================================================================
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// Interface
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interface Mem_Controller_IFC;
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// Reset
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interface Server #(Bit #(0), Bit #(0)) server_reset;
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// set_addr_map should be called after this module's reset
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method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
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// Main Fabric Reqs/Rsps
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interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave;
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// To raw memory (outside the SoC)
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interface MemoryClient #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) to_raw_mem;
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// Catch-all status; return-value can identify the origin (0 = none)
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(* always_ready *)
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method Bit #(8) status;
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// For ISA tests: watch memory writes to <tohost> addr
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method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr);
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endinterface
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// ================================================================
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// AXI4 has independent read and write channels and does not specify
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// which one should be prioritized if requests are available on both
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// channels. We merge them into a single queue.
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typedef enum { REQ_OP_RD, REQ_OP_WR } Req_Op
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deriving (Bits, Eq, FShow);
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typedef struct {Req_Op req_op;
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// AW and AR channel info
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Fabric_Id id;
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Fabric_Addr addr;
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AXI4_Len len;
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AXI4_Size size;
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AXI4_Burst burst;
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AXI4_Lock lock;
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AXI4_Cache cache;
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AXI4_Prot prot;
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AXI4_QoS qos;
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AXI4_Region region;
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Bit #(Wd_User) user;
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// Write data info
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Bit #(TDiv #(Wd_Data, 8)) wstrb;
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Fabric_Data data;
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} Req
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deriving (Bits, FShow);
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// ================================================================
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(* synthesize *)
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module mkMem_Controller (Mem_Controller_IFC);
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// verbosity 0: quiet
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// verbosity 1: reset, initialized
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// verbosity 2: reads, writes
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// verbosity 3: more detail of local raw_mem interactions
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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Reg #(State) rg_state <- mkReg (STATE_POWER_ON_RESET);
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Reg #(Fabric_Addr) rg_addr_base <- mkRegU;
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Reg #(Fabric_Addr) rg_addr_lim <- mkRegU;
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FIFOF #(Bit #(0)) f_reset_reqs <- mkFIFOF;
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FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
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// Communication with fabric
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AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor;
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// Requests merged from the (WrA, WrD) and RdA channels
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FIFOF #(Req) f_reqs <- mkPipelineFIFOF;
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// FIFOFs for requests/responses to raw memory
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FIFOF #(MemoryRequest #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word))
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f_raw_mem_reqs <- mkPipelineFIFOF;
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FIFOF #(MemoryResponse #(Bits_per_Raw_Mem_Word))
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f_raw_mem_rsps <- mkPipelineFIFOF;
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// We maintain a 1-raw_mem_word cache
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Reg #(Bool) rg_cached_clean <- mkRegU;
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Reg #(Raw_Mem_Addr) rg_cached_raw_mem_addr <- mkRegU;
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Reg #(Raw_Mem_Word) rg_cached_raw_mem_word <- mkRegU;
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// Ad hoc ISA-test simulation support: watch <tohost> and stop on non-zero write.
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// The default tohost_addr here is fragile (may change on recompilation of tests).
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// Proper value can be provided with 'set_watch_tohost' method from symbol table
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Reg #(Bool) rg_watch_tohost <- mkReg (False);
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Reg #(Fabric_Addr) rg_tohost_addr <- mkReg ('h_8000_1000);
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// Catch-all status
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Reg #(Bit #(8)) rg_status <- mkReg (0);
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// ================================================================
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// BEHAVIOR
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// ----------------------------------------------------------------
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// Reset
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function Action fa_reset_actions;
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action
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slave_xactor.reset;
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f_raw_mem_reqs.clear;
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f_raw_mem_rsps.clear;
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rg_status <= 0;
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endaction
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endfunction
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rule rl_power_on_reset (rg_state == STATE_POWER_ON_RESET);
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if (cfg_verbosity > 1)
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$display ("%0d: Mem_Controller.rl_power_on_reset", cur_cycle);
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fa_reset_actions ();
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rg_state <= STATE_RESET_RELOAD_CACHE;
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endrule
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rule rl_external_reset (rg_state == STATE_READY);
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if (cfg_verbosity > 1)
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$display ("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE", cur_cycle);
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f_reset_reqs.deq;
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fa_reset_actions ();
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rg_state <= STATE_RESET_RELOAD_CACHE;
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f_reset_rsps.enq (?);
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endrule
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// On reset, we initialize the local cache with contents of raw_mem_addr 0
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rule rl_reset_reload_cache (rg_state == STATE_RESET_RELOAD_CACHE);
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let raw_mem_req = MemoryRequest {write: False,
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byteen: '1,
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address: 0,
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data: ?};
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f_raw_mem_reqs.enq (raw_mem_req);
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rg_cached_raw_mem_addr <= 0;
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rg_state <= STATE_RELOADING;
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if (cfg_verbosity > 1)
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$display ("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING", cur_cycle);
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endrule
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// ----------------------------------------------------------------
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// Merge requests into a single queue, prioritizing reads over writes
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rule rl_merge_rd_req;
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let rda <- pop_o (slave_xactor.o_rd_addr);
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let req = Req {req_op: REQ_OP_RD,
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id: rda.arid,
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addr: rda.araddr,
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len: rda.arlen,
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size: rda.arsize,
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burst: rda.arburst,
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lock: rda.arlock,
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cache: rda.arcache,
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prot: rda.arprot,
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qos: rda.arqos,
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region: rda.arregion,
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user: rda.aruser,
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wstrb: ?,
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data: ?};
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f_reqs.enq (req);
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if (cfg_verbosity > 2) begin
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$display ("%0d: Mem_Controller.rl_merge_rd_req", cur_cycle);
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$display (" ", fshow (rda));
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end
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endrule
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(* descending_urgency = "rl_merge_rd_req, rl_merge_wr_req" *)
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rule rl_merge_wr_req;
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let wra <- pop_o (slave_xactor.o_wr_addr);
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let wrd <- pop_o (slave_xactor.o_wr_data);
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let req = Req {req_op: REQ_OP_WR,
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id: wra.awid,
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addr: wra.awaddr,
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len: wra.awlen,
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size: wra.awsize,
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burst: wra.awburst,
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lock: wra.awlock,
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cache: wra.awcache,
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prot: wra.awprot,
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qos: wra.awqos,
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region: wra.awregion,
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user: wra.awuser,
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wstrb: wrd.wstrb,
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data: wrd.wdata};
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f_reqs.enq (req);
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if (cfg_verbosity > 2) begin
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$display ("%0d: Mem_Controller.rl_merge_wr_req", cur_cycle);
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$display (" ", fshow (wra));
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$display (" ", fshow (wrd));
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end
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endrule
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// ----------------------------------------------------------------
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// Handle request from fabric
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let req_byte_offset = f_reqs.first.addr - rg_addr_base; // within this memory unit
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let req_raw_mem_addr = fn_addr_to_raw_mem_addr (req_byte_offset);
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// ----------------
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// This rule fires when there's no fabric req and the cached raw_mem_word is dirty;
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// it writes back the dirty raw_mem_word; the cached raw_mem_word becomes clean
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rule rl_writeback_dirty_idle ( (rg_state == STATE_READY)
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&& (! f_reqs.notEmpty) // Idle
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&& (! rg_cached_clean));
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let raw_mem_req = MemoryRequest {write: True,
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byteen: '1,
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address: rg_cached_raw_mem_addr,
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data: rg_cached_raw_mem_word};
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f_raw_mem_reqs.enq (raw_mem_req);
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rg_cached_clean <= True;
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if (cfg_verbosity > 2)
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$display ("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h",
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cur_cycle, rg_cached_raw_mem_addr);
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endrule
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// ----------------
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// This rule fires on a fabric req when the cached raw_mem_word has a
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// different raw_mem_word-addr and is dirty;
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// it writes back the dirty raw_mem_word; the cached raw_mem_word becomes clean
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rule rl_writeback_dirty ( (rg_state == STATE_READY)
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&& fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size)
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&& (rg_cached_raw_mem_addr != req_raw_mem_addr)
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&& (! rg_cached_clean));
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let raw_mem_req = MemoryRequest {write: True,
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byteen: '1,
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address: rg_cached_raw_mem_addr,
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data: rg_cached_raw_mem_word};
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f_raw_mem_reqs.enq (raw_mem_req);
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rg_cached_clean <= True;
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if (cfg_verbosity > 2)
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$display ("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h",
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cur_cycle, rg_cached_raw_mem_addr);
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endrule
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// ----------------
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// This rule fires on a fabric req when the cached raw_mem_word has a
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// different addr and is clean; we overwrite with the correct raw_mem_word
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// by reloading from memory; the new cached raw_mem_word is clean.
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rule rl_miss_clean_req ( (rg_state == STATE_READY)
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&& fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size)
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&& (rg_cached_raw_mem_addr != req_raw_mem_addr)
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&& rg_cached_clean);
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let raw_mem_req = MemoryRequest {write: False,
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byteen: '1,
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address: req_raw_mem_addr,
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data: ?};
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f_raw_mem_reqs.enq (raw_mem_req);
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rg_cached_raw_mem_addr <= req_raw_mem_addr;
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rg_state <= STATE_RELOADING;
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if (cfg_verbosity > 2)
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$display ("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h",
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cur_cycle, req_raw_mem_addr);
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endrule
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rule rl_reload (rg_state == STATE_RELOADING);
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let raw_mem_rsp <- pop (f_raw_mem_rsps);
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Raw_Mem_Word raw_mem_word = unpack (raw_mem_rsp.data);
|
|
rg_cached_raw_mem_word <= raw_mem_word;
|
|
rg_state <= STATE_READY;
|
|
rg_cached_clean <= True;
|
|
|
|
if (cfg_verbosity > 2) begin
|
|
$display ("%0d: Mem_Controller.rl_reload: raw addr 0x%0h", cur_cycle, rg_cached_raw_mem_addr);
|
|
$display (" ", fshow (raw_mem_word));
|
|
end
|
|
endrule
|
|
|
|
// ----------------
|
|
// This rule fires on a fabric read request when the cached raw_mem_word has the
|
|
// same addr ('hit'), whether clean or dirty.
|
|
// Returns the full Wd_Data-wide word containing the byte specified by the address.
|
|
// i.e., we do not extract relevant bytes here, leaving that to the requestor.
|
|
|
|
rule rl_process_rd_req ( (rg_state == STATE_READY)
|
|
&& fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size)
|
|
&& (rg_cached_raw_mem_addr == req_raw_mem_addr)
|
|
&& (f_reqs.first.req_op == REQ_OP_RD));
|
|
|
|
// ----------------
|
|
// We need to select the fabric data word from the raw mem word that contains the target address.
|
|
|
|
// View the raw mem word as a vector of fabric data words (Wd_Data width words)
|
|
Vector #(Fabric_Data_per_Raw_Mem_Word, Bit #(Wd_Data)) raw_mem_word_V_fabric_data = unpack (rg_cached_raw_mem_word);
|
|
|
|
// Get the index into this vector of the fabric word containing the target address.
|
|
// For this index, use a generous size (here Bit #(16)), and let zeroExtend pad it automaticallly.
|
|
Fabric_Addr addr = f_reqs.first.addr;
|
|
Bit #(Bits_per_Byte_in_Raw_Mem_Word) n = addr [hi_byte_in_raw_mem_word : 0];
|
|
n = (n >> lo_fabric_data);
|
|
|
|
// Select the fabric data word of interest
|
|
Bit #(Wd_Data) rdata = raw_mem_word_V_fabric_data [n];
|
|
|
|
let rdr = AXI4_Rd_Data {rid: f_reqs.first.id,
|
|
rdata: rdata,
|
|
rresp: axi4_resp_okay,
|
|
rlast: True,
|
|
ruser: f_reqs.first.user};
|
|
slave_xactor.i_rd_data.enq (rdr);
|
|
f_reqs.deq;
|
|
|
|
if (cfg_verbosity > 1) begin
|
|
$display ("%0d: Mem_Controller.rl_process_rd_req: ", cur_cycle);
|
|
$display (" ", fshow (f_reqs.first));
|
|
$display (" => ", fshow (rdr));
|
|
end
|
|
endrule
|
|
|
|
// ----------------
|
|
// This rule fires on a fabric write request when the cached raw_mem_word has the
|
|
// same addr ('hit'), whether clean or dirty.
|
|
|
|
rule rl_process_wr_req ( (rg_state == STATE_READY)
|
|
&& fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size)
|
|
&& (rg_cached_raw_mem_addr == req_raw_mem_addr)
|
|
&& (f_reqs.first.req_op == REQ_OP_WR));
|
|
// Get the old (cached) value of the word64
|
|
Word64_in_Raw_Mem_Word word64_in_raw_mem_word = f_reqs.first.addr [hi_byte_in_raw_mem_word : 3];
|
|
Vector #(Word64s_per_Raw_Mem_Word, Bit #(64)) raw_mem_word_V_Word64 = unpack (rg_cached_raw_mem_word);
|
|
Bit #(64) word64_old = raw_mem_word_V_Word64 [word64_in_raw_mem_word];
|
|
|
|
// Lane-adjust the new word64
|
|
Bit #(64) word64_new = zeroExtend (f_reqs.first.data);
|
|
Bit #(8) strobe = zeroExtend (f_reqs.first.wstrb);
|
|
if ((valueOf (Wd_Data) == 32) && (f_reqs.first.addr [2] == 1'b1)) begin
|
|
// Upper 32b only
|
|
word64_new = { word64_new [31:0], 0 };
|
|
strobe = { strobe [3:0], 0 };
|
|
end
|
|
Bit #(64) mask = fn_strobe_to_mask (strobe);
|
|
let updated_word64 = ((word64_old & (~ mask)) | (word64_new & mask));
|
|
|
|
// Write it back into the cached raw_mem_word
|
|
raw_mem_word_V_Word64 [word64_in_raw_mem_word] = updated_word64;
|
|
rg_cached_raw_mem_word <= pack (raw_mem_word_V_Word64);
|
|
rg_cached_clean <= False;
|
|
|
|
let wrr = AXI4_Wr_Resp {bid: f_reqs.first.id,
|
|
bresp: axi4_resp_okay,
|
|
buser: f_reqs.first.user};
|
|
slave_xactor.i_wr_resp.enq (wrr);
|
|
f_reqs.deq;
|
|
|
|
if (cfg_verbosity > 1) begin
|
|
$display ("%0d: Mem_Controller.rl_process_wr_req: ", cur_cycle);
|
|
$display (" ", fshow (f_reqs.first));
|
|
$display (" => ", fshow (wrr));
|
|
end
|
|
|
|
// For simulation testing of riscv-tests/isa only:
|
|
if ((rg_watch_tohost)
|
|
&& (f_reqs.first.addr == rg_tohost_addr)
|
|
&& (word64_new != 0))
|
|
begin
|
|
|
|
$display ("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h (<tohost>) data 0x%0h",
|
|
cur_cycle, f_reqs.first.addr, word64_new);
|
|
let exit_value = (word64_new >> 1);
|
|
if (exit_value == 0)
|
|
$display ("PASS");
|
|
else
|
|
$display ("FAIL %0d", exit_value);
|
|
rg_status <= fromInteger (status_mem_controller_terminated);
|
|
end
|
|
endrule
|
|
|
|
// ================================================================
|
|
// Zero-memory FSM: zero out memory.
|
|
// If needed, we must provide a way to enable it from the debug_module
|
|
// This rule should be enabled with:
|
|
// rg_cached_raw_mem_addr <= 0;
|
|
// rg_state <= STATE_ZEROING_MEM;
|
|
|
|
`ifdef INCLUDE_INITIAL_MEMZERO
|
|
rule rl_zero_mem (rg_state == STATE_ZEROING_MEM);
|
|
let raw_mem_req = MemoryRequest {write: True,
|
|
byteen: '1,
|
|
address: rg_cached_raw_mem_addr,
|
|
data: 0};
|
|
f_raw_mem_reqs.enq (raw_mem_req);
|
|
|
|
// Last write
|
|
let raw_mem_words_per_mem = fn_raw_mem_words_per_mem (rg_addr_base, rg_addr_lim);
|
|
if (rg_cached_raw_mem_addr == (raw_mem_words_per_mem - 1)) begin
|
|
rg_cached_raw_mem_addr <= rg_cached_raw_mem_addr;
|
|
rg_cached_raw_mem_word <= unpack (0);
|
|
rg_cached_clean <= True;
|
|
rg_state <= STATE_READY;
|
|
|
|
// if (cfg_verbosity != 0)
|
|
$display ("%0d: Mem_Controller: zeroed %0d raw-memory locations (%0d-bit words)",
|
|
cur_cycle, raw_mem_words_per_mem, valueOf (Bits_per_Raw_Mem_Word));
|
|
end
|
|
else
|
|
rg_cached_raw_mem_addr <= rg_cached_raw_mem_addr + 1;
|
|
endrule
|
|
`endif
|
|
|
|
// ================================================================
|
|
// Invalid address
|
|
|
|
rule rl_invalid_rd_address ( (rg_state == STATE_READY)
|
|
&& (! fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size))
|
|
&& (f_reqs.first.req_op == REQ_OP_RD));
|
|
Fabric_Data rdata = zeroExtend (f_reqs.first.addr);
|
|
let rdr = AXI4_Rd_Data {rid: f_reqs.first.id,
|
|
rdata: rdata, // for debugging only
|
|
rresp: axi4_resp_slverr,
|
|
rlast: True,
|
|
ruser: f_reqs.first.user};
|
|
slave_xactor.i_rd_data.enq (rdr);
|
|
f_reqs.deq;
|
|
|
|
$write ("%0d: ERROR: Mem_Controller:", cur_cycle);
|
|
if (! fn_addr_is_aligned (f_reqs.first.addr, f_reqs.first.size))
|
|
$display (" read-addr is misaligned");
|
|
else
|
|
$display (" read-addr is out of bounds");
|
|
$display (" rg_addr_base 0x%0h rg_addr_lim 0x%0h", rg_addr_base, rg_addr_lim);
|
|
$display (" ", fshow (f_reqs.first));
|
|
$display (" => ", fshow (rdr));
|
|
endrule
|
|
|
|
rule rl_invalid_wr_address ( (rg_state == STATE_READY)
|
|
&& (! fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size))
|
|
&& (f_reqs.first.req_op == REQ_OP_WR));
|
|
let wrr = AXI4_Wr_Resp {bid: f_reqs.first.id,
|
|
bresp: axi4_resp_slverr,
|
|
buser: f_reqs.first.user};
|
|
slave_xactor.i_wr_resp.enq (wrr);
|
|
f_reqs.deq;
|
|
|
|
$write ("%0d: ERROR: Mem_Controller:", cur_cycle);
|
|
if (! fn_addr_is_aligned (f_reqs.first.addr, f_reqs.first.size))
|
|
$display (" write-addr is misaligned");
|
|
else
|
|
$display (" write-addr is out of bounds");
|
|
$display (" rg_addr_base 0x%0h rg_addr_lim 0x%0h", rg_addr_base, rg_addr_lim);
|
|
$display (" ", fshow (f_reqs.first));
|
|
$display (" => ", fshow (wrr));
|
|
endrule
|
|
|
|
// ================================================================
|
|
// INTERFACE
|
|
|
|
// Reset
|
|
interface server_reset = toGPServer (f_reset_reqs, f_reset_rsps);
|
|
|
|
// set_addr_map should be called after this module's reset
|
|
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim) if (rg_state == STATE_READY);
|
|
rg_addr_base <= addr_base;
|
|
rg_addr_lim <= addr_lim;
|
|
$display ("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h",
|
|
cur_cycle, addr_base, addr_lim);
|
|
|
|
`ifdef INCLUDE_INITIAL_MEMZERO
|
|
rg_cached_raw_mem_addr <= 0;
|
|
rg_state <= STATE_ZEROING_MEM;
|
|
$display ("%0d: Mem_Controller.set_addr_map: zeroing memory from 0x%0h to 0x%0h",
|
|
cur_cycle, addr_base, addr_lim);
|
|
`endif
|
|
endmethod
|
|
|
|
// Main Fabric Reqs/Rsps
|
|
interface slave = slave_xactor.axi_side;
|
|
|
|
// To raw memory (outside the SoC)
|
|
interface to_raw_mem = toGPClient (f_raw_mem_reqs, f_raw_mem_rsps);
|
|
|
|
// Catch-all status; return-value can identify the origin (0 = none)
|
|
method Bit #(8) status;
|
|
return rg_status;
|
|
endmethod
|
|
|
|
// For ISA tests: watch memory writes to <tohost> addr
|
|
method Action set_watch_tohost (Bool watch_tohost, Fabric_Addr tohost_addr);
|
|
rg_watch_tohost <= watch_tohost;
|
|
rg_tohost_addr <= tohost_addr;
|
|
endmethod
|
|
endmodule
|
|
|
|
// ================================================================
|
|
|
|
endpackage
|