85 lines
2.5 KiB
Plaintext
85 lines
2.5 KiB
Plaintext
// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
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package Mem_Model;
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// ================================================================
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// A simulation model of external DRAM memory.
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// Uses a register file to model memory.
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// ================================================================
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// BSV library imports
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import RegFile :: *;
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import Vector :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Memory :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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// ================================================================
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// Project imports
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import Mem_Controller :: *;
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// ================================================================
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// Mem Model interface
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interface Mem_Model_IFC;
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// The read/write interface
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interface MemoryServer #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) mem_server;
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endinterface
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// ================================================================
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// Mem Model implementation
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(* synthesize *)
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module mkMem_Model (Mem_Model_IFC);
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Integer verbosity = 0; // 0 = quiet; 1 = verbose
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Raw_Mem_Addr alloc_size = 'h_80_0000; // 8M raw mem words, or 256MB
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RegFile #(Raw_Mem_Addr, Bit #(Bits_per_Raw_Mem_Word)) rf <- mkRegFileLoad ("Mem.hex", 0, alloc_size - 1);
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FIFOF #(MemoryResponse #(Bits_per_Raw_Mem_Word)) f_raw_mem_rsps <- mkFIFOF;
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// ----------------------------------------------------------------
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// INTERFACE
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interface MemoryServer mem_server;
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interface Put request;
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method Action put (MemoryRequest #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) req);
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if (req.address >= alloc_size) begin
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$display ("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)",
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cur_cycle, req.address, alloc_size);
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$finish (1); // Assertion failure: address out of bounds
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end
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else if (req.write) begin
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rf.upd (req.address, req.data);
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if (verbosity != 0)
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$display ("%0d: Mem_Model write [0x%0h] <= 0x%0h", cur_cycle, req.address, req.data);
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end
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else begin
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let x = rf.sub (req.address);
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let rsp = MemoryResponse {data: x};
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f_raw_mem_rsps.enq (rsp);
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if (verbosity != 0)
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$display ("%0d: Mem_Model read [0x%0h] => 0x%0h", cur_cycle, req.address, x);
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end
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endmethod
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endinterface
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interface Get response = toGet (f_raw_mem_rsps);
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endinterface
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endmodule
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// ================================================================
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endpackage
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