rsnikhil e02dac1449 In CsrFile.bsv, changed user-privilege bits in MIP/SIP/MIE/SIE to read-only 0 since MISA.N=0

2020-03-02 16:20:07 -05:00

..

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Numerous fixes, so now generating correct Tandem-Verification traces for all 229 ISA tests.

2020-02-14 15:37:20 -05:00

CPU

In CsrFile.bsv, changed user-privilege bits in MIP/SIP/MIE/SIE to read-only 0 since MISA.N=0

2020-03-02 16:20:07 -05:00

Debug_Module

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

ISA

Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow

2020-01-29 13:19:31 -05:00

PLIC

Initial load of files

2019-03-26 14:49:40 -04:00

RISCY_OOO

In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.

2020-02-28 14:07:45 -05:00