2184 lines
84 KiB
Verilog
2184 lines
84 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// getEmptyEntryInit O 2 reg
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// RDY_getEmptyEntryInit O 1
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// sendRsToP_pRq_getRq O 66
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// RDY_sendRsToP_pRq_getRq O 1 const
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// sendRsToP_pRq_getData O 513
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// RDY_sendRsToP_pRq_getData O 1 const
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// RDY_sendRsToP_pRq_releaseEntry O 1
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// pipelineResp_getRq O 66
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// RDY_pipelineResp_getRq O 1 const
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// pipelineResp_getState O 2
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// RDY_pipelineResp_getState O 1 const
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// RDY_pipelineResp_releaseEntry O 1
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// RDY_pipelineResp_setDone_setData O 1 const
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// stuck_get O 68 const
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// RDY_stuck_get O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// getEmptyEntryInit_r I 66
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// sendRsToP_pRq_getRq_n I 2
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// sendRsToP_pRq_getData_n I 2
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// sendRsToP_pRq_releaseEntry_n I 2
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// pipelineResp_getRq_n I 2
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// pipelineResp_getState_n I 2
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// pipelineResp_releaseEntry_n I 2
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// pipelineResp_setDone_setData_n I 2
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// pipelineResp_setDone_setData_d I 513
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// EN_sendRsToP_pRq_releaseEntry I 1
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// EN_pipelineResp_releaseEntry I 1
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// EN_pipelineResp_setDone_setData I 1
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// EN_getEmptyEntryInit I 1
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// EN_stuck_get I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// sendRsToP_pRq_getRq_n -> sendRsToP_pRq_getRq
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// sendRsToP_pRq_getData_n -> sendRsToP_pRq_getData
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// pipelineResp_getRq_n -> pipelineResp_getRq
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// (pipelineResp_getState_n,
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// sendRsToP_pRq_releaseEntry_n,
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// EN_sendRsToP_pRq_releaseEntry) -> pipelineResp_getState
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDPRqMshrWrapper(CLK,
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RST_N,
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getEmptyEntryInit_r,
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EN_getEmptyEntryInit,
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getEmptyEntryInit,
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RDY_getEmptyEntryInit,
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sendRsToP_pRq_getRq_n,
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sendRsToP_pRq_getRq,
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RDY_sendRsToP_pRq_getRq,
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sendRsToP_pRq_getData_n,
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sendRsToP_pRq_getData,
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RDY_sendRsToP_pRq_getData,
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sendRsToP_pRq_releaseEntry_n,
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EN_sendRsToP_pRq_releaseEntry,
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RDY_sendRsToP_pRq_releaseEntry,
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pipelineResp_getRq_n,
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pipelineResp_getRq,
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RDY_pipelineResp_getRq,
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pipelineResp_getState_n,
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pipelineResp_getState,
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RDY_pipelineResp_getState,
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pipelineResp_releaseEntry_n,
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EN_pipelineResp_releaseEntry,
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RDY_pipelineResp_releaseEntry,
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pipelineResp_setDone_setData_n,
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pipelineResp_setDone_setData_d,
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EN_pipelineResp_setDone_setData,
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RDY_pipelineResp_setDone_setData,
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EN_stuck_get,
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stuck_get,
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RDY_stuck_get);
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input CLK;
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input RST_N;
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// actionvalue method getEmptyEntryInit
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input [65 : 0] getEmptyEntryInit_r;
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input EN_getEmptyEntryInit;
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output [1 : 0] getEmptyEntryInit;
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output RDY_getEmptyEntryInit;
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// value method sendRsToP_pRq_getRq
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input [1 : 0] sendRsToP_pRq_getRq_n;
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output [65 : 0] sendRsToP_pRq_getRq;
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output RDY_sendRsToP_pRq_getRq;
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// value method sendRsToP_pRq_getData
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input [1 : 0] sendRsToP_pRq_getData_n;
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output [512 : 0] sendRsToP_pRq_getData;
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output RDY_sendRsToP_pRq_getData;
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// action method sendRsToP_pRq_releaseEntry
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input [1 : 0] sendRsToP_pRq_releaseEntry_n;
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input EN_sendRsToP_pRq_releaseEntry;
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output RDY_sendRsToP_pRq_releaseEntry;
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// value method pipelineResp_getRq
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input [1 : 0] pipelineResp_getRq_n;
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output [65 : 0] pipelineResp_getRq;
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output RDY_pipelineResp_getRq;
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// value method pipelineResp_getState
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input [1 : 0] pipelineResp_getState_n;
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output [1 : 0] pipelineResp_getState;
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output RDY_pipelineResp_getState;
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// action method pipelineResp_releaseEntry
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input [1 : 0] pipelineResp_releaseEntry_n;
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input EN_pipelineResp_releaseEntry;
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output RDY_pipelineResp_releaseEntry;
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// action method pipelineResp_setDone_setData
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input [1 : 0] pipelineResp_setDone_setData_n;
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input [512 : 0] pipelineResp_setDone_setData_d;
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input EN_pipelineResp_setDone_setData;
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output RDY_pipelineResp_setDone_setData;
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// actionvalue method stuck_get
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input EN_stuck_get;
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output [67 : 0] stuck_get;
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output RDY_stuck_get;
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// signals for module outputs
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reg [1 : 0] pipelineResp_getState;
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wire [512 : 0] sendRsToP_pRq_getData;
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wire [67 : 0] stuck_get;
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wire [65 : 0] pipelineResp_getRq, sendRsToP_pRq_getRq;
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wire [1 : 0] getEmptyEntryInit;
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wire RDY_getEmptyEntryInit,
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RDY_pipelineResp_getRq,
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RDY_pipelineResp_getState,
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RDY_pipelineResp_releaseEntry,
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RDY_pipelineResp_setDone_setData,
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RDY_sendRsToP_pRq_getData,
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RDY_sendRsToP_pRq_getRq,
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RDY_sendRsToP_pRq_releaseEntry,
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RDY_stuck_get;
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// inlined wires
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wire [1 : 0] m_m_stateVec_0_lat_1$wget,
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m_m_stateVec_1_lat_1$wget,
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m_m_stateVec_2_lat_1$wget,
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m_m_stateVec_3_lat_1$wget;
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wire m_m_stateVec_0_dummy_1_0$whas,
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m_m_stateVec_0_lat_1$whas,
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m_m_stateVec_0_lat_2$whas,
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m_m_stateVec_1_dummy_1_0$whas,
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m_m_stateVec_1_lat_1$whas,
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m_m_stateVec_1_lat_2$whas,
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m_m_stateVec_2_dummy_1_0$whas,
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m_m_stateVec_2_lat_1$whas,
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m_m_stateVec_2_lat_2$whas,
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m_m_stateVec_3_dummy_1_0$whas,
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m_m_stateVec_3_lat_1$whas,
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m_m_stateVec_3_lat_2$whas;
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// register m_m_dataValidVec_0_rl
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reg m_m_dataValidVec_0_rl;
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wire m_m_dataValidVec_0_rl$D_IN, m_m_dataValidVec_0_rl$EN;
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// register m_m_dataValidVec_1_rl
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reg m_m_dataValidVec_1_rl;
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wire m_m_dataValidVec_1_rl$D_IN, m_m_dataValidVec_1_rl$EN;
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// register m_m_dataValidVec_2_rl
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reg m_m_dataValidVec_2_rl;
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wire m_m_dataValidVec_2_rl$D_IN, m_m_dataValidVec_2_rl$EN;
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// register m_m_dataValidVec_3_rl
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reg m_m_dataValidVec_3_rl;
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wire m_m_dataValidVec_3_rl$D_IN, m_m_dataValidVec_3_rl$EN;
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// register m_m_initIdx
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reg [1 : 0] m_m_initIdx;
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wire [1 : 0] m_m_initIdx$D_IN;
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wire m_m_initIdx$EN;
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// register m_m_inited
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reg m_m_inited;
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wire m_m_inited$D_IN, m_m_inited$EN;
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// register m_m_releaseEntryQ_pipelineResp_data_0_rl
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reg [1 : 0] m_m_releaseEntryQ_pipelineResp_data_0_rl;
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wire [1 : 0] m_m_releaseEntryQ_pipelineResp_data_0_rl$D_IN;
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wire m_m_releaseEntryQ_pipelineResp_data_0_rl$EN;
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// register m_m_releaseEntryQ_pipelineResp_empty_rl
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reg m_m_releaseEntryQ_pipelineResp_empty_rl;
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wire m_m_releaseEntryQ_pipelineResp_empty_rl$D_IN,
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m_m_releaseEntryQ_pipelineResp_empty_rl$EN;
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// register m_m_releaseEntryQ_pipelineResp_full_rl
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reg m_m_releaseEntryQ_pipelineResp_full_rl;
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wire m_m_releaseEntryQ_pipelineResp_full_rl$D_IN,
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m_m_releaseEntryQ_pipelineResp_full_rl$EN;
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// register m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl
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reg [1 : 0] m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl;
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wire [1 : 0] m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$D_IN;
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wire m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$EN;
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// register m_m_releaseEntryQ_sendRsToP_pRq_empty_rl
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reg m_m_releaseEntryQ_sendRsToP_pRq_empty_rl;
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wire m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$D_IN,
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m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$EN;
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// register m_m_releaseEntryQ_sendRsToP_pRq_full_rl
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reg m_m_releaseEntryQ_sendRsToP_pRq_full_rl;
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wire m_m_releaseEntryQ_sendRsToP_pRq_full_rl$D_IN,
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m_m_releaseEntryQ_sendRsToP_pRq_full_rl$EN;
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// register m_m_reqVec_0_rl
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reg [65 : 0] m_m_reqVec_0_rl;
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wire [65 : 0] m_m_reqVec_0_rl$D_IN;
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wire m_m_reqVec_0_rl$EN;
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// register m_m_reqVec_1_rl
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reg [65 : 0] m_m_reqVec_1_rl;
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wire [65 : 0] m_m_reqVec_1_rl$D_IN;
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wire m_m_reqVec_1_rl$EN;
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// register m_m_reqVec_2_rl
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reg [65 : 0] m_m_reqVec_2_rl;
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wire [65 : 0] m_m_reqVec_2_rl$D_IN;
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wire m_m_reqVec_2_rl$EN;
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// register m_m_reqVec_3_rl
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reg [65 : 0] m_m_reqVec_3_rl;
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wire [65 : 0] m_m_reqVec_3_rl$D_IN;
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wire m_m_reqVec_3_rl$EN;
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// register m_m_stateVec_0_rl
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reg [1 : 0] m_m_stateVec_0_rl;
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wire [1 : 0] m_m_stateVec_0_rl$D_IN;
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wire m_m_stateVec_0_rl$EN;
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// register m_m_stateVec_1_rl
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reg [1 : 0] m_m_stateVec_1_rl;
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wire [1 : 0] m_m_stateVec_1_rl$D_IN;
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wire m_m_stateVec_1_rl$EN;
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// register m_m_stateVec_2_rl
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reg [1 : 0] m_m_stateVec_2_rl;
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wire [1 : 0] m_m_stateVec_2_rl$D_IN;
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wire m_m_stateVec_2_rl$EN;
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// register m_m_stateVec_3_rl
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reg [1 : 0] m_m_stateVec_3_rl;
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wire [1 : 0] m_m_stateVec_3_rl$D_IN;
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wire m_m_stateVec_3_rl$EN;
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// ports of submodule m_m_dataFile
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wire [511 : 0] m_m_dataFile$D_IN, m_m_dataFile$D_OUT_1;
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wire [1 : 0] m_m_dataFile$ADDR_1,
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m_m_dataFile$ADDR_2,
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m_m_dataFile$ADDR_3,
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m_m_dataFile$ADDR_4,
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m_m_dataFile$ADDR_5,
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m_m_dataFile$ADDR_IN;
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wire m_m_dataFile$WE;
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// ports of submodule m_m_dataValidVec_0_dummy2_0
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wire m_m_dataValidVec_0_dummy2_0$D_IN,
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m_m_dataValidVec_0_dummy2_0$EN,
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m_m_dataValidVec_0_dummy2_0$Q_OUT;
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// ports of submodule m_m_dataValidVec_0_dummy2_1
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wire m_m_dataValidVec_0_dummy2_1$D_IN,
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m_m_dataValidVec_0_dummy2_1$EN,
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m_m_dataValidVec_0_dummy2_1$Q_OUT;
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// ports of submodule m_m_dataValidVec_0_dummy2_2
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wire m_m_dataValidVec_0_dummy2_2$D_IN,
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m_m_dataValidVec_0_dummy2_2$EN,
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m_m_dataValidVec_0_dummy2_2$Q_OUT;
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// ports of submodule m_m_dataValidVec_1_dummy2_0
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wire m_m_dataValidVec_1_dummy2_0$D_IN,
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m_m_dataValidVec_1_dummy2_0$EN,
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m_m_dataValidVec_1_dummy2_0$Q_OUT;
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// ports of submodule m_m_dataValidVec_1_dummy2_1
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wire m_m_dataValidVec_1_dummy2_1$D_IN,
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m_m_dataValidVec_1_dummy2_1$EN,
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m_m_dataValidVec_1_dummy2_1$Q_OUT;
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// ports of submodule m_m_dataValidVec_1_dummy2_2
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wire m_m_dataValidVec_1_dummy2_2$D_IN,
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m_m_dataValidVec_1_dummy2_2$EN,
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m_m_dataValidVec_1_dummy2_2$Q_OUT;
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// ports of submodule m_m_dataValidVec_2_dummy2_0
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wire m_m_dataValidVec_2_dummy2_0$D_IN,
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m_m_dataValidVec_2_dummy2_0$EN,
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m_m_dataValidVec_2_dummy2_0$Q_OUT;
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// ports of submodule m_m_dataValidVec_2_dummy2_1
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wire m_m_dataValidVec_2_dummy2_1$D_IN,
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m_m_dataValidVec_2_dummy2_1$EN,
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m_m_dataValidVec_2_dummy2_1$Q_OUT;
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// ports of submodule m_m_dataValidVec_2_dummy2_2
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wire m_m_dataValidVec_2_dummy2_2$D_IN,
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m_m_dataValidVec_2_dummy2_2$EN,
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m_m_dataValidVec_2_dummy2_2$Q_OUT;
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// ports of submodule m_m_dataValidVec_3_dummy2_0
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wire m_m_dataValidVec_3_dummy2_0$D_IN,
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m_m_dataValidVec_3_dummy2_0$EN,
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m_m_dataValidVec_3_dummy2_0$Q_OUT;
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// ports of submodule m_m_dataValidVec_3_dummy2_1
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wire m_m_dataValidVec_3_dummy2_1$D_IN,
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m_m_dataValidVec_3_dummy2_1$EN,
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m_m_dataValidVec_3_dummy2_1$Q_OUT;
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// ports of submodule m_m_dataValidVec_3_dummy2_2
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wire m_m_dataValidVec_3_dummy2_2$D_IN,
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m_m_dataValidVec_3_dummy2_2$EN,
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m_m_dataValidVec_3_dummy2_2$Q_OUT;
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// ports of submodule m_m_emptyEntryQ
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reg [1 : 0] m_m_emptyEntryQ$D_IN;
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wire [1 : 0] m_m_emptyEntryQ$D_OUT;
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wire m_m_emptyEntryQ$CLR,
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m_m_emptyEntryQ$DEQ,
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m_m_emptyEntryQ$EMPTY_N,
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m_m_emptyEntryQ$ENQ,
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m_m_emptyEntryQ$FULL_N;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0
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wire m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0$D_IN,
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m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0$EN;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1
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wire m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$D_IN,
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m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$EN,
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m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$Q_OUT;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0
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wire m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0$D_IN,
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m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0$EN;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1
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wire m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1$D_IN,
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m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1$EN;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_0
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wire m_m_releaseEntryQ_pipelineResp_empty_dummy2_0$D_IN,
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m_m_releaseEntryQ_pipelineResp_empty_dummy2_0$EN;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_1
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wire m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$D_IN,
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m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$EN,
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m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$Q_OUT;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_2
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wire m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$D_IN,
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m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$EN,
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m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$Q_OUT;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0
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wire m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0$D_IN,
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m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0$EN;
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// ports of submodule m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1
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wire m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_0
|
|
wire m_m_releaseEntryQ_pipelineResp_full_dummy2_0$D_IN,
|
|
m_m_releaseEntryQ_pipelineResp_full_dummy2_0$EN,
|
|
m_m_releaseEntryQ_pipelineResp_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_1
|
|
wire m_m_releaseEntryQ_pipelineResp_full_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_pipelineResp_full_dummy2_1$EN,
|
|
m_m_releaseEntryQ_pipelineResp_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_2
|
|
wire m_m_releaseEntryQ_pipelineResp_full_dummy2_2$D_IN,
|
|
m_m_releaseEntryQ_pipelineResp_full_dummy2_2$EN,
|
|
m_m_releaseEntryQ_pipelineResp_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$EN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$EN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$EN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$EN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$EN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2
|
|
wire m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$D_IN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$EN,
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_0
|
|
wire m_m_reqVec_0_dummy2_0$D_IN,
|
|
m_m_reqVec_0_dummy2_0$EN,
|
|
m_m_reqVec_0_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_1
|
|
wire m_m_reqVec_0_dummy2_1$D_IN,
|
|
m_m_reqVec_0_dummy2_1$EN,
|
|
m_m_reqVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_0_dummy2_2
|
|
wire m_m_reqVec_0_dummy2_2$D_IN,
|
|
m_m_reqVec_0_dummy2_2$EN,
|
|
m_m_reqVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_0
|
|
wire m_m_reqVec_1_dummy2_0$D_IN,
|
|
m_m_reqVec_1_dummy2_0$EN,
|
|
m_m_reqVec_1_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_1
|
|
wire m_m_reqVec_1_dummy2_1$D_IN,
|
|
m_m_reqVec_1_dummy2_1$EN,
|
|
m_m_reqVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_1_dummy2_2
|
|
wire m_m_reqVec_1_dummy2_2$D_IN,
|
|
m_m_reqVec_1_dummy2_2$EN,
|
|
m_m_reqVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_0
|
|
wire m_m_reqVec_2_dummy2_0$D_IN,
|
|
m_m_reqVec_2_dummy2_0$EN,
|
|
m_m_reqVec_2_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_1
|
|
wire m_m_reqVec_2_dummy2_1$D_IN,
|
|
m_m_reqVec_2_dummy2_1$EN,
|
|
m_m_reqVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_2_dummy2_2
|
|
wire m_m_reqVec_2_dummy2_2$D_IN,
|
|
m_m_reqVec_2_dummy2_2$EN,
|
|
m_m_reqVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_0
|
|
wire m_m_reqVec_3_dummy2_0$D_IN,
|
|
m_m_reqVec_3_dummy2_0$EN,
|
|
m_m_reqVec_3_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_1
|
|
wire m_m_reqVec_3_dummy2_1$D_IN,
|
|
m_m_reqVec_3_dummy2_1$EN,
|
|
m_m_reqVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_reqVec_3_dummy2_2
|
|
wire m_m_reqVec_3_dummy2_2$D_IN,
|
|
m_m_reqVec_3_dummy2_2$EN,
|
|
m_m_reqVec_3_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_0
|
|
wire m_m_stateVec_0_dummy2_0$D_IN, m_m_stateVec_0_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_1
|
|
wire m_m_stateVec_0_dummy2_1$D_IN,
|
|
m_m_stateVec_0_dummy2_1$EN,
|
|
m_m_stateVec_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_0_dummy2_2
|
|
wire m_m_stateVec_0_dummy2_2$D_IN,
|
|
m_m_stateVec_0_dummy2_2$EN,
|
|
m_m_stateVec_0_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_0
|
|
wire m_m_stateVec_1_dummy2_0$D_IN, m_m_stateVec_1_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_1
|
|
wire m_m_stateVec_1_dummy2_1$D_IN,
|
|
m_m_stateVec_1_dummy2_1$EN,
|
|
m_m_stateVec_1_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_1_dummy2_2
|
|
wire m_m_stateVec_1_dummy2_2$D_IN,
|
|
m_m_stateVec_1_dummy2_2$EN,
|
|
m_m_stateVec_1_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_0
|
|
wire m_m_stateVec_2_dummy2_0$D_IN, m_m_stateVec_2_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_1
|
|
wire m_m_stateVec_2_dummy2_1$D_IN,
|
|
m_m_stateVec_2_dummy2_1$EN,
|
|
m_m_stateVec_2_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_2_dummy2_2
|
|
wire m_m_stateVec_2_dummy2_2$D_IN,
|
|
m_m_stateVec_2_dummy2_2$EN,
|
|
m_m_stateVec_2_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_0
|
|
wire m_m_stateVec_3_dummy2_0$D_IN, m_m_stateVec_3_dummy2_0$EN;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_1
|
|
wire m_m_stateVec_3_dummy2_1$D_IN,
|
|
m_m_stateVec_3_dummy2_1$EN,
|
|
m_m_stateVec_3_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule m_m_stateVec_3_dummy2_2
|
|
wire m_m_stateVec_3_dummy2_2$D_IN,
|
|
m_m_stateVec_3_dummy2_2$EN,
|
|
m_m_stateVec_3_dummy2_2$Q_OUT;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_m_dataValidVec_0_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_1_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_2_canon,
|
|
CAN_FIRE_RL_m_m_dataValidVec_3_canon,
|
|
CAN_FIRE_RL_m_m_doReleaseEntry_pipelineResp,
|
|
CAN_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq,
|
|
CAN_FIRE_RL_m_m_initEmptyEntry,
|
|
CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon,
|
|
CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon,
|
|
CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon,
|
|
CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon,
|
|
CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon,
|
|
CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_0_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_1_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_2_canon,
|
|
CAN_FIRE_RL_m_m_reqVec_3_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_0_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_1_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_2_canon,
|
|
CAN_FIRE_RL_m_m_stateVec_3_canon,
|
|
CAN_FIRE_getEmptyEntryInit,
|
|
CAN_FIRE_pipelineResp_releaseEntry,
|
|
CAN_FIRE_pipelineResp_setDone_setData,
|
|
CAN_FIRE_sendRsToP_pRq_releaseEntry,
|
|
CAN_FIRE_stuck_get,
|
|
WILL_FIRE_RL_m_m_dataValidVec_0_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_1_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_2_canon,
|
|
WILL_FIRE_RL_m_m_dataValidVec_3_canon,
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp,
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq,
|
|
WILL_FIRE_RL_m_m_initEmptyEntry,
|
|
WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon,
|
|
WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon,
|
|
WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon,
|
|
WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon,
|
|
WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon,
|
|
WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_0_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_1_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_2_canon,
|
|
WILL_FIRE_RL_m_m_reqVec_3_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_0_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_1_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_2_canon,
|
|
WILL_FIRE_RL_m_m_stateVec_3_canon,
|
|
WILL_FIRE_getEmptyEntryInit,
|
|
WILL_FIRE_pipelineResp_releaseEntry,
|
|
WILL_FIRE_pipelineResp_setDone_setData,
|
|
WILL_FIRE_sendRsToP_pRq_releaseEntry,
|
|
WILL_FIRE_stuck_get;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [1 : 0] MUX_m_m_emptyEntryQ$enq_1__VAL_2,
|
|
MUX_m_m_emptyEntryQ$enq_1__VAL_3;
|
|
wire MUX_m_m_emptyEntryQ$enq_1__SEL_2,
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1,
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1,
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2,
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d243,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d313;
|
|
reg [1 : 0] SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d253,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d327;
|
|
reg SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__54_A_ETC___d279;
|
|
wire [63 : 0] n__read_addr__h42426,
|
|
n__read_addr__h42511,
|
|
n__read_addr__h42596,
|
|
n__read_addr__h42681,
|
|
n__read_addr__h45279,
|
|
n__read_addr__h45369,
|
|
n__read_addr__h45459,
|
|
n__read_addr__h45549;
|
|
wire [1 : 0] IF_m_m_releaseEntryQ_pipelineResp_data_0_lat_0_ETC___d153,
|
|
IF_m_m_releaseEntryQ_sendRsToP_pRq_data_0_lat__ETC___d126,
|
|
IF_m_m_reqVec_0_dummy2_0_read__14_AND_m_m_reqV_ETC___d245,
|
|
IF_m_m_reqVec_1_dummy2_0_read__21_AND_m_m_reqV_ETC___d247,
|
|
IF_m_m_reqVec_2_dummy2_0_read__28_AND_m_m_reqV_ETC___d249,
|
|
IF_m_m_reqVec_3_dummy2_0_read__35_AND_m_m_reqV_ETC___d251,
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8,
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18,
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28,
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38;
|
|
|
|
// actionvalue method getEmptyEntryInit
|
|
assign getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
|
|
assign RDY_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign CAN_FIRE_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
|
|
assign WILL_FIRE_getEmptyEntryInit = EN_getEmptyEntryInit ;
|
|
|
|
// value method sendRsToP_pRq_getRq
|
|
assign sendRsToP_pRq_getRq =
|
|
{ SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d243,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d253 } ;
|
|
assign RDY_sendRsToP_pRq_getRq = 1'd1 ;
|
|
|
|
// value method sendRsToP_pRq_getData
|
|
assign sendRsToP_pRq_getData =
|
|
{ SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__54_A_ETC___d279,
|
|
m_m_dataFile$D_OUT_1 } ;
|
|
assign RDY_sendRsToP_pRq_getData = 1'd1 ;
|
|
|
|
// action method sendRsToP_pRq_releaseEntry
|
|
assign RDY_sendRsToP_pRq_releaseEntry =
|
|
(!m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$Q_OUT ||
|
|
!m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$Q_OUT ||
|
|
!m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$Q_OUT ||
|
|
!m_m_releaseEntryQ_sendRsToP_pRq_full_rl) &&
|
|
m_m_inited ;
|
|
assign CAN_FIRE_sendRsToP_pRq_releaseEntry =
|
|
RDY_sendRsToP_pRq_releaseEntry ;
|
|
assign WILL_FIRE_sendRsToP_pRq_releaseEntry =
|
|
EN_sendRsToP_pRq_releaseEntry ;
|
|
|
|
// value method pipelineResp_getRq
|
|
assign pipelineResp_getRq =
|
|
{ SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d313,
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d327 } ;
|
|
assign RDY_pipelineResp_getRq = 1'd1 ;
|
|
|
|
// value method pipelineResp_getState
|
|
always@(pipelineResp_getState_n or
|
|
m_m_stateVec_0_dummy2_1$Q_OUT or
|
|
m_m_stateVec_0_dummy2_2$Q_OUT or
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 or
|
|
m_m_stateVec_1_dummy2_1$Q_OUT or
|
|
m_m_stateVec_1_dummy2_2$Q_OUT or
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 or
|
|
m_m_stateVec_2_dummy2_1$Q_OUT or
|
|
m_m_stateVec_2_dummy2_2$Q_OUT or
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 or
|
|
m_m_stateVec_3_dummy2_1$Q_OUT or
|
|
m_m_stateVec_3_dummy2_2$Q_OUT or
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38)
|
|
begin
|
|
case (pipelineResp_getState_n)
|
|
2'd0:
|
|
pipelineResp_getState =
|
|
(m_m_stateVec_0_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_0_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 :
|
|
2'd0;
|
|
2'd1:
|
|
pipelineResp_getState =
|
|
(m_m_stateVec_1_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_1_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 :
|
|
2'd0;
|
|
2'd2:
|
|
pipelineResp_getState =
|
|
(m_m_stateVec_2_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_2_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 :
|
|
2'd0;
|
|
2'd3:
|
|
pipelineResp_getState =
|
|
(m_m_stateVec_3_dummy2_1$Q_OUT &&
|
|
m_m_stateVec_3_dummy2_2$Q_OUT) ?
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 :
|
|
2'd0;
|
|
endcase
|
|
end
|
|
assign RDY_pipelineResp_getState = 1'd1 ;
|
|
|
|
// action method pipelineResp_releaseEntry
|
|
assign RDY_pipelineResp_releaseEntry =
|
|
(!m_m_releaseEntryQ_pipelineResp_full_dummy2_0$Q_OUT ||
|
|
!m_m_releaseEntryQ_pipelineResp_full_dummy2_1$Q_OUT ||
|
|
!m_m_releaseEntryQ_pipelineResp_full_dummy2_2$Q_OUT ||
|
|
!m_m_releaseEntryQ_pipelineResp_full_rl) &&
|
|
m_m_inited ;
|
|
assign CAN_FIRE_pipelineResp_releaseEntry = RDY_pipelineResp_releaseEntry ;
|
|
assign WILL_FIRE_pipelineResp_releaseEntry = EN_pipelineResp_releaseEntry ;
|
|
|
|
// action method pipelineResp_setDone_setData
|
|
assign RDY_pipelineResp_setDone_setData = 1'd1 ;
|
|
assign CAN_FIRE_pipelineResp_setDone_setData = 1'd1 ;
|
|
assign WILL_FIRE_pipelineResp_setDone_setData =
|
|
EN_pipelineResp_setDone_setData ;
|
|
|
|
// actionvalue method stuck_get
|
|
assign stuck_get = 68'hAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_stuck_get = 1'd0 ;
|
|
assign CAN_FIRE_stuck_get = 1'd0 ;
|
|
assign WILL_FIRE_stuck_get = EN_stuck_get ;
|
|
|
|
// submodule m_m_dataFile
|
|
RegFile #(.addr_width(32'd2),
|
|
.data_width(32'd512),
|
|
.lo(2'd0),
|
|
.hi(2'd3)) m_m_dataFile(.CLK(CLK),
|
|
.ADDR_1(m_m_dataFile$ADDR_1),
|
|
.ADDR_2(m_m_dataFile$ADDR_2),
|
|
.ADDR_3(m_m_dataFile$ADDR_3),
|
|
.ADDR_4(m_m_dataFile$ADDR_4),
|
|
.ADDR_5(m_m_dataFile$ADDR_5),
|
|
.ADDR_IN(m_m_dataFile$ADDR_IN),
|
|
.D_IN(m_m_dataFile$D_IN),
|
|
.WE(m_m_dataFile$WE),
|
|
.D_OUT_1(m_m_dataFile$D_OUT_1),
|
|
.D_OUT_2(),
|
|
.D_OUT_3(),
|
|
.D_OUT_4(),
|
|
.D_OUT_5());
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_dataValidVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_dataValidVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_dataValidVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_dataValidVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_dataValidVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_dataValidVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_dataValidVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_dataValidVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
SizedFIFO #(.p1width(32'd2),
|
|
.p2depth(32'd4),
|
|
.p3cntr_width(32'd2),
|
|
.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(m_m_emptyEntryQ$D_IN),
|
|
.ENQ(m_m_emptyEntryQ$ENQ),
|
|
.DEQ(m_m_emptyEntryQ$DEQ),
|
|
.CLR(m_m_emptyEntryQ$CLR),
|
|
.D_OUT(m_m_emptyEntryQ$D_OUT),
|
|
.FULL_N(m_m_emptyEntryQ$FULL_N),
|
|
.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_empty_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_full_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_full_dummy2_0$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_pipelineResp_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_full_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_full_dummy2_1$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_pipelineResp_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_pipelineResp_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_pipelineResp_full_dummy2_2$D_IN),
|
|
.EN(m_m_releaseEntryQ_pipelineResp_full_dummy2_2$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_pipelineResp_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$D_IN),
|
|
.EN(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$EN),
|
|
.Q_OUT(m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_0$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_0$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_reqVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_reqVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_reqVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_reqVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_reqVec_3_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_stateVec_0_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_0_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_0_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_0_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_0_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_0_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_stateVec_1_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_1_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_1_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_1_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_1_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_1_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_stateVec_2_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_2_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_2_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_2_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_2_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_2_dummy2_2$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_0(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_0$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule m_m_stateVec_3_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_1$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_1$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_1$Q_OUT));
|
|
|
|
// submodule m_m_stateVec_3_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) m_m_stateVec_3_dummy2_2(.CLK(CLK),
|
|
.D_IN(m_m_stateVec_3_dummy2_2$D_IN),
|
|
.EN(m_m_stateVec_3_dummy2_2$EN),
|
|
.Q_OUT(m_m_stateVec_3_dummy2_2$Q_OUT));
|
|
|
|
// rule RL_m_m_initEmptyEntry
|
|
assign CAN_FIRE_RL_m_m_initEmptyEntry =
|
|
m_m_emptyEntryQ$FULL_N && !m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// rule RL_m_m_doReleaseEntry_sendRsToP_pRq
|
|
assign CAN_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
|
|
assign WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
|
|
|
|
// rule RL_m_m_doReleaseEntry_pipelineResp
|
|
assign CAN_FIRE_RL_m_m_doReleaseEntry_pipelineResp =
|
|
(!m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$Q_OUT ||
|
|
!m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$Q_OUT ||
|
|
EN_pipelineResp_releaseEntry ||
|
|
!m_m_releaseEntryQ_pipelineResp_empty_rl) &&
|
|
m_m_emptyEntryQ$FULL_N &&
|
|
m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp =
|
|
CAN_FIRE_RL_m_m_doReleaseEntry_pipelineResp &&
|
|
!WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq ;
|
|
|
|
// rule RL_m_m_stateVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_dataValidVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_dataValidVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_dataValidVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_pipelineResp_data_0_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_pipelineResp_empty_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_pipelineResp_full_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_m_emptyEntryQ$enq_1__SEL_2 =
|
|
(!m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$Q_OUT ||
|
|
!m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$Q_OUT ||
|
|
EN_sendRsToP_pRq_releaseEntry ||
|
|
!m_m_releaseEntryQ_sendRsToP_pRq_empty_rl) &&
|
|
m_m_emptyEntryQ$FULL_N &&
|
|
m_m_inited ;
|
|
assign MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd0 ;
|
|
assign MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd0 ;
|
|
assign MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd1 ;
|
|
assign MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd1 ;
|
|
assign MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd2 ;
|
|
assign MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd2 ;
|
|
assign MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd3 ;
|
|
assign MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 =
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd3 ;
|
|
assign MUX_m_m_emptyEntryQ$enq_1__VAL_2 =
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$Q_OUT ?
|
|
IF_m_m_releaseEntryQ_sendRsToP_pRq_data_0_lat__ETC___d126 :
|
|
2'd0 ;
|
|
assign MUX_m_m_emptyEntryQ$enq_1__VAL_3 =
|
|
m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$Q_OUT ?
|
|
IF_m_m_releaseEntryQ_pipelineResp_data_0_lat_0_ETC___d153 :
|
|
2'd0 ;
|
|
assign MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd0 ;
|
|
assign MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd1 ;
|
|
assign MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd2 ;
|
|
assign MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd3 ;
|
|
|
|
// inlined wires
|
|
assign m_m_stateVec_0_lat_1$wget =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_0_lat_1$whas =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_0_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd0 ;
|
|
assign m_m_stateVec_0_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd0 ||
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd0 ;
|
|
assign m_m_stateVec_1_lat_1$wget =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_1_lat_1$whas =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_1_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd1 ;
|
|
assign m_m_stateVec_1_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd1 ||
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd1 ;
|
|
assign m_m_stateVec_2_lat_1$wget =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_2_lat_1$whas =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_2_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd2 ;
|
|
assign m_m_stateVec_2_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd2 ||
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd2 ;
|
|
assign m_m_stateVec_3_lat_1$wget =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_3_lat_1$whas =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_1 ||
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 ;
|
|
assign m_m_stateVec_3_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd3 ;
|
|
assign m_m_stateVec_3_dummy_1_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd3 ||
|
|
EN_pipelineResp_setDone_setData &&
|
|
pipelineResp_setDone_setData_n == 2'd3 ;
|
|
|
|
// register m_m_dataValidVec_0_rl
|
|
assign m_m_dataValidVec_0_rl$D_IN =
|
|
!m_m_stateVec_0_lat_2$whas &&
|
|
(MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setDone_setData_d[512] :
|
|
m_m_dataValidVec_0_rl) ;
|
|
assign m_m_dataValidVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_1_rl
|
|
assign m_m_dataValidVec_1_rl$D_IN =
|
|
!m_m_stateVec_1_lat_2$whas &&
|
|
(MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setDone_setData_d[512] :
|
|
m_m_dataValidVec_1_rl) ;
|
|
assign m_m_dataValidVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_2_rl
|
|
assign m_m_dataValidVec_2_rl$D_IN =
|
|
!m_m_stateVec_2_lat_2$whas &&
|
|
(MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setDone_setData_d[512] :
|
|
m_m_dataValidVec_2_rl) ;
|
|
assign m_m_dataValidVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_dataValidVec_3_rl
|
|
assign m_m_dataValidVec_3_rl$D_IN =
|
|
!m_m_stateVec_3_lat_2$whas &&
|
|
(MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 ?
|
|
pipelineResp_setDone_setData_d[512] :
|
|
m_m_dataValidVec_3_rl) ;
|
|
assign m_m_dataValidVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_initIdx
|
|
assign m_m_initIdx$D_IN = m_m_initIdx + 2'd1 ;
|
|
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// register m_m_inited
|
|
assign m_m_inited$D_IN = 1'd1 ;
|
|
assign m_m_inited$EN =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 2'd3 ;
|
|
|
|
// register m_m_releaseEntryQ_pipelineResp_data_0_rl
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_rl$D_IN =
|
|
IF_m_m_releaseEntryQ_pipelineResp_data_0_lat_0_ETC___d153 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_pipelineResp_empty_rl
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_rl$D_IN =
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ||
|
|
!EN_pipelineResp_releaseEntry &&
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl ;
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_pipelineResp_full_rl
|
|
assign m_m_releaseEntryQ_pipelineResp_full_rl$D_IN =
|
|
!WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp &&
|
|
(EN_pipelineResp_releaseEntry ||
|
|
m_m_releaseEntryQ_pipelineResp_full_rl) ;
|
|
assign m_m_releaseEntryQ_pipelineResp_full_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$D_IN =
|
|
IF_m_m_releaseEntryQ_sendRsToP_pRq_data_0_lat__ETC___d126 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_sendRsToP_pRq_empty_rl
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$D_IN =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ||
|
|
!EN_sendRsToP_pRq_releaseEntry &&
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_sendRsToP_pRq_full_rl
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_rl$D_IN =
|
|
!MUX_m_m_emptyEntryQ$enq_1__SEL_2 &&
|
|
(EN_sendRsToP_pRq_releaseEntry ||
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl) ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
assign m_m_reqVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_0_rl ;
|
|
assign m_m_reqVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
assign m_m_reqVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_1_rl ;
|
|
assign m_m_reqVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
assign m_m_reqVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_2_rl ;
|
|
assign m_m_reqVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
assign m_m_reqVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_3_rl ;
|
|
assign m_m_reqVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
assign m_m_stateVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
2'd1 :
|
|
(m_m_stateVec_0_lat_1$whas ?
|
|
m_m_stateVec_0_lat_1$wget :
|
|
IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8) ;
|
|
assign m_m_stateVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
assign m_m_stateVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
2'd1 :
|
|
(m_m_stateVec_1_lat_1$whas ?
|
|
m_m_stateVec_1_lat_1$wget :
|
|
IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18) ;
|
|
assign m_m_stateVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
assign m_m_stateVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
2'd1 :
|
|
(m_m_stateVec_2_lat_1$whas ?
|
|
m_m_stateVec_2_lat_1$wget :
|
|
IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28) ;
|
|
assign m_m_stateVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
assign m_m_stateVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
2'd1 :
|
|
(m_m_stateVec_3_lat_1$whas ?
|
|
m_m_stateVec_3_lat_1$wget :
|
|
IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38) ;
|
|
assign m_m_stateVec_3_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_m_dataFile
|
|
assign m_m_dataFile$ADDR_1 = sendRsToP_pRq_getData_n ;
|
|
assign m_m_dataFile$ADDR_2 = 2'h0 ;
|
|
assign m_m_dataFile$ADDR_3 = 2'h0 ;
|
|
assign m_m_dataFile$ADDR_4 = 2'h0 ;
|
|
assign m_m_dataFile$ADDR_5 = 2'h0 ;
|
|
assign m_m_dataFile$ADDR_IN = pipelineResp_setDone_setData_n ;
|
|
assign m_m_dataFile$D_IN = pipelineResp_setDone_setData_d[511:0] ;
|
|
assign m_m_dataFile$WE = EN_pipelineResp_setDone_setData ;
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_0
|
|
assign m_m_dataValidVec_0_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_dataValidVec_0_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_1
|
|
assign m_m_dataValidVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_0_dummy2_1$EN =
|
|
MUX_m_m_stateVec_0_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_dataValidVec_0_dummy2_2
|
|
assign m_m_dataValidVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_0
|
|
assign m_m_dataValidVec_1_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_dataValidVec_1_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_1
|
|
assign m_m_dataValidVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_1_dummy2_1$EN =
|
|
MUX_m_m_stateVec_1_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_dataValidVec_1_dummy2_2
|
|
assign m_m_dataValidVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_0
|
|
assign m_m_dataValidVec_2_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_dataValidVec_2_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_1
|
|
assign m_m_dataValidVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_2_dummy2_1$EN =
|
|
MUX_m_m_stateVec_2_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_dataValidVec_2_dummy2_2
|
|
assign m_m_dataValidVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_0
|
|
assign m_m_dataValidVec_3_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_dataValidVec_3_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_1
|
|
assign m_m_dataValidVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_3_dummy2_1$EN =
|
|
MUX_m_m_stateVec_3_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule m_m_dataValidVec_3_dummy2_2
|
|
assign m_m_dataValidVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_dataValidVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
always@(WILL_FIRE_RL_m_m_initEmptyEntry or
|
|
m_m_initIdx or
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq or
|
|
MUX_m_m_emptyEntryQ$enq_1__VAL_2 or
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp or
|
|
MUX_m_m_emptyEntryQ$enq_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_m_m_initEmptyEntry: m_m_emptyEntryQ$D_IN = m_m_initIdx;
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq:
|
|
m_m_emptyEntryQ$D_IN = MUX_m_m_emptyEntryQ$enq_1__VAL_2;
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp:
|
|
m_m_emptyEntryQ$D_IN = MUX_m_m_emptyEntryQ$enq_1__VAL_3;
|
|
default: m_m_emptyEntryQ$D_IN = 2'b10 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign m_m_emptyEntryQ$ENQ =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry ||
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq ||
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ;
|
|
assign m_m_emptyEntryQ$DEQ = EN_getEmptyEntryInit ;
|
|
assign m_m_emptyEntryQ$CLR = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_dummy2_0$EN =
|
|
EN_pipelineResp_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0
|
|
assign m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_deqP_dummy2_0$EN =
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1
|
|
assign m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_0
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_dummy2_0$EN =
|
|
EN_pipelineResp_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_1
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_dummy2_1$EN =
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_empty_dummy2_2
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0
|
|
assign m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_enqP_dummy2_0$EN =
|
|
EN_pipelineResp_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1
|
|
assign m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_0
|
|
assign m_m_releaseEntryQ_pipelineResp_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_full_dummy2_0$EN =
|
|
EN_pipelineResp_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_1
|
|
assign m_m_releaseEntryQ_pipelineResp_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_full_dummy2_1$EN =
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ;
|
|
|
|
// submodule m_m_releaseEntryQ_pipelineResp_full_dummy2_2
|
|
assign m_m_releaseEntryQ_pipelineResp_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_0$EN =
|
|
EN_sendRsToP_pRq_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_0$EN =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_0$EN =
|
|
EN_sendRsToP_pRq_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_1$EN =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_0$EN =
|
|
EN_sendRsToP_pRq_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_0$EN =
|
|
EN_sendRsToP_pRq_releaseEntry ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_1$EN =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
|
|
|
|
// submodule m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_0
|
|
assign m_m_reqVec_0_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_0_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_1
|
|
assign m_m_reqVec_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_0_dummy2_2
|
|
assign m_m_reqVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_0
|
|
assign m_m_reqVec_1_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_1_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_1
|
|
assign m_m_reqVec_1_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_1_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_1_dummy2_2
|
|
assign m_m_reqVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_0
|
|
assign m_m_reqVec_2_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_2_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_1
|
|
assign m_m_reqVec_2_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_2_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_2_dummy2_2
|
|
assign m_m_reqVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_0
|
|
assign m_m_reqVec_3_dummy2_0$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_3_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_1
|
|
assign m_m_reqVec_3_dummy2_1$D_IN = 1'b0 ;
|
|
assign m_m_reqVec_3_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule m_m_reqVec_3_dummy2_2
|
|
assign m_m_reqVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_reqVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_0
|
|
assign m_m_stateVec_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_0$EN =
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_1
|
|
assign m_m_stateVec_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_1$EN = m_m_stateVec_0_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_0_dummy2_2
|
|
assign m_m_stateVec_0_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_0_dummy2_2$EN = m_m_stateVec_0_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_0
|
|
assign m_m_stateVec_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_0$EN =
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_1
|
|
assign m_m_stateVec_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_1$EN = m_m_stateVec_1_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_1_dummy2_2
|
|
assign m_m_stateVec_1_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_1_dummy2_2$EN = m_m_stateVec_1_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_0
|
|
assign m_m_stateVec_2_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_0$EN =
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_1
|
|
assign m_m_stateVec_2_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_1$EN = m_m_stateVec_2_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_2_dummy2_2
|
|
assign m_m_stateVec_2_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_2_dummy2_2$EN = m_m_stateVec_2_lat_2$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_0
|
|
assign m_m_stateVec_3_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_0$EN =
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_1
|
|
assign m_m_stateVec_3_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_1$EN = m_m_stateVec_3_dummy_1_0$whas ;
|
|
|
|
// submodule m_m_stateVec_3_dummy2_2
|
|
assign m_m_stateVec_3_dummy2_2$D_IN = 1'd1 ;
|
|
assign m_m_stateVec_3_dummy2_2$EN = m_m_stateVec_3_lat_2$whas ;
|
|
|
|
// remaining internal signals
|
|
assign IF_m_m_releaseEntryQ_pipelineResp_data_0_lat_0_ETC___d153 =
|
|
EN_pipelineResp_releaseEntry ?
|
|
pipelineResp_releaseEntry_n :
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl ;
|
|
assign IF_m_m_releaseEntryQ_sendRsToP_pRq_data_0_lat__ETC___d126 =
|
|
EN_sendRsToP_pRq_releaseEntry ?
|
|
sendRsToP_pRq_releaseEntry_n :
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl ;
|
|
assign IF_m_m_reqVec_0_dummy2_0_read__14_AND_m_m_reqV_ETC___d245 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[1:0] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_1_dummy2_0_read__21_AND_m_m_reqV_ETC___d247 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[1:0] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_2_dummy2_0_read__28_AND_m_m_reqV_ETC___d249 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[1:0] :
|
|
2'd0 ;
|
|
assign IF_m_m_reqVec_3_dummy2_0_read__35_AND_m_m_reqV_ETC___d251 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[1:0] :
|
|
2'd0 ;
|
|
assign IF_m_m_stateVec_0_lat_0_whas_THEN_m_m_stateVec_ETC___d8 =
|
|
MUX_m_m_stateVec_0_dummy_1_0$wset_1__VAL_1 ?
|
|
2'd0 :
|
|
m_m_stateVec_0_rl ;
|
|
assign IF_m_m_stateVec_1_lat_0_whas__5_THEN_m_m_state_ETC___d18 =
|
|
MUX_m_m_stateVec_1_dummy_1_0$wset_1__VAL_1 ?
|
|
2'd0 :
|
|
m_m_stateVec_1_rl ;
|
|
assign IF_m_m_stateVec_2_lat_0_whas__5_THEN_m_m_state_ETC___d28 =
|
|
MUX_m_m_stateVec_2_dummy_1_0$wset_1__VAL_1 ?
|
|
2'd0 :
|
|
m_m_stateVec_2_rl ;
|
|
assign IF_m_m_stateVec_3_lat_0_whas__5_THEN_m_m_state_ETC___d38 =
|
|
MUX_m_m_stateVec_3_dummy_1_0$wset_1__VAL_1 ?
|
|
2'd0 :
|
|
m_m_stateVec_3_rl ;
|
|
assign n__read_addr__h42426 =
|
|
(m_m_reqVec_0_dummy2_0$Q_OUT && m_m_reqVec_0_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h42511 =
|
|
(m_m_reqVec_1_dummy2_0$Q_OUT && m_m_reqVec_1_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h42596 =
|
|
(m_m_reqVec_2_dummy2_0$Q_OUT && m_m_reqVec_2_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h42681 =
|
|
(m_m_reqVec_3_dummy2_0$Q_OUT && m_m_reqVec_3_dummy2_1$Q_OUT &&
|
|
m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h45279 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h45369 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h45459 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[65:2] :
|
|
64'd0 ;
|
|
assign n__read_addr__h45549 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[65:2] :
|
|
64'd0 ;
|
|
always@(sendRsToP_pRq_getData_n or
|
|
m_m_dataValidVec_0_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_0_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_0_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_0_rl or
|
|
m_m_dataValidVec_1_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_1_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_1_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_1_rl or
|
|
m_m_dataValidVec_2_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_2_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_2_dummy2_2$Q_OUT or
|
|
m_m_dataValidVec_2_rl or
|
|
m_m_dataValidVec_3_dummy2_0$Q_OUT or
|
|
m_m_dataValidVec_3_dummy2_1$Q_OUT or
|
|
m_m_dataValidVec_3_dummy2_2$Q_OUT or m_m_dataValidVec_3_rl)
|
|
begin
|
|
case (sendRsToP_pRq_getData_n)
|
|
2'd0:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__54_A_ETC___d279 =
|
|
m_m_dataValidVec_0_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_0_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_0_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_0_rl;
|
|
2'd1:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__54_A_ETC___d279 =
|
|
m_m_dataValidVec_1_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_1_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_1_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_1_rl;
|
|
2'd2:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__54_A_ETC___d279 =
|
|
m_m_dataValidVec_2_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_2_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_2_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_2_rl;
|
|
2'd3:
|
|
SEL_ARR_m_m_dataValidVec_0_dummy2_0_read__54_A_ETC___d279 =
|
|
m_m_dataValidVec_3_dummy2_0$Q_OUT &&
|
|
m_m_dataValidVec_3_dummy2_1$Q_OUT &&
|
|
m_m_dataValidVec_3_dummy2_2$Q_OUT &&
|
|
m_m_dataValidVec_3_rl;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_pRq_getRq_n or
|
|
n__read_addr__h42426 or
|
|
n__read_addr__h42511 or
|
|
n__read_addr__h42596 or n__read_addr__h42681)
|
|
begin
|
|
case (sendRsToP_pRq_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d243 =
|
|
n__read_addr__h42426;
|
|
2'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d243 =
|
|
n__read_addr__h42511;
|
|
2'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d243 =
|
|
n__read_addr__h42596;
|
|
2'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d243 =
|
|
n__read_addr__h42681;
|
|
endcase
|
|
end
|
|
always@(sendRsToP_pRq_getRq_n or
|
|
IF_m_m_reqVec_0_dummy2_0_read__14_AND_m_m_reqV_ETC___d245 or
|
|
IF_m_m_reqVec_1_dummy2_0_read__21_AND_m_m_reqV_ETC___d247 or
|
|
IF_m_m_reqVec_2_dummy2_0_read__28_AND_m_m_reqV_ETC___d249 or
|
|
IF_m_m_reqVec_3_dummy2_0_read__35_AND_m_m_reqV_ETC___d251)
|
|
begin
|
|
case (sendRsToP_pRq_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d253 =
|
|
IF_m_m_reqVec_0_dummy2_0_read__14_AND_m_m_reqV_ETC___d245;
|
|
2'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d253 =
|
|
IF_m_m_reqVec_1_dummy2_0_read__21_AND_m_m_reqV_ETC___d247;
|
|
2'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d253 =
|
|
IF_m_m_reqVec_2_dummy2_0_read__28_AND_m_m_reqV_ETC___d249;
|
|
2'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_0_read__14_AND__ETC___d253 =
|
|
IF_m_m_reqVec_3_dummy2_0_read__35_AND_m_m_reqV_ETC___d251;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
n__read_addr__h45279 or
|
|
n__read_addr__h45369 or
|
|
n__read_addr__h45459 or n__read_addr__h45549)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d313 =
|
|
n__read_addr__h45279;
|
|
2'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d313 =
|
|
n__read_addr__h45369;
|
|
2'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d313 =
|
|
n__read_addr__h45459;
|
|
2'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d313 =
|
|
n__read_addr__h45549;
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_dummy2_1$Q_OUT or
|
|
m_m_reqVec_0_dummy2_2$Q_OUT or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_dummy2_1$Q_OUT or
|
|
m_m_reqVec_1_dummy2_2$Q_OUT or
|
|
m_m_reqVec_1_rl or
|
|
m_m_reqVec_2_dummy2_1$Q_OUT or
|
|
m_m_reqVec_2_dummy2_2$Q_OUT or
|
|
m_m_reqVec_2_rl or
|
|
m_m_reqVec_3_dummy2_1$Q_OUT or
|
|
m_m_reqVec_3_dummy2_2$Q_OUT or m_m_reqVec_3_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d327 =
|
|
(m_m_reqVec_0_dummy2_1$Q_OUT && m_m_reqVec_0_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_0_rl[1:0] :
|
|
2'd0;
|
|
2'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d327 =
|
|
(m_m_reqVec_1_dummy2_1$Q_OUT && m_m_reqVec_1_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_1_rl[1:0] :
|
|
2'd0;
|
|
2'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d327 =
|
|
(m_m_reqVec_2_dummy2_1$Q_OUT && m_m_reqVec_2_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_2_rl[1:0] :
|
|
2'd0;
|
|
2'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_dummy2_1_read__15_AND__ETC___d327 =
|
|
(m_m_reqVec_3_dummy2_1$Q_OUT && m_m_reqVec_3_dummy2_2$Q_OUT) ?
|
|
m_m_reqVec_3_rl[1:0] :
|
|
2'd0;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_dataValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_dataValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
2'h2;
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_m_releaseEntryQ_pipelineResp_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
2'h2;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_dataValidVec_0_rl$EN)
|
|
m_m_dataValidVec_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_0_rl$D_IN;
|
|
if (m_m_dataValidVec_1_rl$EN)
|
|
m_m_dataValidVec_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_1_rl$D_IN;
|
|
if (m_m_dataValidVec_2_rl$EN)
|
|
m_m_dataValidVec_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_2_rl$D_IN;
|
|
if (m_m_dataValidVec_3_rl$EN)
|
|
m_m_dataValidVec_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_dataValidVec_3_rl$D_IN;
|
|
if (m_m_initIdx$EN)
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
|
|
if (m_m_inited$EN)
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
|
|
if (m_m_releaseEntryQ_pipelineResp_data_0_rl$EN)
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl$D_IN;
|
|
if (m_m_releaseEntryQ_pipelineResp_empty_rl$EN)
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl$D_IN;
|
|
if (m_m_releaseEntryQ_pipelineResp_full_rl$EN)
|
|
m_m_releaseEntryQ_pipelineResp_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_pipelineResp_full_rl$D_IN;
|
|
if (m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$EN)
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$D_IN;
|
|
if (m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$EN)
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$D_IN;
|
|
if (m_m_releaseEntryQ_sendRsToP_pRq_full_rl$EN)
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl$D_IN;
|
|
if (m_m_reqVec_0_rl$EN)
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
|
|
if (m_m_reqVec_1_rl$EN)
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
|
|
if (m_m_reqVec_2_rl$EN)
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
|
|
if (m_m_reqVec_3_rl$EN)
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
|
|
if (m_m_stateVec_0_rl$EN)
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
|
|
if (m_m_stateVec_1_rl$EN)
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
|
|
if (m_m_stateVec_2_rl$EN)
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
|
|
if (m_m_stateVec_3_rl$EN)
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_dataValidVec_0_rl = 1'h0;
|
|
m_m_dataValidVec_1_rl = 1'h0;
|
|
m_m_dataValidVec_2_rl = 1'h0;
|
|
m_m_dataValidVec_3_rl = 1'h0;
|
|
m_m_initIdx = 2'h2;
|
|
m_m_inited = 1'h0;
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl = 2'h2;
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl = 1'h0;
|
|
m_m_releaseEntryQ_pipelineResp_full_rl = 1'h0;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl = 2'h2;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl = 1'h0;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl = 1'h0;
|
|
m_m_reqVec_0_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl = 2'h2;
|
|
m_m_stateVec_1_rl = 2'h2;
|
|
m_m_stateVec_2_rl = 2'h2;
|
|
m_m_stateVec_3_rl = 2'h2;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkDPRqMshrWrapper
|
|
|