341 lines
12 KiB
Plaintext
341 lines
12 KiB
Plaintext
// Copyright (c) 2019-2020 Bluespec, Inc.
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package MMIO_AXI4_Adapter;
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// ================================================================
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// This is an adapter to connect MIT's RISCY-OOO to an AXI4 fabric in
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// Bluespec's Toooba setup. All IO traffic to the fabric flows through
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// this. Note: a few IO addresses (e.g., MTIME, MTIMECMP, MSIP,
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// TOHOST, FROMHOST are intercepted and handled before they reach this
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// adapter).
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// ================================================================
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// BSV lib imports
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import Assert :: *;
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import ConfigReg :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Vector :: *;
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// ----------------
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// BSV additional libs
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import GetPut_Aux :: *;
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import Cur_Cycle :: *;
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import Semi_FIFOF :: *;
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import CreditCounter :: *;
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// ================================================================
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// Project imports
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// ----------------
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// From MIT RISCY-OOO
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import Types :: *;
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import ProcTypes :: *;
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// ----------------
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// From Bluespec Pipes
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import AXI4 :: *;
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import SourceSink :: *;
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import Fabric_Defs :: *;
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import SoC_Map :: *;
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// ================================================================
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interface MMIO_AXI4_Adapter_IFC;
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method Action reset;
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interface Server #(MMIOCRq, MMIODataPRs) core_side;
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// Fabric master interface for IO
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interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
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, Wd_AW_User, Wd_W_User, Wd_B_User
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, Wd_AR_User, Wd_R_User) mmio_master;
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endinterface
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// ================================================================
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module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
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// Verbosity: 0: quiet; 1: transactions
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Integer verbosity = 0;
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
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// ================================================================
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// Requests from and responses to core
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FIFOF #(MMIOCRq) f_reqs_from_core <- mkFIFOF;
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FIFOF #(MMIODataPRs) f_rsps_to_core <- mkFIFOF;
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Reg#(Fabric_Addr) read_req_addr <- mkRegU;
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SoC_Map_IFC soc_map <- mkSoC_Map; // for m_is_IO_addr
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// ================================================================
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// Fabric request/response
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let master_shim <- mkAXI4ShimFF;
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// For discarding write-responses
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CreditCounter_IFC #(4) ctr_wr_rsps_pending <- mkCreditCounter; // Max 15 writes outstanding
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// ================================================================
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// Handle read requests and responses.
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// Don't do a read while a write is outstanding.
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// This is just an adapter from MMIOCRq/MMIODataPRs to AXI4
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Reg #(Bit #(1)) rg_rd_rsp_beat <- mkReg (0);
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Reg #(MemTaggedData) rspData <- mkReg (unpack(0));
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// ================================================================
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// Convert a request's byte enables to an AXI 4 size, to ensure that
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// peripherals don't get confused about how large our access is.
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function AXI4_Size byteEnToAxiSize (MemDataByteEn byteEn);
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return toAXI4_Size(zeroExtend(pack(countIf(id, byteEn)))).Valid;
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endfunction
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rule rl_handle_read_req (f_reqs_from_core.first.func matches Ld
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&&& (ctr_wr_rsps_pending.value == 0));
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let req <- pop (f_reqs_from_core);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_read_req: Ld request", cur_cycle);
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$display (" ", fshow (req));
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end
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AXI4_Size size = byteEnToAxiSize(req.byteEn);
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Bool burst = size > 8;
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if (burst) size = 8;
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// Technically the following check for legal IO addrs is not
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// necessary; the AXI4 fabric should return a DECERR for illegal
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// addrs; but not all AXI4 fabrics do the right thing.
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if (soc_map.m_is_IO_addr (req.addr, False)) begin
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let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_corew_bus_default_mid,
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araddr: req.addr,
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arlen: (burst) ? 1:0, // burst len = arlen+1
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arsize: size,
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arburst: fabric_default_burst,
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arlock: fabric_default_lock,
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arcache: fabric_default_arcache,
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arprot: fabric_default_prot,
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arqos: fabric_default_qos,
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arregion: fabric_default_region,
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aruser: fabric_default_aruser};
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master_shim.slave.ar.put(mem_req_rd_addr);
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read_req_addr <= req.addr;
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// Debugging
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if (cfg_verbosity > 0) begin
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$display (" ", fshow (mem_req_rd_addr));
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end
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end else begin
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let rsp = MMIODataPRs {valid: False,
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data: toMemTaggedData(req.addr)}; // For debugging convenience only
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f_rsps_to_core.enq (rsp);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response",
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cur_cycle);
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$display (" ", fshow (req));
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end
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end
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endrule
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// ----------------
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rule rl_handle_read_rsps;
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let mem_rsp <- get(master_shim.slave.r);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_read_rsps ", cur_cycle);
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$display (" ", fshow (mem_rsp));
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end
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if ((cfg_verbosity > 0) && (mem_rsp.rresp != OKAY)) begin
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$display ("%0d: %m.rl_handle_read_rsp: fabric response error", cur_cycle);
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$display (" ", fshow (mem_rsp));
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end
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let newData = rspData;
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newData.data[read_req_addr[3]+rg_rd_rsp_beat] = mem_rsp.rdata;
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let rsp = MMIODataPRs {valid: (mem_rsp.rresp == OKAY),
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data: newData };
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if (mem_rsp.rlast) begin
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f_rsps_to_core.enq (rsp);
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if (cfg_verbosity > 0)
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$display (" Response MMIO to core: ", fshow (rsp));
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rg_rd_rsp_beat <= 0;
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rspData <= unpack(0);
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end else begin
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rg_rd_rsp_beat <= rg_rd_rsp_beat + 1;
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rspData <= newData;
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end
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endrule
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// ================================================================
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// Handle write requests and responses
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// Each 128b word takes 2 beats, each handling 64 bits
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Reg #(Bit #(1)) rg_wr_req_beat <- mkReg (0);
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rule rl_handle_write_req (f_reqs_from_core.first.func matches St);
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let req = f_reqs_from_core.first;
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if (cfg_verbosity > 0) begin
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$display ("%d: %m.rl_handle_write_req: St request:", cur_cycle);
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$display (" ", fshow (req));
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end
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AXI4_Size size = byteEnToAxiSize(req.byteEn);
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Bool burst = size > 8;
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if (burst) size = 8;
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Vector #(2, Bit #(8)) line_strb = unpack(pack(req.byteEn));
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Bit#(1) whichHalf = rg_wr_req_beat;
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if (!burst) whichHalf = (line_strb[0]!=0) ? 0:1;
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Bool first = (burst) ? whichHalf==0:True;
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Bool last = (burst) ? whichHalf==1:True;
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// Technically the following check for legal IO addrs is not
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// necessary; the AXI4 fabric should return a DECERR for illegal
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// addrs; but not all AXI4 fabrics do the right thing.
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if (soc_map.m_is_IO_addr (req.addr, False)) begin
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//fa_fabric_send_write_req (req.addr, truncate(pack(req.byteEn)), fromMemTaggedData(req.data));
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// on first flit...
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// ================
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if (first) begin
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AXI4_AWFlit #(Wd_CoreW_Bus_MId, Wd_Addr, Wd_AW_User)
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mem_req_wr_addr = AXI4_AWFlit {awid: fabric_corew_bus_default_mid,
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awaddr: req.addr,
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awlen: (burst) ? 1:0, // burst len = awlen+1
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awsize: size,
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awburst: fabric_default_burst,
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awlock: fabric_default_lock,
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awcache: fabric_default_awcache,
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awprot: fabric_default_prot,
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awqos: fabric_default_qos,
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awregion: fabric_default_region,
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awuser: 0};
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master_shim.slave.aw.put (mem_req_wr_addr);
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if (cfg_verbosity > 0) begin
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$display ("%d: %m.rl_handle_write_req: sent aw flit:", cur_cycle);
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$display (" ", fshow (mem_req_wr_addr));
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end
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// Expect a fabric response
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ctr_wr_rsps_pending.incr;
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end
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// on last flit...
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// ===============
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if (last) begin
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f_reqs_from_core.deq;
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rg_wr_req_beat <= 0;
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end else // increment flit counter
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rg_wr_req_beat <= rg_wr_req_beat + 1;
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// on each flit...
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// ===============
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AXI4_WFlit #(Wd_Data, Wd_W_User)
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wflit = AXI4_WFlit {wdata: req.data.data[whichHalf],
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wstrb: line_strb[whichHalf],
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wlast: last,
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wuser: 0};
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master_shim.slave.w.put (wflit);
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if (cfg_verbosity > 0) begin
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$display ("%d: %m.rl_handle_write_req: sent w flit:", cur_cycle);
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$display (" ", fshow (wflit), "first: %d, last: %d, whichHalf: %d", first, last, whichHalf);
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end
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end else begin
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let rsp = MMIODataPRs {valid: False,
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data: toMemTaggedData(req.addr)}; // For debugging convenience only
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f_reqs_from_core.deq;
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f_rsps_to_core.enq (rsp);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response",
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cur_cycle);
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$display (" ", fshow (req));
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end
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end
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endrule
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// ----------------
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// Discard write-responses from the fabric
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rule rl_discard_write_rsp;
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let wr_resp <- get(master_shim.slave.b);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_discard_write_rsp", cur_cycle);
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$display (" ", fshow (wr_resp));
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end
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if (ctr_wr_rsps_pending.value == 0) begin
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$display ("%0d:%m.rl_discard_write_rsp: ERROR:unexpected Wr response (ctr_wr_rsps_pending.value == 0)",
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cur_cycle);
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$display (" ", fshow (wr_resp));
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$finish (1); // Assertion failure
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end
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ctr_wr_rsps_pending.decr;
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if (wr_resp.bresp != OKAY) begin
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// TODO: need to raise a non-maskable interrupt (NMI) here
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$display ("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", cur_cycle);
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$display (" ", fshow (wr_resp));
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$finish (1);
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end
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f_rsps_to_core.enq (MMIODataPRs {valid: wr_resp.bresp == OKAY, data: 0});
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endrule
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// ================================================================
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// This adapter should only receive Ld/St requests, no Inst or AMO reqs.
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function Bool fn_is_Ld_or_St (MMIOCRq req);
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return case (req.func) matches
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Ld : True;
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St : True;
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default: False;
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endcase;
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endfunction
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rule rl_handle_non_Ld_St (! fn_is_Ld_or_St (f_reqs_from_core.first));
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let req <- pop (f_reqs_from_core);
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$display ("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", cur_cycle);
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$display (" ", fshow (req));
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$finish (1); // Assertion failure
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endrule
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// ================================================================
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// INTERFACE
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method Action reset;
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ctr_wr_rsps_pending.clear;
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endmethod
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interface Server core_side = toGPServer (f_reqs_from_core, f_rsps_to_core);
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// Fabric master interface for IO
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interface mmio_master = master_shim.master;
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endmodule
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// ================================================================
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endpackage
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