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e7fbf32b3842782bef451f7420fa7a9c6fefc01f
Toooba/src_SSITH_P3/Verilog_RTL/mkCore.v
rsnikhil e7fbf32b38 Bugfix in MMIOPlatform.bsv for instruction-fetch from IO addrs 
Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response.  This was causing a deadlock.
2019-04-17 15:29:10 -04:00

37947 lines
1.7 MiB
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//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_coreReq_start O 1 const
// RDY_coreReq_perfReq O 1 reg
// coreIndInv_perfResp O 73
// RDY_coreIndInv_perfResp O 1 reg
// RDY_coreIndInv_terminate O 1 reg
// dCacheToParent_rsToP_notEmpty O 1
// RDY_dCacheToParent_rsToP_notEmpty O 1 const
// RDY_dCacheToParent_rsToP_deq O 1
// dCacheToParent_rsToP_first O 579
// RDY_dCacheToParent_rsToP_first O 1
// dCacheToParent_rqToP_notEmpty O 1
// RDY_dCacheToParent_rqToP_notEmpty O 1 const
// RDY_dCacheToParent_rqToP_deq O 1
// dCacheToParent_rqToP_first O 72
// RDY_dCacheToParent_rqToP_first O 1
// dCacheToParent_fromP_notFull O 1
// RDY_dCacheToParent_fromP_notFull O 1 const
// RDY_dCacheToParent_fromP_enq O 1
// iCacheToParent_rsToP_notEmpty O 1
// RDY_iCacheToParent_rsToP_notEmpty O 1 const
// RDY_iCacheToParent_rsToP_deq O 1
// iCacheToParent_rsToP_first O 579
// RDY_iCacheToParent_rsToP_first O 1
// iCacheToParent_rqToP_notEmpty O 1
// RDY_iCacheToParent_rqToP_notEmpty O 1 const
// RDY_iCacheToParent_rqToP_deq O 1
// iCacheToParent_rqToP_first O 72
// RDY_iCacheToParent_rqToP_first O 1
// iCacheToParent_fromP_notFull O 1
// RDY_iCacheToParent_fromP_notFull O 1 const
// RDY_iCacheToParent_fromP_enq O 1
// tlbToMem_memReq_notEmpty O 1
// RDY_tlbToMem_memReq_notEmpty O 1 const
// RDY_tlbToMem_memReq_deq O 1
// tlbToMem_memReq_first O 65
// RDY_tlbToMem_memReq_first O 1
// tlbToMem_respLd_notFull O 1
// RDY_tlbToMem_respLd_notFull O 1 const
// RDY_tlbToMem_respLd_enq O 1
// mmioToPlatform_cRq_notEmpty O 1
// RDY_mmioToPlatform_cRq_notEmpty O 1 const
// RDY_mmioToPlatform_cRq_deq O 1
// mmioToPlatform_cRq_first O 142
// RDY_mmioToPlatform_cRq_first O 1
// mmioToPlatform_pRs_notFull O 1
// RDY_mmioToPlatform_pRs_notFull O 1 const
// RDY_mmioToPlatform_pRs_enq O 1
// mmioToPlatform_pRq_notFull O 1
// RDY_mmioToPlatform_pRq_notFull O 1 const
// RDY_mmioToPlatform_pRq_enq O 1
// mmioToPlatform_cRs_notEmpty O 1
// RDY_mmioToPlatform_cRs_notEmpty O 1 const
// RDY_mmioToPlatform_cRs_deq O 1
// mmioToPlatform_cRs_first O 1 reg
// RDY_mmioToPlatform_cRs_first O 1
// RDY_mmioToPlatform_setTime O 1 const
// sendDoStats O 1 reg
// RDY_sendDoStats O 1 reg
// RDY_recvDoStats O 1 const
// deadlock_dCacheCRqStuck_get O 73 const
// RDY_deadlock_dCacheCRqStuck_get O 1 const
// deadlock_dCachePRqStuck_get O 68 const
// RDY_deadlock_dCachePRqStuck_get O 1 const
// deadlock_iCacheCRqStuck_get O 68 const
// RDY_deadlock_iCacheCRqStuck_get O 1 const
// deadlock_iCachePRqStuck_get O 68 const
// RDY_deadlock_iCachePRqStuck_get O 1 const
// deadlock_renameInstStuck_get O 78 const
// RDY_deadlock_renameInstStuck_get O 1 const
// deadlock_renameCorrectPathStuck_get O 78 const
// RDY_deadlock_renameCorrectPathStuck_get O 1 const
// deadlock_commitInstStuck_get O 163 const
// RDY_deadlock_commitInstStuck_get O 1 const
// deadlock_commitUserInstStuck_get O 163 const
// RDY_deadlock_commitUserInstStuck_get O 1 const
// RDY_deadlock_checkStarted_get O 1 const
// renameDebug_renameErr_get O 89 const
// RDY_renameDebug_renameErr_get O 1 const
// RDY_setMEIP O 1 const
// RDY_setSEIP O 1 const
// RDY_setDEIP O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// coreReq_start_startpc I 64
// coreReq_start_toHostAddr I 64 reg
// coreReq_start_fromHostAddr I 64 reg
// coreReq_perfReq_loc I 4 reg
// coreReq_perfReq_t I 5 reg
// dCacheToParent_fromP_enq_x I 583
// iCacheToParent_fromP_enq_x I 583
// tlbToMem_respLd_enq_x I 65
// mmioToPlatform_pRs_enq_x I 67
// mmioToPlatform_pRq_enq_x I 39
// mmioToPlatform_setTime_t I 64 reg
// recvDoStats_x I 1 reg
// setMEIP_v I 1
// setSEIP_v I 1
// setDEIP_v I 1
// EN_coreReq_start I 1
// EN_coreReq_perfReq I 1
// EN_coreIndInv_terminate I 1
// EN_dCacheToParent_rsToP_deq I 1
// EN_dCacheToParent_rqToP_deq I 1
// EN_dCacheToParent_fromP_enq I 1
// EN_iCacheToParent_rsToP_deq I 1
// EN_iCacheToParent_rqToP_deq I 1
// EN_iCacheToParent_fromP_enq I 1
// EN_tlbToMem_memReq_deq I 1
// EN_tlbToMem_respLd_enq I 1
// EN_mmioToPlatform_cRq_deq I 1
// EN_mmioToPlatform_pRs_enq I 1
// EN_mmioToPlatform_pRq_enq I 1
// EN_mmioToPlatform_cRs_deq I 1
// EN_mmioToPlatform_setTime I 1
// EN_recvDoStats I 1
// EN_deadlock_checkStarted_get I 1 unused
// EN_setMEIP I 1
// EN_setSEIP I 1
// EN_setDEIP I 1
// EN_coreIndInv_perfResp I 1
// EN_sendDoStats I 1
// EN_deadlock_dCacheCRqStuck_get I 1 unused
// EN_deadlock_dCachePRqStuck_get I 1 unused
// EN_deadlock_iCacheCRqStuck_get I 1 unused
// EN_deadlock_iCachePRqStuck_get I 1 unused
// EN_deadlock_renameInstStuck_get I 1 unused
// EN_deadlock_renameCorrectPathStuck_get I 1 unused
// EN_deadlock_commitInstStuck_get I 1 unused
// EN_deadlock_commitUserInstStuck_get I 1 unused
// EN_renameDebug_renameErr_get I 1 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCore(CLK,
RST_N,
coreReq_start_startpc,
coreReq_start_toHostAddr,
coreReq_start_fromHostAddr,
EN_coreReq_start,
RDY_coreReq_start,
coreReq_perfReq_loc,
coreReq_perfReq_t,
EN_coreReq_perfReq,
RDY_coreReq_perfReq,
EN_coreIndInv_perfResp,
coreIndInv_perfResp,
RDY_coreIndInv_perfResp,
EN_coreIndInv_terminate,
RDY_coreIndInv_terminate,
dCacheToParent_rsToP_notEmpty,
RDY_dCacheToParent_rsToP_notEmpty,
EN_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_deq,
dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_first,
dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rqToP_notEmpty,
EN_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_deq,
dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_first,
dCacheToParent_fromP_notFull,
RDY_dCacheToParent_fromP_notFull,
dCacheToParent_fromP_enq_x,
EN_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_enq,
iCacheToParent_rsToP_notEmpty,
RDY_iCacheToParent_rsToP_notEmpty,
EN_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_deq,
iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_first,
iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rqToP_notEmpty,
EN_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_deq,
iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_first,
iCacheToParent_fromP_notFull,
RDY_iCacheToParent_fromP_notFull,
iCacheToParent_fromP_enq_x,
EN_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_enq,
tlbToMem_memReq_notEmpty,
RDY_tlbToMem_memReq_notEmpty,
EN_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_deq,
tlbToMem_memReq_first,
RDY_tlbToMem_memReq_first,
tlbToMem_respLd_notFull,
RDY_tlbToMem_respLd_notFull,
tlbToMem_respLd_enq_x,
EN_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_enq,
mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRq_notEmpty,
EN_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_deq,
mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_first,
mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_pRs_notFull,
mmioToPlatform_pRs_enq_x,
EN_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_enq,
mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRq_notFull,
mmioToPlatform_pRq_enq_x,
EN_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_enq,
mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_cRs_notEmpty,
EN_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_deq,
mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_first,
mmioToPlatform_setTime_t,
EN_mmioToPlatform_setTime,
RDY_mmioToPlatform_setTime,
EN_sendDoStats,
sendDoStats,
RDY_sendDoStats,
recvDoStats_x,
EN_recvDoStats,
RDY_recvDoStats,
EN_deadlock_dCacheCRqStuck_get,
deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
EN_deadlock_dCachePRqStuck_get,
deadlock_dCachePRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
EN_deadlock_iCacheCRqStuck_get,
deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
EN_deadlock_iCachePRqStuck_get,
deadlock_iCachePRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
EN_deadlock_renameInstStuck_get,
deadlock_renameInstStuck_get,
RDY_deadlock_renameInstStuck_get,
EN_deadlock_renameCorrectPathStuck_get,
deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
EN_deadlock_commitInstStuck_get,
deadlock_commitInstStuck_get,
RDY_deadlock_commitInstStuck_get,
EN_deadlock_commitUserInstStuck_get,
deadlock_commitUserInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
EN_deadlock_checkStarted_get,
RDY_deadlock_checkStarted_get,
EN_renameDebug_renameErr_get,
renameDebug_renameErr_get,
RDY_renameDebug_renameErr_get,
setMEIP_v,
EN_setMEIP,
RDY_setMEIP,
setSEIP_v,
EN_setSEIP,
RDY_setSEIP,
setDEIP_v,
EN_setDEIP,
RDY_setDEIP);
input CLK;
input RST_N;
// action method coreReq_start
input [63 : 0] coreReq_start_startpc;
input [63 : 0] coreReq_start_toHostAddr;
input [63 : 0] coreReq_start_fromHostAddr;
input EN_coreReq_start;
output RDY_coreReq_start;
// action method coreReq_perfReq
input [3 : 0] coreReq_perfReq_loc;
input [4 : 0] coreReq_perfReq_t;
input EN_coreReq_perfReq;
output RDY_coreReq_perfReq;
// actionvalue method coreIndInv_perfResp
input EN_coreIndInv_perfResp;
output [72 : 0] coreIndInv_perfResp;
output RDY_coreIndInv_perfResp;
// action method coreIndInv_terminate
input EN_coreIndInv_terminate;
output RDY_coreIndInv_terminate;
// value method dCacheToParent_rsToP_notEmpty
output dCacheToParent_rsToP_notEmpty;
output RDY_dCacheToParent_rsToP_notEmpty;
// action method dCacheToParent_rsToP_deq
input EN_dCacheToParent_rsToP_deq;
output RDY_dCacheToParent_rsToP_deq;
// value method dCacheToParent_rsToP_first
output [578 : 0] dCacheToParent_rsToP_first;
output RDY_dCacheToParent_rsToP_first;
// value method dCacheToParent_rqToP_notEmpty
output dCacheToParent_rqToP_notEmpty;
output RDY_dCacheToParent_rqToP_notEmpty;
// action method dCacheToParent_rqToP_deq
input EN_dCacheToParent_rqToP_deq;
output RDY_dCacheToParent_rqToP_deq;
// value method dCacheToParent_rqToP_first
output [71 : 0] dCacheToParent_rqToP_first;
output RDY_dCacheToParent_rqToP_first;
// value method dCacheToParent_fromP_notFull
output dCacheToParent_fromP_notFull;
output RDY_dCacheToParent_fromP_notFull;
// action method dCacheToParent_fromP_enq
input [582 : 0] dCacheToParent_fromP_enq_x;
input EN_dCacheToParent_fromP_enq;
output RDY_dCacheToParent_fromP_enq;
// value method iCacheToParent_rsToP_notEmpty
output iCacheToParent_rsToP_notEmpty;
output RDY_iCacheToParent_rsToP_notEmpty;
// action method iCacheToParent_rsToP_deq
input EN_iCacheToParent_rsToP_deq;
output RDY_iCacheToParent_rsToP_deq;
// value method iCacheToParent_rsToP_first
output [578 : 0] iCacheToParent_rsToP_first;
output RDY_iCacheToParent_rsToP_first;
// value method iCacheToParent_rqToP_notEmpty
output iCacheToParent_rqToP_notEmpty;
output RDY_iCacheToParent_rqToP_notEmpty;
// action method iCacheToParent_rqToP_deq
input EN_iCacheToParent_rqToP_deq;
output RDY_iCacheToParent_rqToP_deq;
// value method iCacheToParent_rqToP_first
output [71 : 0] iCacheToParent_rqToP_first;
output RDY_iCacheToParent_rqToP_first;
// value method iCacheToParent_fromP_notFull
output iCacheToParent_fromP_notFull;
output RDY_iCacheToParent_fromP_notFull;
// action method iCacheToParent_fromP_enq
input [582 : 0] iCacheToParent_fromP_enq_x;
input EN_iCacheToParent_fromP_enq;
output RDY_iCacheToParent_fromP_enq;
// value method tlbToMem_memReq_notEmpty
output tlbToMem_memReq_notEmpty;
output RDY_tlbToMem_memReq_notEmpty;
// action method tlbToMem_memReq_deq
input EN_tlbToMem_memReq_deq;
output RDY_tlbToMem_memReq_deq;
// value method tlbToMem_memReq_first
output [64 : 0] tlbToMem_memReq_first;
output RDY_tlbToMem_memReq_first;
// value method tlbToMem_respLd_notFull
output tlbToMem_respLd_notFull;
output RDY_tlbToMem_respLd_notFull;
// action method tlbToMem_respLd_enq
input [64 : 0] tlbToMem_respLd_enq_x;
input EN_tlbToMem_respLd_enq;
output RDY_tlbToMem_respLd_enq;
// value method mmioToPlatform_cRq_notEmpty
output mmioToPlatform_cRq_notEmpty;
output RDY_mmioToPlatform_cRq_notEmpty;
// action method mmioToPlatform_cRq_deq
input EN_mmioToPlatform_cRq_deq;
output RDY_mmioToPlatform_cRq_deq;
// value method mmioToPlatform_cRq_first
output [141 : 0] mmioToPlatform_cRq_first;
output RDY_mmioToPlatform_cRq_first;
// value method mmioToPlatform_pRs_notFull
output mmioToPlatform_pRs_notFull;
output RDY_mmioToPlatform_pRs_notFull;
// action method mmioToPlatform_pRs_enq
input [66 : 0] mmioToPlatform_pRs_enq_x;
input EN_mmioToPlatform_pRs_enq;
output RDY_mmioToPlatform_pRs_enq;
// value method mmioToPlatform_pRq_notFull
output mmioToPlatform_pRq_notFull;
output RDY_mmioToPlatform_pRq_notFull;
// action method mmioToPlatform_pRq_enq
input [38 : 0] mmioToPlatform_pRq_enq_x;
input EN_mmioToPlatform_pRq_enq;
output RDY_mmioToPlatform_pRq_enq;
// value method mmioToPlatform_cRs_notEmpty
output mmioToPlatform_cRs_notEmpty;
output RDY_mmioToPlatform_cRs_notEmpty;
// action method mmioToPlatform_cRs_deq
input EN_mmioToPlatform_cRs_deq;
output RDY_mmioToPlatform_cRs_deq;
// value method mmioToPlatform_cRs_first
output mmioToPlatform_cRs_first;
output RDY_mmioToPlatform_cRs_first;
// action method mmioToPlatform_setTime
input [63 : 0] mmioToPlatform_setTime_t;
input EN_mmioToPlatform_setTime;
output RDY_mmioToPlatform_setTime;
// actionvalue method sendDoStats
input EN_sendDoStats;
output sendDoStats;
output RDY_sendDoStats;
// action method recvDoStats
input recvDoStats_x;
input EN_recvDoStats;
output RDY_recvDoStats;
// actionvalue method deadlock_dCacheCRqStuck_get
input EN_deadlock_dCacheCRqStuck_get;
output [72 : 0] deadlock_dCacheCRqStuck_get;
output RDY_deadlock_dCacheCRqStuck_get;
// actionvalue method deadlock_dCachePRqStuck_get
input EN_deadlock_dCachePRqStuck_get;
output [67 : 0] deadlock_dCachePRqStuck_get;
output RDY_deadlock_dCachePRqStuck_get;
// actionvalue method deadlock_iCacheCRqStuck_get
input EN_deadlock_iCacheCRqStuck_get;
output [67 : 0] deadlock_iCacheCRqStuck_get;
output RDY_deadlock_iCacheCRqStuck_get;
// actionvalue method deadlock_iCachePRqStuck_get
input EN_deadlock_iCachePRqStuck_get;
output [67 : 0] deadlock_iCachePRqStuck_get;
output RDY_deadlock_iCachePRqStuck_get;
// actionvalue method deadlock_renameInstStuck_get
input EN_deadlock_renameInstStuck_get;
output [77 : 0] deadlock_renameInstStuck_get;
output RDY_deadlock_renameInstStuck_get;
// actionvalue method deadlock_renameCorrectPathStuck_get
input EN_deadlock_renameCorrectPathStuck_get;
output [77 : 0] deadlock_renameCorrectPathStuck_get;
output RDY_deadlock_renameCorrectPathStuck_get;
// actionvalue method deadlock_commitInstStuck_get
input EN_deadlock_commitInstStuck_get;
output [162 : 0] deadlock_commitInstStuck_get;
output RDY_deadlock_commitInstStuck_get;
// actionvalue method deadlock_commitUserInstStuck_get
input EN_deadlock_commitUserInstStuck_get;
output [162 : 0] deadlock_commitUserInstStuck_get;
output RDY_deadlock_commitUserInstStuck_get;
// action method deadlock_checkStarted_get
input EN_deadlock_checkStarted_get;
output RDY_deadlock_checkStarted_get;
// actionvalue method renameDebug_renameErr_get
input EN_renameDebug_renameErr_get;
output [88 : 0] renameDebug_renameErr_get;
output RDY_renameDebug_renameErr_get;
// action method setMEIP
input setMEIP_v;
input EN_setMEIP;
output RDY_setMEIP;
// action method setSEIP
input setSEIP_v;
input EN_setSEIP;
output RDY_setSEIP;
// action method setDEIP
input setDEIP_v;
input EN_setDEIP;
output RDY_setDEIP;
// signals for module outputs
wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
wire [162 : 0] deadlock_commitInstStuck_get,
deadlock_commitUserInstStuck_get;
wire [141 : 0] mmioToPlatform_cRq_first;
wire [88 : 0] renameDebug_renameErr_get;
wire [77 : 0] deadlock_renameCorrectPathStuck_get,
deadlock_renameInstStuck_get;
wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
wire [67 : 0] deadlock_dCachePRqStuck_get,
deadlock_iCacheCRqStuck_get,
deadlock_iCachePRqStuck_get;
wire [64 : 0] tlbToMem_memReq_first;
wire RDY_coreIndInv_perfResp,
RDY_coreIndInv_terminate,
RDY_coreReq_perfReq,
RDY_coreReq_start,
RDY_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_notFull,
RDY_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_notEmpty,
RDY_deadlock_checkStarted_get,
RDY_deadlock_commitInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameInstStuck_get,
RDY_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_notFull,
RDY_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_notEmpty,
RDY_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_setTime,
RDY_recvDoStats,
RDY_renameDebug_renameErr_get,
RDY_sendDoStats,
RDY_setDEIP,
RDY_setMEIP,
RDY_setSEIP,
RDY_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_first,
RDY_tlbToMem_memReq_notEmpty,
RDY_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_notFull,
dCacheToParent_fromP_notFull,
dCacheToParent_rqToP_notEmpty,
dCacheToParent_rsToP_notEmpty,
iCacheToParent_fromP_notFull,
iCacheToParent_rqToP_notEmpty,
iCacheToParent_rsToP_notEmpty,
mmioToPlatform_cRq_notEmpty,
mmioToPlatform_cRs_first,
mmioToPlatform_cRs_notEmpty,
mmioToPlatform_pRq_notFull,
mmioToPlatform_pRs_notFull,
sendDoStats,
tlbToMem_memReq_notEmpty,
tlbToMem_respLd_notFull;
// inlined wires
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
wire [76 : 0] coreFix_memExe_issueLd$wget;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
coreFix_aluExe_0_bypassWire_1$wget,
coreFix_aluExe_0_bypassWire_2$wget,
coreFix_aluExe_0_bypassWire_3$wget;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
mmio_dataRespQ_enqReq_lat_0$wget;
wire [63 : 0] csrf_mcycle_ehr_data_lat_0$wget;
wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
wire coreFix_aluExe_0_bypassWire_0$whas,
coreFix_aluExe_0_bypassWire_1$whas,
coreFix_aluExe_0_bypassWire_2$whas,
coreFix_aluExe_0_bypassWire_3$whas,
coreFix_aluExe_1_bypassWire_2$whas,
coreFix_aluExe_1_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_bypassWire_2$whas,
coreFix_fpuMulDivExe_0_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_globalSpecUpdate_correctSpecTag_0$whas,
coreFix_globalSpecUpdate_correctSpecTag_1$whas,
coreFix_memExe_bypassWire_2$whas,
coreFix_memExe_bypassWire_3$whas,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
coreFix_memExe_forwardQ_enqReq_lat_0$whas,
coreFix_memExe_issueLd$whas,
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
coreFix_memExe_reqLdQ_data_0_lat_0$whas,
coreFix_memExe_reqLdQ_empty_lat_0$whas,
coreFix_memExe_reqLdQ_full_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
csrInstOrInterruptInflight_lat_1$whas,
csrf_mcycle_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_dummy_1_0$whas,
csrf_minstret_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_lat_1$whas,
mmio_cRqQ_enqReq_lat_0$whas,
mmio_dataPendQ_enqReq_lat_0$whas,
mmio_dataReqQ_enqReq_lat_0$whas,
mmio_dataRespQ_deqReq_lat_0$whas,
mmio_pRsQ_deqReq_lat_0$whas;
// register commitStage_commitTrap
reg [133 : 0] commitStage_commitTrap;
wire [133 : 0] commitStage_commitTrap$D_IN;
wire commitStage_commitTrap$EN;
// register commitStage_rg_instret
reg [63 : 0] commitStage_rg_instret;
wire [63 : 0] commitStage_rg_instret$D_IN;
wire commitStage_rg_instret$EN;
// register coreFix_doStatsReg
reg coreFix_doStatsReg;
wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1
reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1;
wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_data_0
reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
wire coreFix_memExe_dMem_perfReqQ_data_0$EN;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_empty
reg coreFix_memExe_dMem_perfReqQ_empty;
wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
coreFix_memExe_dMem_perfReqQ_empty$EN;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_full
reg coreFix_memExe_dMem_perfReqQ_full;
wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
coreFix_memExe_dMem_perfReqQ_full$EN;
// register coreFix_memExe_forwardQ_clearReq_rl
reg coreFix_memExe_forwardQ_clearReq_rl;
wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
coreFix_memExe_forwardQ_clearReq_rl$EN;
// register coreFix_memExe_forwardQ_data_0
reg [68 : 0] coreFix_memExe_forwardQ_data_0;
wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
wire coreFix_memExe_forwardQ_data_0$EN;
// register coreFix_memExe_forwardQ_data_1
reg [68 : 0] coreFix_memExe_forwardQ_data_1;
wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
wire coreFix_memExe_forwardQ_data_1$EN;
// register coreFix_memExe_forwardQ_deqP
reg coreFix_memExe_forwardQ_deqP;
wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;
// register coreFix_memExe_forwardQ_deqReq_rl
reg coreFix_memExe_forwardQ_deqReq_rl;
wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
coreFix_memExe_forwardQ_deqReq_rl$EN;
// register coreFix_memExe_forwardQ_empty
reg coreFix_memExe_forwardQ_empty;
wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;
// register coreFix_memExe_forwardQ_enqP
reg coreFix_memExe_forwardQ_enqP;
wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;
// register coreFix_memExe_forwardQ_enqReq_rl
reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
wire coreFix_memExe_forwardQ_enqReq_rl$EN;
// register coreFix_memExe_forwardQ_full
reg coreFix_memExe_forwardQ_full;
wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;
// register coreFix_memExe_memRespLdQ_clearReq_rl
reg coreFix_memExe_memRespLdQ_clearReq_rl;
wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
coreFix_memExe_memRespLdQ_clearReq_rl$EN;
// register coreFix_memExe_memRespLdQ_data_0
reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
wire coreFix_memExe_memRespLdQ_data_0$EN;
// register coreFix_memExe_memRespLdQ_data_1
reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
wire coreFix_memExe_memRespLdQ_data_1$EN;
// register coreFix_memExe_memRespLdQ_deqP
reg coreFix_memExe_memRespLdQ_deqP;
wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;
// register coreFix_memExe_memRespLdQ_deqReq_rl
reg coreFix_memExe_memRespLdQ_deqReq_rl;
wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
coreFix_memExe_memRespLdQ_deqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_empty
reg coreFix_memExe_memRespLdQ_empty;
wire coreFix_memExe_memRespLdQ_empty$D_IN,
coreFix_memExe_memRespLdQ_empty$EN;
// register coreFix_memExe_memRespLdQ_enqP
reg coreFix_memExe_memRespLdQ_enqP;
wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;
// register coreFix_memExe_memRespLdQ_enqReq_rl
reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_full
reg coreFix_memExe_memRespLdQ_full;
wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;
// register coreFix_memExe_reqLdQ_data_0_rl
reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLdQ_data_0_rl$EN;
// register coreFix_memExe_reqLdQ_empty_rl
reg coreFix_memExe_reqLdQ_empty_rl;
wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;
// register coreFix_memExe_reqLdQ_full_rl
reg coreFix_memExe_reqLdQ_full_rl;
wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
reg coreFix_memExe_reqLrScAmoQ_empty_rl;
wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_full_rl
reg coreFix_memExe_reqLrScAmoQ_full_rl;
wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_full_rl$EN;
// register coreFix_memExe_reqStQ_data_0_rl
reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
wire coreFix_memExe_reqStQ_data_0_rl$EN;
// register coreFix_memExe_reqStQ_empty_rl
reg coreFix_memExe_reqStQ_empty_rl;
wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;
// register coreFix_memExe_reqStQ_full_rl
reg coreFix_memExe_reqStQ_full_rl;
wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_data_0
reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
wire coreFix_memExe_respLrScAmoQ_data_0$EN;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_empty
reg coreFix_memExe_respLrScAmoQ_empty;
wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
coreFix_memExe_respLrScAmoQ_empty$EN;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_full
reg coreFix_memExe_respLrScAmoQ_full;
wire coreFix_memExe_respLrScAmoQ_full$D_IN,
coreFix_memExe_respLrScAmoQ_full$EN;
// register coreFix_memExe_waitLrScAmoMMIOResp
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
wire coreFix_memExe_waitLrScAmoMMIOResp$EN;
// register csrInstOrInterruptInflight_rl
reg csrInstOrInterruptInflight_rl;
wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;
// register csrf_debug_int_pend
reg csrf_debug_int_pend;
wire csrf_debug_int_pend$D_IN, csrf_debug_int_pend$EN;
// register csrf_external_int_en_vec_0
reg csrf_external_int_en_vec_0;
wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;
// register csrf_external_int_en_vec_1
reg csrf_external_int_en_vec_1;
wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;
// register csrf_external_int_en_vec_3
reg csrf_external_int_en_vec_3;
wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;
// register csrf_external_int_pend_vec_0
reg csrf_external_int_pend_vec_0;
wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;
// register csrf_external_int_pend_vec_1
reg csrf_external_int_pend_vec_1;
wire csrf_external_int_pend_vec_1$D_IN, csrf_external_int_pend_vec_1$EN;
// register csrf_external_int_pend_vec_3
reg csrf_external_int_pend_vec_3;
wire csrf_external_int_pend_vec_3$D_IN, csrf_external_int_pend_vec_3$EN;
// register csrf_fflags_reg
reg [4 : 0] csrf_fflags_reg;
wire [4 : 0] csrf_fflags_reg$D_IN;
wire csrf_fflags_reg$EN;
// register csrf_frm_reg
reg [2 : 0] csrf_frm_reg;
wire [2 : 0] csrf_frm_reg$D_IN;
wire csrf_frm_reg$EN;
// register csrf_fs_reg
reg [1 : 0] csrf_fs_reg;
wire [1 : 0] csrf_fs_reg$D_IN;
wire csrf_fs_reg$EN;
// register csrf_ie_vec_0
reg csrf_ie_vec_0;
wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;
// register csrf_ie_vec_1
reg csrf_ie_vec_1;
wire csrf_ie_vec_1$D_IN, csrf_ie_vec_1$EN;
// register csrf_ie_vec_3
reg csrf_ie_vec_3;
wire csrf_ie_vec_3$D_IN, csrf_ie_vec_3$EN;
// register csrf_mcause_code_reg
reg [3 : 0] csrf_mcause_code_reg;
wire [3 : 0] csrf_mcause_code_reg$D_IN;
wire csrf_mcause_code_reg$EN;
// register csrf_mcause_interrupt_reg
reg csrf_mcause_interrupt_reg;
wire csrf_mcause_interrupt_reg$D_IN, csrf_mcause_interrupt_reg$EN;
// register csrf_mcounteren_cy_reg
reg csrf_mcounteren_cy_reg;
wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;
// register csrf_mcounteren_ir_reg
reg csrf_mcounteren_ir_reg;
wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;
// register csrf_mcounteren_tm_reg
reg csrf_mcounteren_tm_reg;
wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;
// register csrf_mcycle_ehr_data_rl
reg [63 : 0] csrf_mcycle_ehr_data_rl;
wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
wire csrf_mcycle_ehr_data_rl$EN;
// register csrf_medeleg_13_11_reg
reg [2 : 0] csrf_medeleg_13_11_reg;
wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
wire csrf_medeleg_13_11_reg$EN;
// register csrf_medeleg_15_reg
reg csrf_medeleg_15_reg;
wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;
// register csrf_medeleg_9_0_reg
reg [9 : 0] csrf_medeleg_9_0_reg;
wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
wire csrf_medeleg_9_0_reg$EN;
// register csrf_mepc_csr
reg [63 : 0] csrf_mepc_csr;
wire [63 : 0] csrf_mepc_csr$D_IN;
wire csrf_mepc_csr$EN;
// register csrf_mideleg_11_reg
reg csrf_mideleg_11_reg;
wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;
// register csrf_mideleg_1_0_reg
reg [1 : 0] csrf_mideleg_1_0_reg;
wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
wire csrf_mideleg_1_0_reg$EN;
// register csrf_mideleg_5_3_reg
reg [2 : 0] csrf_mideleg_5_3_reg;
wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
wire csrf_mideleg_5_3_reg$EN;
// register csrf_mideleg_9_7_reg
reg [2 : 0] csrf_mideleg_9_7_reg;
wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
wire csrf_mideleg_9_7_reg$EN;
// register csrf_minstret_ehr_data_rl
reg [63 : 0] csrf_minstret_ehr_data_rl;
wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
wire csrf_minstret_ehr_data_rl$EN;
// register csrf_mpp_reg
reg [1 : 0] csrf_mpp_reg;
wire [1 : 0] csrf_mpp_reg$D_IN;
wire csrf_mpp_reg$EN;
// register csrf_mprv_reg
reg csrf_mprv_reg;
wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;
// register csrf_mscratch_csr
reg [63 : 0] csrf_mscratch_csr;
wire [63 : 0] csrf_mscratch_csr$D_IN;
wire csrf_mscratch_csr$EN;
// register csrf_mtval_csr
reg [63 : 0] csrf_mtval_csr;
wire [63 : 0] csrf_mtval_csr$D_IN;
wire csrf_mtval_csr$EN;
// register csrf_mtvec_base_hi_reg
reg [61 : 0] csrf_mtvec_base_hi_reg;
wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
wire csrf_mtvec_base_hi_reg$EN;
// register csrf_mtvec_mode_low_reg
reg csrf_mtvec_mode_low_reg;
wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;
// register csrf_mxr_reg
reg csrf_mxr_reg;
wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;
// register csrf_ppn_reg
reg [43 : 0] csrf_ppn_reg;
wire [43 : 0] csrf_ppn_reg$D_IN;
wire csrf_ppn_reg$EN;
// register csrf_prev_ie_vec_0
reg csrf_prev_ie_vec_0;
wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;
// register csrf_prev_ie_vec_1
reg csrf_prev_ie_vec_1;
wire csrf_prev_ie_vec_1$D_IN, csrf_prev_ie_vec_1$EN;
// register csrf_prev_ie_vec_3
reg csrf_prev_ie_vec_3;
wire csrf_prev_ie_vec_3$D_IN, csrf_prev_ie_vec_3$EN;
// register csrf_prv_reg
reg [1 : 0] csrf_prv_reg;
wire [1 : 0] csrf_prv_reg$D_IN;
wire csrf_prv_reg$EN;
// register csrf_scause_code_reg
reg [3 : 0] csrf_scause_code_reg;
wire [3 : 0] csrf_scause_code_reg$D_IN;
wire csrf_scause_code_reg$EN;
// register csrf_scause_interrupt_reg
reg csrf_scause_interrupt_reg;
wire csrf_scause_interrupt_reg$D_IN, csrf_scause_interrupt_reg$EN;
// register csrf_scounteren_cy_reg
reg csrf_scounteren_cy_reg;
wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;
// register csrf_scounteren_ir_reg
reg csrf_scounteren_ir_reg;
wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;
// register csrf_scounteren_tm_reg
reg csrf_scounteren_tm_reg;
wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;
// register csrf_sepc_csr
reg [63 : 0] csrf_sepc_csr;
wire [63 : 0] csrf_sepc_csr$D_IN;
wire csrf_sepc_csr$EN;
// register csrf_software_int_en_vec_0
reg csrf_software_int_en_vec_0;
wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;
// register csrf_software_int_en_vec_1
reg csrf_software_int_en_vec_1;
wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;
// register csrf_software_int_en_vec_3
reg csrf_software_int_en_vec_3;
wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;
// register csrf_software_int_pend_vec_0
reg csrf_software_int_pend_vec_0;
wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;
// register csrf_software_int_pend_vec_1
reg csrf_software_int_pend_vec_1;
wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;
// register csrf_software_int_pend_vec_3
reg csrf_software_int_pend_vec_3;
wire csrf_software_int_pend_vec_3$D_IN, csrf_software_int_pend_vec_3$EN;
// register csrf_spp_reg
reg csrf_spp_reg;
wire csrf_spp_reg$D_IN, csrf_spp_reg$EN;
// register csrf_sscratch_csr
reg [63 : 0] csrf_sscratch_csr;
wire [63 : 0] csrf_sscratch_csr$D_IN;
wire csrf_sscratch_csr$EN;
// register csrf_stats_module_doStats
reg csrf_stats_module_doStats;
wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;
// register csrf_stval_csr
reg [63 : 0] csrf_stval_csr;
wire [63 : 0] csrf_stval_csr$D_IN;
wire csrf_stval_csr$EN;
// register csrf_stvec_base_hi_reg
reg [61 : 0] csrf_stvec_base_hi_reg;
wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
wire csrf_stvec_base_hi_reg$EN;
// register csrf_stvec_mode_low_reg
reg csrf_stvec_mode_low_reg;
wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;
// register csrf_sum_reg
reg csrf_sum_reg;
wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;
// register csrf_time_reg
reg [63 : 0] csrf_time_reg;
wire [63 : 0] csrf_time_reg$D_IN;
wire csrf_time_reg$EN;
// register csrf_timer_int_en_vec_0
reg csrf_timer_int_en_vec_0;
wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;
// register csrf_timer_int_en_vec_1
reg csrf_timer_int_en_vec_1;
wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;
// register csrf_timer_int_en_vec_3
reg csrf_timer_int_en_vec_3;
wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;
// register csrf_timer_int_pend_vec_0
reg csrf_timer_int_pend_vec_0;
wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;
// register csrf_timer_int_pend_vec_1
reg csrf_timer_int_pend_vec_1;
wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;
// register csrf_timer_int_pend_vec_3
reg csrf_timer_int_pend_vec_3;
wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;
// register csrf_tsr_reg
reg csrf_tsr_reg;
wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;
// register csrf_tvm_reg
reg csrf_tvm_reg;
wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;
// register csrf_tw_reg
reg csrf_tw_reg;
wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;
// register csrf_vm_mode_sv39_reg
reg csrf_vm_mode_sv39_reg;
wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;
// register flush_reservation
reg flush_reservation;
wire flush_reservation$D_IN, flush_reservation$EN;
// register flush_tlbs
reg flush_tlbs;
wire flush_tlbs$D_IN, flush_tlbs$EN;
// register mmio_cRqQ_clearReq_rl
reg mmio_cRqQ_clearReq_rl;
wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;
// register mmio_cRqQ_data_0
reg [141 : 0] mmio_cRqQ_data_0;
wire [141 : 0] mmio_cRqQ_data_0$D_IN;
wire mmio_cRqQ_data_0$EN;
// register mmio_cRqQ_deqReq_rl
reg mmio_cRqQ_deqReq_rl;
wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;
// register mmio_cRqQ_empty
reg mmio_cRqQ_empty;
wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;
// register mmio_cRqQ_enqReq_rl
reg [142 : 0] mmio_cRqQ_enqReq_rl;
wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
wire mmio_cRqQ_enqReq_rl$EN;
// register mmio_cRqQ_full
reg mmio_cRqQ_full;
wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;
// register mmio_cRsQ_clearReq_rl
reg mmio_cRsQ_clearReq_rl;
wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;
// register mmio_cRsQ_data_0
reg mmio_cRsQ_data_0;
wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;
// register mmio_cRsQ_deqReq_rl
reg mmio_cRsQ_deqReq_rl;
wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;
// register mmio_cRsQ_empty
reg mmio_cRsQ_empty;
wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;
// register mmio_cRsQ_enqReq_rl
reg [1 : 0] mmio_cRsQ_enqReq_rl;
wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
wire mmio_cRsQ_enqReq_rl$EN;
// register mmio_cRsQ_full
reg mmio_cRsQ_full;
wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;
// register mmio_dataPendQ_clearReq_rl
reg mmio_dataPendQ_clearReq_rl;
wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;
// register mmio_dataPendQ_deqReq_rl
reg mmio_dataPendQ_deqReq_rl;
wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;
// register mmio_dataPendQ_empty
reg mmio_dataPendQ_empty;
wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;
// register mmio_dataPendQ_enqReq_rl
reg mmio_dataPendQ_enqReq_rl;
wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;
// register mmio_dataPendQ_full
reg mmio_dataPendQ_full;
wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;
// register mmio_dataReqQ_clearReq_rl
reg mmio_dataReqQ_clearReq_rl;
wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;
// register mmio_dataReqQ_data_0
reg [141 : 0] mmio_dataReqQ_data_0;
wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
wire mmio_dataReqQ_data_0$EN;
// register mmio_dataReqQ_deqReq_rl
reg mmio_dataReqQ_deqReq_rl;
wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;
// register mmio_dataReqQ_empty
reg mmio_dataReqQ_empty;
wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;
// register mmio_dataReqQ_enqReq_rl
reg [142 : 0] mmio_dataReqQ_enqReq_rl;
wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
wire mmio_dataReqQ_enqReq_rl$EN;
// register mmio_dataReqQ_full
reg mmio_dataReqQ_full;
wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;
// register mmio_dataRespQ_clearReq_rl
reg mmio_dataRespQ_clearReq_rl;
wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;
// register mmio_dataRespQ_data_0
reg [64 : 0] mmio_dataRespQ_data_0;
wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
wire mmio_dataRespQ_data_0$EN;
// register mmio_dataRespQ_deqReq_rl
reg mmio_dataRespQ_deqReq_rl;
wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;
// register mmio_dataRespQ_empty
reg mmio_dataRespQ_empty;
wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;
// register mmio_dataRespQ_enqReq_rl
reg [65 : 0] mmio_dataRespQ_enqReq_rl;
wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
wire mmio_dataRespQ_enqReq_rl$EN;
// register mmio_dataRespQ_full
reg mmio_dataRespQ_full;
wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;
// register mmio_fromHostAddr
reg [60 : 0] mmio_fromHostAddr;
wire [60 : 0] mmio_fromHostAddr$D_IN;
wire mmio_fromHostAddr$EN;
// register mmio_pRqQ_clearReq_rl
reg mmio_pRqQ_clearReq_rl;
wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;
// register mmio_pRqQ_data_0
reg [38 : 0] mmio_pRqQ_data_0;
wire [38 : 0] mmio_pRqQ_data_0$D_IN;
wire mmio_pRqQ_data_0$EN;
// register mmio_pRqQ_deqReq_rl
reg mmio_pRqQ_deqReq_rl;
wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;
// register mmio_pRqQ_empty
reg mmio_pRqQ_empty;
wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;
// register mmio_pRqQ_enqReq_rl
reg [39 : 0] mmio_pRqQ_enqReq_rl;
wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
wire mmio_pRqQ_enqReq_rl$EN;
// register mmio_pRqQ_full
reg mmio_pRqQ_full;
wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;
// register mmio_pRsQ_clearReq_rl
reg mmio_pRsQ_clearReq_rl;
wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;
// register mmio_pRsQ_data_0
reg [66 : 0] mmio_pRsQ_data_0;
wire [66 : 0] mmio_pRsQ_data_0$D_IN;
wire mmio_pRsQ_data_0$EN;
// register mmio_pRsQ_deqReq_rl
reg mmio_pRsQ_deqReq_rl;
wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;
// register mmio_pRsQ_empty
reg mmio_pRsQ_empty;
wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;
// register mmio_pRsQ_enqReq_rl
reg [67 : 0] mmio_pRsQ_enqReq_rl;
wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
wire mmio_pRsQ_enqReq_rl$EN;
// register mmio_pRsQ_full
reg mmio_pRsQ_full;
wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;
// register mmio_toHostAddr
reg [60 : 0] mmio_toHostAddr;
wire [60 : 0] mmio_toHostAddr$D_IN;
wire mmio_toHostAddr$EN;
// register outOfReset
reg outOfReset;
wire outOfReset$D_IN, outOfReset$EN;
// register started
reg started;
wire started$D_IN, started$EN;
// register update_vm_info
reg update_vm_info;
wire update_vm_info$D_IN, update_vm_info$EN;
// ports of submodule coreFix_aluExe_0_dispToRegQ
reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
coreFix_aluExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_dispToRegQ$EN_deq,
coreFix_aluExe_0_dispToRegQ$EN_enq,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_dispToRegQ$RDY_deq,
coreFix_aluExe_0_dispToRegQ$RDY_enq,
coreFix_aluExe_0_dispToRegQ$RDY_first,
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_exeToFinQ
reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [325 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
coreFix_aluExe_0_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_exeToFinQ$EN_deq,
coreFix_aluExe_0_exeToFinQ$EN_enq,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_exeToFinQ$RDY_deq,
coreFix_aluExe_0_exeToFinQ$RDY_enq,
coreFix_aluExe_0_exeToFinQ$RDY_first,
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_regToExeQ
reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
coreFix_aluExe_0_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_regToExeQ$EN_deq,
coreFix_aluExe_0_regToExeQ$EN_enq,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_regToExeQ$RDY_deq,
coreFix_aluExe_0_regToExeQ$RDY_enq,
coreFix_aluExe_0_regToExeQ$RDY_first,
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_rsAlu
reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
coreFix_aluExe_0_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
coreFix_aluExe_0_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
coreFix_aluExe_0_rsAlu$setRegReady_1_put,
coreFix_aluExe_0_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
coreFix_aluExe_0_rsAlu$EN_enq,
coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_rsAlu$RDY_dispatchData,
coreFix_aluExe_0_rsAlu$RDY_doDispatch,
coreFix_aluExe_0_rsAlu$RDY_enq,
coreFix_aluExe_0_rsAlu$canEnq,
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_dispToRegQ
reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
coreFix_aluExe_1_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_dispToRegQ$EN_deq,
coreFix_aluExe_1_dispToRegQ$EN_enq,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_dispToRegQ$RDY_deq,
coreFix_aluExe_1_dispToRegQ$RDY_enq,
coreFix_aluExe_1_dispToRegQ$RDY_first,
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_exeToFinQ
reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [325 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
coreFix_aluExe_1_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_exeToFinQ$EN_deq,
coreFix_aluExe_1_exeToFinQ$EN_enq,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_exeToFinQ$RDY_deq,
coreFix_aluExe_1_exeToFinQ$RDY_enq,
coreFix_aluExe_1_exeToFinQ$RDY_first,
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_regToExeQ
reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
coreFix_aluExe_1_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_regToExeQ$EN_deq,
coreFix_aluExe_1_regToExeQ$EN_enq,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_regToExeQ$RDY_deq,
coreFix_aluExe_1_regToExeQ$RDY_enq,
coreFix_aluExe_1_regToExeQ$RDY_first,
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_rsAlu
reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
coreFix_aluExe_1_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
coreFix_aluExe_1_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
coreFix_aluExe_1_rsAlu$setRegReady_1_put,
coreFix_aluExe_1_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
coreFix_aluExe_1_rsAlu$EN_enq,
coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_rsAlu$RDY_dispatchData,
coreFix_aluExe_1_rsAlu$RDY_doDispatch,
coreFix_aluExe_1_rsAlu$RDY_enq,
coreFix_aluExe_1_rsAlu$canEnq,
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
coreFix_fpuMulDivExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
wire [139 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
wire [203 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;
// ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
coreFix_fpuMulDivExe_0_regToExeQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dTlb
reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
wire [174 : 0] coreFix_memExe_dTlb$procResp;
wire [105 : 0] coreFix_memExe_dTlb$procReq_req;
wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
wire coreFix_memExe_dTlb$EN_deqProcResp,
coreFix_memExe_dTlb$EN_flush,
coreFix_memExe_dTlb$EN_perf_req,
coreFix_memExe_dTlb$EN_perf_resp,
coreFix_memExe_dTlb$EN_perf_setStatus,
coreFix_memExe_dTlb$EN_procReq,
coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dTlb$EN_toParent_flush_request_get,
coreFix_memExe_dTlb$EN_toParent_flush_response_put,
coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
coreFix_memExe_dTlb$EN_updateVMInfo,
coreFix_memExe_dTlb$RDY_deqProcResp,
coreFix_memExe_dTlb$RDY_flush,
coreFix_memExe_dTlb$RDY_procReq,
coreFix_memExe_dTlb$RDY_procResp,
coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
coreFix_memExe_dTlb$flush_done,
coreFix_memExe_dTlb$noPendingReq,
coreFix_memExe_dTlb$perf_setStatus_doStats,
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dispToRegQ
reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
coreFix_memExe_dispToRegQ$first;
wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_dispToRegQ$EN_deq,
coreFix_memExe_dispToRegQ$EN_enq,
coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dispToRegQ$RDY_deq,
coreFix_memExe_dispToRegQ$RDY_enq,
coreFix_memExe_dispToRegQ$RDY_first,
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_lsq
reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
wire [170 : 0] coreFix_memExe_lsq$firstSt;
wire [113 : 0] coreFix_memExe_lsq$firstLd;
wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
wire [74 : 0] coreFix_memExe_lsq$issueLd;
wire [73 : 0] coreFix_memExe_lsq$respLd;
wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
coreFix_memExe_lsq$respLd_alignedData,
coreFix_memExe_lsq$updateAddr_paddr,
coreFix_memExe_lsq$updateData_d;
wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
coreFix_memExe_lsq$enqSt_mem_inst;
wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
coreFix_memExe_lsq$enqLd_spec_bits,
coreFix_memExe_lsq$enqSt_inst_tag,
coreFix_memExe_lsq$enqSt_spec_bits,
coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
wire [9 : 0] coreFix_memExe_lsq$getHit;
wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
coreFix_memExe_lsq$issueLd_shiftedBE,
coreFix_memExe_lsq$updateAddr_shiftedBE;
wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
wire [5 : 0] coreFix_memExe_lsq$getHit_t,
coreFix_memExe_lsq$getOrigBE_t,
coreFix_memExe_lsq$setAtCommit_0_put,
coreFix_memExe_lsq$setAtCommit_1_put,
coreFix_memExe_lsq$updateAddr_lsqTag;
wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
coreFix_memExe_lsq$respLd_t,
coreFix_memExe_lsq$updateAddr_fault;
wire [3 : 0] coreFix_memExe_lsq$updateData_t;
wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
wire coreFix_memExe_lsq$EN_deqLd,
coreFix_memExe_lsq$EN_deqSt,
coreFix_memExe_lsq$EN_enqLd,
coreFix_memExe_lsq$EN_enqSt,
coreFix_memExe_lsq$EN_getHit,
coreFix_memExe_lsq$EN_getIssueLd,
coreFix_memExe_lsq$EN_issueLd,
coreFix_memExe_lsq$EN_respLd,
coreFix_memExe_lsq$EN_setAtCommit_0_put,
coreFix_memExe_lsq$EN_setAtCommit_1_put,
coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_lsq$EN_updateAddr,
coreFix_memExe_lsq$EN_updateData,
coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
coreFix_memExe_lsq$RDY_deqLd,
coreFix_memExe_lsq$RDY_deqSt,
coreFix_memExe_lsq$RDY_enqLd,
coreFix_memExe_lsq$RDY_enqSt,
coreFix_memExe_lsq$RDY_firstLd,
coreFix_memExe_lsq$RDY_firstSt,
coreFix_memExe_lsq$RDY_getIssueLd,
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
coreFix_memExe_lsq$stqEmpty,
coreFix_memExe_lsq$updateAddr,
coreFix_memExe_lsq$updateAddr_isMMIO;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_regToExeQ
reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
coreFix_memExe_regToExeQ$first;
wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_regToExeQ$EN_deq,
coreFix_memExe_regToExeQ$EN_enq,
coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_regToExeQ$RDY_deq,
coreFix_memExe_regToExeQ$RDY_enq,
coreFix_memExe_regToExeQ$RDY_first,
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_0$EN,
coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_1$EN,
coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_2$EN,
coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_1$EN,
coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_2$EN,
coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
coreFix_memExe_reqStQ_full_dummy2_0$EN,
coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
coreFix_memExe_reqStQ_full_dummy2_1$EN,
coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
coreFix_memExe_reqStQ_full_dummy2_2$EN,
coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_rsMem
reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
coreFix_memExe_rsMem$setRegReady_4_put;
reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
coreFix_memExe_rsMem$enq_x;
wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
coreFix_memExe_rsMem$setRegReady_1_put,
coreFix_memExe_rsMem$setRegReady_3_put;
wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
wire coreFix_memExe_rsMem$EN_doDispatch,
coreFix_memExe_rsMem$EN_enq,
coreFix_memExe_rsMem$EN_setRegReady_0_put,
coreFix_memExe_rsMem$EN_setRegReady_1_put,
coreFix_memExe_rsMem$EN_setRegReady_2_put,
coreFix_memExe_rsMem$EN_setRegReady_3_put,
coreFix_memExe_rsMem$EN_setRegReady_4_put,
coreFix_memExe_rsMem$EN_setRobEnqTime,
coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_rsMem$RDY_dispatchData,
coreFix_memExe_rsMem$RDY_doDispatch,
coreFix_memExe_rsMem$RDY_enq,
coreFix_memExe_rsMem$canEnq,
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_stb
wire [635 : 0] coreFix_memExe_stb$issue;
wire [633 : 0] coreFix_memExe_stb$deq;
wire [67 : 0] coreFix_memExe_stb$search;
wire [63 : 0] coreFix_memExe_stb$enq_data,
coreFix_memExe_stb$enq_paddr,
coreFix_memExe_stb$getEnqIndex_paddr,
coreFix_memExe_stb$noMatchLdQ_paddr,
coreFix_memExe_stb$noMatchStQ_paddr,
coreFix_memExe_stb$search_paddr;
wire [7 : 0] coreFix_memExe_stb$enq_be,
coreFix_memExe_stb$noMatchLdQ_be,
coreFix_memExe_stb$noMatchStQ_be,
coreFix_memExe_stb$search_be;
wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
wire coreFix_memExe_stb$EN_deq,
coreFix_memExe_stb$EN_enq,
coreFix_memExe_stb$EN_issue,
coreFix_memExe_stb$RDY_deq,
coreFix_memExe_stb$RDY_enq,
coreFix_memExe_stb$RDY_issue,
coreFix_memExe_stb$isEmpty,
coreFix_memExe_stb$noMatchLdQ,
coreFix_memExe_stb$noMatchStQ;
// ports of submodule coreFix_trainBPQ_0
wire [158 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
wire coreFix_trainBPQ_0$CLR,
coreFix_trainBPQ_0$DEQ,
coreFix_trainBPQ_0$EMPTY_N,
coreFix_trainBPQ_0$ENQ,
coreFix_trainBPQ_0$FULL_N;
// ports of submodule coreFix_trainBPQ_1
wire [158 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
wire coreFix_trainBPQ_1$CLR,
coreFix_trainBPQ_1$DEQ,
coreFix_trainBPQ_1$EMPTY_N,
coreFix_trainBPQ_1$ENQ,
coreFix_trainBPQ_1$FULL_N;
// ports of submodule csrInstOrInterruptInflight_dummy2_0
wire csrInstOrInterruptInflight_dummy2_0$D_IN,
csrInstOrInterruptInflight_dummy2_0$EN,
csrInstOrInterruptInflight_dummy2_0$Q_OUT;
// ports of submodule csrInstOrInterruptInflight_dummy2_1
wire csrInstOrInterruptInflight_dummy2_1$D_IN,
csrInstOrInterruptInflight_dummy2_1$EN,
csrInstOrInterruptInflight_dummy2_1$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_0
wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
csrf_mcycle_ehr_data_dummy2_0$EN,
csrf_mcycle_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_1
wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
csrf_mcycle_ehr_data_dummy2_1$EN,
csrf_mcycle_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_0
wire csrf_minstret_ehr_data_dummy2_0$D_IN,
csrf_minstret_ehr_data_dummy2_0$EN,
csrf_minstret_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_1
wire csrf_minstret_ehr_data_dummy2_1$D_IN,
csrf_minstret_ehr_data_dummy2_1$EN,
csrf_minstret_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_stats_module_writeQ
wire csrf_stats_module_writeQ$CLR,
csrf_stats_module_writeQ$DEQ,
csrf_stats_module_writeQ$D_IN,
csrf_stats_module_writeQ$D_OUT,
csrf_stats_module_writeQ$EMPTY_N,
csrf_stats_module_writeQ$ENQ,
csrf_stats_module_writeQ$FULL_N;
// ports of submodule csrf_terminate_module_terminateQ
wire csrf_terminate_module_terminateQ$CLR,
csrf_terminate_module_terminateQ$DEQ,
csrf_terminate_module_terminateQ$EMPTY_N,
csrf_terminate_module_terminateQ$ENQ,
csrf_terminate_module_terminateQ$FULL_N;
// ports of submodule epochManager
wire [3 : 0] epochManager$checkEpoch_0_check_e,
epochManager$checkEpoch_1_check_e,
epochManager$updatePrevEpoch_0_update_e,
epochManager$updatePrevEpoch_1_update_e;
wire epochManager$EN_incrementEpoch,
epochManager$EN_updatePrevEpoch_0_update,
epochManager$EN_updatePrevEpoch_1_update,
epochManager$RDY_incrementEpoch,
epochManager$checkEpoch_0_check,
epochManager$checkEpoch_1_check;
// ports of submodule fetchStage
reg [63 : 0] fetchStage$redirect_pc;
wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
fetchStage$iMemIfc_pRqStuck_get;
wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
fetchStage$iTlbIfc_to_proc_request_put,
fetchStage$mmioIfc_instReq_first_fst,
fetchStage$mmioIfc_setHtifAddrs_fromHost,
fetchStage$mmioIfc_setHtifAddrs_toHost,
fetchStage$start_pc,
fetchStage$train_predictors_next_pc,
fetchStage$train_predictors_pc;
wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
wire [23 : 0] fetchStage$train_predictors_dpTrain;
wire [4 : 0] fetchStage$train_predictors_iType;
wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
wire fetchStage$EN_done_flushing,
fetchStage$EN_flush_predictors,
fetchStage$EN_iMemIfc_cRqStuck_get,
fetchStage$EN_iMemIfc_flush,
fetchStage$EN_iMemIfc_pRqStuck_get,
fetchStage$EN_iMemIfc_perf_req,
fetchStage$EN_iMemIfc_perf_resp,
fetchStage$EN_iMemIfc_perf_setStatus,
fetchStage$EN_iMemIfc_to_parent_fromP_enq,
fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
fetchStage$EN_iMemIfc_to_proc_request_put,
fetchStage$EN_iMemIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_flush,
fetchStage$EN_iTlbIfc_perf_req,
fetchStage$EN_iTlbIfc_perf_resp,
fetchStage$EN_iTlbIfc_perf_setStatus,
fetchStage$EN_iTlbIfc_toParent_flush_request_get,
fetchStage$EN_iTlbIfc_toParent_flush_response_put,
fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
fetchStage$EN_iTlbIfc_to_proc_request_put,
fetchStage$EN_iTlbIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_updateVMInfo,
fetchStage$EN_mmioIfc_instReq_deq,
fetchStage$EN_mmioIfc_instResp_enq,
fetchStage$EN_mmioIfc_setHtifAddrs,
fetchStage$EN_perf_req,
fetchStage$EN_perf_resp,
fetchStage$EN_perf_setStatus,
fetchStage$EN_pipelines_0_deq,
fetchStage$EN_pipelines_1_deq,
fetchStage$EN_redirect,
fetchStage$EN_setWaitRedirect,
fetchStage$EN_start,
fetchStage$EN_stop,
fetchStage$EN_train_predictors,
fetchStage$RDY_done_flushing,
fetchStage$RDY_iMemIfc_cRqStuck_get,
fetchStage$RDY_iMemIfc_pRqStuck_get,
fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
fetchStage$RDY_iTlbIfc_flush,
fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
fetchStage$RDY_mmioIfc_instReq_deq,
fetchStage$RDY_mmioIfc_instReq_first_fst,
fetchStage$RDY_mmioIfc_instReq_first_snd,
fetchStage$RDY_mmioIfc_instResp_enq,
fetchStage$RDY_pipelines_0_deq,
fetchStage$RDY_pipelines_0_first,
fetchStage$RDY_pipelines_1_deq,
fetchStage$RDY_pipelines_1_first,
fetchStage$iMemIfc_perf_setStatus_doStats,
fetchStage$iMemIfc_to_parent_fromP_notFull,
fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
fetchStage$iTlbIfc_flush_done,
fetchStage$iTlbIfc_noPendingReq,
fetchStage$iTlbIfc_perf_setStatus_doStats,
fetchStage$mmioIfc_instReq_first_snd,
fetchStage$perf_setStatus_doStats,
fetchStage$pipelines_0_canDeq,
fetchStage$pipelines_1_canDeq,
fetchStage$train_predictors_mispred,
fetchStage$train_predictors_taken;
// ports of submodule l2Tlb
wire [83 : 0] l2Tlb$toChildren_rsToC_first;
wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
wire [3 : 0] l2Tlb$perf_req_r;
wire l2Tlb$EN_perf_req,
l2Tlb$EN_perf_resp,
l2Tlb$EN_perf_setStatus,
l2Tlb$EN_toChildren_dTlbReqFlush_put,
l2Tlb$EN_toChildren_flushDone_get,
l2Tlb$EN_toChildren_iTlbReqFlush_put,
l2Tlb$EN_toChildren_rqFromC_put,
l2Tlb$EN_toChildren_rsToC_deq,
l2Tlb$EN_toMem_memReq_deq,
l2Tlb$EN_toMem_respLd_enq,
l2Tlb$EN_updateVMInfo,
l2Tlb$RDY_toChildren_dTlbReqFlush_put,
l2Tlb$RDY_toChildren_flushDone_get,
l2Tlb$RDY_toChildren_iTlbReqFlush_put,
l2Tlb$RDY_toChildren_rqFromC_put,
l2Tlb$RDY_toChildren_rsToC_deq,
l2Tlb$RDY_toChildren_rsToC_first,
l2Tlb$RDY_toMem_memReq_deq,
l2Tlb$RDY_toMem_memReq_first,
l2Tlb$RDY_toMem_respLd_enq,
l2Tlb$perf_setStatus_doStats,
l2Tlb$toMem_memReq_notEmpty,
l2Tlb$toMem_respLd_notFull;
// ports of submodule mmio_cRqQ_clearReq_dummy2_0
wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_clearReq_dummy2_1
wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
mmio_cRqQ_clearReq_dummy2_1$EN,
mmio_cRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRqQ_deqReq_dummy2_0
wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_1
wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_2
wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
mmio_cRqQ_deqReq_dummy2_2$EN,
mmio_cRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRqQ_enqReq_dummy2_0
wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_1
wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_2
wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
mmio_cRqQ_enqReq_dummy2_2$EN,
mmio_cRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_clearReq_dummy2_0
wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_clearReq_dummy2_1
wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
mmio_cRsQ_clearReq_dummy2_1$EN,
mmio_cRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRsQ_deqReq_dummy2_0
wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_1
wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_2
wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
mmio_cRsQ_deqReq_dummy2_2$EN,
mmio_cRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_enqReq_dummy2_0
wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_1
wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_2
wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
mmio_cRsQ_enqReq_dummy2_2$EN,
mmio_cRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_0
wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
mmio_dataPendQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_1
wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
mmio_dataPendQ_clearReq_dummy2_1$EN,
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_0
wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_1
wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_2
wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
mmio_dataPendQ_deqReq_dummy2_2$EN,
mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_0
wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_1
wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_2
wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
mmio_dataPendQ_enqReq_dummy2_2$EN,
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_0
wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
mmio_dataReqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_1
wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
mmio_dataReqQ_clearReq_dummy2_1$EN,
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_0
wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_1
wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_2
wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
mmio_dataReqQ_deqReq_dummy2_2$EN,
mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_0
wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_1
wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_2
wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
mmio_dataReqQ_enqReq_dummy2_2$EN,
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_0
wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
mmio_dataRespQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_1
wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
mmio_dataRespQ_clearReq_dummy2_1$EN,
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_0
wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_1
wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_2
wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
mmio_dataRespQ_deqReq_dummy2_2$EN,
mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_0
wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_1
wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_2
wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
mmio_dataRespQ_enqReq_dummy2_2$EN,
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_clearReq_dummy2_0
wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_clearReq_dummy2_1
wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
mmio_pRqQ_clearReq_dummy2_1$EN,
mmio_pRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRqQ_deqReq_dummy2_0
wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_1
wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_2
wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
mmio_pRqQ_deqReq_dummy2_2$EN,
mmio_pRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_enqReq_dummy2_0
wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_1
wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_2
wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
mmio_pRqQ_enqReq_dummy2_2$EN,
mmio_pRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_clearReq_dummy2_0
wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_clearReq_dummy2_1
wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
mmio_pRsQ_clearReq_dummy2_1$EN,
mmio_pRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRsQ_deqReq_dummy2_0
wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_1
wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_2
wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
mmio_pRsQ_deqReq_dummy2_2$EN,
mmio_pRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_enqReq_dummy2_0
wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_1
wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_2
wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
mmio_pRsQ_enqReq_dummy2_2$EN,
mmio_pRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ
wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
wire perfReqQ$CLR,
perfReqQ$DEQ,
perfReqQ$EMPTY_N,
perfReqQ$ENQ,
perfReqQ$FULL_N;
// ports of submodule regRenamingTable
reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
wire [32 : 0] regRenamingTable$rename_0_getRename,
regRenamingTable$rename_1_getRename;
wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
regRenamingTable$rename_0_getRename_r,
regRenamingTable$rename_1_claimRename_r,
regRenamingTable$rename_1_getRename_r;
wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
regRenamingTable$rename_1_claimRename_sb,
regRenamingTable$specUpdate_correctSpeculation_mask;
wire regRenamingTable$EN_commit_0_commit,
regRenamingTable$EN_commit_1_commit,
regRenamingTable$EN_rename_0_claimRename,
regRenamingTable$EN_rename_1_claimRename,
regRenamingTable$EN_specUpdate_correctSpeculation,
regRenamingTable$EN_specUpdate_incorrectSpeculation,
regRenamingTable$RDY_commit_0_commit,
regRenamingTable$RDY_commit_1_commit,
regRenamingTable$RDY_rename_0_claimRename,
regRenamingTable$RDY_rename_0_getRename,
regRenamingTable$RDY_rename_1_claimRename,
regRenamingTable$RDY_rename_1_getRename,
regRenamingTable$rename_0_canRename,
regRenamingTable$rename_1_canRename,
regRenamingTable$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule rf
reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
wire [63 : 0] rf$read_0_rd1,
rf$read_0_rd2,
rf$read_1_rd1,
rf$read_1_rd2,
rf$read_2_rd1,
rf$read_2_rd2,
rf$read_2_rd3,
rf$read_3_rd1,
rf$read_3_rd2,
rf$write_0_wr_data,
rf$write_1_wr_data;
wire [6 : 0] rf$read_0_rd1_rindx,
rf$read_0_rd2_rindx,
rf$read_0_rd3_rindx,
rf$read_1_rd1_rindx,
rf$read_1_rd2_rindx,
rf$read_1_rd3_rindx,
rf$read_2_rd1_rindx,
rf$read_2_rd2_rindx,
rf$read_2_rd3_rindx,
rf$read_3_rd1_rindx,
rf$read_3_rd2_rindx,
rf$read_3_rd3_rindx,
rf$write_0_wr_rindx,
rf$write_1_wr_rindx;
wire rf$EN_write_0_wr, rf$EN_write_1_wr, rf$EN_write_2_wr, rf$EN_write_3_wr;
// ports of submodule rob
reg [282 : 0] rob$enqPort_0_enq_x;
reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
rob$specUpdate_incorrectSpeculation_inst_tag;
reg [4 : 0] rob$setExecuted_deqLSQ_cause,
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
wire [282 : 0] rob$deqPort_0_deq_data,
rob$deqPort_1_deq_data,
rob$enqPort_1_enq_x;
wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
rob$setExecuted_doFinishAlu_1_set_cf;
wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
rob$setExecuted_doFinishAlu_1_set_csrData;
wire [63 : 0] rob$getOrigPC_0_get,
rob$getOrigPC_1_get,
rob$getOrigPredPC_0_get,
rob$getOrigPredPC_1_get,
rob$setExecuted_doFinishMem_vaddr;
wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get;
wire [11 : 0] rob$deqPort_0_getDeqInstTag,
rob$enqPort_0_getEnqInstTag,
rob$enqPort_1_getEnqInstTag,
rob$getOrigPC_0_get_x,
rob$getOrigPC_1_get_x,
rob$getOrigPC_2_get_x,
rob$getOrigPredPC_0_get_x,
rob$getOrigPredPC_1_get_x,
rob$getOrig_Inst_0_get_x,
rob$getOrig_Inst_1_get_x,
rob$setExecuted_deqLSQ_x,
rob$setExecuted_doFinishAlu_0_set_x,
rob$setExecuted_doFinishAlu_1_set_x,
rob$setExecuted_doFinishMem_x,
rob$setLSQAtCommitNotified_x,
rob$specUpdate_correctSpeculation_mask;
wire [5 : 0] rob$getEnqTime;
wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
wire rob$EN_deqPort_0_deq,
rob$EN_deqPort_1_deq,
rob$EN_enqPort_0_enq,
rob$EN_enqPort_1_enq,
rob$EN_setExecuted_deqLSQ,
rob$EN_setExecuted_doFinishAlu_0_set,
rob$EN_setExecuted_doFinishAlu_1_set,
rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
rob$EN_setExecuted_doFinishMem,
rob$EN_setLSQAtCommitNotified,
rob$EN_specUpdate_correctSpeculation,
rob$EN_specUpdate_incorrectSpeculation,
rob$RDY_deqPort_0_deq,
rob$RDY_deqPort_0_deq_data,
rob$RDY_deqPort_1_deq,
rob$RDY_deqPort_1_deq_data,
rob$RDY_enqPort_0_enq,
rob$RDY_enqPort_1_enq,
rob$RDY_setExecuted_deqLSQ,
rob$RDY_setExecuted_doFinishAlu_0_set,
rob$RDY_setExecuted_doFinishAlu_1_set,
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
rob$RDY_setExecuted_doFinishMem,
rob$RDY_setLSQAtCommitNotified,
rob$deqPort_0_canDeq,
rob$deqPort_1_canDeq,
rob$enqPort_0_canEnq,
rob$enqPort_1_canEnq,
rob$isEmpty,
rob$setExecuted_doFinishMem_access_at_commit,
rob$setExecuted_doFinishMem_non_mmio_st_done,
rob$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule sbAggr
reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
wire [6 : 0] sbAggr$setReady_0_put,
sbAggr$setReady_1_put,
sbAggr$setReady_3_put;
wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
wire sbAggr$EN_setBusy_0_set,
sbAggr$EN_setBusy_1_set,
sbAggr$EN_setReady_0_put,
sbAggr$EN_setReady_1_put,
sbAggr$EN_setReady_2_put,
sbAggr$EN_setReady_3_put,
sbAggr$EN_setReady_4_put;
// ports of submodule sbCons
reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
wire [32 : 0] sbCons$eagerLookup_0_get_r,
sbCons$eagerLookup_1_get_r,
sbCons$lazyLookup_0_get_r,
sbCons$lazyLookup_1_get_r,
sbCons$lazyLookup_2_get_r,
sbCons$lazyLookup_3_get_r;
wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
wire [6 : 0] sbCons$setReady_0_put, sbCons$setReady_1_put;
wire [3 : 0] sbCons$lazyLookup_0_get,
sbCons$lazyLookup_1_get,
sbCons$lazyLookup_2_get,
sbCons$lazyLookup_3_get;
wire sbCons$EN_setBusy_0_set,
sbCons$EN_setBusy_1_set,
sbCons$EN_setReady_0_put,
sbCons$EN_setReady_1_put,
sbCons$EN_setReady_2_put,
sbCons$EN_setReady_3_put;
// ports of submodule specTagManager
reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
wire [11 : 0] specTagManager$currentSpecBits,
specTagManager$specUpdate_correctSpeculation_mask;
wire [3 : 0] specTagManager$nextSpecTag;
wire specTagManager$EN_claimSpecTag,
specTagManager$EN_specUpdate_correctSpeculation,
specTagManager$EN_specUpdate_incorrectSpeculation,
specTagManager$RDY_claimSpecTag,
specTagManager$RDY_nextSpecTag,
specTagManager$canClaim,
specTagManager$specUpdate_incorrectSpeculation_kill_all;
// rule scheduling signals
wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
CAN_FIRE_RL_commitStage_doCommitNormalInst,
CAN_FIRE_RL_commitStage_doCommitSystemInst,
CAN_FIRE_RL_commitStage_doCommitTrap_flush,
CAN_FIRE_RL_commitStage_doCommitTrap_handle,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
CAN_FIRE_RL_commitStage_notifyLSQCommit,
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
CAN_FIRE_RL_coreFix_doFetchTrainBP,
CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon,
CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
CAN_FIRE_RL_coreFix_memExe_doExeMem,
CAN_FIRE_RL_coreFix_memExe_doFinishMem,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
CAN_FIRE_RL_coreFix_memExe_doIssueSB,
CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
CAN_FIRE_RL_coreFix_memExe_sendStToMem,
CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
CAN_FIRE_RL_csrf_incCycle,
CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
CAN_FIRE_RL_csrf_minstret_ehr_setRead,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_mmio_cRqQ_canonicalize,
CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_canonicalize,
CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
CAN_FIRE_RL_mmio_handlePRq,
CAN_FIRE_RL_mmio_pRqQ_canonicalize,
CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_canonicalize,
CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_sendDataReq,
CAN_FIRE_RL_mmio_sendDataResp,
CAN_FIRE_RL_mmio_sendInstReq,
CAN_FIRE_RL_mmio_sendInstResp,
CAN_FIRE_RL_prepareCachesAndTlbs,
CAN_FIRE_RL_readyToFetch,
CAN_FIRE_RL_renameStage_doRenaming,
CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
CAN_FIRE_RL_renameStage_doRenaming_Trap,
CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
CAN_FIRE_RL_rl_outOfReset,
CAN_FIRE_RL_sendDTlbReq,
CAN_FIRE_RL_sendFlushDone,
CAN_FIRE_RL_sendITlbReq,
CAN_FIRE_RL_sendRobEnqTime,
CAN_FIRE_RL_sendRsToDTlb,
CAN_FIRE_RL_sendRsToITlb,
CAN_FIRE_coreIndInv_perfResp,
CAN_FIRE_coreIndInv_terminate,
CAN_FIRE_coreReq_perfReq,
CAN_FIRE_coreReq_start,
CAN_FIRE_dCacheToParent_fromP_enq,
CAN_FIRE_dCacheToParent_rqToP_deq,
CAN_FIRE_dCacheToParent_rsToP_deq,
CAN_FIRE_deadlock_checkStarted_get,
CAN_FIRE_deadlock_commitInstStuck_get,
CAN_FIRE_deadlock_commitUserInstStuck_get,
CAN_FIRE_deadlock_dCacheCRqStuck_get,
CAN_FIRE_deadlock_dCachePRqStuck_get,
CAN_FIRE_deadlock_iCacheCRqStuck_get,
CAN_FIRE_deadlock_iCachePRqStuck_get,
CAN_FIRE_deadlock_renameCorrectPathStuck_get,
CAN_FIRE_deadlock_renameInstStuck_get,
CAN_FIRE_iCacheToParent_fromP_enq,
CAN_FIRE_iCacheToParent_rqToP_deq,
CAN_FIRE_iCacheToParent_rsToP_deq,
CAN_FIRE_mmioToPlatform_cRq_deq,
CAN_FIRE_mmioToPlatform_cRs_deq,
CAN_FIRE_mmioToPlatform_pRq_enq,
CAN_FIRE_mmioToPlatform_pRs_enq,
CAN_FIRE_mmioToPlatform_setTime,
CAN_FIRE_recvDoStats,
CAN_FIRE_renameDebug_renameErr_get,
CAN_FIRE_sendDoStats,
CAN_FIRE_setDEIP,
CAN_FIRE_setMEIP,
CAN_FIRE_setSEIP,
CAN_FIRE_tlbToMem_memReq_deq,
CAN_FIRE_tlbToMem_respLd_enq,
WILL_FIRE_RL_commitStage_doCommitKilledLd,
WILL_FIRE_RL_commitStage_doCommitNormalInst,
WILL_FIRE_RL_commitStage_doCommitSystemInst,
WILL_FIRE_RL_commitStage_doCommitTrap_flush,
WILL_FIRE_RL_commitStage_doCommitTrap_handle,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
WILL_FIRE_RL_commitStage_notifyLSQCommit,
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
WILL_FIRE_RL_coreFix_doFetchTrainBP,
WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon,
WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
WILL_FIRE_RL_coreFix_memExe_doExeMem,
WILL_FIRE_RL_coreFix_memExe_doFinishMem,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
WILL_FIRE_RL_coreFix_memExe_doIssueSB,
WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
WILL_FIRE_RL_coreFix_memExe_sendStToMem,
WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
WILL_FIRE_RL_csrf_incCycle,
WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
WILL_FIRE_RL_csrf_minstret_ehr_setRead,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_mmio_cRqQ_canonicalize,
WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_canonicalize,
WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
WILL_FIRE_RL_mmio_handlePRq,
WILL_FIRE_RL_mmio_pRqQ_canonicalize,
WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_canonicalize,
WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_sendDataReq,
WILL_FIRE_RL_mmio_sendDataResp,
WILL_FIRE_RL_mmio_sendInstReq,
WILL_FIRE_RL_mmio_sendInstResp,
WILL_FIRE_RL_prepareCachesAndTlbs,
WILL_FIRE_RL_readyToFetch,
WILL_FIRE_RL_renameStage_doRenaming,
WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
WILL_FIRE_RL_renameStage_doRenaming_Trap,
WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
WILL_FIRE_RL_rl_outOfReset,
WILL_FIRE_RL_sendDTlbReq,
WILL_FIRE_RL_sendFlushDone,
WILL_FIRE_RL_sendITlbReq,
WILL_FIRE_RL_sendRobEnqTime,
WILL_FIRE_RL_sendRsToDTlb,
WILL_FIRE_RL_sendRsToITlb,
WILL_FIRE_coreIndInv_perfResp,
WILL_FIRE_coreIndInv_terminate,
WILL_FIRE_coreReq_perfReq,
WILL_FIRE_coreReq_start,
WILL_FIRE_dCacheToParent_fromP_enq,
WILL_FIRE_dCacheToParent_rqToP_deq,
WILL_FIRE_dCacheToParent_rsToP_deq,
WILL_FIRE_deadlock_checkStarted_get,
WILL_FIRE_deadlock_commitInstStuck_get,
WILL_FIRE_deadlock_commitUserInstStuck_get,
WILL_FIRE_deadlock_dCacheCRqStuck_get,
WILL_FIRE_deadlock_dCachePRqStuck_get,
WILL_FIRE_deadlock_iCacheCRqStuck_get,
WILL_FIRE_deadlock_iCachePRqStuck_get,
WILL_FIRE_deadlock_renameCorrectPathStuck_get,
WILL_FIRE_deadlock_renameInstStuck_get,
WILL_FIRE_iCacheToParent_fromP_enq,
WILL_FIRE_iCacheToParent_rqToP_deq,
WILL_FIRE_iCacheToParent_rsToP_deq,
WILL_FIRE_mmioToPlatform_cRq_deq,
WILL_FIRE_mmioToPlatform_cRs_deq,
WILL_FIRE_mmioToPlatform_pRq_enq,
WILL_FIRE_mmioToPlatform_pRs_enq,
WILL_FIRE_mmioToPlatform_setTime,
WILL_FIRE_recvDoStats,
WILL_FIRE_renameDebug_renameErr_get,
WILL_FIRE_sendDoStats,
WILL_FIRE_setDEIP,
WILL_FIRE_setMEIP,
WILL_FIRE_setSEIP,
WILL_FIRE_tlbToMem_memReq_deq,
WILL_FIRE_tlbToMem_respLd_enq;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
MUX_fetchStage$redirect_1__VAL_5;
reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_1;
wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
wire [282 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
MUX_rob$enqPort_0_enq_1__VAL_2,
MUX_rob$enqPort_0_enq_1__VAL_3;
wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
wire [158 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
wire [133 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
wire [63 : 0] MUX_commitStage_rg_instret$write_1__VAL_1,
MUX_commitStage_rg_instret$write_1__VAL_2,
MUX_csrf_mepc_csr$write_1__VAL_2,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
MUX_csrf_mtval_csr$write_1__VAL_1,
MUX_csrf_mtval_csr$write_1__VAL_2,
MUX_csrf_sepc_csr$write_1__VAL_2,
MUX_fetchStage$redirect_1__VAL_4,
MUX_rf$write_2_wr_2__VAL_2,
MUX_rf$write_2_wr_2__VAL_3,
MUX_rf$write_2_wr_2__VAL_4,
MUX_rf$write_2_wr_2__VAL_5,
MUX_rf$write_2_wr_2__VAL_6,
MUX_rf$write_3_wr_2__VAL_3,
MUX_rf$write_3_wr_2__VAL_4;
wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1;
wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2,
MUX_rob$setExecuted_deqLSQ_2__VAL_2,
MUX_rob$setExecuted_deqLSQ_2__VAL_6,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4;
wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1;
wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__VAL_2;
wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__SEL_2,
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
MUX_csrf_debug_int_pend$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1,
MUX_csrf_fflags_reg$write_1__SEL_1,
MUX_csrf_fs_reg$write_1__SEL_1,
MUX_csrf_ie_vec_1$write_1__SEL_1,
MUX_csrf_ie_vec_1$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__VAL_1,
MUX_csrf_ie_vec_3$write_1__SEL_1,
MUX_csrf_ie_vec_3$write_1__SEL_2,
MUX_csrf_ie_vec_3$write_1__VAL_1,
MUX_csrf_mpp_reg$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__VAL_1,
MUX_csrf_prev_ie_vec_3$write_1__SEL_1,
MUX_csrf_prev_ie_vec_3$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__SEL_1,
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2,
MUX_csrf_spp_reg$write_1__SEL_1,
MUX_csrf_spp_reg$write_1__VAL_1,
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
MUX_flush_reservation$write_1__SEL_1,
MUX_flush_tlbs$write_1__SEL_1,
MUX_rf$write_3_wr_1__PSEL_5,
MUX_rf$write_3_wr_1__SEL_1,
MUX_rf$write_3_wr_1__SEL_2,
MUX_rf$write_3_wr_1__SEL_3,
MUX_rf$write_3_wr_1__SEL_4,
MUX_rf$write_3_wr_1__SEL_5,
MUX_rf$write_3_wr_2__SEL_5,
MUX_rob$setExecuted_deqLSQ_1__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_1,
MUX_sbCons$setReady_3_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_3,
MUX_update_vm_info$write_1__SEL_1;
// remaining internal signals
reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496;
reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9918,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871,
addr__h288139,
curData__h190989,
rVal1__h608010,
rVal1__h631544,
trap_val__h695358,
x__h195199;
reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9,
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q211,
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q212,
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q209,
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q210,
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q197,
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q198,
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q199,
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q200,
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q201,
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q202,
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q213,
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q214,
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q215,
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q216,
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q217,
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q218,
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q207,
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q208,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850;
reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398;
reg [22 : 0] CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q78,
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q79,
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q80,
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q81,
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q111,
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q112,
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q41,
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q42,
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q109,
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q110,
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q39,
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q40,
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q113,
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q114,
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q43,
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q44,
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q115,
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q116,
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q45,
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q46,
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q76,
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q77,
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q74,
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q75,
_theResult___fst_sfd__h344136,
_theResult___fst_sfd__h352859,
_theResult___fst_sfd__h361441,
_theResult___fst_sfd__h370625,
_theResult___fst_sfd__h379261,
_theResult___fst_sfd__h389828,
_theResult___fst_sfd__h398549,
_theResult___fst_sfd__h407131,
_theResult___fst_sfd__h416315,
_theResult___fst_sfd__h424951,
_theResult___fst_sfd__h435516,
_theResult___fst_sfd__h444237,
_theResult___fst_sfd__h452819,
_theResult___fst_sfd__h462003,
_theResult___fst_sfd__h470639;
reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778,
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408;
reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407;
reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275,
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229,
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852;
reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8,
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q203,
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q204,
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q205,
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q206,
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q175,
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q176,
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q177,
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q178,
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q181,
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q182,
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q152,
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q153,
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q179,
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q180,
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q183,
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q184,
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q135,
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q136,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779;
reg [7 : 0] CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q67,
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q68,
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q72,
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q73,
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q96,
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q97,
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q26,
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q27,
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q94,
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q95,
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q24,
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q25,
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q102,
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q103,
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q32,
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q33,
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q107,
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q108,
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q37,
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q38,
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q61,
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q62,
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q59,
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q60,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420,
_theResult___fst_exp__h344135,
_theResult___fst_exp__h352858,
_theResult___fst_exp__h361440,
_theResult___fst_exp__h370624,
_theResult___fst_exp__h379260,
_theResult___fst_exp__h389827,
_theResult___fst_exp__h398548,
_theResult___fst_exp__h407130,
_theResult___fst_exp__h416314,
_theResult___fst_exp__h424950,
_theResult___fst_exp__h435515,
_theResult___fst_exp__h444236,
_theResult___fst_exp__h452818,
_theResult___fst_exp__h462002,
_theResult___fst_exp__h470638;
reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266,
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1,
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263,
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398;
reg [4 : 0] IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13912,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14041;
reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227,
CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226,
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12,
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13915,
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14042,
i__h694342,
i__h694502;
reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255,
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225,
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684,
x__h283918,
x__h289688;
reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248;
reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
CASE_fetchStage_pipelines_0_canDeq__2650_AND_N_ETC__q234,
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235,
CASE_guard00893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139,
CASE_guard07492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87,
CASE_guard07492_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86,
CASE_guard09962_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141,
CASE_guard16328_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89,
CASE_guard16328_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88,
CASE_guard30382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195,
CASE_guard30382_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185,
CASE_guard35543_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118,
CASE_guard35543_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117,
CASE_guard39694_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191,
CASE_guard39694_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187,
CASE_guard44163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48,
CASE_guard44163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47,
CASE_guard44250_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120,
CASE_guard44250_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119,
CASE_guard48763_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193,
CASE_guard48763_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189,
CASE_guard52872_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50,
CASE_guard52872_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49,
CASE_guard53180_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122,
CASE_guard53180_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121,
CASE_guard61802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q52,
CASE_guard61802_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51,
CASE_guard62016_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124,
CASE_guard62016_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123,
CASE_guard69583_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164,
CASE_guard69583_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154,
CASE_guard70638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54,
CASE_guard70638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53,
CASE_guard78895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160,
CASE_guard78895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156,
CASE_guard87964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162,
CASE_guard87964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158,
CASE_guard89855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83,
CASE_guard89855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82,
CASE_guard91581_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137,
CASE_guard98562_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85,
CASE_guard98562_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84,
CASE_k63183_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10821,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10857,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10905,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10947,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10989,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8382,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8395,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13906,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13909,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13348,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13648,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13669,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13686,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13739,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13755,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13762,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13831,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13842,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14039,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14040,
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697,
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13828,
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13853,
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308,
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__265_ETC___d13789,
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274,
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575;
wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243;
wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518;
wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941;
wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14911;
wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004;
wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14902;
wire [321 : 0] basicExec___d11907, basicExec___d12516;
wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999;
wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14893,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11043,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11056,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11049;
wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994;
wire [127 : 0] b__h600853, b__h600929, b__h601030, b__h601042, x__h601842;
wire [68 : 0] execFpuSimple___d11023;
wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627;
wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566;
wire [63 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12363,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12364,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12375,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12376,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11754,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11755,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11766,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11767,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8322,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8323,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659,
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9154,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9860,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9914,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563,
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377,
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424,
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378,
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425,
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14710,
_theResult___fst__h601253,
_theResult___snd__h601254,
a___1__h600867,
a___1__h601258,
a__h600705,
amoExec___d880,
b___1__h600868,
b___1__h601319,
b__h600706,
base__h696929,
base__h697132,
data___1__h473058,
data___1__h473880,
data__h473346,
fcsr_csr__read__h608288,
fflags_csr__read__h608263,
frm_csr__read__h608274,
mcause_csr__read__h609935,
mcounteren_csr__read__h609680,
medeleg_csr__read__h609280,
mideleg_csr__read__h609375,
mie_csr__read__h609506,
mip_csr__read__h610175,
mstatus_csr__read__h609132,
mtvec_csr__read__h609588,
n___1__h196602,
n__h192527,
n__read__h610279,
n__read__h610470,
n__read__h6134,
n__read__h705337,
next_pc__h704680,
q___1__h473956,
q__h601833,
rVal1__h479827,
rVal2__h479828,
r___1__h473983,
r__h601834,
res_data__h335940,
res_data__h335945,
res_data__h381635,
res_data__h381640,
res_data__h427323,
res_data__h427328,
resp_addr__h290043,
robdeqPort_0_deq_data_BITS_95_TO_32__q262,
satp_csr__read__h608989,
scause_csr__read__h608787,
scounteren_csr__read__h608649,
shiftData__h181366,
sie_csr__read__h608553,
sip_csr__read__h608926,
sstatus_csr__read__h608484,
stvec_csr__read__h608596,
upd__h3639,
upd__h4956,
v__h606895,
v__h630583,
vaddr__h181361,
x__h153739,
x__h157286,
x__h160100,
x__h161948,
x__h17672,
x__h181275,
x__h181276,
x__h20210,
x__h285363,
x__h287217,
x__h45579,
x__h479736,
x__h479737,
x__h479738,
x__h48115,
x__h601242,
x__h615173,
x__h615174,
x__h636394,
x__h636395,
x__h690863,
x_addr__h312146,
x_quotient__h473246,
x_reg_ifc__read__h608393,
x_remainder__h473247,
y__h707788,
y_avValue__h180363,
y_avValue__h180969,
y_avValue__h476872,
y_avValue__h477480,
y_avValue__h478082,
y_avValue__h607800,
y_avValue__h613062,
y_avValue__h631336,
y_avValue__h634293,
y_avValue__h695205,
y_avValue__h696966,
y_avValue_snd_snd_snd_snd_snd__h707288,
y_avValue_snd_snd_snd_snd_snd__h707841,
y_avValue_snd_snd_snd_snd_snd__h707870;
wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10621,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9858,
r1__read__h610977,
r1__read__h611381,
r1__read__h611911,
r1__read__h611916,
r1__read__h611935,
r1__read__h612188,
r1__read__h612366,
r1__read__h612484,
r1__read__h612489,
r1__read__h612508;
wire [61 : 0] r1__read__h610979,
r1__read__h611383,
r1__read__h611918,
r1__read__h611937,
r1__read__h612190,
r1__read__h612342,
r1__read__h612368,
r1__read__h612491,
r1__read__h612510;
wire [60 : 0] r1__read__h612192,
r1__read__h612344,
r1__read__h612370,
r1__read__h612512;
wire [59 : 0] r1__read__h610981,
r1__read__h611385,
r1__read__h611929,
r1__read__h611939,
r1__read__h612194,
r1__read__h612372,
r1__read__h612502,
r1__read__h612514;
wire [58 : 0] r1__read__h610983,
r1__read__h611387,
r1__read__h611941,
r1__read__h612196,
r1__read__h612374,
r1__read__h612516;
wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709,
r1__read__h610985,
r1__read__h611389,
r1__read__h611943,
r1__read__h612198,
r1__read__h612346,
r1__read__h612376,
r1__read__h612518,
y__h252876;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10107,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8634,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9344,
_theResult____h344153,
_theResult____h361792,
_theResult____h389845,
_theResult____h407482,
_theResult____h435533,
_theResult____h453170,
_theResult____h500883,
_theResult____h539684,
_theResult____h578885,
_theResult___snd__h352275,
_theResult___snd__h352286,
_theResult___snd__h352288,
_theResult___snd__h352298,
_theResult___snd__h352304,
_theResult___snd__h352327,
_theResult___snd__h360871,
_theResult___snd__h360873,
_theResult___snd__h360880,
_theResult___snd__h360886,
_theResult___snd__h360909,
_theResult___snd__h370041,
_theResult___snd__h370052,
_theResult___snd__h370054,
_theResult___snd__h370064,
_theResult___snd__h370070,
_theResult___snd__h370093,
_theResult___snd__h378661,
_theResult___snd__h378675,
_theResult___snd__h378681,
_theResult___snd__h378699,
_theResult___snd__h397965,
_theResult___snd__h397976,
_theResult___snd__h397978,
_theResult___snd__h397988,
_theResult___snd__h397994,
_theResult___snd__h398017,
_theResult___snd__h406561,
_theResult___snd__h406563,
_theResult___snd__h406570,
_theResult___snd__h406576,
_theResult___snd__h406599,
_theResult___snd__h415731,
_theResult___snd__h415742,
_theResult___snd__h415744,
_theResult___snd__h415754,
_theResult___snd__h415760,
_theResult___snd__h415783,
_theResult___snd__h424351,
_theResult___snd__h424365,
_theResult___snd__h424371,
_theResult___snd__h424389,
_theResult___snd__h443653,
_theResult___snd__h443664,
_theResult___snd__h443666,
_theResult___snd__h443676,
_theResult___snd__h443682,
_theResult___snd__h443705,
_theResult___snd__h452249,
_theResult___snd__h452251,
_theResult___snd__h452258,
_theResult___snd__h452264,
_theResult___snd__h452287,
_theResult___snd__h461419,
_theResult___snd__h461430,
_theResult___snd__h461432,
_theResult___snd__h461442,
_theResult___snd__h461448,
_theResult___snd__h461471,
_theResult___snd__h470039,
_theResult___snd__h470053,
_theResult___snd__h470059,
_theResult___snd__h470077,
_theResult___snd__h499493,
_theResult___snd__h499495,
_theResult___snd__h499502,
_theResult___snd__h499508,
_theResult___snd__h499531,
_theResult___snd__h509130,
_theResult___snd__h509141,
_theResult___snd__h509143,
_theResult___snd__h509153,
_theResult___snd__h509159,
_theResult___snd__h509182,
_theResult___snd__h517898,
_theResult___snd__h517912,
_theResult___snd__h517918,
_theResult___snd__h517936,
_theResult___snd__h538294,
_theResult___snd__h538296,
_theResult___snd__h538303,
_theResult___snd__h538309,
_theResult___snd__h538332,
_theResult___snd__h547931,
_theResult___snd__h547942,
_theResult___snd__h547944,
_theResult___snd__h547954,
_theResult___snd__h547960,
_theResult___snd__h547983,
_theResult___snd__h556699,
_theResult___snd__h556713,
_theResult___snd__h556719,
_theResult___snd__h556737,
_theResult___snd__h577495,
_theResult___snd__h577497,
_theResult___snd__h577504,
_theResult___snd__h577510,
_theResult___snd__h577533,
_theResult___snd__h587132,
_theResult___snd__h587143,
_theResult___snd__h587145,
_theResult___snd__h587155,
_theResult___snd__h587161,
_theResult___snd__h587184,
_theResult___snd__h595900,
_theResult___snd__h595914,
_theResult___snd__h595920,
_theResult___snd__h595938,
r1__read__h612200,
r1__read__h612348,
r1__read__h612378,
r1__read__h612520,
result__h362405,
result__h408095,
result__h453783,
result__h501496,
result__h540297,
result__h579498,
sfd__h336548,
sfd__h382243,
sfd__h427931,
sfd__h480541,
sfd__h519483,
sfd__h558684,
sfdin__h352258,
sfdin__h370024,
sfdin__h397948,
sfdin__h415714,
sfdin__h443636,
sfdin__h461402,
sfdin__h509113,
sfdin__h547914,
sfdin__h587115,
x__h362502,
x__h408192,
x__h453880,
x__h501591,
x__h540392,
x__h579593;
wire [55 : 0] r1__read__h610987,
r1__read__h611391,
r1__read__h611945,
r1__read__h612202,
r1__read__h612380,
r1__read__h612522;
wire [54 : 0] r1__read__h610989,
r1__read__h611393,
r1__read__h611947,
r1__read__h612204,
r1__read__h612382,
r1__read__h612524;
wire [53 : 0] r1__read__h612325,
r1__read__h612350,
r1__read__h612384,
r1__read__h612526,
sfd__h499560,
sfd__h509211,
sfd__h517971,
sfd__h538361,
sfd__h548012,
sfd__h556772,
sfd__h577562,
sfd__h587213,
sfd__h595973,
value__h344775,
value__h390465,
value__h436153;
wire [52 : 0] r1__read__h612206,
r1__read__h612327,
r1__read__h612352,
r1__read__h612386,
r1__read__h612528;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10588,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10590,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9121,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9123,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9825,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9827,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10562,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10564,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10607,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10609,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9094,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9140,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9142,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9799,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9801,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9844,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9846,
_theResult___fst_sfd__h484470,
_theResult___fst_sfd__h500298,
_theResult___fst_sfd__h500301,
_theResult___fst_sfd__h509949,
_theResult___fst_sfd__h509952,
_theResult___fst_sfd__h518733,
_theResult___fst_sfd__h518736,
_theResult___fst_sfd__h518745,
_theResult___fst_sfd__h518751,
_theResult___fst_sfd__h523271,
_theResult___fst_sfd__h539099,
_theResult___fst_sfd__h539102,
_theResult___fst_sfd__h548750,
_theResult___fst_sfd__h548753,
_theResult___fst_sfd__h557534,
_theResult___fst_sfd__h557537,
_theResult___fst_sfd__h557546,
_theResult___fst_sfd__h557552,
_theResult___fst_sfd__h562472,
_theResult___fst_sfd__h578300,
_theResult___fst_sfd__h578303,
_theResult___fst_sfd__h587951,
_theResult___fst_sfd__h587954,
_theResult___fst_sfd__h596735,
_theResult___fst_sfd__h596738,
_theResult___fst_sfd__h596747,
_theResult___fst_sfd__h596753,
_theResult___sfd__h500198,
_theResult___sfd__h509849,
_theResult___sfd__h518633,
_theResult___sfd__h538999,
_theResult___sfd__h548650,
_theResult___sfd__h557434,
_theResult___sfd__h578200,
_theResult___sfd__h587851,
_theResult___sfd__h596635,
_theResult___snd_fst_sfd__h480495,
_theResult___snd_fst_sfd__h500304,
_theResult___snd_fst_sfd__h518739,
_theResult___snd_fst_sfd__h519437,
_theResult___snd_fst_sfd__h539105,
_theResult___snd_fst_sfd__h557540,
_theResult___snd_fst_sfd__h558638,
_theResult___snd_fst_sfd__h578306,
_theResult___snd_fst_sfd__h596741,
out___1_sfd__h480244,
out___1_sfd__h519186,
out___1_sfd__h558387,
out_sfd__h500201,
out_sfd__h509852,
out_sfd__h518636,
out_sfd__h539002,
out_sfd__h548653,
out_sfd__h557437,
out_sfd__h578203,
out_sfd__h587854,
out_sfd__h596638,
r1__read__h612530;
wire [50 : 0] r1__read__h610991, r1__read__h612208;
wire [49 : 0] r1__read__h612329, r1__read__h612532;
wire [48 : 0] r1__read__h610993, r1__read__h612210, r1__read__h612331;
wire [46 : 0] r1__read__h610995, r1__read__h612212;
wire [45 : 0] r1__read__h610997, r1__read__h612214;
wire [44 : 0] r1__read__h610999, r1__read__h612216;
wire [43 : 0] r1__read__h611001, r1__read__h612218;
wire [42 : 0] r1__read__h612220;
wire [41 : 0] r1__read__h612222;
wire [40 : 0] r1__read__h612224;
wire [37 : 0] IF_fetchStage_pipelines_0_first__2652_BIT_160__ETC___d13918,
IF_fetchStage_pipelines_1_first__2661_BIT_160__ETC___d14045;
wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2,
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4,
data73346_BITS_31_TO_0__q5,
imm__h651592,
r1__read__h611003,
r1__read__h612226,
x__h191752,
x__h335952,
x__h381647,
x__h427335,
x__h75524,
x_data__h65373,
x_data_imm__h670087,
x_data_imm__h684830;
wire [29 : 0] r1__read__h611005, r1__read__h612228;
wire [27 : 0] r1__read__h612230;
wire [24 : 0] NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13950,
sfd__h352356,
sfd__h360938,
sfd__h370122,
sfd__h378734,
sfd__h398046,
sfd__h406628,
sfd__h415812,
sfd__h424424,
sfd__h443734,
sfd__h452316,
sfd__h461500,
sfd__h470112,
value__h485099,
value__h523900,
value__h563101;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804,
_theResult___fst_sfd__h352862,
_theResult___fst_sfd__h361444,
_theResult___fst_sfd__h370628,
_theResult___fst_sfd__h379264,
_theResult___fst_sfd__h379273,
_theResult___fst_sfd__h379279,
_theResult___fst_sfd__h398552,
_theResult___fst_sfd__h407134,
_theResult___fst_sfd__h416318,
_theResult___fst_sfd__h424954,
_theResult___fst_sfd__h424963,
_theResult___fst_sfd__h424969,
_theResult___fst_sfd__h444240,
_theResult___fst_sfd__h452822,
_theResult___fst_sfd__h462006,
_theResult___fst_sfd__h470642,
_theResult___fst_sfd__h470651,
_theResult___fst_sfd__h470657,
_theResult___sfd__h352781,
_theResult___sfd__h361363,
_theResult___sfd__h370547,
_theResult___sfd__h379183,
_theResult___sfd__h379285,
_theResult___sfd__h398471,
_theResult___sfd__h407053,
_theResult___sfd__h416237,
_theResult___sfd__h424873,
_theResult___sfd__h424975,
_theResult___sfd__h444159,
_theResult___sfd__h452741,
_theResult___sfd__h461925,
_theResult___sfd__h470561,
_theResult___sfd__h470663,
_theResult___snd_fst_sfd__h336498,
_theResult___snd_fst_sfd__h361447,
_theResult___snd_fst_sfd__h379267,
_theResult___snd_fst_sfd__h382193,
_theResult___snd_fst_sfd__h407137,
_theResult___snd_fst_sfd__h424957,
_theResult___snd_fst_sfd__h427881,
_theResult___snd_fst_sfd__h452825,
_theResult___snd_fst_sfd__h470645,
out_f_sfd__h379562,
out_f_sfd__h425252,
out_f_sfd__h470940,
out_sfd__h352784,
out_sfd__h361366,
out_sfd__h370550,
out_sfd__h379186,
out_sfd__h398474,
out_sfd__h407056,
out_sfd__h416240,
out_sfd__h424876,
out_sfd__h444162,
out_sfd__h452744,
out_sfd__h461928,
out_sfd__h470564;
wire [19 : 0] r1__read__h612165;
wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721,
_theResult____h647536,
enabled_ints___1__h648033,
enabled_ints__h648080,
pend_ints__h647534,
y__h648045;
wire [12 : 0] fetchStage_pipelines_1_first__2661_BIT_173_340_ETC___d13484,
r1__read_BITS_12_TO_0___h648056;
wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10400,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8927,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9637,
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593,
IF_fetchStage_pipelines_0_first__2652_BIT_173__ETC___d12913,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10100,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8627,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9337,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791,
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10103,
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8630,
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9340,
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8490,
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9215,
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9978,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334,
renaming_spec_bits__h677486,
result__h643243,
result__h643294,
spec_bits__h680581,
w__h643238,
x__h362535,
x__h408225,
x__h453913,
x__h501624,
x__h540425,
x__h579626,
x__h643242,
x__h643293,
y__h643272,
y__h680594,
y_avValue_fst__h673978,
y_avValue_snd_fst__h674252,
y_avValue_snd_fst__h674287;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9037,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9039,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9742,
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9744,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10469,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10536,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10538,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8994,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8996,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9068,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9070,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9704,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9706,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9773,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9775,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172,
_theResult___exp__h500197,
_theResult___exp__h509848,
_theResult___exp__h518632,
_theResult___exp__h538998,
_theResult___exp__h548649,
_theResult___exp__h557433,
_theResult___exp__h578199,
_theResult___exp__h587850,
_theResult___exp__h596634,
_theResult___fst_exp__h484469,
_theResult___fst_exp__h499533,
_theResult___fst_exp__h499539,
_theResult___fst_exp__h499542,
_theResult___fst_exp__h500297,
_theResult___fst_exp__h500300,
_theResult___fst_exp__h509119,
_theResult___fst_exp__h509184,
_theResult___fst_exp__h509190,
_theResult___fst_exp__h509193,
_theResult___fst_exp__h509948,
_theResult___fst_exp__h509951,
_theResult___fst_exp__h517904,
_theResult___fst_exp__h517943,
_theResult___fst_exp__h517949,
_theResult___fst_exp__h517952,
_theResult___fst_exp__h518732,
_theResult___fst_exp__h518735,
_theResult___fst_exp__h518744,
_theResult___fst_exp__h518747,
_theResult___fst_exp__h523270,
_theResult___fst_exp__h538334,
_theResult___fst_exp__h538340,
_theResult___fst_exp__h538343,
_theResult___fst_exp__h539098,
_theResult___fst_exp__h539101,
_theResult___fst_exp__h547920,
_theResult___fst_exp__h547985,
_theResult___fst_exp__h547991,
_theResult___fst_exp__h547994,
_theResult___fst_exp__h548749,
_theResult___fst_exp__h548752,
_theResult___fst_exp__h556705,
_theResult___fst_exp__h556744,
_theResult___fst_exp__h556750,
_theResult___fst_exp__h556753,
_theResult___fst_exp__h557533,
_theResult___fst_exp__h557536,
_theResult___fst_exp__h557545,
_theResult___fst_exp__h557548,
_theResult___fst_exp__h562471,
_theResult___fst_exp__h577535,
_theResult___fst_exp__h577541,
_theResult___fst_exp__h577544,
_theResult___fst_exp__h578299,
_theResult___fst_exp__h578302,
_theResult___fst_exp__h587121,
_theResult___fst_exp__h587186,
_theResult___fst_exp__h587192,
_theResult___fst_exp__h587195,
_theResult___fst_exp__h587950,
_theResult___fst_exp__h587953,
_theResult___fst_exp__h595906,
_theResult___fst_exp__h595945,
_theResult___fst_exp__h595951,
_theResult___fst_exp__h595954,
_theResult___fst_exp__h596734,
_theResult___fst_exp__h596737,
_theResult___fst_exp__h596746,
_theResult___fst_exp__h596749,
_theResult___snd_fst_exp__h500303,
_theResult___snd_fst_exp__h518738,
_theResult___snd_fst_exp__h539104,
_theResult___snd_fst_exp__h557539,
_theResult___snd_fst_exp__h578305,
_theResult___snd_fst_exp__h596740,
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63,
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98,
csrf_debug_int_pend_read__1696_CONCAT_0b0_2684_ETC___d12694,
din_inc___2_exp__h518792,
din_inc___2_exp__h518827,
din_inc___2_exp__h518853,
din_inc___2_exp__h557593,
din_inc___2_exp__h557628,
din_inc___2_exp__h557654,
din_inc___2_exp__h596794,
din_inc___2_exp__h596829,
din_inc___2_exp__h596855,
out_exp__h500200,
out_exp__h509851,
out_exp__h518635,
out_exp__h539001,
out_exp__h548652,
out_exp__h557436,
out_exp__h578202,
out_exp__h587853,
out_exp__h596637;
wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104,
_theResult___exp__h352780,
_theResult___exp__h361362,
_theResult___exp__h370546,
_theResult___exp__h379182,
_theResult___exp__h379284,
_theResult___exp__h398470,
_theResult___exp__h407052,
_theResult___exp__h416236,
_theResult___exp__h424872,
_theResult___exp__h424974,
_theResult___exp__h444158,
_theResult___exp__h452740,
_theResult___exp__h461924,
_theResult___exp__h470560,
_theResult___exp__h470662,
_theResult___fst_exp__h352264,
_theResult___fst_exp__h352329,
_theResult___fst_exp__h352335,
_theResult___fst_exp__h352338,
_theResult___fst_exp__h352861,
_theResult___fst_exp__h360911,
_theResult___fst_exp__h360917,
_theResult___fst_exp__h360920,
_theResult___fst_exp__h361443,
_theResult___fst_exp__h370030,
_theResult___fst_exp__h370095,
_theResult___fst_exp__h370101,
_theResult___fst_exp__h370104,
_theResult___fst_exp__h370627,
_theResult___fst_exp__h378667,
_theResult___fst_exp__h378706,
_theResult___fst_exp__h378712,
_theResult___fst_exp__h378715,
_theResult___fst_exp__h379263,
_theResult___fst_exp__h379272,
_theResult___fst_exp__h379275,
_theResult___fst_exp__h397954,
_theResult___fst_exp__h398019,
_theResult___fst_exp__h398025,
_theResult___fst_exp__h398028,
_theResult___fst_exp__h398551,
_theResult___fst_exp__h406601,
_theResult___fst_exp__h406607,
_theResult___fst_exp__h406610,
_theResult___fst_exp__h407133,
_theResult___fst_exp__h415720,
_theResult___fst_exp__h415785,
_theResult___fst_exp__h415791,
_theResult___fst_exp__h415794,
_theResult___fst_exp__h416317,
_theResult___fst_exp__h424357,
_theResult___fst_exp__h424396,
_theResult___fst_exp__h424402,
_theResult___fst_exp__h424405,
_theResult___fst_exp__h424953,
_theResult___fst_exp__h424962,
_theResult___fst_exp__h424965,
_theResult___fst_exp__h443642,
_theResult___fst_exp__h443707,
_theResult___fst_exp__h443713,
_theResult___fst_exp__h443716,
_theResult___fst_exp__h444239,
_theResult___fst_exp__h452289,
_theResult___fst_exp__h452295,
_theResult___fst_exp__h452298,
_theResult___fst_exp__h452821,
_theResult___fst_exp__h461408,
_theResult___fst_exp__h461473,
_theResult___fst_exp__h461479,
_theResult___fst_exp__h461482,
_theResult___fst_exp__h462005,
_theResult___fst_exp__h470045,
_theResult___fst_exp__h470084,
_theResult___fst_exp__h470090,
_theResult___fst_exp__h470093,
_theResult___fst_exp__h470641,
_theResult___fst_exp__h470650,
_theResult___fst_exp__h470653,
_theResult___snd_fst_exp__h361446,
_theResult___snd_fst_exp__h379266,
_theResult___snd_fst_exp__h407136,
_theResult___snd_fst_exp__h424956,
_theResult___snd_fst_exp__h452824,
_theResult___snd_fst_exp__h470644,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145,
din_inc___2_exp__h379297,
din_inc___2_exp__h379321,
din_inc___2_exp__h379351,
din_inc___2_exp__h379375,
din_inc___2_exp__h424987,
din_inc___2_exp__h425011,
din_inc___2_exp__h425041,
din_inc___2_exp__h425065,
din_inc___2_exp__h470675,
din_inc___2_exp__h470699,
din_inc___2_exp__h470729,
din_inc___2_exp__h470753,
out_exp__h352783,
out_exp__h361365,
out_exp__h370549,
out_exp__h379185,
out_exp__h398473,
out_exp__h407055,
out_exp__h416239,
out_exp__h424875,
out_exp__h444161,
out_exp__h452743,
out_exp__h461927,
out_exp__h470563,
out_f_exp__h379561,
out_f_exp__h425251,
out_f_exp__h470939,
x__h610962;
wire [6 : 0] csrf_debug_int_pend_read__1696_CONCAT_0b0_2684_ETC___d12689;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10349,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8876,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9586,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578,
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14937,
x__h181498,
x__h696944;
wire [4 : 0] IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d14086,
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14796,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793,
checkForException___d12886,
checkForException___d13505,
fflags__h707765,
res_fflags__h335941,
res_fflags__h381636,
res_fflags__h427324,
rs1__h651591,
x__h153733,
x__h157280,
x__h160096,
x__h285351,
y_avValue_snd_fst__h707272,
y_avValue_snd_fst__h707825,
y_avValue_snd_fst__h707854;
wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13064,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13065,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13066,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13067,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13068,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13069,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13070,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13071,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13072,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13073,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13074,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13075,
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13076,
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3__ETC___d13102,
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791,
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832,
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d13121,
cause_code__h694327,
vm_mode_reg__read__h612171;
wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
_theResult_____2__h294593,
next_deqP___1__h294872,
v__h294013,
v__h294244,
x__h300223,
x_decodeInfo_frm__h651275;
wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14818,
IF_sfdin09113_BIT_4_THEN_2_ELSE_0__q131,
IF_sfdin15714_BIT_33_THEN_2_ELSE_0__q66,
IF_sfdin43636_BIT_33_THEN_2_ELSE_0__q91,
IF_sfdin47914_BIT_4_THEN_2_ELSE_0__q171,
IF_sfdin52258_BIT_33_THEN_2_ELSE_0__q21,
IF_sfdin61402_BIT_33_THEN_2_ELSE_0__q101,
IF_sfdin70024_BIT_33_THEN_2_ELSE_0__q31,
IF_sfdin87115_BIT_4_THEN_2_ELSE_0__q148,
IF_sfdin97948_BIT_33_THEN_2_ELSE_0__q56,
IF_theResult___snd06561_BIT_33_THEN_2_ELSE_0__q58,
IF_theResult___snd17898_BIT_4_THEN_2_ELSE_0__q134,
IF_theResult___snd24351_BIT_33_THEN_2_ELSE_0__q71,
IF_theResult___snd38294_BIT_4_THEN_2_ELSE_0__q167,
IF_theResult___snd52249_BIT_33_THEN_2_ELSE_0__q93,
IF_theResult___snd56699_BIT_4_THEN_2_ELSE_0__q174,
IF_theResult___snd60871_BIT_33_THEN_2_ELSE_0__q23,
IF_theResult___snd70039_BIT_33_THEN_2_ELSE_0__q106,
IF_theResult___snd77495_BIT_4_THEN_2_ELSE_0__q144,
IF_theResult___snd78661_BIT_33_THEN_2_ELSE_0__q36,
IF_theResult___snd95900_BIT_4_THEN_2_ELSE_0__q151,
IF_theResult___snd99493_BIT_4_THEN_2_ELSE_0__q127,
guard__h344163,
guard__h352872,
guard__h361802,
guard__h370638,
guard__h389855,
guard__h398562,
guard__h407492,
guard__h416328,
guard__h435543,
guard__h444250,
guard__h453180,
guard__h462016,
guard__h491581,
guard__h500893,
guard__h509962,
guard__h530382,
guard__h539694,
guard__h548763,
guard__h569583,
guard__h578895,
guard__h587964,
prv__h709280,
prv__h709324,
r1__read_BITS_13_TO_12___h651460,
sbIdx__h157159,
v__h601904,
v__h601914,
v__h602945,
x__h704740,
x__h708013,
y_avValue_snd_snd_snd_fst__h707282,
y_avValue_snd_snd_snd_fst__h707835,
y_avValue_snd_snd_snd_fst__h707864;
wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899,
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10646,
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9884,
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10393,
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10658,
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8920,
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9630,
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9896,
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12928,
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d13560,
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d13596,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10439,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10643,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10670,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8966,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9676,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9908,
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10098,
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8625,
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9335,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12180,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12181,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12182,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12205,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12206,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12207,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11385,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11386,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11387,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11410,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11411,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11412,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8227,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8228,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8229,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8251,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8252,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8253,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8275,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8276,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8277,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099,
IF_NOT_fetchStage_pipelines_0_canDeq__2650_265_ETC___d13703,
IF_NOT_fetchStage_pipelines_0_canDeq__2650_265_ETC___d13711,
IF_NOT_fetchStage_pipelines_1_first__2661_BITS_ETC___d13633,
IF_NOT_fetchStage_pipelines_1_first__2661_BITS_ETC___d13710,
IF_NOT_rob_deqPort_1_deq_data__4609_BIT_25_461_ETC___d14809,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10441,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10672,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10867,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10881,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10896,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10913,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10925,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10938,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10955,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10967,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10980,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8968,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9678,
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9910,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2124_ETC___d12156,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2124_ETC___d12190,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1329_ETC___d11361,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1329_ETC___d11395,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8203,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8236,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8260,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10443,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10674,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10729,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10770,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10814,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10829,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10839,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10850,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10869,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10883,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10898,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10915,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10927,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10940,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10957,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10969,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10982,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8416,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8970,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9680,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9912,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844,
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578,
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611,
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746,
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739,
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724,
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652,
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645,
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630,
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554,
IF_fetchStage_RDY_pipelines_0_first__2649_AND__ETC___d13261,
IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13635,
IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13700,
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13748,
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13869,
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339,
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783,
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46,
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201,
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642,
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491,
IF_rob_deqPort_1_canDeq__4606_THEN_IF_NOT_rob__ETC___d14810,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029,
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13175,
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13249,
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13532,
NOT_IF_NOT_rob_deqPort_0_canDeq__4602_4603_OR__ETC___d14815,
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13310,
NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12172,
NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12200,
NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11377,
NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11405,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8219,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8246,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8270,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10025,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10732,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10774,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10832,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10843,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10872,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10887,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10918,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10931,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10960,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10973,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8415,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8537,
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d9262,
NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13644,
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594,
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074,
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123,
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179,
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447,
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879,
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923,
NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751,
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713,
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768,
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619,
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674,
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473,
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024,
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543,
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585,
NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078,
NOT_coreFix_memExe_rsMem_canEnq__3278_3340_OR__ETC___d13645,
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13168,
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13247,
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13530,
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13616,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13627,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13666,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13683,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13804,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13823,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13875,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13977,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13988,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14033,
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14063,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13164,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13292,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13550,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13556,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13708,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881,
NOT_fetchStage_pipelines_0_first__2652_BIT_68__ETC___d13303,
NOT_fetchStage_pipelines_1_canDeq__2658_2659_O_ETC___d12667,
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13541,
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13543,
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13654,
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13675,
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13692,
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13985,
NOT_fetchStage_pipelines_1_first__2661_BIT_68__ETC___d13982,
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431,
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452,
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823,
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844,
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091,
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390,
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325,
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140,
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161,
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241,
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262,
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734,
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755,
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593,
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614,
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334,
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13660,
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715,
NOT_regRenamingTable_rename_1_canRename__3354__ETC___d13773,
NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_RDY_ETC___d14641,
NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_deq_ETC___d14789,
NOT_rob_deqPort_0_deq_data__4100_BITS_186_TO_1_ETC___d14408,
NOT_rob_deqPort_1_deq_data__4609_BIT_25_4610_4_ETC___d14638,
NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13794,
NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13859,
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13605,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338,
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339,
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_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10351,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8878,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9588,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10054,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10401,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8566,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8928,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9291,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9638,
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_0_OR_NOT_fetchStage_pipelines_1_first__2661_BI_ETC___d13807,
_0_OR_fetchStage_RDY_pipelines_0_first__2649_36_ETC___d13630,
_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14274,
_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14256,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008,
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_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491,
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493,
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216,
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_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981,
_dfoo12,
_dfoo18,
_dfoo2,
_dfoo20,
_dfoo26,
_dfoo7,
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
_dor1coreFix_memExe_bypassWire_2$EN_wset,
_dor1coreFix_memExe_bypassWire_3$EN_wset,
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
_dor1rf$EN_write_0_wr,
_dor1rf$EN_write_1_wr,
_dor1sbAggr$EN_setReady_3_put,
_dor1sbCons$EN_setReady_0_put,
_dor1sbCons$EN_setReady_1_put,
_theResult_____2__h302589,
_theResult_____2__h308583,
_theResult_____2__h316437,
_theResult_____2__h326781,
_theResult_____2__h330006,
coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148,
coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187,
coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12161,
coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12193,
coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12169,
coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12197,
coreFix_aluExe_0_dispToRegQ_first__2125_BIT_13_ETC___d12210,
coreFix_aluExe_0_exeToFinQ_RDY_first__2537_AND_ETC___d12575,
coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270,
coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353,
coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392,
coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11366,
coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11398,
coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11374,
coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11402,
coreFix_aluExe_1_dispToRegQ_first__1330_BIT_13_ETC___d11415,
coreFix_aluExe_1_exeToFinQ_RDY_first__1928_AND_ETC___d11967,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8208,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8239,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8263,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8216,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8243,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8267,
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660,
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8413,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052,
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10819,
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10855,
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10903,
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10945,
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10987,
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__37_ETC___d13814,
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570,
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608,
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583,
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614,
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591,
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731,
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570,
coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14413,
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d12921,
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13327,
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13594,
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276,
csrf_prv_reg_read__2680_ULE_1___d14236,
csrf_prv_reg_read__2680_ULT_IF_fetchStage_pipe_ETC___d12918,
fetchStage_RDY_pipelines_0_first__2649_AND_NOT_ETC___d13257,
fetchStage_RDY_pipelines_0_first__2649_AND_fet_ETC___d13324,
fetchStage_RDY_pipelines_1_deq__2664_AND_NOT_f_ETC___d13863,
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13805,
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13884,
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13971,
fetchStage_pipelines_0_canDeq__2650_AND_fetchS_ETC___d13873,
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13811,
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13818,
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13839,
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13850,
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d14076,
fetchStage_pipelines_0_canDeq__2650_AND_specTa_ETC___d13936,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d12916,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13549,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13570,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13642,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13750,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13756,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13778,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13785,
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13966,
fetchStage_pipelines_0_first__2652_BITS_199_TO_ETC___d13563,
fetchStage_pipelines_0_first__2652_BIT_68_2679_ETC___d13332,
fetchStage_pipelines_1_first__2661_BITS_194_TO_ETC___d13767,
fetchStage_pipelines_1_first__2661_BITS_199_TO_ETC___d13602,
fetchStage_pipelines_1_first__2661_BIT_68_3382_ETC___d13771,
guard__h362400,
guard__h408090,
guard__h453778,
guard__h501491,
guard__h540292,
guard__h579493,
idx__h677617,
k__h663183,
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12932,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13194,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13878,
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
msip__h75409,
next_deqP___1__h302868,
next_deqP___1__h309149,
next_deqP___1__h317003,
next_deqP___1__h327060,
next_deqP___1__h330285,
r1__read_BIT_20___h652088,
r__h611009,
regRenamingTable_RDY_rename_0_getRename__3134__ETC___d13735,
regRenamingTable_RDY_rename_1_getRename__3791__ETC___d13809,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13319,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13625,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13764,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13896,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13902,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930,
regRenamingTable_rename_0_canRename__3230_AND__ETC___d14074,
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984,
regRenamingTable_rename_1_canRename__3354_AND__ETC___d14028,
rob_RDY_enqPort_0_enq__2674_AND_regRenamingTab_ETC___d13142,
rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13539,
rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13673,
rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13690,
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8280,
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8281,
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631,
v__h297358,
v__h297876,
v__h307872,
v__h308103,
v__h311748,
v__h311979,
v__h326349,
v__h326580,
v__h329574,
v__h329805,
value_BIT_23___h531040,
value_BIT_52___h399220,
x__h601268;
// action method coreReq_start
assign RDY_coreReq_start = 1'd1 ;
assign CAN_FIRE_coreReq_start = 1'd1 ;
assign WILL_FIRE_coreReq_start = EN_coreReq_start ;
// action method coreReq_perfReq
assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;
// actionvalue method coreIndInv_perfResp
assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;
// action method coreIndInv_terminate
assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_terminate =
csrf_terminate_module_terminateQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;
// value method dCacheToParent_rsToP_notEmpty
assign dCacheToParent_rsToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rsToP_deq
assign RDY_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;
// value method dCacheToParent_rsToP_first
assign dCacheToParent_rsToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14911 } ;
assign RDY_dCacheToParent_rsToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
// value method dCacheToParent_rqToP_notEmpty
assign dCacheToParent_rqToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rqToP_deq
assign RDY_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;
// value method dCacheToParent_rqToP_first
assign dCacheToParent_rqToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14937 } ;
assign RDY_dCacheToParent_rqToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
// value method dCacheToParent_fromP_notFull
assign dCacheToParent_fromP_notFull =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;
// action method dCacheToParent_fromP_enq
assign RDY_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign CAN_FIRE_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;
// value method iCacheToParent_rsToP_notEmpty
assign iCacheToParent_rsToP_notEmpty =
fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rsToP_deq
assign RDY_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign CAN_FIRE_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;
// value method iCacheToParent_rsToP_first
assign iCacheToParent_rsToP_first =
fetchStage$iMemIfc_to_parent_rsToP_first ;
assign RDY_iCacheToParent_rsToP_first =
fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;
// value method iCacheToParent_rqToP_notEmpty
assign iCacheToParent_rqToP_notEmpty =
fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rqToP_deq
assign RDY_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign CAN_FIRE_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;
// value method iCacheToParent_rqToP_first
assign iCacheToParent_rqToP_first =
fetchStage$iMemIfc_to_parent_rqToP_first ;
assign RDY_iCacheToParent_rqToP_first =
fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;
// value method iCacheToParent_fromP_notFull
assign iCacheToParent_fromP_notFull =
fetchStage$iMemIfc_to_parent_fromP_notFull ;
assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;
// action method iCacheToParent_fromP_enq
assign RDY_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign CAN_FIRE_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;
// value method tlbToMem_memReq_notEmpty
assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;
// action method tlbToMem_memReq_deq
assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;
// value method tlbToMem_memReq_first
assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;
// value method tlbToMem_respLd_notFull
assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
assign RDY_tlbToMem_respLd_notFull = 1'd1 ;
// action method tlbToMem_respLd_enq
assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;
// value method mmioToPlatform_cRq_notEmpty
assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRq_deq
assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;
// value method mmioToPlatform_cRq_first
assign mmioToPlatform_cRq_first =
{ mmio_cRqQ_data_0[141:78],
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1,
mmio_cRqQ_data_0[71:0] } ;
assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;
// value method mmioToPlatform_pRs_notFull
assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;
// action method mmioToPlatform_pRs_enq
assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;
// value method mmioToPlatform_pRq_notFull
assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;
// action method mmioToPlatform_pRq_enq
assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;
// value method mmioToPlatform_cRs_notEmpty
assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRs_deq
assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;
// value method mmioToPlatform_cRs_first
assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;
// action method mmioToPlatform_setTime
assign RDY_mmioToPlatform_setTime = 1'd1 ;
assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;
// actionvalue method sendDoStats
assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign WILL_FIRE_sendDoStats = EN_sendDoStats ;
// action method recvDoStats
assign RDY_recvDoStats = 1'd1 ;
assign CAN_FIRE_recvDoStats = 1'd1 ;
assign WILL_FIRE_recvDoStats = EN_recvDoStats ;
// actionvalue method deadlock_dCacheCRqStuck_get
assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
EN_deadlock_dCacheCRqStuck_get ;
// actionvalue method deadlock_dCachePRqStuck_get
assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCachePRqStuck_get =
EN_deadlock_dCachePRqStuck_get ;
// actionvalue method deadlock_iCacheCRqStuck_get
assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
assign RDY_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
EN_deadlock_iCacheCRqStuck_get ;
// actionvalue method deadlock_iCachePRqStuck_get
assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
assign RDY_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign CAN_FIRE_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign WILL_FIRE_deadlock_iCachePRqStuck_get =
EN_deadlock_iCachePRqStuck_get ;
// actionvalue method deadlock_renameInstStuck_get
assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameInstStuck_get =
EN_deadlock_renameInstStuck_get ;
// actionvalue method deadlock_renameCorrectPathStuck_get
assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
EN_deadlock_renameCorrectPathStuck_get ;
// actionvalue method deadlock_commitInstStuck_get
assign deadlock_commitInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitInstStuck_get =
EN_deadlock_commitInstStuck_get ;
// actionvalue method deadlock_commitUserInstStuck_get
assign deadlock_commitUserInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitUserInstStuck_get =
EN_deadlock_commitUserInstStuck_get ;
// action method deadlock_checkStarted_get
assign RDY_deadlock_checkStarted_get = 1'd0 ;
assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;
// actionvalue method renameDebug_renameErr_get
assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_renameDebug_renameErr_get = 1'd0 ;
assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;
// action method setMEIP
assign RDY_setMEIP = 1'd1 ;
assign CAN_FIRE_setMEIP = 1'd1 ;
assign WILL_FIRE_setMEIP = EN_setMEIP ;
// action method setSEIP
assign RDY_setSEIP = 1'd1 ;
assign CAN_FIRE_setSEIP = 1'd1 ;
assign WILL_FIRE_setSEIP = EN_setSEIP ;
// action method setDEIP
assign RDY_setDEIP = 1'd1 ;
assign CAN_FIRE_setDEIP = 1'd1 ;
assign WILL_FIRE_setDEIP = EN_setDEIP ;
// submodule coreFix_aluExe_0_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_0_dispToRegQ$first),
.RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_0_exeToFinQ$first),
.RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
.first(coreFix_aluExe_0_regToExeQ$first),
.RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_rsAlu
mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_0_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_1_dispToRegQ$first),
.RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_1_exeToFinQ$first),
.RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
.first(coreFix_aluExe_1_regToExeQ$first),
.RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_rsAlu
mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_1_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
FIFO2 #(.width(32'd140),
.guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT),
.FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
FIFO2 #(.width(32'd64),
.guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT),
.FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
FIFO2 #(.width(32'd204),
.guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT),
.FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
reset_guard coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg(.CLK(CLK),
.RST(RST_N),
.IS_READY(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
.FULL_N(),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_regToExeQ
mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_regToExeQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
.setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
.setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
.setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
.setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
.setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
.setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
.EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
.EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
.canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
.RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
.RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
.RST_N(RST_N),
.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
.RDY_cRqTransfer_getRq(),
.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
.sendRsToP_cRq_getState(),
.RDY_sendRsToP_cRq_getState(),
.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
.RDY_sendRsToP_cRq_getRq(),
.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
.RDY_sendRsToP_cRq_getSlot(),
.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
.RDY_sendRsToP_cRq_getData(),
.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
.RDY_sendRqToP_getRq(),
.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
.RDY_sendRqToP_getSlot(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
.RDY_pipelineResp_getState(),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getSlot(),
.RDY_pipelineResp_getSlot(),
.RDY_pipelineResp_setData(),
.RDY_pipelineResp_setStateSlot(),
.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
.RDY_pipelineResp_getSucc(),
.RDY_pipelineResp_setSucc(),
.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
.RDY_pipelineResp_searchEndOfChain(),
.emptyForFlush(),
.RDY_emptyForFlush(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
.RST_N(RST_N),
.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
.RDY_sendRsToP_pRq_getRq(),
.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
.RDY_sendRsToP_pRq_getData(),
.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getState(),
.RDY_pipelineResp_getState(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
.RDY_pipelineResp_setDone_setData(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
.RST_N(RST_N),
.deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
.deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
.deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
.send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
.EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
.EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
.RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
.first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
.RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
.RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
SizedFIFO #(.p1width(32'd3),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd12),
.p3cntr_width(32'd4),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dTlb
mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(coreFix_memExe_dTlb$perf_req_r),
.perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
.procReq_req(coreFix_memExe_dTlb$procReq_req),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
.toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
.updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
.EN_flush(coreFix_memExe_dTlb$EN_flush),
.EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
.EN_procReq(coreFix_memExe_dTlb$EN_procReq),
.EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
.EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
.EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
.EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
.EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
.EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
.EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
.EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
.flush_done(coreFix_memExe_dTlb$flush_done),
.RDY_flush_done(),
.RDY_flush(coreFix_memExe_dTlb$RDY_flush),
.RDY_updateVMInfo(),
.noPendingReq(coreFix_memExe_dTlb$noPendingReq),
.RDY_noPendingReq(),
.RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
.procResp(coreFix_memExe_dTlb$procResp),
.RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
.RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
.toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
.toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
.RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
.toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
.RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
.RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule coreFix_memExe_dispToRegQ
mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
.EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
.first(coreFix_memExe_dispToRegQ$first),
.RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_lsq
mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
.RST_N(RST_N),
.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
.getHit_t(coreFix_memExe_lsq$getHit_t),
.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
.respLd_t(coreFix_memExe_lsq$respLd_t),
.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
.updateData_d(coreFix_memExe_lsq$updateData_d),
.updateData_t(coreFix_memExe_lsq$updateData_t),
.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
.EN_getHit(coreFix_memExe_lsq$EN_getHit),
.EN_updateData(coreFix_memExe_lsq$EN_updateData),
.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
.EN_respLd(coreFix_memExe_lsq$EN_respLd),
.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
.enqLdTag(coreFix_memExe_lsq$enqLdTag),
.RDY_enqLdTag(),
.enqStTag(coreFix_memExe_lsq$enqStTag),
.RDY_enqStTag(),
.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
.getOrigBE(coreFix_memExe_lsq$getOrigBE),
.RDY_getOrigBE(),
.getHit(coreFix_memExe_lsq$getHit),
.RDY_getHit(),
.RDY_updateData(),
.updateAddr(coreFix_memExe_lsq$updateAddr),
.RDY_updateAddr(),
.issueLd(coreFix_memExe_lsq$issueLd),
.RDY_issueLd(),
.getIssueLd(coreFix_memExe_lsq$getIssueLd),
.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
.respLd(coreFix_memExe_lsq$respLd),
.RDY_respLd(),
.firstLd(coreFix_memExe_lsq$firstLd),
.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
.firstSt(coreFix_memExe_lsq$firstSt),
.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
.RDY_wakeupLdStalledBySB(),
.stqEmpty(coreFix_memExe_lsq$stqEmpty),
.RDY_stqEmpty(),
.RDY_setAtCommit_0_put(),
.RDY_setAtCommit_1_put(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.stqFull_ehrPort0(),
.RDY_stqFull_ehrPort0(),
.ldqFull_ehrPort0(),
.RDY_ldqFull_ehrPort0(),
.noWrongPathLoads(),
.RDY_noWrongPathLoads());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_regToExeQ
mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_regToExeQ$EN_enq),
.EN_deq(coreFix_memExe_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
.RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
.first(coreFix_memExe_regToExeQ$first),
.RDY_first(coreFix_memExe_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_rsMem
mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_rsMem$enq_x),
.setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
.setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
.setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
.setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
.setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
.setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_rsMem$EN_enq),
.EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
.EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_rsMem$RDY_enq),
.canEnq(coreFix_memExe_rsMem$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_memExe_rsMem$dispatchData),
.RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
.RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_stb
mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
.RST_N(RST_N),
.deq_idx(coreFix_memExe_stb$deq_idx),
.enq_be(coreFix_memExe_stb$enq_be),
.enq_data(coreFix_memExe_stb$enq_data),
.enq_idx(coreFix_memExe_stb$enq_idx),
.enq_paddr(coreFix_memExe_stb$enq_paddr),
.getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
.noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
.noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
.noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
.noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
.search_be(coreFix_memExe_stb$search_be),
.search_paddr(coreFix_memExe_stb$search_paddr),
.EN_enq(coreFix_memExe_stb$EN_enq),
.EN_deq(coreFix_memExe_stb$EN_deq),
.EN_issue(coreFix_memExe_stb$EN_issue),
.isEmpty(coreFix_memExe_stb$isEmpty),
.RDY_isEmpty(),
.getEnqIndex(coreFix_memExe_stb$getEnqIndex),
.RDY_getEnqIndex(),
.RDY_enq(coreFix_memExe_stb$RDY_enq),
.deq(coreFix_memExe_stb$deq),
.RDY_deq(coreFix_memExe_stb$RDY_deq),
.issue(coreFix_memExe_stb$issue),
.RDY_issue(coreFix_memExe_stb$RDY_issue),
.search(coreFix_memExe_stb$search),
.RDY_search(),
.noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
.RDY_noMatchLdQ(),
.noMatchStQ(coreFix_memExe_stb$noMatchStQ),
.RDY_noMatchStQ());
// submodule coreFix_trainBPQ_0
FIFO2 #(.width(32'd159), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_0$D_IN),
.ENQ(coreFix_trainBPQ_0$ENQ),
.DEQ(coreFix_trainBPQ_0$DEQ),
.CLR(coreFix_trainBPQ_0$CLR),
.D_OUT(coreFix_trainBPQ_0$D_OUT),
.FULL_N(coreFix_trainBPQ_0$FULL_N),
.EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));
// submodule coreFix_trainBPQ_1
FIFO2 #(.width(32'd159), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_1$D_IN),
.ENQ(coreFix_trainBPQ_1$ENQ),
.DEQ(coreFix_trainBPQ_1$DEQ),
.CLR(coreFix_trainBPQ_1$CLR),
.D_OUT(coreFix_trainBPQ_1$D_OUT),
.FULL_N(coreFix_trainBPQ_1$FULL_N),
.EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));
// submodule csrInstOrInterruptInflight_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_0$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));
// submodule csrInstOrInterruptInflight_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_1$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_stats_module_writeQ
FIFO1 #(.width(32'd1),
.guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
.CLK(CLK),
.D_IN(csrf_stats_module_writeQ$D_IN),
.ENQ(csrf_stats_module_writeQ$ENQ),
.DEQ(csrf_stats_module_writeQ$DEQ),
.CLR(csrf_stats_module_writeQ$CLR),
.D_OUT(csrf_stats_module_writeQ$D_OUT),
.FULL_N(csrf_stats_module_writeQ$FULL_N),
.EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));
// submodule csrf_terminate_module_terminateQ
FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
.CLK(CLK),
.ENQ(csrf_terminate_module_terminateQ$ENQ),
.DEQ(csrf_terminate_module_terminateQ$DEQ),
.CLR(csrf_terminate_module_terminateQ$CLR),
.FULL_N(csrf_terminate_module_terminateQ$FULL_N),
.EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));
// submodule epochManager
mkEpochManager epochManager(.CLK(CLK),
.RST_N(RST_N),
.checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
.checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
.updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
.updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
.EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
.EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
.EN_incrementEpoch(epochManager$EN_incrementEpoch),
.checkEpoch_0_check(epochManager$checkEpoch_0_check),
.RDY_checkEpoch_0_check(),
.checkEpoch_1_check(epochManager$checkEpoch_1_check),
.RDY_checkEpoch_1_check(),
.RDY_updatePrevEpoch_0_update(),
.RDY_updatePrevEpoch_1_update(),
.getEpoch(),
.RDY_getEpoch(),
.RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
.getEpochState(),
.RDY_getEpochState(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule fetchStage
mkFetchStage fetchStage(.CLK(CLK),
.RST_N(RST_N),
.iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
.iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
.iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
.iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
.iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
.iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
.iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
.iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
.iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
.mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
.mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
.mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
.perf_req_r(fetchStage$perf_req_r),
.perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
.redirect_pc(fetchStage$redirect_pc),
.start_pc(fetchStage$start_pc),
.train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
.train_predictors_iType(fetchStage$train_predictors_iType),
.train_predictors_mispred(fetchStage$train_predictors_mispred),
.train_predictors_next_pc(fetchStage$train_predictors_next_pc),
.train_predictors_pc(fetchStage$train_predictors_pc),
.train_predictors_taken(fetchStage$train_predictors_taken),
.EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
.EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
.EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
.EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
.EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
.EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
.EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
.EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
.EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
.EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
.EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
.EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
.EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
.EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
.EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
.EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
.EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
.EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
.EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
.EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
.EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
.EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
.EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
.EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
.EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
.EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
.EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
.EN_start(fetchStage$EN_start),
.EN_stop(fetchStage$EN_stop),
.EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
.EN_redirect(fetchStage$EN_redirect),
.EN_done_flushing(fetchStage$EN_done_flushing),
.EN_train_predictors(fetchStage$EN_train_predictors),
.EN_flush_predictors(fetchStage$EN_flush_predictors),
.EN_perf_setStatus(fetchStage$EN_perf_setStatus),
.EN_perf_req(fetchStage$EN_perf_req),
.EN_perf_resp(fetchStage$EN_perf_resp),
.pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
.RDY_pipelines_0_canDeq(),
.RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
.pipelines_0_first(fetchStage$pipelines_0_first),
.RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
.pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
.RDY_pipelines_1_canDeq(),
.RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
.pipelines_1_first(fetchStage$pipelines_1_first),
.RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
.iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
.RDY_iTlbIfc_flush_done(),
.RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
.RDY_iTlbIfc_updateVMInfo(),
.iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
.RDY_iTlbIfc_noPendingReq(),
.RDY_iTlbIfc_to_proc_request_put(),
.iTlbIfc_to_proc_response_get(),
.RDY_iTlbIfc_to_proc_response_get(),
.iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
.iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
.RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
.iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
.RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
.RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
.RDY_iTlbIfc_perf_setStatus(),
.RDY_iTlbIfc_perf_req(),
.iTlbIfc_perf_resp(),
.RDY_iTlbIfc_perf_resp(),
.iTlbIfc_perf_respValid(),
.RDY_iTlbIfc_perf_respValid(),
.RDY_iMemIfc_to_proc_request_put(),
.iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_flush(),
.iMemIfc_flush_done(),
.RDY_iMemIfc_flush_done(),
.RDY_iMemIfc_perf_setStatus(),
.RDY_iMemIfc_perf_req(),
.iMemIfc_perf_resp(),
.RDY_iMemIfc_perf_resp(),
.iMemIfc_perf_respValid(),
.RDY_iMemIfc_perf_respValid(),
.iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
.RDY_iMemIfc_to_parent_rsToP_notEmpty(),
.RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
.iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
.RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
.iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
.RDY_iMemIfc_to_parent_rqToP_notEmpty(),
.RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
.iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
.RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
.iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
.RDY_iMemIfc_to_parent_fromP_notFull(),
.RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
.iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
.RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
.iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
.RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
.mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
.mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
.RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
.mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
.RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
.mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
.RDY_mmioIfc_setHtifAddrs(),
.RDY_start(),
.RDY_stop(),
.RDY_setWaitRedirect(),
.RDY_redirect(),
.RDY_done_flushing(fetchStage$RDY_done_flushing),
.RDY_train_predictors(),
.emptyForFlush(),
.RDY_emptyForFlush(),
.RDY_flush_predictors(),
.flush_predictors_done(),
.RDY_flush_predictors_done(),
.getFetchState(),
.RDY_getFetchState(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule l2Tlb
mkL2Tlb l2Tlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(l2Tlb$perf_req_r),
.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
.EN_perf_req(l2Tlb$EN_perf_req),
.EN_perf_resp(l2Tlb$EN_perf_resp),
.RDY_updateVMInfo(),
.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
.toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
.RDY_toMem_memReq_notEmpty(),
.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
.toMem_memReq_first(l2Tlb$toMem_memReq_first),
.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
.RDY_toMem_respLd_notFull(),
.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule mmio_cRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataPendQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataRespQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));
// submodule perfReqQ
FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
.CLK(CLK),
.D_IN(perfReqQ$D_IN),
.ENQ(perfReqQ$ENQ),
.DEQ(perfReqQ$DEQ),
.CLR(perfReqQ$CLR),
.D_OUT(perfReqQ$D_OUT),
.FULL_N(perfReqQ$FULL_N),
.EMPTY_N(perfReqQ$EMPTY_N));
// submodule regRenamingTable
mkRegRenamingTable regRenamingTable(.CLK(CLK),
.RST_N(RST_N),
.rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
.rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
.rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
.rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
.rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
.rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
.specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
.EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
.EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
.EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
.EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
.EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
.rename_0_getRename(regRenamingTable$rename_0_getRename),
.RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
.RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
.rename_0_canRename(regRenamingTable$rename_0_canRename),
.RDY_rename_0_canRename(),
.rename_1_getRename(regRenamingTable$rename_1_getRename),
.RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
.RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
.rename_1_canRename(regRenamingTable$rename_1_canRename),
.RDY_rename_1_canRename(),
.RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
.commit_0_canCommit(),
.RDY_commit_0_canCommit(),
.RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
.commit_1_canCommit(),
.RDY_commit_1_canCommit(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule rf
mkRFileSynth rf(.CLK(CLK),
.RST_N(RST_N),
.read_0_rd1_rindx(rf$read_0_rd1_rindx),
.read_0_rd2_rindx(rf$read_0_rd2_rindx),
.read_0_rd3_rindx(rf$read_0_rd3_rindx),
.read_1_rd1_rindx(rf$read_1_rd1_rindx),
.read_1_rd2_rindx(rf$read_1_rd2_rindx),
.read_1_rd3_rindx(rf$read_1_rd3_rindx),
.read_2_rd1_rindx(rf$read_2_rd1_rindx),
.read_2_rd2_rindx(rf$read_2_rd2_rindx),
.read_2_rd3_rindx(rf$read_2_rd3_rindx),
.read_3_rd1_rindx(rf$read_3_rd1_rindx),
.read_3_rd2_rindx(rf$read_3_rd2_rindx),
.read_3_rd3_rindx(rf$read_3_rd3_rindx),
.write_0_wr_data(rf$write_0_wr_data),
.write_0_wr_rindx(rf$write_0_wr_rindx),
.write_1_wr_data(rf$write_1_wr_data),
.write_1_wr_rindx(rf$write_1_wr_rindx),
.write_2_wr_data(rf$write_2_wr_data),
.write_2_wr_rindx(rf$write_2_wr_rindx),
.write_3_wr_data(rf$write_3_wr_data),
.write_3_wr_rindx(rf$write_3_wr_rindx),
.EN_write_0_wr(rf$EN_write_0_wr),
.EN_write_1_wr(rf$EN_write_1_wr),
.EN_write_2_wr(rf$EN_write_2_wr),
.EN_write_3_wr(rf$EN_write_3_wr),
.RDY_write_0_wr(),
.RDY_write_1_wr(),
.RDY_write_2_wr(),
.RDY_write_3_wr(),
.read_0_rd1(rf$read_0_rd1),
.RDY_read_0_rd1(),
.read_0_rd2(rf$read_0_rd2),
.RDY_read_0_rd2(),
.read_0_rd3(),
.RDY_read_0_rd3(),
.read_1_rd1(rf$read_1_rd1),
.RDY_read_1_rd1(),
.read_1_rd2(rf$read_1_rd2),
.RDY_read_1_rd2(),
.read_1_rd3(),
.RDY_read_1_rd3(),
.read_2_rd1(rf$read_2_rd1),
.RDY_read_2_rd1(),
.read_2_rd2(rf$read_2_rd2),
.RDY_read_2_rd2(),
.read_2_rd3(rf$read_2_rd3),
.RDY_read_2_rd3(),
.read_3_rd1(rf$read_3_rd1),
.RDY_read_3_rd1(),
.read_3_rd2(rf$read_3_rd2),
.RDY_read_3_rd2(),
.read_3_rd3(),
.RDY_read_3_rd3());
// submodule rob
mkReorderBufferSynth rob(.CLK(CLK),
.RST_N(RST_N),
.enqPort_0_enq_x(rob$enqPort_0_enq_x),
.enqPort_1_enq_x(rob$enqPort_1_enq_x),
.getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
.getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
.getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
.getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
.getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
.getOrig_Inst_0_get_x(rob$getOrig_Inst_0_get_x),
.getOrig_Inst_1_get_x(rob$getOrig_Inst_1_get_x),
.setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
.setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
.setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
.setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
.setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
.setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
.setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
.setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
.setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
.setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
.setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
.setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
.setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
.setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
.setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
.setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
.specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
.specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
.EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
.EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
.EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
.EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
.EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
.EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
.EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
.EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
.EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
.EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
.EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
.enqPort_0_canEnq(rob$enqPort_0_canEnq),
.RDY_enqPort_0_canEnq(),
.RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
.enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
.RDY_enqPort_0_getEnqInstTag(),
.enqPort_1_canEnq(rob$enqPort_1_canEnq),
.RDY_enqPort_1_canEnq(),
.RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
.enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
.RDY_enqPort_1_getEnqInstTag(),
.isEmpty(rob$isEmpty),
.RDY_isEmpty(),
.deqPort_0_canDeq(rob$deqPort_0_canDeq),
.RDY_deqPort_0_canDeq(),
.RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
.deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
.RDY_deqPort_0_getDeqInstTag(),
.deqPort_0_deq_data(rob$deqPort_0_deq_data),
.RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
.deqPort_1_canDeq(rob$deqPort_1_canDeq),
.RDY_deqPort_1_canDeq(),
.RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
.deqPort_1_getDeqInstTag(),
.RDY_deqPort_1_getDeqInstTag(),
.deqPort_1_deq_data(rob$deqPort_1_deq_data),
.RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
.RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
.RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
.RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
.RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
.RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
.RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
.getOrigPC_0_get(rob$getOrigPC_0_get),
.RDY_getOrigPC_0_get(),
.getOrigPC_1_get(rob$getOrigPC_1_get),
.RDY_getOrigPC_1_get(),
.getOrigPC_2_get(),
.RDY_getOrigPC_2_get(),
.getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
.RDY_getOrigPredPC_0_get(),
.getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
.RDY_getOrigPredPC_1_get(),
.getOrig_Inst_0_get(rob$getOrig_Inst_0_get),
.RDY_getOrig_Inst_0_get(),
.getOrig_Inst_1_get(rob$getOrig_Inst_1_get),
.RDY_getOrig_Inst_1_get(),
.getEnqTime(rob$getEnqTime),
.RDY_getEnqTime(),
.isEmpty_ehrPort0(),
.RDY_isEmpty_ehrPort0(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule sbAggr
mkScoreboardAggr sbAggr(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
.setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
.setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
.setReady_0_put(sbAggr$setReady_0_put),
.setReady_1_put(sbAggr$setReady_1_put),
.setReady_2_put(sbAggr$setReady_2_put),
.setReady_3_put(sbAggr$setReady_3_put),
.setReady_4_put(sbAggr$setReady_4_put),
.EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
.EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
.EN_setReady_0_put(sbAggr$EN_setReady_0_put),
.EN_setReady_1_put(sbAggr$EN_setReady_1_put),
.EN_setReady_2_put(sbAggr$EN_setReady_2_put),
.EN_setReady_3_put(sbAggr$EN_setReady_3_put),
.EN_setReady_4_put(sbAggr$EN_setReady_4_put),
.eagerLookup_0_get(sbAggr$eagerLookup_0_get),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(sbAggr$eagerLookup_1_get),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put());
// submodule sbCons
mkScoreboardCons sbCons(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
.lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
.lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
.lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
.lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
.setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
.setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
.setReady_0_put(sbCons$setReady_0_put),
.setReady_1_put(sbCons$setReady_1_put),
.setReady_2_put(sbCons$setReady_2_put),
.setReady_3_put(sbCons$setReady_3_put),
.EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
.EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
.EN_setReady_0_put(sbCons$EN_setReady_0_put),
.EN_setReady_1_put(sbCons$EN_setReady_1_put),
.EN_setReady_2_put(sbCons$EN_setReady_2_put),
.EN_setReady_3_put(sbCons$EN_setReady_3_put),
.eagerLookup_0_get(),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.lazyLookup_0_get(sbCons$lazyLookup_0_get),
.RDY_lazyLookup_0_get(),
.lazyLookup_1_get(sbCons$lazyLookup_1_get),
.RDY_lazyLookup_1_get(),
.lazyLookup_2_get(sbCons$lazyLookup_2_get),
.RDY_lazyLookup_2_get(),
.lazyLookup_3_get(sbCons$lazyLookup_3_get),
.RDY_lazyLookup_3_get());
// submodule specTagManager
mkSpecTagManager specTagManager(.CLK(CLK),
.RST_N(RST_N),
.specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
.EN_claimSpecTag(specTagManager$EN_claimSpecTag),
.EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
.currentSpecBits(specTagManager$currentSpecBits),
.RDY_currentSpecBits(),
.nextSpecTag(specTagManager$nextSpecTag),
.RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
.RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
.canClaim(specTagManager$canClaim),
.RDY_canClaim(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// rule RL_rl_outOfReset
assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;
// rule RL_sendDTlbReq
assign CAN_FIRE_RL_sendDTlbReq =
coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
l2Tlb$RDY_toChildren_rqFromC_put ;
assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;
// rule RL_sendITlbReq
assign CAN_FIRE_RL_sendITlbReq =
l2Tlb$RDY_toChildren_rqFromC_put &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ;
assign WILL_FIRE_RL_sendITlbReq =
CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;
// rule RL_sendRsToDTlb
assign CAN_FIRE_RL_sendRsToDTlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;
// rule RL_sendRsToITlb
assign CAN_FIRE_RL_sendRsToITlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
!l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
l2Tlb$RDY_toChildren_iTlbReqFlush_put &&
fetchStage$RDY_iTlbIfc_toParent_flush_request_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
// rule RL_sendFlushDone
assign CAN_FIRE_RL_sendFlushDone =
coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
l2Tlb$RDY_toChildren_flushDone_get &&
fetchStage$RDY_iTlbIfc_toParent_flush_response_put ;
assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;
// rule RL_sendRobEnqTime
assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;
// rule RL_readyToFetch
assign CAN_FIRE_RL_readyToFetch =
fetchStage$RDY_done_flushing && !flush_reservation &&
!flush_tlbs &&
!update_vm_info &&
fetchStage$iTlbIfc_flush_done &&
coreFix_memExe_dTlb$flush_done ;
assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;
// rule RL_csrf_minstret_ehr_setRead
assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
// rule RL_csrf_mcycle_ehr_setRead
assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
// rule RL_mmio_handlePRq
assign CAN_FIRE_RL_mmio_handlePRq =
!mmio_pRqQ_empty && !mmio_cRsQ_full &&
(!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
!csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
!csrInstOrInterruptInflight_rl) ;
assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;
// rule RL_mmio_sendDataReq
assign CAN_FIRE_RL_mmio_sendDataReq =
!mmio_dataReqQ_empty && !mmio_cRqQ_full ;
assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendInstReq
assign CAN_FIRE_RL_mmio_sendInstReq =
!mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd &&
fetchStage$RDY_mmioIfc_instReq_first_fst &&
fetchStage$RDY_mmioIfc_instReq_deq ;
assign WILL_FIRE_RL_mmio_sendInstReq =
CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendDataResp
assign CAN_FIRE_RL_mmio_sendDataResp =
!mmio_dataRespQ_full && !mmio_pRsQ_empty &&
mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;
// rule RL_mmio_sendInstResp
assign CAN_FIRE_RL_mmio_sendInstResp =
!mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
!mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;
// rule RL_mmio_cRqQ_canonicalize
assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_canonicalize
assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_canonicalize
assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_doFetchTrainBP
assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_doFetchTrainBP_1
assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_memExe_doIssueSB
assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
(!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqStQ_full_rl) &&
coreFix_memExe_stb$RDY_issue ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_lsq$firstLd[101] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchLdQ &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
// rule RL_renameStage_doRenaming_wrongPath
assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
fetchStage$RDY_pipelines_0_first &&
(!fetchStage$pipelines_0_canDeq ||
epochManager$checkEpoch_0_check ||
fetchStage$RDY_pipelines_0_deq) &&
NOT_fetchStage_pipelines_1_canDeq__2658_2659_O_ETC___d12667 &&
!epochManager$checkEpoch_0_check ;
assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;
// rule RL_commitStage_doCommitTrap_flush
assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
(rob$deqPort_0_deq_data[12] ||
epochManager$RDY_incrementEpoch) &&
!commitStage_commitTrap[133] &&
rob$deqPort_0_deq_data[167] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_doCommitTrap_handle
assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq &&
commitStage_commitTrap[133] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_commitStage_doCommitKilledLd
assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data &&
rob$RDY_deqPort_0_deq &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[18] ;
assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
CAN_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_doCommitSystemInst
assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14413 &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
rob$deqPort_0_deq_data[25] &&
(rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ;
assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
CAN_FIRE_RL_commitStage_doCommitSystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_csrf_incCycle
assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;
// rule RL_csrf_mcycle_ehr_data_canon
assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
// rule RL_commitStage_notifyLSQCommit
assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[25] &&
rob$deqPort_0_deq_data[15] &&
!rob$deqPort_0_deq_data[14] ;
assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
// rule RL_commitStage_doCommitNormalInst
assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
rob$RDY_deqPort_0_deq_data &&
NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_RDY_ETC___d14641 &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
rob$deqPort_0_deq_data[25] &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd21 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20 ;
assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
CAN_FIRE_RL_commitStage_doCommitNormalInst ;
// rule RL_csrf_minstret_ehr_data_canon
assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
// rule RL_coreFix_aluExe_1_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_1$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_aluExe_0_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_0$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_aluExe_0_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
!coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ_RDY_first__2537_AND_ETC___d12575 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
!coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ_RDY_first__1928_AND_ETC___d11967 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ;
// rule RL_coreFix_aluExe_1_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
coreFix_aluExe_1_regToExeQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_enq &&
coreFix_aluExe_1_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
coreFix_aluExe_0_regToExeQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_enq &&
coreFix_aluExe_0_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
coreFix_aluExe_1_dispToRegQ$RDY_deq &&
coreFix_aluExe_1_regToExeQ$RDY_enq &&
coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_1_dispToRegQ_first__1330_BIT_13_ETC___d11415 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
coreFix_aluExe_0_dispToRegQ$RDY_deq &&
coreFix_aluExe_0_regToExeQ$RDY_enq &&
coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_dispToRegQ_first__2125_BIT_13_ETC___d12210 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
coreFix_aluExe_0_dispToRegQ$RDY_enq &&
coreFix_aluExe_0_rsAlu$RDY_doDispatch &&
coreFix_aluExe_0_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
coreFix_aluExe_1_dispToRegQ$RDY_enq &&
coreFix_aluExe_1_rsAlu$RDY_doDispatch &&
coreFix_aluExe_1_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_memExe_doDeqLdQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_lsq$firstLd[7] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[101] &&
!coreFix_memExe_lsq$firstLd[16] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doFinishMem
assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
rob$RDY_setExecuted_doFinishMem &&
coreFix_memExe_dTlb$RDY_deqProcResp &&
coreFix_memExe_dTlb$RDY_procResp ;
assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
!coreFix_memExe_lsq$firstSt[77] &&
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchStQ &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_mmio_dataReqQ_canonicalize
assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataReqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLrScAmoToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
(!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
!coreFix_memExe_reqLrScAmoQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_doIssueLdFromIssueQ
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
coreFix_memExe_lsq$RDY_getIssueLd &&
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doIssueLdFromUpdate
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 &&
coreFix_memExe_issueLd$whas ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_lsq$firstSt[4] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_Fence
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_mmio_dataRespQ_canonicalize
assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataRespQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_canonicalize
assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataPendQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLdToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
(!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLdQ_empty_lat_0$whas ||
!coreFix_memExe_reqLdQ_empty_rl) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 ;
assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_sendStToMem
assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
(!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
!coreFix_memExe_reqStQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_St_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
!coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_stb$getEnqIndex[2] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doRespLdMem
assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
!coreFix_memExe_memRespLdQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doRespLdForward
assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
!coreFix_memExe_forwardQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doExeMem
assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
coreFix_memExe_regToExeQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_first &&
coreFix_memExe_dTlb$RDY_procReq ;
assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
// rule RL_prepareCachesAndTlbs
assign CAN_FIRE_RL_prepareCachesAndTlbs =
(!flush_tlbs ||
coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush) &&
(flush_reservation || flush_tlbs || update_vm_info) ;
assign WILL_FIRE_RL_prepareCachesAndTlbs =
CAN_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_coreFix_memExe_doRegReadMem
assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
coreFix_memExe_dispToRegQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_enq &&
coreFix_memExe_dispToRegQ$RDY_first &&
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 ;
assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doDispatchMem
assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
coreFix_memExe_dispToRegQ$RDY_enq &&
coreFix_memExe_rsMem$RDY_doDispatch &&
coreFix_memExe_rsMem$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
(!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8416 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
// rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8281 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
!coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon =
1'd1 ;
// rule RL_renameStage_doRenaming_Trap
assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12932 ;
assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
CAN_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_renameStage_doRenaming_SystemInst
assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
epochManager$RDY_incrementEpoch &&
rob_RDY_enqPort_0_enq__2674_AND_regRenamingTab_ETC___d13142 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13194 &&
rob$isEmpty ;
assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_csrInstOrInterruptInflight_canon
assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
// rule RL_commitStage_doSetLSQAtCommit
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
WILL_FIRE_RL_commitStage_notifyLSQCommit ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
// rule RL_commitStage_doSetLSQAtCommit_1
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 &&
rob$deqPort_1_deq_data[13] ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
// rule RL_renameStage_doRenaming
assign CAN_FIRE_RL_renameStage_doRenaming =
(!fetchStage$pipelines_0_canDeq ||
IF_fetchStage_RDY_pipelines_0_first__2649_AND__ETC___d13261) &&
IF_NOT_fetchStage_pipelines_0_canDeq__2650_265_ETC___d13703 &&
IF_NOT_fetchStage_pipelines_0_canDeq__2650_265_ETC___d13711 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13875 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13878 ;
assign WILL_FIRE_RL_renameStage_doRenaming =
CAN_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_mmio_pRqQ_canonicalize
assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_globalSpecUpdate_canon_correct_spec
assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[13] ;
assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013) ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601) ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626) ;
assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd10) ;
assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd10) ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap[4] ;
assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!fetchStage$pipelines_0_first[68] &&
(IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14]) ;
assign MUX_csrf_debug_int_pend$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd29 ;
assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd16 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd29) ;
assign MUX_csrf_fflags_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd2) ;
assign MUX_csrf_fs_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd2 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ;
assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_ie_vec_1$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ;
assign MUX_csrf_mpp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;
assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;
assign MUX_csrf_prv_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ;
assign MUX_csrf_spp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ;
assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13985 &&
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 ;
assign MUX_flush_reservation$write_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
assign MUX_flush_tlbs$write_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
assign MUX_rf$write_3_wr_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__PSEL_5 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
assign MUX_rf$write_3_wr_1__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
assign MUX_rf$write_3_wr_2__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbCons$setReady_3_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_3 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
assign MUX_update_vm_info$write_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
assign MUX_commitStage_commitTrap$write_1__VAL_2 =
{ 1'd1,
rob$deqPort_0_deq_data[282:219],
x__h690863,
rob$deqPort_0_deq_data[166],
rob$deqPort_0_deq_data[166] ?
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 :
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 } ;
assign MUX_commitStage_rg_instret$write_1__VAL_1 =
commitStage_rg_instret + 64'd1 ;
assign MUX_commitStage_rg_instret$write_1__VAL_2 =
commitStage_rg_instret + y__h707788 ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
(k__h663183 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13884) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408,
fetchStage_pipelines_1_first__2661_BIT_173_340_ETC___d13484,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h677486,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
5'd10,
sbAggr$eagerLookup_0_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
{ 1'd1,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
{ 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
{ 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 =
{ 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
3'd3 :
3'd5) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 } :
58'h155555555555554) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
55'h15555555555555 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
{ (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
{ coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd0) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) :
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
x__h283918 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
x__h285363,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
{ 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
{ 2'd2,
addr__h288139,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
{ x__h153733, x__h153739, 84'h82AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
{ x__h157280, x__h157286, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
{ x__h160096,
x__h160100,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
x__h161948,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
resp_addr__h290043,
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$getIssueLd[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_issueLd$wget[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
{ coreFix_memExe_stb$search[67],
coreFix_memExe_stb$search[67] ?
coreFix_memExe_stb$search[66:65] :
2'h2,
coreFix_memExe_stb$search[64],
coreFix_memExe_stb$search[64] ?
coreFix_memExe_stb$search[63:0] :
64'hAAAAAAAAAAAAAAAA } ;
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_1[63:0];
endcase
end
assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
x__h195199 } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
{ 5'd0,
coreFix_memExe_lsq$firstSt[141:78],
2'd3,
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
coreFix_memExe_lsq$firstSt[76:5],
coreFix_memExe_lsq$firstSt[156:153],
coreFix_memExe_lsq$firstSt[69] &&
coreFix_memExe_lsq$firstSt[70] &&
coreFix_memExe_lsq$firstSt[71] &&
coreFix_memExe_lsq$firstSt[72] &&
coreFix_memExe_lsq$firstSt[73] &&
coreFix_memExe_lsq$firstSt[74] &&
coreFix_memExe_lsq$firstSt[75] &&
coreFix_memExe_lsq$firstSt[76],
coreFix_memExe_lsq$firstSt[152:151] } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
{ 5'd0,
coreFix_memExe_lsq$firstLd[80:17],
84'h92AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } :
65'h10000000000000001) :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
curData__h190989 :
{ {32{x__h191752[31]}}, x__h191752 } } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[325:321],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[299:276],
1'd0 } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[325:321],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[299:276],
1'd1 } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[325:321],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[299:276],
1'd0 } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[325:321],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[299:276],
1'd1 } ;
assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
assign MUX_csrf_fflags_reg$write_1__VAL_2 =
csrf_fflags_reg | fflags__h707765 ;
always@(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 or
robdeqPort_0_deq_data_BITS_95_TO_32__q262)
begin
case (IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398)
6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_1 =
robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13];
endcase
end
assign MUX_csrf_ie_vec_1$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18)) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] :
csrf_prev_ie_vec_1 ;
assign MUX_csrf_ie_vec_3$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q262[3] :
csrf_prev_ie_vec_3 ;
assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
n__read__h705337 + 64'd1 ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
n__read__h705337 + { 62'd0, x__h708013 } ;
assign MUX_csrf_mpp_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ?
MUX_csrf_mepc_csr$write_1__VAL_2[12:11] :
2'd0 ;
assign MUX_csrf_mtval_csr$write_1__VAL_1 =
commitStage_commitTrap[4] ? 64'd0 : trap_val__h695358 ;
assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 =
rob$deqPort_0_deq_data[186:182] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 !=
6'd8 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_2[5] ;
assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 =
rob$deqPort_0_deq_data[186:182] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 !=
6'd18 ||
MUX_csrf_mepc_csr$write_1__VAL_2[7] ;
assign MUX_csrf_prv_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd19) ?
x__h704740 :
csrf_mpp_reg ;
assign MUX_csrf_prv_reg$write_1__VAL_2 =
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ?
2'd1 :
2'd3 ;
assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 =
(mmio_pRqQ_data_0[37:36] == 2'd2) ?
mmio_pRqQ_data_0[0] :
amoExec___d880[0] ;
assign MUX_csrf_spp_reg$write_1__VAL_1 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) &&
MUX_csrf_sepc_csr$write_1__VAL_2[8] ;
assign MUX_fetchStage$redirect_1__VAL_4 =
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ?
y_avValue__h695205 :
y_avValue__h696966 ;
always@(rob$deqPort_0_deq_data or
next_pc__h704680 or csrf_sepc_csr or csrf_mepc_csr)
begin
case (rob$deqPort_0_deq_data[186:182])
5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr;
5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr;
default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h704680;
endcase
end
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
{ 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
mmio_dataReqQ_data_0[141:78],
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263,
mmio_dataReqQ_data_0[71:0] } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
fetchStage$mmioIfc_instReq_first_fst,
5'd2,
fetchStage$mmioIfc_instReq_first_snd,
72'hAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$firstSt[141:78],
(coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
6'd42 :
{ 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
coreFix_memExe_lsq$firstSt[76:5] } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_lsq$firstLd[80:17],
6'd26,
coreFix_memExe_lsq$firstLd[15:0],
56'hAAAAAAAAAAAAAA } ;
assign MUX_rf$write_2_wr_2__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
res_data__h335945 :
res_data__h335940 ;
assign MUX_rf$write_2_wr_2__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
res_data__h381640 :
res_data__h381635 ;
assign MUX_rf$write_2_wr_2__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
res_data__h427328 :
res_data__h427323 ;
assign MUX_rf$write_2_wr_2__VAL_5 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
data___1__h473058 :
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ;
assign MUX_rf$write_2_wr_2__VAL_6 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
data___1__h473880 :
data__h473346 ;
assign MUX_rf$write_3_wr_2__VAL_3 =
coreFix_memExe_lsq$firstLd[100] ?
coreFix_memExe_respLrScAmoQ_data_0 :
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 ;
assign MUX_rf$write_3_wr_2__VAL_4 =
coreFix_memExe_lsq$firstLd[100] ?
mmio_dataRespQ_data_0[63:0] :
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 ;
assign MUX_rob$enqPort_0_enq_1__VAL_1 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 &&
fetchStage$pipelines_0_first[194:192] != 3'd2 &&
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4,
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13950 } ;
assign MUX_rob$enqPort_0_enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852,
2'd1,
!fetchStage$pipelines_0_first[68] &&
(IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14]),
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d13121,
fetchStage$pipelines_0_first[63:0],
2'd0,
fetchStage$pipelines_0_first[323:260],
20'd13601,
specTagManager$currentSpecBits } ;
assign MUX_rob$enqPort_0_enq_1__VAL_3 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0,
13'h1521,
specTagManager$currentSpecBits } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 } ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
res_fflags__h335941 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
res_fflags__h381636 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
res_fflags__h427324 ;
// inlined wires
assign csrf_minstret_ehr_data_lat_0$whas =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd31 ;
assign csrf_minstret_ehr_data_lat_1$whas =
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitNormalInst ;
assign csrf_minstret_ehr_data_dummy_1_0$whas =
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign csrf_mcycle_ehr_data_lat_0$wget = rob$deqPort_0_deq_data[95:32] ;
assign csrf_mcycle_ehr_data_lat_0$whas =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd30 ;
assign csrInstOrInterruptInflight_lat_1$whas =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__SEL_2 ;
assign mmio_dataReqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_dataReqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
assign mmio_dataRespQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
assign mmio_dataPendQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
assign mmio_cRqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_mmio_sendDataReq ?
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_cRqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
assign mmio_pRsQ_deqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendInstResp ||
WILL_FIRE_RL_mmio_sendDataResp ;
assign mmio_pRqQ_enqReq_lat_0$wget =
{ 1'd1,
mmioToPlatform_pRq_enq_x[38],
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266,
mmioToPlatform_pRq_enq_x[31:0] } ;
assign mmio_cRsQ_enqReq_lat_0$wget =
{ 1'd1, csrf_software_int_pend_vec_3 } ;
assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
coreFix_aluExe_0_exeToFinQ$first[16] ;
assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
coreFix_aluExe_1_exeToFinQ$first[16] ;
assign coreFix_aluExe_0_bypassWire_0$wget =
{ coreFix_aluExe_0_regToExeQ$first[348:342],
basicExec___d12516[321:258] } ;
assign coreFix_aluExe_0_bypassWire_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_1$wget =
{ coreFix_aluExe_1_regToExeQ$first[348:342],
basicExec___d11907[321:258] } ;
assign coreFix_aluExe_0_bypassWire_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_2$wget =
{ coreFix_aluExe_0_exeToFinQ$first[319:313],
coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_2$whas =
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[320] ;
assign coreFix_aluExe_0_bypassWire_3$wget =
{ coreFix_aluExe_1_exeToFinQ$first[319:313],
coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_3$whas =
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[320] ;
assign coreFix_aluExe_1_bypassWire_2$whas =
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[320] ;
assign coreFix_aluExe_1_bypassWire_3$whas =
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[320] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[320] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[320] ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] != 2'd1 ;
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
2'd0, 2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_memExe_bypassWire_2$whas =
_dor1coreFix_memExe_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[320] ;
assign coreFix_memExe_bypassWire_3$whas =
_dor1coreFix_memExe_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[320] ;
assign coreFix_memExe_issueLd$wget =
{ coreFix_memExe_dTlb$procResp[89:85],
coreFix_memExe_dTlb$procResp[174:111],
coreFix_memExe_dTlb$procResp[84:77] } ;
assign coreFix_memExe_issueLd$whas =
WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
coreFix_memExe_dTlb$procResp[105:103] == 3'd0 &&
NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 &&
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 &&
!coreFix_memExe_lsq$updateAddr ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
coreFix_memExe_issueLd$wget[76:8] :
coreFix_memExe_lsq$getIssueLd[76:8] ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_full_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
{ coreFix_memExe_stb$issue[635:576], 6'd0 } ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_sendStToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_sendStToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
{ 1'd1, dCacheToParent_fromP_enq_x } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645 ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// register commitStage_commitTrap
assign commitStage_commitTrap$D_IN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_commitStage_commitTrap$write_1__VAL_2 ;
assign commitStage_commitTrap$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
// register commitStage_rg_instret
assign commitStage_rg_instret$D_IN =
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
MUX_commitStage_rg_instret$write_1__VAL_1 :
MUX_commitStage_rg_instret$write_1__VAL_2 ;
assign commitStage_rg_instret$EN = csrf_minstret_ehr_data_lat_1$whas ;
// register coreFix_doStatsReg
assign coreFix_doStatsReg$D_IN = 1'b0 ;
assign coreFix_doStatsReg$EN = 1'b0 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
v__h602945 :
v__h601904 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11056[127:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11043[127:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11049[127:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN =
1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd2 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd4 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd5 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd6 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
_theResult_____2__h294593 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
v__h294013 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
4'b0010 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
{ !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
_theResult_____2__h302589 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
v__h297358 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
_theResult_____2__h308583 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
v__h307872 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
73'h0AAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
{ x_addr__h312146,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 ||
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
_theResult_____2__h316437 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
v__h311748 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_data_0
assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_empty
assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923 ;
assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_full
assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907 ;
assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_clearReq_rl
assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_data_0
assign coreFix_memExe_forwardQ_data_0$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_0$EN =
coreFix_memExe_forwardQ_enqP == 1'd0 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ;
// register coreFix_memExe_forwardQ_data_1
assign coreFix_memExe_forwardQ_data_1$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_1$EN =
coreFix_memExe_forwardQ_enqP == 1'd1 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ;
// register coreFix_memExe_forwardQ_deqP
assign coreFix_memExe_forwardQ_deqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
_theResult_____2__h330006 ;
assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_deqReq_rl
assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_empty
assign coreFix_memExe_forwardQ_empty$D_IN =
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_forwardQ_clearReq_rl ||
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 &&
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768 ;
assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqP
assign coreFix_memExe_forwardQ_enqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
v__h329574 ;
assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqReq_rl
assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_full
assign coreFix_memExe_forwardQ_full$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755 ;
assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_clearReq_rl
assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_data_0
assign coreFix_memExe_memRespLdQ_data_0$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_0$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ;
// register coreFix_memExe_memRespLdQ_data_1
assign coreFix_memExe_memRespLdQ_data_1$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_1$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ;
// register coreFix_memExe_memRespLdQ_deqP
assign coreFix_memExe_memRespLdQ_deqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
_theResult_____2__h326781 ;
assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_deqReq_rl
assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_empty
assign coreFix_memExe_memRespLdQ_empty$D_IN =
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_memRespLdQ_clearReq_rl ||
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 &&
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674 ;
assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqP
assign coreFix_memExe_memRespLdQ_enqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
v__h326349 ;
assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqReq_rl
assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_full
assign coreFix_memExe_memRespLdQ_full$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661 ;
assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_data_0_rl
assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget :
coreFix_memExe_reqLdQ_data_0_rl ;
assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_empty_rl
assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
!coreFix_memExe_reqLdQ_empty_lat_0$whas &&
coreFix_memExe_reqLdQ_empty_rl ;
assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_full_rl
assign coreFix_memExe_reqLdQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
(coreFix_memExe_reqLdQ_full_lat_0$whas ||
coreFix_memExe_reqLdQ_full_rl) ;
assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
coreFix_memExe_reqLrScAmoQ_data_0_rl ;
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
!coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
coreFix_memExe_reqLrScAmoQ_empty_rl ;
assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_full_rl
assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
!CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
(coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
coreFix_memExe_reqLrScAmoQ_full_rl) ;
assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_data_0_rl
assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget :
coreFix_memExe_reqStQ_data_0_rl ;
assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_empty_rl
assign coreFix_memExe_reqStQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
!CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
coreFix_memExe_reqStQ_empty_rl ;
assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_full_rl
assign coreFix_memExe_reqStQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
coreFix_memExe_reqStQ_full_rl) ;
assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_data_0
assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
assign coreFix_memExe_respLrScAmoQ_data_0$EN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 ;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_empty
assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_respLrScAmoQ_clearReq_rl ||
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585 ;
assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_full
assign coreFix_memExe_respLrScAmoQ_full$D_IN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570 ;
assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;
// register coreFix_memExe_waitLrScAmoMMIOResp
always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// register csrInstOrInterruptInflight_rl
assign csrInstOrInterruptInflight_rl$D_IN =
csrInstOrInterruptInflight_lat_1$whas ?
1'd1 :
(MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
1'd0 :
csrInstOrInterruptInflight_rl) ;
assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;
// register csrf_debug_int_pend
assign csrf_debug_int_pend$D_IN =
MUX_csrf_debug_int_pend$write_1__SEL_1 ?
csrf_mcycle_ehr_data_lat_0$wget[14] :
setDEIP_v ;
assign csrf_debug_int_pend$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd29 ||
EN_setDEIP ;
// register csrf_external_int_en_vec_0
assign csrf_external_int_en_vec_0$D_IN =
csrf_mcycle_ehr_data_lat_0$wget[8] ;
assign csrf_external_int_en_vec_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22) ;
// register csrf_external_int_en_vec_1
assign csrf_external_int_en_vec_1$D_IN =
csrf_mcycle_ehr_data_lat_0$wget[9] ;
assign csrf_external_int_en_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22) ;
// register csrf_external_int_en_vec_3
assign csrf_external_int_en_vec_3$D_IN =
csrf_mcycle_ehr_data_lat_0$wget[11] ;
assign csrf_external_int_en_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22 ;
// register csrf_external_int_pend_vec_0
assign csrf_external_int_pend_vec_0$D_IN =
csrf_mcycle_ehr_data_lat_0$wget[8] ;
assign csrf_external_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
// register csrf_external_int_pend_vec_1
assign csrf_external_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
csrf_mcycle_ehr_data_lat_0$wget[9] :
setSEIP_v ;
assign csrf_external_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || EN_setSEIP ;
// register csrf_external_int_pend_vec_3
assign csrf_external_int_pend_vec_3$D_IN =
MUX_csrf_debug_int_pend$write_1__SEL_1 ?
csrf_mcycle_ehr_data_lat_0$wget[11] :
setMEIP_v ;
assign csrf_external_int_pend_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd29 ||
EN_setMEIP ;
// register csrf_fflags_reg
assign csrf_fflags_reg$D_IN =
MUX_csrf_fflags_reg$write_1__SEL_1 ?
csrf_mcycle_ehr_data_lat_0$wget[4:0] :
MUX_csrf_fflags_reg$write_1__VAL_2 ;
assign csrf_fflags_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd2) ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__4602_4603_OR__ETC___d14815 ;
// register csrf_frm_reg
assign csrf_frm_reg$D_IN =
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd1) ?
csrf_mcycle_ehr_data_lat_0$wget[2:0] :
csrf_mcycle_ehr_data_lat_0$wget[7:5] ;
assign csrf_frm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd2) ;
// register csrf_fs_reg
assign csrf_fs_reg$D_IN =
MUX_csrf_fs_reg$write_1__SEL_1 ?
MUX_csrf_fs_reg$write_1__VAL_1 :
2'b11 ;
assign csrf_fs_reg$EN =
MUX_csrf_fs_reg$write_1__SEL_1 ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__4602_4603_OR__ETC___d14815 ;
// register csrf_ie_vec_0
assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ;
assign csrf_ie_vec_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ;
// register csrf_ie_vec_1
assign csrf_ie_vec_1$D_IN =
MUX_csrf_ie_vec_1$write_1__SEL_1 &&
MUX_csrf_ie_vec_1$write_1__VAL_1 ;
assign csrf_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ;
// register csrf_ie_vec_3
assign csrf_ie_vec_3$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_1 &&
MUX_csrf_ie_vec_3$write_1__VAL_1 ;
assign csrf_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ;
// register csrf_mcause_code_reg
assign csrf_mcause_code_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
cause_code__h694327 :
csrf_mcycle_ehr_data_lat_0$wget[3:0] ;
assign csrf_mcause_code_reg$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd27 ;
// register csrf_mcause_interrupt_reg
assign csrf_mcause_interrupt_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
commitStage_commitTrap[4] :
csrf_mcycle_ehr_data_lat_0$wget[63] ;
assign csrf_mcause_interrupt_reg$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd27 ;
// register csrf_mcounteren_cy_reg
assign csrf_mcounteren_cy_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ;
assign csrf_mcounteren_cy_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd24 ;
// register csrf_mcounteren_ir_reg
assign csrf_mcounteren_ir_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[2] ;
assign csrf_mcounteren_ir_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd24 ;
// register csrf_mcounteren_tm_reg
assign csrf_mcounteren_tm_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1] ;
assign csrf_mcounteren_tm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd24 ;
// register csrf_mcycle_ehr_data_rl
assign csrf_mcycle_ehr_data_rl$D_IN = upd__h4956 ;
assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;
// register csrf_medeleg_13_11_reg
assign csrf_medeleg_13_11_reg$D_IN =
csrf_mcycle_ehr_data_lat_0$wget[13:11] ;
assign csrf_medeleg_13_11_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd20 ;
// register csrf_medeleg_15_reg
assign csrf_medeleg_15_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[15] ;
assign csrf_medeleg_15_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd20 ;
// register csrf_medeleg_9_0_reg
assign csrf_medeleg_9_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:0] ;
assign csrf_medeleg_9_0_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd20 ;
// register csrf_mepc_csr
assign csrf_mepc_csr$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
commitStage_commitTrap[132:69] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_mepc_csr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd26 ;
// register csrf_mideleg_11_reg
assign csrf_mideleg_11_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[11] ;
assign csrf_mideleg_11_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd21 ;
// register csrf_mideleg_1_0_reg
assign csrf_mideleg_1_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1:0] ;
assign csrf_mideleg_1_0_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd21 ;
// register csrf_mideleg_5_3_reg
assign csrf_mideleg_5_3_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[5:3] ;
assign csrf_mideleg_5_3_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd21 ;
// register csrf_mideleg_9_7_reg
assign csrf_mideleg_9_7_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:7] ;
assign csrf_mideleg_9_7_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd21 ;
// register csrf_minstret_ehr_data_rl
assign csrf_minstret_ehr_data_rl$D_IN =
csrf_minstret_ehr_data_lat_1$whas ?
upd__h3639 :
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;
// register csrf_mpp_reg
assign csrf_mpp_reg$D_IN =
MUX_csrf_mpp_reg$write_1__SEL_1 ?
MUX_csrf_mpp_reg$write_1__VAL_1 :
csrf_prv_reg ;
assign csrf_mpp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ;
// register csrf_mprv_reg
assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ;
assign csrf_mprv_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18 ;
// register csrf_mscratch_csr
assign csrf_mscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ;
assign csrf_mscratch_csr$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd25 ;
// register csrf_mtval_csr
assign csrf_mtval_csr$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
MUX_csrf_mtval_csr$write_1__VAL_1 :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_mtval_csr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd28 ;
// register csrf_mtvec_base_hi_reg
assign csrf_mtvec_base_hi_reg$D_IN = csrf_mscratch_csr$D_IN[63:2] ;
assign csrf_mtvec_base_hi_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd23 ;
// register csrf_mtvec_mode_low_reg
assign csrf_mtvec_mode_low_reg$D_IN = csrf_mscratch_csr$D_IN[0] ;
assign csrf_mtvec_mode_low_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd23 ;
// register csrf_mxr_reg
assign csrf_mxr_reg$D_IN = csrf_mscratch_csr$D_IN[19] ;
assign csrf_mxr_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ;
// register csrf_ppn_reg
assign csrf_ppn_reg$D_IN = csrf_mscratch_csr$D_IN[43:0] ;
assign csrf_ppn_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd17 ;
// register csrf_prev_ie_vec_0
assign csrf_prev_ie_vec_0$D_IN = csrf_mscratch_csr$D_IN[4] ;
assign csrf_prev_ie_vec_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ;
// register csrf_prev_ie_vec_1
assign csrf_prev_ie_vec_1$D_IN =
MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ?
MUX_csrf_prev_ie_vec_1$write_1__VAL_1 :
csrf_ie_vec_1 ;
assign csrf_prev_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ;
// register csrf_prev_ie_vec_3
assign csrf_prev_ie_vec_3$D_IN =
MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ?
MUX_csrf_prev_ie_vec_3$write_1__VAL_1 :
csrf_ie_vec_3 ;
assign csrf_prev_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 ;
// register csrf_prv_reg
assign csrf_prv_reg$D_IN =
MUX_csrf_prv_reg$write_1__SEL_1 ?
MUX_csrf_prv_reg$write_1__VAL_1 :
MUX_csrf_prv_reg$write_1__VAL_2 ;
assign csrf_prv_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
// register csrf_scause_code_reg
assign csrf_scause_code_reg$D_IN =
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
cause_code__h694327 :
csrf_mscratch_csr$D_IN[3:0] ;
assign csrf_scause_code_reg$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd14 ;
// register csrf_scause_interrupt_reg
assign csrf_scause_interrupt_reg$D_IN =
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
commitStage_commitTrap[4] :
csrf_mscratch_csr$D_IN[63] ;
assign csrf_scause_interrupt_reg$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd14 ;
// register csrf_scounteren_cy_reg
assign csrf_scounteren_cy_reg$D_IN = csrf_mscratch_csr$D_IN[0] ;
assign csrf_scounteren_cy_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd11 ;
// register csrf_scounteren_ir_reg
assign csrf_scounteren_ir_reg$D_IN = csrf_mscratch_csr$D_IN[2] ;
assign csrf_scounteren_ir_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd11 ;
// register csrf_scounteren_tm_reg
assign csrf_scounteren_tm_reg$D_IN = csrf_mscratch_csr$D_IN[1] ;
assign csrf_scounteren_tm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd11 ;
// register csrf_sepc_csr
assign csrf_sepc_csr$D_IN =
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
commitStage_commitTrap[132:69] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_sepc_csr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd13 ;
// register csrf_software_int_en_vec_0
assign csrf_software_int_en_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ;
assign csrf_software_int_en_vec_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22) ;
// register csrf_software_int_en_vec_1
assign csrf_software_int_en_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ;
assign csrf_software_int_en_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22) ;
// register csrf_software_int_en_vec_3
assign csrf_software_int_en_vec_3$D_IN = csrf_mscratch_csr$D_IN[3] ;
assign csrf_software_int_en_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22 ;
// register csrf_software_int_pend_vec_0
assign csrf_software_int_pend_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ;
assign csrf_software_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
// register csrf_software_int_pend_vec_1
assign csrf_software_int_pend_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ;
assign csrf_software_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
// register csrf_software_int_pend_vec_3
assign csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_debug_int_pend$write_1__SEL_1 ?
csrf_mscratch_csr$D_IN[3] :
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 ;
assign csrf_software_int_pend_vec_3$EN =
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd29 ;
// register csrf_spp_reg
assign csrf_spp_reg$D_IN =
MUX_csrf_spp_reg$write_1__SEL_1 ?
MUX_csrf_spp_reg$write_1__VAL_1 :
csrf_prv_reg[0] ;
assign csrf_spp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ;
// register csrf_sscratch_csr
assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ;
assign csrf_sscratch_csr$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd12 ;
// register csrf_stats_module_doStats
assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
assign csrf_stats_module_doStats$EN = EN_recvDoStats ;
// register csrf_stval_csr
assign csrf_stval_csr$D_IN =
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
MUX_csrf_mtval_csr$write_1__VAL_1 :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_stval_csr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd15 ;
// register csrf_stvec_base_hi_reg
assign csrf_stvec_base_hi_reg$D_IN = csrf_sscratch_csr$D_IN[63:2] ;
assign csrf_stvec_base_hi_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd10 ;
// register csrf_stvec_mode_low_reg
assign csrf_stvec_mode_low_reg$D_IN = csrf_sscratch_csr$D_IN[0] ;
assign csrf_stvec_mode_low_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd10 ;
// register csrf_sum_reg
assign csrf_sum_reg$D_IN = csrf_sscratch_csr$D_IN[18] ;
assign csrf_sum_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ;
// register csrf_time_reg
assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;
// register csrf_timer_int_en_vec_0
assign csrf_timer_int_en_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ;
assign csrf_timer_int_en_vec_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22) ;
// register csrf_timer_int_en_vec_1
assign csrf_timer_int_en_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ;
assign csrf_timer_int_en_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22) ;
// register csrf_timer_int_en_vec_3
assign csrf_timer_int_en_vec_3$D_IN = csrf_sscratch_csr$D_IN[7] ;
assign csrf_timer_int_en_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd22 ;
// register csrf_timer_int_pend_vec_0
assign csrf_timer_int_pend_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ;
assign csrf_timer_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
// register csrf_timer_int_pend_vec_1
assign csrf_timer_int_pend_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ;
assign csrf_timer_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
// register csrf_timer_int_pend_vec_3
assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
assign csrf_timer_int_pend_vec_3$EN =
WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] == 2'd2 ;
// register csrf_tsr_reg
assign csrf_tsr_reg$D_IN = csrf_sscratch_csr$D_IN[22] ;
assign csrf_tsr_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18 ;
// register csrf_tvm_reg
assign csrf_tvm_reg$D_IN = csrf_sscratch_csr$D_IN[20] ;
assign csrf_tvm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18 ;
// register csrf_tw_reg
assign csrf_tw_reg$D_IN = csrf_sscratch_csr$D_IN[21] ;
assign csrf_tw_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18 ;
// register csrf_vm_mode_sv39_reg
assign csrf_vm_mode_sv39_reg$D_IN = csrf_sscratch_csr$D_IN[63] ;
assign csrf_vm_mode_sv39_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd17 ;
// register flush_reservation
assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ;
assign flush_reservation$EN =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
// register flush_tlbs
assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
assign flush_tlbs$EN =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd17) ;
// register mmio_cRqQ_clearReq_rl
assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_data_0
assign mmio_cRqQ_data_0$D_IN =
{ x__h45579,
(mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[72] :
mmio_cRqQ_enqReq_rl[72] } :
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[71:64] :
mmio_cRqQ_enqReq_rl[71:64],
x__h48115 } ;
assign mmio_cRqQ_data_0$EN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;
// register mmio_cRqQ_deqReq_rl
assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_empty
assign mmio_cRqQ_empty$D_IN =
mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
assign mmio_cRqQ_empty$EN = 1'd1 ;
// register mmio_cRqQ_enqReq_rl
assign mmio_cRqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_full
assign mmio_cRqQ_full$D_IN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
assign mmio_cRqQ_full$EN = 1'd1 ;
// register mmio_cRsQ_clearReq_rl
assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_data_0
assign mmio_cRsQ_data_0$D_IN =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[0] :
mmio_cRsQ_enqReq_rl[0] ;
assign mmio_cRsQ_data_0$EN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;
// register mmio_cRsQ_deqReq_rl
assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_empty
assign mmio_cRsQ_empty$D_IN =
mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
assign mmio_cRsQ_empty$EN = 1'd1 ;
// register mmio_cRsQ_enqReq_rl
assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_full
assign mmio_cRsQ_full$D_IN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
assign mmio_cRsQ_full$EN = 1'd1 ;
// register mmio_dataPendQ_clearReq_rl
assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_deqReq_rl
assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_empty
assign mmio_dataPendQ_empty$D_IN =
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataPendQ_clearReq_rl ||
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
assign mmio_dataPendQ_empty$EN = 1'd1 ;
// register mmio_dataPendQ_enqReq_rl
assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_full
assign mmio_dataPendQ_full$D_IN =
(!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataPendQ_clearReq_rl) &&
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
assign mmio_dataPendQ_full$EN = 1'd1 ;
// register mmio_dataReqQ_clearReq_rl
assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_data_0
assign mmio_dataReqQ_data_0$D_IN =
{ x__h17672,
(mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[72] :
mmio_dataReqQ_enqReq_rl[72] } :
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
mmio_dataReqQ_enqReq_rl[71:64],
x__h20210 } ;
assign mmio_dataReqQ_data_0$EN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;
// register mmio_dataReqQ_deqReq_rl
assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_empty
assign mmio_dataReqQ_empty$D_IN =
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataReqQ_clearReq_rl ||
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
assign mmio_dataReqQ_empty$EN = 1'd1 ;
// register mmio_dataReqQ_enqReq_rl
assign mmio_dataReqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_full
assign mmio_dataReqQ_full$D_IN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
assign mmio_dataReqQ_full$EN = 1'd1 ;
// register mmio_dataRespQ_clearReq_rl
assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_data_0
assign mmio_dataRespQ_data_0$D_IN =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
mmio_dataRespQ_enqReq_rl[64:0] ;
assign mmio_dataRespQ_data_0$EN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;
// register mmio_dataRespQ_deqReq_rl
assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_empty
assign mmio_dataRespQ_empty$D_IN =
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataRespQ_clearReq_rl ||
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
assign mmio_dataRespQ_empty$EN = 1'd1 ;
// register mmio_dataRespQ_enqReq_rl
assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_full
assign mmio_dataRespQ_full$D_IN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
assign mmio_dataRespQ_full$EN = 1'd1 ;
// register mmio_fromHostAddr
assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
assign mmio_fromHostAddr$EN = EN_coreReq_start ;
// register mmio_pRqQ_clearReq_rl
assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_data_0
assign mmio_pRqQ_data_0$D_IN =
{ EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[38] :
mmio_pRqQ_enqReq_rl[38],
(EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
{ 5'd2,
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[32] :
mmio_pRqQ_enqReq_rl[32] } :
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
x_data__h65373 } ;
assign mmio_pRqQ_data_0$EN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;
// register mmio_pRqQ_deqReq_rl
assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_empty
assign mmio_pRqQ_empty$D_IN =
mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
assign mmio_pRqQ_empty$EN = 1'd1 ;
// register mmio_pRqQ_enqReq_rl
assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_full
assign mmio_pRqQ_full$D_IN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
assign mmio_pRqQ_full$EN = 1'd1 ;
// register mmio_pRsQ_clearReq_rl
assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_data_0
assign mmio_pRsQ_data_0$D_IN =
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[66] :
mmio_pRsQ_enqReq_rl[66],
IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
assign mmio_pRsQ_data_0$EN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;
// register mmio_pRsQ_deqReq_rl
assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_empty
assign mmio_pRsQ_empty$D_IN =
mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
assign mmio_pRsQ_empty$EN = 1'd1 ;
// register mmio_pRsQ_enqReq_rl
assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_full
assign mmio_pRsQ_full$D_IN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
assign mmio_pRsQ_full$EN = 1'd1 ;
// register mmio_toHostAddr
assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
assign mmio_toHostAddr$EN = EN_coreReq_start ;
// register outOfReset
assign outOfReset$D_IN = 1'd1 ;
assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;
// register started
assign started$D_IN = 1'd1 ;
assign started$EN = EN_coreReq_start ;
// register update_vm_info
assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_1 ;
assign update_vm_info$EN =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
// submodule coreFix_aluExe_0_dispToRegQ
assign coreFix_aluExe_0_dispToRegQ$enq_x =
{ coreFix_aluExe_0_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268,
coreFix_aluExe_0_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269,
coreFix_aluExe_0_rsAlu$dispatchData[122:90],
coreFix_aluExe_0_rsAlu$dispatchData[65:21],
coreFix_aluExe_0_rsAlu$dispatchData[89:66],
coreFix_aluExe_0_rsAlu$dispatchData[8:4],
coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_exeToFinQ
assign coreFix_aluExe_0_exeToFinQ$enq_x =
{ coreFix_aluExe_0_regToExeQ$first[421:417],
coreFix_aluExe_0_regToExeQ$first[349:305],
basicExec___d12516[321:258],
coreFix_aluExe_0_regToExeQ$first[395],
basicExec___d12516[257:194],
basicExec___d12516[129:0],
coreFix_aluExe_0_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_regToExeQ
assign coreFix_aluExe_0_regToExeQ$enq_x =
{ coreFix_aluExe_0_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271,
coreFix_aluExe_0_dispToRegQ$first[131],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272,
coreFix_aluExe_0_dispToRegQ$first[118:86],
coreFix_aluExe_0_dispToRegQ$first[61:17],
x__h636394,
x__h636395,
rob$getOrigPC_0_get,
rob$getOrigPredPC_0_get,
rob$getOrig_Inst_0_get,
coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_rsAlu
assign coreFix_aluExe_0_rsAlu$enq_x =
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
{ 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
{ 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
{ 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] == 3'd0 ;
assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_dispToRegQ
assign coreFix_aluExe_1_dispToRegQ$enq_x =
{ coreFix_aluExe_1_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274,
coreFix_aluExe_1_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275,
coreFix_aluExe_1_rsAlu$dispatchData[122:90],
coreFix_aluExe_1_rsAlu$dispatchData[65:21],
coreFix_aluExe_1_rsAlu$dispatchData[89:66],
coreFix_aluExe_1_rsAlu$dispatchData[8:4],
coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_exeToFinQ
assign coreFix_aluExe_1_exeToFinQ$enq_x =
{ coreFix_aluExe_1_regToExeQ$first[421:417],
coreFix_aluExe_1_regToExeQ$first[349:305],
basicExec___d11907[321:258],
coreFix_aluExe_1_regToExeQ$first[395],
basicExec___d11907[257:194],
basicExec___d11907[129:0],
coreFix_aluExe_1_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_regToExeQ
assign coreFix_aluExe_1_regToExeQ$enq_x =
{ coreFix_aluExe_1_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277,
coreFix_aluExe_1_dispToRegQ$first[131],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278,
coreFix_aluExe_1_dispToRegQ$first[118:86],
coreFix_aluExe_1_dispToRegQ$first[61:17],
x__h615173,
x__h615174,
rob$getOrigPC_1_get,
rob$getOrigPredPC_1_get,
rob$getOrig_Inst_1_get,
coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_rsAlu
assign coreFix_aluExe_1_rsAlu$enq_x =
(k__h663183 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13884) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408,
fetchStage_pipelines_1_first__2661_BIT_173_340_ETC___d13484,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h677486,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
(k__h663183 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13884 ||
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13971 ==
1'd1 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13988) ;
assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684,
coreFix_fpuMulDivExe_0_regToExeQ$first[225],
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10821,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10857,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10905,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10947,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10989,
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9918,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
{ execFpuSimple___d11023,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN =
{ x__h601242,
b__h600706 == 64'd0,
a__h600705,
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
x__h601268,
a__h600705[63],
8'd0 } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR =
1'b0 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___snd__h601254 :
b__h600706 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR =
1'b0 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN =
{ x__h601842,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR = 1'b0 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1)
begin
case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
2'd0:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1[127:0];
2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1[127:0];
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1[127:0];
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;
// submodule coreFix_fpuMulDivExe_0_regToExeQ
assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284,
coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
x__h479736,
x__h479737,
x__h479738,
coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13896) ?
{ IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h677486,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13896 ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
regRenamingTable_rename_1_canRename__3354_AND__ETC___d14028) ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
{ x__h285351,
x__h285363,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824,
x__h287217,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
x__h283918 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
3'd0) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
3'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
3'd3 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
3'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
55'h15555555555555 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
EN_dCacheToParent_fromP_enq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
MUX_flush_reservation$write_1__SEL_1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
2'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
{ !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
4'b1010 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd0;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd1;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'b0 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rqToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rsToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dTlb
assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
assign coreFix_memExe_dTlb$procReq_req =
{ coreFix_memExe_regToExeQ$first[192:190],
coreFix_memExe_regToExeQ$first[157:140],
coreFix_memExe_lsq$getOrigBE << vaddr__h181361[2:0],
vaddr__h181361,
coreFix_memExe_lsq$getOrigBE[7] ?
vaddr__h181361[2:0] != 3'd0 :
(coreFix_memExe_lsq$getOrigBE[3] ?
vaddr__h181361[1:0] != 2'd0 :
coreFix_memExe_lsq$getOrigBE[1] && vaddr__h181361[0]),
coreFix_memExe_regToExeQ$first[11:0] } ;
assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
{ l2Tlb$toChildren_rsToC_first[80:0],
l2Tlb$toChildren_rsToC_first[82:81] } ;
assign coreFix_memExe_dTlb$updateVMInfo_vm =
{ prv__h709324,
prv__h709324 != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ;
assign coreFix_memExe_dTlb$EN_updateVMInfo =
MUX_update_vm_info$write_1__SEL_1 ;
assign coreFix_memExe_dTlb$EN_procReq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_dTlb$EN_deqProcResp =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
CAN_FIRE_RL_sendRsToDTlb ;
assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut ;
assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;
// submodule coreFix_memExe_dispToRegQ
assign coreFix_memExe_dispToRegQ$enq_x =
{ coreFix_memExe_rsMem$dispatchData[106:72],
coreFix_memExe_rsMem$dispatchData[65:21],
coreFix_memExe_rsMem$dispatchData[71:66],
coreFix_memExe_rsMem$dispatchData[20:9] } ;
assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_lsq
assign coreFix_memExe_lsq$enqLd_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqLd_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqLd_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqLd_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h677486 ;
assign coreFix_memExe_lsq$enqSt_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqSt_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqSt_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqSt_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h677486 ;
assign coreFix_memExe_lsq$getHit_t =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 :
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ;
assign coreFix_memExe_lsq$getOrigBE_t =
coreFix_memExe_regToExeQ$first[145:140] ;
assign coreFix_memExe_lsq$issueLd_lsqTag =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[76:72] :
coreFix_memExe_issueLd$wget[76:72] ;
assign coreFix_memExe_lsq$issueLd_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_lsq$issueLd_sbRes =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
coreFix_memExe_stb$search ;
assign coreFix_memExe_lsq$issueLd_shiftedBE =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_lsq$respLd_alignedData =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
assign coreFix_memExe_lsq$respLd_t =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
assign coreFix_memExe_lsq$setAtCommit_0_put =
rob$deqPort_0_deq_data[24:19] ;
assign coreFix_memExe_lsq$setAtCommit_1_put =
rob$deqPort_1_deq_data[24:19] ;
assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_lsq$updateAddr_fault =
{ (!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
coreFix_memExe_dTlb$procResp[12] :
coreFix_memExe_dTlb$procResp[12] ||
coreFix_memExe_dTlb$procResp[110],
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857 } ;
assign coreFix_memExe_lsq$updateAddr_isMMIO =
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 ;
assign coreFix_memExe_lsq$updateAddr_lsqTag =
coreFix_memExe_dTlb$procResp[90:85] ;
assign coreFix_memExe_lsq$updateAddr_paddr =
coreFix_memExe_dTlb$procResp[174:111] ;
assign coreFix_memExe_lsq$updateAddr_shiftedBE =
coreFix_memExe_dTlb$procResp[84:77] ;
assign coreFix_memExe_lsq$updateData_d =
(coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
coreFix_memExe_regToExeQ$first[75:12] :
shiftData__h181366 ;
assign coreFix_memExe_lsq$updateData_t =
coreFix_memExe_regToExeQ$first[143:140] ;
assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_lsq$EN_enqLd =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
assign coreFix_memExe_lsq$EN_enqSt =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
assign coreFix_memExe_lsq$EN_getHit =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign coreFix_memExe_lsq$EN_updateData =
WILL_FIRE_RL_coreFix_memExe_doExeMem &&
coreFix_memExe_regToExeQ$first[145] ;
assign coreFix_memExe_lsq$EN_updateAddr =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_lsq$EN_issueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign coreFix_memExe_lsq$EN_getIssueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
assign coreFix_memExe_lsq$EN_respLd =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
assign coreFix_memExe_lsq$EN_deqLd =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign coreFix_memExe_lsq$EN_deqSt =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_regToExeQ
assign coreFix_memExe_regToExeQ$enq_x =
{ coreFix_memExe_dispToRegQ$first[97:63],
coreFix_memExe_dispToRegQ$first[29:12],
x__h181275,
x__h181276,
coreFix_memExe_dispToRegQ$first[11:0] } ;
assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_regToExeQ$EN_deq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_full_dummy2_0
assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_full_dummy2_1
assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_full_dummy2_2
assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_rsMem
assign coreFix_memExe_rsMem$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13902) ?
{ fetchStage$pipelines_0_first[191:189],
IF_fetchStage_pipelines_0_first__2652_BIT_160__ETC___d13918,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[191:189],
IF_fetchStage_pipelines_1_first__2661_BIT_160__ETC___d14045,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h677486,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_memExe_rsMem$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_memExe_rsMem$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_memExe_rsMem$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_memExe_rsMem$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
assign coreFix_memExe_rsMem$EN_doDispatch =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_stb
assign coreFix_memExe_stb$deq_idx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$getEnqIndex_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
assign coreFix_memExe_stb$noMatchLdQ_paddr =
coreFix_memExe_lsq$firstLd[80:17] ;
assign coreFix_memExe_stb$noMatchStQ_be =
coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$noMatchStQ_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$search_be =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_stb$search_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_stb$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
assign coreFix_memExe_stb$EN_deq =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_trainBPQ_0
assign coreFix_trainBPQ_0$D_IN =
MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
assign coreFix_trainBPQ_0$ENQ =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign coreFix_trainBPQ_0$CLR = 1'b0 ;
// submodule coreFix_trainBPQ_1
assign coreFix_trainBPQ_1$D_IN =
MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
assign coreFix_trainBPQ_1$ENQ =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
assign coreFix_trainBPQ_1$CLR = 1'b0 ;
// submodule csrInstOrInterruptInflight_dummy2_0
assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap[4] ;
// submodule csrInstOrInterruptInflight_dummy2_1
assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_1$EN =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__SEL_2 ;
// submodule csrf_mcycle_ehr_data_dummy2_0
assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_0$EN = csrf_mcycle_ehr_data_lat_0$whas ;
// submodule csrf_mcycle_ehr_data_dummy2_1
assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;
// submodule csrf_minstret_ehr_data_dummy2_0
assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_0$EN =
csrf_minstret_ehr_data_lat_0$whas ;
// submodule csrf_minstret_ehr_data_dummy2_1
assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_1$EN =
csrf_minstret_ehr_data_dummy_1_0$whas ;
// submodule csrf_stats_module_writeQ
assign csrf_stats_module_writeQ$D_IN = csrf_sscratch_csr$D_IN[0] ;
assign csrf_stats_module_writeQ$ENQ =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd7 ;
assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
assign csrf_stats_module_writeQ$CLR = 1'b0 ;
// submodule csrf_terminate_module_terminateQ
assign csrf_terminate_module_terminateQ$ENQ =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd6 ;
assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;
// submodule epochManager
assign epochManager$checkEpoch_0_check_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$checkEpoch_1_check_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$updatePrevEpoch_0_update_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$updatePrevEpoch_1_update_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$EN_updatePrevEpoch_0_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign epochManager$EN_updatePrevEpoch_1_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13985 &&
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 ;
assign epochManager$EN_incrementEpoch =
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
// submodule fetchStage
assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
iCacheToParent_fromP_enq_x ;
assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
l2Tlb$toChildren_rsToC_first[80:0] ;
assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_updateVMInfo_vm =
{ csrf_prv_reg,
csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
coreReq_start_fromHostAddr ;
assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
assign fetchStage$perf_req_r = 2'h0 ;
assign fetchStage$perf_setStatus_doStats = 1'b0 ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
WILL_FIRE_RL_commitStage_doCommitKilledLd or
rob$deqPort_0_deq_data or
WILL_FIRE_RL_commitStage_doCommitTrap_handle or
MUX_fetchStage$redirect_1__VAL_4 or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
MUX_fetchStage$redirect_1__VAL_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
WILL_FIRE_RL_commitStage_doCommitKilledLd:
fetchStage$redirect_pc = rob$deqPort_0_deq_data[282:219];
WILL_FIRE_RL_commitStage_doCommitTrap_handle:
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_4;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_5;
default: fetchStage$redirect_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fetchStage$start_pc = coreReq_start_startpc ;
assign fetchStage$train_predictors_dpTrain =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[24:1] :
coreFix_trainBPQ_0$D_OUT[24:1] ;
assign fetchStage$train_predictors_iType =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[30:26] :
coreFix_trainBPQ_0$D_OUT[30:26] ;
assign fetchStage$train_predictors_mispred =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[0] :
coreFix_trainBPQ_0$D_OUT[0] ;
assign fetchStage$train_predictors_next_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[94:31] :
coreFix_trainBPQ_0$D_OUT[94:31] ;
assign fetchStage$train_predictors_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[158:95] :
coreFix_trainBPQ_0$D_OUT[158:95] ;
assign fetchStage$train_predictors_taken =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[25] :
coreFix_trainBPQ_0$D_OUT[25] ;
assign fetchStage$EN_pipelines_0_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_pipelines_1_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13985 &&
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 ;
assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ;
assign fetchStage$EN_iTlbIfc_updateVMInfo =
MUX_update_vm_info$write_1__SEL_1 ;
assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
CAN_FIRE_RL_sendRsToITlb ;
assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iMemIfc_flush = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
EN_iCacheToParent_rsToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
EN_iCacheToParent_rqToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
EN_iCacheToParent_fromP_enq ;
assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
assign fetchStage$EN_start = EN_coreReq_start ;
assign fetchStage$EN_stop = 1'b0 ;
assign fetchStage$EN_setWaitRedirect =
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_redirect =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
assign fetchStage$EN_train_predictors =
coreFix_trainBPQ_1$EMPTY_N ||
WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign fetchStage$EN_flush_predictors = 1'b0 ;
assign fetchStage$EN_perf_setStatus = 1'b0 ;
assign fetchStage$EN_perf_req = 1'b0 ;
assign fetchStage$EN_perf_resp = 1'b0 ;
// submodule l2Tlb
assign l2Tlb$perf_req_r = 4'h0 ;
assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
assign l2Tlb$toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq ?
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ;
assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ;
assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_1 ;
assign l2Tlb$EN_toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
assign l2Tlb$EN_toChildren_rsToC_deq =
WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut ;
assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
assign l2Tlb$EN_perf_setStatus = 1'b0 ;
assign l2Tlb$EN_perf_req = 1'b0 ;
assign l2Tlb$EN_perf_resp = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_0
assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_1
assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRqQ_deqReq_dummy2_0
assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;
// submodule mmio_cRqQ_deqReq_dummy2_1
assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_deqReq_dummy2_2
assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRqQ_enqReq_dummy2_0
assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_cRqQ_enqReq_dummy2_1
assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_enqReq_dummy2_2
assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_clearReq_dummy2_0
assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRsQ_clearReq_dummy2_1
assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRsQ_deqReq_dummy2_0
assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;
// submodule mmio_cRsQ_deqReq_dummy2_1
assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_deqReq_dummy2_2
assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_enqReq_dummy2_0
assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_cRsQ_enqReq_dummy2_1
assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_enqReq_dummy2_2
assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_clearReq_dummy2_0
assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataPendQ_clearReq_dummy2_1
assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataPendQ_deqReq_dummy2_0
assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataPendQ_deqReq_dummy2_1
assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_deqReq_dummy2_2
assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_enqReq_dummy2_0
assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_0$EN =
mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataPendQ_enqReq_dummy2_1
assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_enqReq_dummy2_2
assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_clearReq_dummy2_0
assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataReqQ_clearReq_dummy2_1
assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataReqQ_deqReq_dummy2_0
assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_dataReqQ_deqReq_dummy2_1
assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_deqReq_dummy2_2
assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_enqReq_dummy2_0
assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataReqQ_enqReq_dummy2_1
assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_enqReq_dummy2_2
assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_clearReq_dummy2_0
assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataRespQ_clearReq_dummy2_1
assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataRespQ_deqReq_dummy2_0
assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataRespQ_deqReq_dummy2_1
assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_deqReq_dummy2_2
assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_enqReq_dummy2_0
assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;
// submodule mmio_dataRespQ_enqReq_dummy2_1
assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_enqReq_dummy2_2
assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_clearReq_dummy2_0
assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRqQ_clearReq_dummy2_1
assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRqQ_deqReq_dummy2_0
assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_pRqQ_deqReq_dummy2_1
assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_deqReq_dummy2_2
assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_enqReq_dummy2_0
assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;
// submodule mmio_pRqQ_enqReq_dummy2_1
assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_enqReq_dummy2_2
assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_clearReq_dummy2_0
assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRsQ_clearReq_dummy2_1
assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRsQ_deqReq_dummy2_0
assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ;
// submodule mmio_pRsQ_deqReq_dummy2_1
assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_deqReq_dummy2_2
assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_enqReq_dummy2_0
assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;
// submodule mmio_pRsQ_enqReq_dummy2_1
assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_enqReq_dummy2_2
assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ
assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
assign perfReqQ$ENQ = EN_coreReq_perfReq ;
assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
assign perfReqQ$CLR = 1'b0 ;
// submodule regRenamingTable
assign regRenamingTable$rename_0_claimRename_r =
fetchStage$pipelines_0_first[95:69] ;
assign regRenamingTable$rename_0_claimRename_sb =
specTagManager$currentSpecBits ;
assign regRenamingTable$rename_0_getRename_r =
fetchStage$pipelines_0_first[95:69] ;
assign regRenamingTable$rename_1_claimRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$rename_1_claimRename_sb =
renaming_spec_bits__h677486 ;
assign regRenamingTable$rename_1_getRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$EN_rename_0_claimRename =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign regRenamingTable$EN_rename_1_claimRename =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign regRenamingTable$EN_commit_0_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign regRenamingTable$EN_commit_1_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 ;
assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule rf
assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign rf$read_0_rd3_rindx = 7'h0 ;
assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign rf$read_1_rd3_rindx = 7'h0 ;
assign rf$read_2_rd1_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign rf$read_2_rd2_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign rf$read_2_rd3_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
assign rf$read_3_rd3_rindx = 7'h0 ;
assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[319:313] ;
assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[319:313] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_rf$write_2_wr_2__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_rf$write_2_wr_2__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_rf$write_2_wr_2__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_rf$write_2_wr_2__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_rf$write_2_wr_2__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_data =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
default: rf$write_2_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_1 or
coreFix_memExe_respLrScAmoQ_data_0 or
MUX_rf$write_3_wr_1__SEL_2 or
mmio_dataRespQ_data_0 or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_2__VAL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_2__VAL_4 or
MUX_rf$write_3_wr_2__SEL_5 or coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_1:
rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
MUX_rf$write_3_wr_1__SEL_3:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_3;
MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
MUX_rf$write_3_wr_2__SEL_5:
rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
default: rf$write_3_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_5 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
coreFix_memExe_lsq$firstLd or
MUX_rf$write_3_wr_1__SEL_1 or
MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_5:
rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[71:65];
MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
assign rf$EN_write_0_wr =
_dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[320] ;
assign rf$EN_write_1_wr =
_dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[320] ;
assign rf$EN_write_2_wr =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign rf$EN_write_3_wr =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[72] ;
// submodule rob
always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
MUX_rob$enqPort_0_enq_1__VAL_1 or
WILL_FIRE_RL_renameStage_doRenaming_Trap or
MUX_rob$enqPort_0_enq_1__VAL_2 or
WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
MUX_rob$enqPort_0_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
WILL_FIRE_RL_renameStage_doRenaming_Trap:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
default: rob$enqPort_0_enq_x =
283'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rob$enqPort_1_enq_x =
{ fetchStage$pipelines_1_first[387:324],
fetchStage$pipelines_1_first[127:96],
fetchStage$pipelines_1_first[199:195],
fetchStage_pipelines_1_first__2661_BIT_173_340_ETC___d13484,
73'h1280000000000000000,
fetchStage$pipelines_1_first[323:260],
5'd0,
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74],
fetchStage$pipelines_1_first[194:192] != 3'd0 &&
fetchStage$pipelines_1_first[194:192] != 3'd1 &&
fetchStage$pipelines_1_first[194:192] != 3'd2 &&
fetchStage$pipelines_1_first[194:192] != 3'd3 &&
fetchStage$pipelines_1_first[194:192] != 3'd4,
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d14076 ||
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14039,
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d14086,
7'd32,
renaming_spec_bits__h677486 } ;
assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_2_get_x = 12'h0 ;
assign rob$getOrigPredPC_0_get_x =
coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPredPC_1_get_x =
coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
MUX_rob$setExecuted_deqLSQ_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
MUX_rob$setExecuted_deqLSQ_1__SEL_1 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem:
rob$setExecuted_deqLSQ_cause = 5'd10;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd21;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd23;
default: rob$setExecuted_deqLSQ_cause =
5'b01010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_deqLSQ_ld_killed =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
coreFix_memExe_lsq$firstLd[2:0] :
3'd2 ;
assign rob$setExecuted_deqLSQ_x =
(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
coreFix_memExe_lsq$firstLd[113:102] :
coreFix_memExe_lsq$firstSt[170:159] ;
assign rob$setExecuted_doFinishAlu_0_set_cf =
coreFix_aluExe_0_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_0_set_csrData =
coreFix_aluExe_0_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_0_set_x =
coreFix_aluExe_0_exeToFinQ$first[311:300] ;
assign rob$setExecuted_doFinishAlu_1_set_cf =
coreFix_aluExe_1_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_1_set_csrData =
coreFix_aluExe_1_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_1_set_x =
coreFix_aluExe_1_exeToFinQ$first[311:300] ;
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
5'b01010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_doFinishMem_access_at_commit =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 &&
(coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd4) ;
assign rob$setExecuted_doFinishMem_non_mmio_st_done =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 &&
NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 &&
coreFix_memExe_dTlb$procResp[105:103] == 3'd1 ;
assign rob$setExecuted_doFinishMem_vaddr =
coreFix_memExe_dTlb$procResp[76:13] ;
assign rob$setExecuted_doFinishMem_x =
coreFix_memExe_dTlb$procResp[102:91] ;
assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
assign rob$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_1_exeToFinQ$first[311:300];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_0_exeToFinQ$first[311:300];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign rob$EN_enqPort_0_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign rob$EN_enqPort_1_enq =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign rob$EN_deqPort_0_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign rob$EN_deqPort_1_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 ;
assign rob$EN_setLSQAtCommitNotified =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
assign rob$EN_setExecuted_deqLSQ =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ;
assign rob$EN_setExecuted_doFinishAlu_0_set =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishAlu_1_set =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign rob$EN_setExecuted_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign rob$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule sbAggr
assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
coreFix_memExe_lsq$getHit or
MUX_sbAggr$setReady_4_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
MUX_sbAggr$setReady_4_put_1__SEL_2:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbAggr$setReady_4_put_1__SEL_1:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbAggr$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbAggr$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign sbAggr$EN_setReady_3_put =
_dor1sbAggr$EN_setReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign sbAggr$EN_setReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
// submodule sbCons
assign sbCons$eagerLookup_0_get_r = 33'h0 ;
assign sbCons$eagerLookup_1_get_r = 33'h0 ;
assign sbCons$lazyLookup_0_get_r =
coreFix_aluExe_0_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_1_get_r =
coreFix_aluExe_1_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_2_get_r =
coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[319:313] ;
assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[319:313] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
coreFix_memExe_lsq$firstSt or
MUX_sbCons$setReady_3_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_sbCons$setReady_3_put_1__SEL_1:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
MUX_sbCons$setReady_3_put_1__SEL_2:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbCons$setReady_3_put_1__SEL_3:
sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[71:65];
default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbCons$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbCons$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbCons$EN_setReady_0_put =
_dor1sbCons$EN_setReady_0_put &&
coreFix_aluExe_0_exeToFinQ$first[320] ;
assign sbCons$EN_setReady_1_put =
_dor1sbCons$EN_setReady_1_put &&
coreFix_aluExe_1_exeToFinQ$first[320] ;
assign sbCons$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign sbCons$EN_setReady_3_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[72] ;
// submodule specTagManager
assign specTagManager$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 ;
assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign specTagManager$EN_claimSpecTag =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage_pipelines_0_canDeq__2650_AND_specTa_ETC___d13936 ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14063) ;
assign specTagManager$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;
// remaining internal signals
module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
.amoExec_current_data(curData__h190989),
.amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
.amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
.amoExec(n__h192527));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
3'd0 }),
.amoExec_current_data({ 63'd0,
msip__h75409 }),
.amoExec_in_data({ 32'd0, x__h75524 }),
.amoExec_upper_32_bits(1'd0),
.amoExec(amoExec___d880));
module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220,
{ coreFix_aluExe_1_regToExeQ$first[395],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221,
coreFix_aluExe_1_regToExeQ$first[382],
coreFix_aluExe_1_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]),
.basicExec(basicExec___d11907));
module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223,
{ coreFix_aluExe_0_regToExeQ$first[395],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224,
coreFix_aluExe_0_regToExeQ$first[382],
coreFix_aluExe_0_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]),
.basicExec(basicExec___d12516));
module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778,
{ { fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852 },
fetchStage$pipelines_0_first[160],
x_data_imm__h670087 } }),
.checkForException_regs({ fetchStage$pipelines_0_first[95],
fetchStage$pipelines_0_first[94:89],
{ fetchStage$pipelines_0_first[88],
fetchStage$pipelines_0_first[87:82] },
{ fetchStage$pipelines_0_first[81],
fetchStage$pipelines_0_first[80:76],
fetchStage$pipelines_0_first[75],
fetchStage$pipelines_0_first[74:69] } }),
.checkForException_csrState({ x_decodeInfo_frm__h651275,
r1__read_BITS_13_TO_12___h651460 !=
2'd0,
{ prv__h709280,
csrf_tvm_reg,
{ r1__read_BIT_20___h652088,
csrf_tsr_reg,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d12886));
module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408,
{ fetchStage_pipelines_1_first__2661_BIT_173_340_ETC___d13484,
fetchStage$pipelines_1_first[160],
x_data_imm__h684830 } }),
.checkForException_regs({ fetchStage$pipelines_1_first[95],
fetchStage$pipelines_1_first[94:89],
{ fetchStage$pipelines_1_first[88],
fetchStage$pipelines_1_first[87:82] },
{ fetchStage$pipelines_1_first[81],
fetchStage$pipelines_1_first[80:76],
fetchStage$pipelines_1_first[75],
fetchStage$pipelines_1_first[74:69] } }),
.checkForException_csrState({ x_decodeInfo_frm__h651275,
r1__read_BITS_13_TO_12___h651460 !=
2'd0,
{ prv__h709280,
csrf_tvm_reg,
{ r1__read_BIT_20___h652088,
csrf_tsr_reg,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d13505));
module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242,
coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
.execFpuSimple_rVal1(rVal1__h479827),
.execFpuSimple_rVal2(rVal2__h479828),
.execFpuSimple(execFpuSimple___d11023));
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ?
_theResult___snd__h352327 :
_theResult____h344153 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ?
_theResult___snd__h398017 :
_theResult____h389845 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ?
_theResult___snd__h443705 :
_theResult____h435533 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8878 ?
_theResult___snd__h509182 :
_theResult____h500883 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9588 ?
_theResult___snd__h587184 :
_theResult____h578885 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10351 ?
_theResult___snd__h547983 :
_theResult____h539684 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ?
_theResult___snd__h461471 :
_theResult____h453170 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ?
_theResult___snd__h370093 :
_theResult____h361792 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ?
_theResult___snd__h415783 :
_theResult____h407482 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ?
_theResult___snd__h452287 :
_theResult___snd__h470077 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ?
_theResult___snd__h360909 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ?
_theResult___snd__h360909 :
_theResult___snd__h378699 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ?
_theResult___snd__h406599 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ?
_theResult___snd__h406599 :
_theResult___snd__h424389 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ?
_theResult___snd__h452287 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8566 ?
_theResult___snd__h499531 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8928 ?
_theResult___snd__h499531 :
_theResult___snd__h517936 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9291 ?
_theResult___snd__h577533 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9638 ?
_theResult___snd__h577533 :
_theResult___snd__h595938 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10054 ?
_theResult___snd__h538332 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10401 ?
_theResult___snd__h538332 :
_theResult___snd__h556737 ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
((_theResult___fst_exp__h352264 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) :
((_theResult___fst_exp__h360920 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
((_theResult___fst_exp__h352264 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) :
((_theResult___fst_exp__h360920 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
((_theResult___fst_exp__h397954 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) :
((_theResult___fst_exp__h406610 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
((_theResult___fst_exp__h397954 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) :
((_theResult___fst_exp__h406610 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
((_theResult___fst_exp__h443642 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) :
((_theResult___fst_exp__h452298 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
((_theResult___fst_exp__h443642 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) :
((_theResult___fst_exp__h452298 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ;
assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10646 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10643) :
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9884 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881) :
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 =
(_theResult____h344153[56] ?
6'd0 :
(_theResult____h344153[55] ?
6'd1 :
(_theResult____h344153[54] ?
6'd2 :
(_theResult____h344153[53] ?
6'd3 :
(_theResult____h344153[52] ?
6'd4 :
(_theResult____h344153[51] ?
6'd5 :
(_theResult____h344153[50] ?
6'd6 :
(_theResult____h344153[49] ?
6'd7 :
(_theResult____h344153[48] ?
6'd8 :
(_theResult____h344153[47] ?
6'd9 :
(_theResult____h344153[46] ?
6'd10 :
(_theResult____h344153[45] ?
6'd11 :
(_theResult____h344153[44] ?
6'd12 :
(_theResult____h344153[43] ?
6'd13 :
(_theResult____h344153[42] ?
6'd14 :
(_theResult____h344153[41] ?
6'd15 :
(_theResult____h344153[40] ?
6'd16 :
(_theResult____h344153[39] ?
6'd17 :
(_theResult____h344153[38] ?
6'd18 :
(_theResult____h344153[37] ?
6'd19 :
(_theResult____h344153[36] ?
6'd20 :
(_theResult____h344153[35] ?
6'd21 :
(_theResult____h344153[34] ?
6'd22 :
(_theResult____h344153[33] ?
6'd23 :
(_theResult____h344153[32] ?
6'd24 :
(_theResult____h344153[31] ?
6'd25 :
(_theResult____h344153[30] ?
6'd26 :
(_theResult____h344153[29] ?
6'd27 :
(_theResult____h344153[28] ?
6'd28 :
(_theResult____h344153[27] ?
6'd29 :
(_theResult____h344153[26] ?
6'd30 :
(_theResult____h344153[25] ?
6'd31 :
(_theResult____h344153[24] ?
6'd32 :
(_theResult____h344153[23] ?
6'd33 :
(_theResult____h344153[22] ?
6'd34 :
(_theResult____h344153[21] ?
6'd35 :
(_theResult____h344153[20] ?
6'd36 :
(_theResult____h344153[19] ?
6'd37 :
(_theResult____h344153[18] ?
6'd38 :
(_theResult____h344153[17] ?
6'd39 :
(_theResult____h344153[16] ?
6'd40 :
(_theResult____h344153[15] ?
6'd41 :
(_theResult____h344153[14] ?
6'd42 :
(_theResult____h344153[13] ?
6'd43 :
(_theResult____h344153[12] ?
6'd44 :
(_theResult____h344153[11] ?
6'd45 :
(_theResult____h344153[10] ?
6'd46 :
(_theResult____h344153[9] ?
6'd47 :
(_theResult____h344153[8] ?
6'd48 :
(_theResult____h344153[7] ?
6'd49 :
(_theResult____h344153[6] ?
6'd50 :
(_theResult____h344153[5] ?
6'd51 :
(_theResult____h344153[4] ?
6'd52 :
(_theResult____h344153[3] ?
6'd53 :
(_theResult____h344153[2] ?
6'd54 :
(_theResult____h344153[1] ?
6'd55 :
(_theResult____h344153[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 =
(_theResult____h389845[56] ?
6'd0 :
(_theResult____h389845[55] ?
6'd1 :
(_theResult____h389845[54] ?
6'd2 :
(_theResult____h389845[53] ?
6'd3 :
(_theResult____h389845[52] ?
6'd4 :
(_theResult____h389845[51] ?
6'd5 :
(_theResult____h389845[50] ?
6'd6 :
(_theResult____h389845[49] ?
6'd7 :
(_theResult____h389845[48] ?
6'd8 :
(_theResult____h389845[47] ?
6'd9 :
(_theResult____h389845[46] ?
6'd10 :
(_theResult____h389845[45] ?
6'd11 :
(_theResult____h389845[44] ?
6'd12 :
(_theResult____h389845[43] ?
6'd13 :
(_theResult____h389845[42] ?
6'd14 :
(_theResult____h389845[41] ?
6'd15 :
(_theResult____h389845[40] ?
6'd16 :
(_theResult____h389845[39] ?
6'd17 :
(_theResult____h389845[38] ?
6'd18 :
(_theResult____h389845[37] ?
6'd19 :
(_theResult____h389845[36] ?
6'd20 :
(_theResult____h389845[35] ?
6'd21 :
(_theResult____h389845[34] ?
6'd22 :
(_theResult____h389845[33] ?
6'd23 :
(_theResult____h389845[32] ?
6'd24 :
(_theResult____h389845[31] ?
6'd25 :
(_theResult____h389845[30] ?
6'd26 :
(_theResult____h389845[29] ?
6'd27 :
(_theResult____h389845[28] ?
6'd28 :
(_theResult____h389845[27] ?
6'd29 :
(_theResult____h389845[26] ?
6'd30 :
(_theResult____h389845[25] ?
6'd31 :
(_theResult____h389845[24] ?
6'd32 :
(_theResult____h389845[23] ?
6'd33 :
(_theResult____h389845[22] ?
6'd34 :
(_theResult____h389845[21] ?
6'd35 :
(_theResult____h389845[20] ?
6'd36 :
(_theResult____h389845[19] ?
6'd37 :
(_theResult____h389845[18] ?
6'd38 :
(_theResult____h389845[17] ?
6'd39 :
(_theResult____h389845[16] ?
6'd40 :
(_theResult____h389845[15] ?
6'd41 :
(_theResult____h389845[14] ?
6'd42 :
(_theResult____h389845[13] ?
6'd43 :
(_theResult____h389845[12] ?
6'd44 :
(_theResult____h389845[11] ?
6'd45 :
(_theResult____h389845[10] ?
6'd46 :
(_theResult____h389845[9] ?
6'd47 :
(_theResult____h389845[8] ?
6'd48 :
(_theResult____h389845[7] ?
6'd49 :
(_theResult____h389845[6] ?
6'd50 :
(_theResult____h389845[5] ?
6'd51 :
(_theResult____h389845[4] ?
6'd52 :
(_theResult____h389845[3] ?
6'd53 :
(_theResult____h389845[2] ?
6'd54 :
(_theResult____h389845[1] ?
6'd55 :
(_theResult____h389845[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 =
(_theResult____h435533[56] ?
6'd0 :
(_theResult____h435533[55] ?
6'd1 :
(_theResult____h435533[54] ?
6'd2 :
(_theResult____h435533[53] ?
6'd3 :
(_theResult____h435533[52] ?
6'd4 :
(_theResult____h435533[51] ?
6'd5 :
(_theResult____h435533[50] ?
6'd6 :
(_theResult____h435533[49] ?
6'd7 :
(_theResult____h435533[48] ?
6'd8 :
(_theResult____h435533[47] ?
6'd9 :
(_theResult____h435533[46] ?
6'd10 :
(_theResult____h435533[45] ?
6'd11 :
(_theResult____h435533[44] ?
6'd12 :
(_theResult____h435533[43] ?
6'd13 :
(_theResult____h435533[42] ?
6'd14 :
(_theResult____h435533[41] ?
6'd15 :
(_theResult____h435533[40] ?
6'd16 :
(_theResult____h435533[39] ?
6'd17 :
(_theResult____h435533[38] ?
6'd18 :
(_theResult____h435533[37] ?
6'd19 :
(_theResult____h435533[36] ?
6'd20 :
(_theResult____h435533[35] ?
6'd21 :
(_theResult____h435533[34] ?
6'd22 :
(_theResult____h435533[33] ?
6'd23 :
(_theResult____h435533[32] ?
6'd24 :
(_theResult____h435533[31] ?
6'd25 :
(_theResult____h435533[30] ?
6'd26 :
(_theResult____h435533[29] ?
6'd27 :
(_theResult____h435533[28] ?
6'd28 :
(_theResult____h435533[27] ?
6'd29 :
(_theResult____h435533[26] ?
6'd30 :
(_theResult____h435533[25] ?
6'd31 :
(_theResult____h435533[24] ?
6'd32 :
(_theResult____h435533[23] ?
6'd33 :
(_theResult____h435533[22] ?
6'd34 :
(_theResult____h435533[21] ?
6'd35 :
(_theResult____h435533[20] ?
6'd36 :
(_theResult____h435533[19] ?
6'd37 :
(_theResult____h435533[18] ?
6'd38 :
(_theResult____h435533[17] ?
6'd39 :
(_theResult____h435533[16] ?
6'd40 :
(_theResult____h435533[15] ?
6'd41 :
(_theResult____h435533[14] ?
6'd42 :
(_theResult____h435533[13] ?
6'd43 :
(_theResult____h435533[12] ?
6'd44 :
(_theResult____h435533[11] ?
6'd45 :
(_theResult____h435533[10] ?
6'd46 :
(_theResult____h435533[9] ?
6'd47 :
(_theResult____h435533[8] ?
6'd48 :
(_theResult____h435533[7] ?
6'd49 :
(_theResult____h435533[6] ?
6'd50 :
(_theResult____h435533[5] ?
6'd51 :
(_theResult____h435533[4] ?
6'd52 :
(_theResult____h435533[3] ?
6'd53 :
(_theResult____h435533[2] ?
6'd54 :
(_theResult____h435533[1] ?
6'd55 :
(_theResult____h435533[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10349 =
(_theResult____h539684[56] ?
6'd0 :
(_theResult____h539684[55] ?
6'd1 :
(_theResult____h539684[54] ?
6'd2 :
(_theResult____h539684[53] ?
6'd3 :
(_theResult____h539684[52] ?
6'd4 :
(_theResult____h539684[51] ?
6'd5 :
(_theResult____h539684[50] ?
6'd6 :
(_theResult____h539684[49] ?
6'd7 :
(_theResult____h539684[48] ?
6'd8 :
(_theResult____h539684[47] ?
6'd9 :
(_theResult____h539684[46] ?
6'd10 :
(_theResult____h539684[45] ?
6'd11 :
(_theResult____h539684[44] ?
6'd12 :
(_theResult____h539684[43] ?
6'd13 :
(_theResult____h539684[42] ?
6'd14 :
(_theResult____h539684[41] ?
6'd15 :
(_theResult____h539684[40] ?
6'd16 :
(_theResult____h539684[39] ?
6'd17 :
(_theResult____h539684[38] ?
6'd18 :
(_theResult____h539684[37] ?
6'd19 :
(_theResult____h539684[36] ?
6'd20 :
(_theResult____h539684[35] ?
6'd21 :
(_theResult____h539684[34] ?
6'd22 :
(_theResult____h539684[33] ?
6'd23 :
(_theResult____h539684[32] ?
6'd24 :
(_theResult____h539684[31] ?
6'd25 :
(_theResult____h539684[30] ?
6'd26 :
(_theResult____h539684[29] ?
6'd27 :
(_theResult____h539684[28] ?
6'd28 :
(_theResult____h539684[27] ?
6'd29 :
(_theResult____h539684[26] ?
6'd30 :
(_theResult____h539684[25] ?
6'd31 :
(_theResult____h539684[24] ?
6'd32 :
(_theResult____h539684[23] ?
6'd33 :
(_theResult____h539684[22] ?
6'd34 :
(_theResult____h539684[21] ?
6'd35 :
(_theResult____h539684[20] ?
6'd36 :
(_theResult____h539684[19] ?
6'd37 :
(_theResult____h539684[18] ?
6'd38 :
(_theResult____h539684[17] ?
6'd39 :
(_theResult____h539684[16] ?
6'd40 :
(_theResult____h539684[15] ?
6'd41 :
(_theResult____h539684[14] ?
6'd42 :
(_theResult____h539684[13] ?
6'd43 :
(_theResult____h539684[12] ?
6'd44 :
(_theResult____h539684[11] ?
6'd45 :
(_theResult____h539684[10] ?
6'd46 :
(_theResult____h539684[9] ?
6'd47 :
(_theResult____h539684[8] ?
6'd48 :
(_theResult____h539684[7] ?
6'd49 :
(_theResult____h539684[6] ?
6'd50 :
(_theResult____h539684[5] ?
6'd51 :
(_theResult____h539684[4] ?
6'd52 :
(_theResult____h539684[3] ?
6'd53 :
(_theResult____h539684[2] ?
6'd54 :
(_theResult____h539684[1] ?
6'd55 :
(_theResult____h539684[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8876 =
(_theResult____h500883[56] ?
6'd0 :
(_theResult____h500883[55] ?
6'd1 :
(_theResult____h500883[54] ?
6'd2 :
(_theResult____h500883[53] ?
6'd3 :
(_theResult____h500883[52] ?
6'd4 :
(_theResult____h500883[51] ?
6'd5 :
(_theResult____h500883[50] ?
6'd6 :
(_theResult____h500883[49] ?
6'd7 :
(_theResult____h500883[48] ?
6'd8 :
(_theResult____h500883[47] ?
6'd9 :
(_theResult____h500883[46] ?
6'd10 :
(_theResult____h500883[45] ?
6'd11 :
(_theResult____h500883[44] ?
6'd12 :
(_theResult____h500883[43] ?
6'd13 :
(_theResult____h500883[42] ?
6'd14 :
(_theResult____h500883[41] ?
6'd15 :
(_theResult____h500883[40] ?
6'd16 :
(_theResult____h500883[39] ?
6'd17 :
(_theResult____h500883[38] ?
6'd18 :
(_theResult____h500883[37] ?
6'd19 :
(_theResult____h500883[36] ?
6'd20 :
(_theResult____h500883[35] ?
6'd21 :
(_theResult____h500883[34] ?
6'd22 :
(_theResult____h500883[33] ?
6'd23 :
(_theResult____h500883[32] ?
6'd24 :
(_theResult____h500883[31] ?
6'd25 :
(_theResult____h500883[30] ?
6'd26 :
(_theResult____h500883[29] ?
6'd27 :
(_theResult____h500883[28] ?
6'd28 :
(_theResult____h500883[27] ?
6'd29 :
(_theResult____h500883[26] ?
6'd30 :
(_theResult____h500883[25] ?
6'd31 :
(_theResult____h500883[24] ?
6'd32 :
(_theResult____h500883[23] ?
6'd33 :
(_theResult____h500883[22] ?
6'd34 :
(_theResult____h500883[21] ?
6'd35 :
(_theResult____h500883[20] ?
6'd36 :
(_theResult____h500883[19] ?
6'd37 :
(_theResult____h500883[18] ?
6'd38 :
(_theResult____h500883[17] ?
6'd39 :
(_theResult____h500883[16] ?
6'd40 :
(_theResult____h500883[15] ?
6'd41 :
(_theResult____h500883[14] ?
6'd42 :
(_theResult____h500883[13] ?
6'd43 :
(_theResult____h500883[12] ?
6'd44 :
(_theResult____h500883[11] ?
6'd45 :
(_theResult____h500883[10] ?
6'd46 :
(_theResult____h500883[9] ?
6'd47 :
(_theResult____h500883[8] ?
6'd48 :
(_theResult____h500883[7] ?
6'd49 :
(_theResult____h500883[6] ?
6'd50 :
(_theResult____h500883[5] ?
6'd51 :
(_theResult____h500883[4] ?
6'd52 :
(_theResult____h500883[3] ?
6'd53 :
(_theResult____h500883[2] ?
6'd54 :
(_theResult____h500883[1] ?
6'd55 :
(_theResult____h500883[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9586 =
(_theResult____h578885[56] ?
6'd0 :
(_theResult____h578885[55] ?
6'd1 :
(_theResult____h578885[54] ?
6'd2 :
(_theResult____h578885[53] ?
6'd3 :
(_theResult____h578885[52] ?
6'd4 :
(_theResult____h578885[51] ?
6'd5 :
(_theResult____h578885[50] ?
6'd6 :
(_theResult____h578885[49] ?
6'd7 :
(_theResult____h578885[48] ?
6'd8 :
(_theResult____h578885[47] ?
6'd9 :
(_theResult____h578885[46] ?
6'd10 :
(_theResult____h578885[45] ?
6'd11 :
(_theResult____h578885[44] ?
6'd12 :
(_theResult____h578885[43] ?
6'd13 :
(_theResult____h578885[42] ?
6'd14 :
(_theResult____h578885[41] ?
6'd15 :
(_theResult____h578885[40] ?
6'd16 :
(_theResult____h578885[39] ?
6'd17 :
(_theResult____h578885[38] ?
6'd18 :
(_theResult____h578885[37] ?
6'd19 :
(_theResult____h578885[36] ?
6'd20 :
(_theResult____h578885[35] ?
6'd21 :
(_theResult____h578885[34] ?
6'd22 :
(_theResult____h578885[33] ?
6'd23 :
(_theResult____h578885[32] ?
6'd24 :
(_theResult____h578885[31] ?
6'd25 :
(_theResult____h578885[30] ?
6'd26 :
(_theResult____h578885[29] ?
6'd27 :
(_theResult____h578885[28] ?
6'd28 :
(_theResult____h578885[27] ?
6'd29 :
(_theResult____h578885[26] ?
6'd30 :
(_theResult____h578885[25] ?
6'd31 :
(_theResult____h578885[24] ?
6'd32 :
(_theResult____h578885[23] ?
6'd33 :
(_theResult____h578885[22] ?
6'd34 :
(_theResult____h578885[21] ?
6'd35 :
(_theResult____h578885[20] ?
6'd36 :
(_theResult____h578885[19] ?
6'd37 :
(_theResult____h578885[18] ?
6'd38 :
(_theResult____h578885[17] ?
6'd39 :
(_theResult____h578885[16] ?
6'd40 :
(_theResult____h578885[15] ?
6'd41 :
(_theResult____h578885[14] ?
6'd42 :
(_theResult____h578885[13] ?
6'd43 :
(_theResult____h578885[12] ?
6'd44 :
(_theResult____h578885[11] ?
6'd45 :
(_theResult____h578885[10] ?
6'd46 :
(_theResult____h578885[9] ?
6'd47 :
(_theResult____h578885[8] ?
6'd48 :
(_theResult____h578885[7] ?
6'd49 :
(_theResult____h578885[6] ?
6'd50 :
(_theResult____h578885[5] ?
6'd51 :
(_theResult____h578885[4] ?
6'd52 :
(_theResult____h578885[3] ?
6'd53 :
(_theResult____h578885[2] ?
6'd54 :
(_theResult____h578885[1] ?
6'd55 :
(_theResult____h578885[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 =
(_theResult____h361792[56] ?
6'd0 :
(_theResult____h361792[55] ?
6'd1 :
(_theResult____h361792[54] ?
6'd2 :
(_theResult____h361792[53] ?
6'd3 :
(_theResult____h361792[52] ?
6'd4 :
(_theResult____h361792[51] ?
6'd5 :
(_theResult____h361792[50] ?
6'd6 :
(_theResult____h361792[49] ?
6'd7 :
(_theResult____h361792[48] ?
6'd8 :
(_theResult____h361792[47] ?
6'd9 :
(_theResult____h361792[46] ?
6'd10 :
(_theResult____h361792[45] ?
6'd11 :
(_theResult____h361792[44] ?
6'd12 :
(_theResult____h361792[43] ?
6'd13 :
(_theResult____h361792[42] ?
6'd14 :
(_theResult____h361792[41] ?
6'd15 :
(_theResult____h361792[40] ?
6'd16 :
(_theResult____h361792[39] ?
6'd17 :
(_theResult____h361792[38] ?
6'd18 :
(_theResult____h361792[37] ?
6'd19 :
(_theResult____h361792[36] ?
6'd20 :
(_theResult____h361792[35] ?
6'd21 :
(_theResult____h361792[34] ?
6'd22 :
(_theResult____h361792[33] ?
6'd23 :
(_theResult____h361792[32] ?
6'd24 :
(_theResult____h361792[31] ?
6'd25 :
(_theResult____h361792[30] ?
6'd26 :
(_theResult____h361792[29] ?
6'd27 :
(_theResult____h361792[28] ?
6'd28 :
(_theResult____h361792[27] ?
6'd29 :
(_theResult____h361792[26] ?
6'd30 :
(_theResult____h361792[25] ?
6'd31 :
(_theResult____h361792[24] ?
6'd32 :
(_theResult____h361792[23] ?
6'd33 :
(_theResult____h361792[22] ?
6'd34 :
(_theResult____h361792[21] ?
6'd35 :
(_theResult____h361792[20] ?
6'd36 :
(_theResult____h361792[19] ?
6'd37 :
(_theResult____h361792[18] ?
6'd38 :
(_theResult____h361792[17] ?
6'd39 :
(_theResult____h361792[16] ?
6'd40 :
(_theResult____h361792[15] ?
6'd41 :
(_theResult____h361792[14] ?
6'd42 :
(_theResult____h361792[13] ?
6'd43 :
(_theResult____h361792[12] ?
6'd44 :
(_theResult____h361792[11] ?
6'd45 :
(_theResult____h361792[10] ?
6'd46 :
(_theResult____h361792[9] ?
6'd47 :
(_theResult____h361792[8] ?
6'd48 :
(_theResult____h361792[7] ?
6'd49 :
(_theResult____h361792[6] ?
6'd50 :
(_theResult____h361792[5] ?
6'd51 :
(_theResult____h361792[4] ?
6'd52 :
(_theResult____h361792[3] ?
6'd53 :
(_theResult____h361792[2] ?
6'd54 :
(_theResult____h361792[1] ?
6'd55 :
(_theResult____h361792[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 =
(_theResult____h407482[56] ?
6'd0 :
(_theResult____h407482[55] ?
6'd1 :
(_theResult____h407482[54] ?
6'd2 :
(_theResult____h407482[53] ?
6'd3 :
(_theResult____h407482[52] ?
6'd4 :
(_theResult____h407482[51] ?
6'd5 :
(_theResult____h407482[50] ?
6'd6 :
(_theResult____h407482[49] ?
6'd7 :
(_theResult____h407482[48] ?
6'd8 :
(_theResult____h407482[47] ?
6'd9 :
(_theResult____h407482[46] ?
6'd10 :
(_theResult____h407482[45] ?
6'd11 :
(_theResult____h407482[44] ?
6'd12 :
(_theResult____h407482[43] ?
6'd13 :
(_theResult____h407482[42] ?
6'd14 :
(_theResult____h407482[41] ?
6'd15 :
(_theResult____h407482[40] ?
6'd16 :
(_theResult____h407482[39] ?
6'd17 :
(_theResult____h407482[38] ?
6'd18 :
(_theResult____h407482[37] ?
6'd19 :
(_theResult____h407482[36] ?
6'd20 :
(_theResult____h407482[35] ?
6'd21 :
(_theResult____h407482[34] ?
6'd22 :
(_theResult____h407482[33] ?
6'd23 :
(_theResult____h407482[32] ?
6'd24 :
(_theResult____h407482[31] ?
6'd25 :
(_theResult____h407482[30] ?
6'd26 :
(_theResult____h407482[29] ?
6'd27 :
(_theResult____h407482[28] ?
6'd28 :
(_theResult____h407482[27] ?
6'd29 :
(_theResult____h407482[26] ?
6'd30 :
(_theResult____h407482[25] ?
6'd31 :
(_theResult____h407482[24] ?
6'd32 :
(_theResult____h407482[23] ?
6'd33 :
(_theResult____h407482[22] ?
6'd34 :
(_theResult____h407482[21] ?
6'd35 :
(_theResult____h407482[20] ?
6'd36 :
(_theResult____h407482[19] ?
6'd37 :
(_theResult____h407482[18] ?
6'd38 :
(_theResult____h407482[17] ?
6'd39 :
(_theResult____h407482[16] ?
6'd40 :
(_theResult____h407482[15] ?
6'd41 :
(_theResult____h407482[14] ?
6'd42 :
(_theResult____h407482[13] ?
6'd43 :
(_theResult____h407482[12] ?
6'd44 :
(_theResult____h407482[11] ?
6'd45 :
(_theResult____h407482[10] ?
6'd46 :
(_theResult____h407482[9] ?
6'd47 :
(_theResult____h407482[8] ?
6'd48 :
(_theResult____h407482[7] ?
6'd49 :
(_theResult____h407482[6] ?
6'd50 :
(_theResult____h407482[5] ?
6'd51 :
(_theResult____h407482[4] ?
6'd52 :
(_theResult____h407482[3] ?
6'd53 :
(_theResult____h407482[2] ?
6'd54 :
(_theResult____h407482[1] ?
6'd55 :
(_theResult____h407482[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 =
(_theResult____h453170[56] ?
6'd0 :
(_theResult____h453170[55] ?
6'd1 :
(_theResult____h453170[54] ?
6'd2 :
(_theResult____h453170[53] ?
6'd3 :
(_theResult____h453170[52] ?
6'd4 :
(_theResult____h453170[51] ?
6'd5 :
(_theResult____h453170[50] ?
6'd6 :
(_theResult____h453170[49] ?
6'd7 :
(_theResult____h453170[48] ?
6'd8 :
(_theResult____h453170[47] ?
6'd9 :
(_theResult____h453170[46] ?
6'd10 :
(_theResult____h453170[45] ?
6'd11 :
(_theResult____h453170[44] ?
6'd12 :
(_theResult____h453170[43] ?
6'd13 :
(_theResult____h453170[42] ?
6'd14 :
(_theResult____h453170[41] ?
6'd15 :
(_theResult____h453170[40] ?
6'd16 :
(_theResult____h453170[39] ?
6'd17 :
(_theResult____h453170[38] ?
6'd18 :
(_theResult____h453170[37] ?
6'd19 :
(_theResult____h453170[36] ?
6'd20 :
(_theResult____h453170[35] ?
6'd21 :
(_theResult____h453170[34] ?
6'd22 :
(_theResult____h453170[33] ?
6'd23 :
(_theResult____h453170[32] ?
6'd24 :
(_theResult____h453170[31] ?
6'd25 :
(_theResult____h453170[30] ?
6'd26 :
(_theResult____h453170[29] ?
6'd27 :
(_theResult____h453170[28] ?
6'd28 :
(_theResult____h453170[27] ?
6'd29 :
(_theResult____h453170[26] ?
6'd30 :
(_theResult____h453170[25] ?
6'd31 :
(_theResult____h453170[24] ?
6'd32 :
(_theResult____h453170[23] ?
6'd33 :
(_theResult____h453170[22] ?
6'd34 :
(_theResult____h453170[21] ?
6'd35 :
(_theResult____h453170[20] ?
6'd36 :
(_theResult____h453170[19] ?
6'd37 :
(_theResult____h453170[18] ?
6'd38 :
(_theResult____h453170[17] ?
6'd39 :
(_theResult____h453170[16] ?
6'd40 :
(_theResult____h453170[15] ?
6'd41 :
(_theResult____h453170[14] ?
6'd42 :
(_theResult____h453170[13] ?
6'd43 :
(_theResult____h453170[12] ?
6'd44 :
(_theResult____h453170[11] ?
6'd45 :
(_theResult____h453170[10] ?
6'd46 :
(_theResult____h453170[9] ?
6'd47 :
(_theResult____h453170[8] ?
6'd48 :
(_theResult____h453170[7] ?
6'd49 :
(_theResult____h453170[6] ?
6'd50 :
(_theResult____h453170[5] ?
6'd51 :
(_theResult____h453170[4] ?
6'd52 :
(_theResult____h453170[3] ?
6'd53 :
(_theResult____h453170[2] ?
6'd54 :
(_theResult____h453170[1] ?
6'd55 :
(_theResult____h453170[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10393 =
(_theResult___fst_exp__h547920 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39694_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ;
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10658 =
(_theResult___fst_exp__h547920 == 11'd2047) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39694_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ;
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8920 =
(_theResult___fst_exp__h509119 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard00893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ;
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9630 =
(_theResult___fst_exp__h587121 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ;
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9896 =
(_theResult___fst_exp__h587121 == 11'd2047) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 =
(guard__h344163 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h352264 :
_theResult___exp__h352780 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 =
(guard__h344163 == 2'b0) ?
_theResult___fst_exp__h352264 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h352780 :
_theResult___fst_exp__h352264) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 =
(guard__h344163 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h352258[56:34] :
_theResult___sfd__h352781 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 =
(guard__h344163 == 2'b0) ?
sfdin__h352258[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h352781 :
sfdin__h352258[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 =
(guard__h389855 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h397954 :
_theResult___exp__h398470 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 =
(guard__h389855 == 2'b0) ?
_theResult___fst_exp__h397954 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h398470 :
_theResult___fst_exp__h397954) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 =
(guard__h389855 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h397948[56:34] :
_theResult___sfd__h398471 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 =
(guard__h389855 == 2'b0) ?
sfdin__h397948[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h398471 :
sfdin__h397948[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 =
(guard__h435543 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h443642 :
_theResult___exp__h444158 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 =
(guard__h435543 == 2'b0) ?
_theResult___fst_exp__h443642 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h444158 :
_theResult___fst_exp__h443642) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 =
(guard__h435543 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h443636[56:34] :
_theResult___sfd__h444159 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 =
(guard__h435543 == 2'b0) ?
sfdin__h443636[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h444159 :
sfdin__h443636[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 =
(guard__h539694 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h547920 :
_theResult___exp__h548649 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 =
(guard__h539694 == 2'b0) ?
_theResult___fst_exp__h547920 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
_theResult___exp__h548649 :
_theResult___fst_exp__h547920) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10588 =
(guard__h539694 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
sfdin__h547914[56:5] :
_theResult___sfd__h548650 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10590 =
(guard__h539694 == 2'b0) ?
sfdin__h547914[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
_theResult___sfd__h548650 :
sfdin__h547914[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9037 =
(guard__h500893 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h509119 :
_theResult___exp__h509848 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9039 =
(guard__h500893 == 2'b0) ?
_theResult___fst_exp__h509119 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
_theResult___exp__h509848 :
_theResult___fst_exp__h509119) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9121 =
(guard__h500893 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
sfdin__h509113[56:5] :
_theResult___sfd__h509849 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9123 =
(guard__h500893 == 2'b0) ?
sfdin__h509113[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
_theResult___sfd__h509849 :
sfdin__h509113[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9742 =
(guard__h578895 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h587121 :
_theResult___exp__h587850 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9744 =
(guard__h578895 == 2'b0) ?
_theResult___fst_exp__h587121 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
_theResult___exp__h587850 :
_theResult___fst_exp__h587121) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9825 =
(guard__h578895 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
sfdin__h587115[56:5] :
_theResult___sfd__h587851 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9827 =
(guard__h578895 == 2'b0) ?
sfdin__h587115[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
_theResult___sfd__h587851 :
sfdin__h587115[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 =
(guard__h361802 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h370030 :
_theResult___exp__h370546 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 =
(guard__h361802 == 2'b0) ?
_theResult___fst_exp__h370030 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h370546 :
_theResult___fst_exp__h370030) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 =
(guard__h361802 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h370024[56:34] :
_theResult___sfd__h370547 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 =
(guard__h361802 == 2'b0) ?
sfdin__h370024[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h370547 :
sfdin__h370024[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 =
(guard__h407492 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h415720 :
_theResult___exp__h416236 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 =
(guard__h407492 == 2'b0) ?
_theResult___fst_exp__h415720 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h416236 :
_theResult___fst_exp__h415720) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 =
(guard__h407492 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h415714[56:34] :
_theResult___sfd__h416237 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 =
(guard__h407492 == 2'b0) ?
sfdin__h415714[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h416237 :
sfdin__h415714[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 =
(guard__h453180 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h461408 :
_theResult___exp__h461924 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 =
(guard__h453180 == 2'b0) ?
_theResult___fst_exp__h461408 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h461924 :
_theResult___fst_exp__h461408) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 =
(guard__h453180 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h461402[56:34] :
_theResult___sfd__h461925 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 =
(guard__h453180 == 2'b0) ?
sfdin__h461402[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h461925 :
sfdin__h461402[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 =
(guard__h352872 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h360920 :
_theResult___exp__h361362 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 =
(guard__h352872 == 2'b0) ?
_theResult___fst_exp__h360920 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h361362 :
_theResult___fst_exp__h360920) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 =
(guard__h370638 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h378715 :
_theResult___exp__h379182 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 =
(guard__h370638 == 2'b0) ?
_theResult___fst_exp__h378715 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h379182 :
_theResult___fst_exp__h378715) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 =
(guard__h352872 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h360871[56:34] :
_theResult___sfd__h361363 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 =
(guard__h352872 == 2'b0) ?
_theResult___snd__h360871[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h361363 :
_theResult___snd__h360871[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 =
(guard__h370638 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h378661[56:34] :
_theResult___sfd__h379183 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 =
(guard__h370638 == 2'b0) ?
_theResult___snd__h378661[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h379183 :
_theResult___snd__h378661[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 =
(guard__h398562 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h406610 :
_theResult___exp__h407052 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 =
(guard__h398562 == 2'b0) ?
_theResult___fst_exp__h406610 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h407052 :
_theResult___fst_exp__h406610) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 =
(guard__h416328 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h424405 :
_theResult___exp__h424872 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 =
(guard__h416328 == 2'b0) ?
_theResult___fst_exp__h424405 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h424872 :
_theResult___fst_exp__h424405) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 =
(guard__h398562 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h406561[56:34] :
_theResult___sfd__h407053 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 =
(guard__h398562 == 2'b0) ?
_theResult___snd__h406561[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h407053 :
_theResult___snd__h406561[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 =
(guard__h416328 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h424351[56:34] :
_theResult___sfd__h424873 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 =
(guard__h416328 == 2'b0) ?
_theResult___snd__h424351[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h424873 :
_theResult___snd__h424351[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 =
(guard__h444250 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h452298 :
_theResult___exp__h452740 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 =
(guard__h444250 == 2'b0) ?
_theResult___fst_exp__h452298 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h452740 :
_theResult___fst_exp__h452298) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 =
(guard__h462016 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h470093 :
_theResult___exp__h470560 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 =
(guard__h462016 == 2'b0) ?
_theResult___fst_exp__h470093 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h470560 :
_theResult___fst_exp__h470093) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 =
(guard__h444250 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h452249[56:34] :
_theResult___sfd__h452741 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 =
(guard__h444250 == 2'b0) ?
_theResult___snd__h452249[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h452741 :
_theResult___snd__h452249[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 =
(guard__h462016 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h470039[56:34] :
_theResult___sfd__h470561 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 =
(guard__h462016 == 2'b0) ?
_theResult___snd__h470039[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h470561 :
_theResult___snd__h470039[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467 =
(guard__h530382 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h538343 :
_theResult___exp__h538998 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10469 =
(guard__h530382 == 2'b0) ?
_theResult___fst_exp__h538343 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
_theResult___exp__h538998 :
_theResult___fst_exp__h538343) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10536 =
(guard__h548763 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h556753 :
_theResult___exp__h557433 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10538 =
(guard__h548763 == 2'b0) ?
_theResult___fst_exp__h556753 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
_theResult___exp__h557433 :
_theResult___fst_exp__h556753) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10562 =
(guard__h530382 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h538294[56:5] :
_theResult___sfd__h538999 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10564 =
(guard__h530382 == 2'b0) ?
_theResult___snd__h538294[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
_theResult___sfd__h538999 :
_theResult___snd__h538294[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10607 =
(guard__h548763 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h556699[56:5] :
_theResult___sfd__h557434 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10609 =
(guard__h548763 == 2'b0) ?
_theResult___snd__h556699[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
_theResult___sfd__h557434 :
_theResult___snd__h556699[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8994 =
(guard__h491581 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h499542 :
_theResult___exp__h500197 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8996 =
(guard__h491581 == 2'b0) ?
_theResult___fst_exp__h499542 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
_theResult___exp__h500197 :
_theResult___fst_exp__h499542) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9068 =
(guard__h509962 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h517952 :
_theResult___exp__h518632 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9070 =
(guard__h509962 == 2'b0) ?
_theResult___fst_exp__h517952 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
_theResult___exp__h518632 :
_theResult___fst_exp__h517952) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9094 =
(guard__h491581 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h499493[56:5] :
_theResult___sfd__h500198 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 =
(guard__h491581 == 2'b0) ?
_theResult___snd__h499493[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
_theResult___sfd__h500198 :
_theResult___snd__h499493[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9140 =
(guard__h509962 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h517898[56:5] :
_theResult___sfd__h518633 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9142 =
(guard__h509962 == 2'b0) ?
_theResult___snd__h517898[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
_theResult___sfd__h518633 :
_theResult___snd__h517898[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9704 =
(guard__h569583 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h577544 :
_theResult___exp__h578199 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9706 =
(guard__h569583 == 2'b0) ?
_theResult___fst_exp__h577544 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
_theResult___exp__h578199 :
_theResult___fst_exp__h577544) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9773 =
(guard__h587964 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h595954 :
_theResult___exp__h596634 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9775 =
(guard__h587964 == 2'b0) ?
_theResult___fst_exp__h595954 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
_theResult___exp__h596634 :
_theResult___fst_exp__h595954) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9799 =
(guard__h569583 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h577495[56:5] :
_theResult___sfd__h578200 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9801 =
(guard__h569583 == 2'b0) ?
_theResult___snd__h577495[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
_theResult___sfd__h578200 :
_theResult___snd__h577495[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9844 =
(guard__h587964 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h595900[56:5] :
_theResult___sfd__h596635 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9846 =
(guard__h587964 == 2'b0) ?
_theResult___snd__h595900[56:5] :
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
_theResult___sfd__h596635 :
_theResult___snd__h595900[56:5]) ;
assign IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721 =
(_theResult____h647536 == 15'd0 &&
(csrf_prv_reg == 2'd0 ||
csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
enabled_ints__h648080 :
_theResult____h647536 ;
assign IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12928 =
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] ||
checkForException___d12886[4] ||
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d12921 ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d13560 =
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] ||
checkForException___d12886[4] ||
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13327 ;
assign IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d13596 =
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] ||
checkForException___d13505[4] ||
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13594 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10439 =
(_theResult___fst_exp__h556753 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48763_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10643 =
(_theResult___fst_exp__h538343 == 11'd2047) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10670 =
(_theResult___fst_exp__h556753 == 11'd2047) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48763_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8966 =
(_theResult___fst_exp__h517952 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard09962_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9676 =
(_theResult___fst_exp__h595954 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 =
(_theResult___fst_exp__h577544 == 11'd2047) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69583_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9908 =
(_theResult___fst_exp__h595954 == 11'd2047) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ?
4'd11 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 ?
4'd12 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844 ?
4'd13 :
4'd15)) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 ?
4'd8 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 ?
4'd9 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 ?
4'd6 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 ?
4'd7 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 ?
4'd4 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 ?
4'd5 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 ?
4'd2 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 ?
4'd3 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 ?
4'd0 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 ?
4'd1 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855) ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13064 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd12 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd12) ?
4'd13 :
4'd15 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13065 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd11 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd11) ?
4'd12 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13064 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13066 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd10 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd10) ?
4'd11 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13065 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13067 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd9 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd9) ?
4'd9 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13066 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13068 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd8 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd8) ?
4'd8 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13067 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13069 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd7 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd7) ?
4'd7 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13068 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13070 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd6 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd6) ?
4'd6 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13069 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13071 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd5 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd5) ?
4'd5 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13070 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13072 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd4 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd4) ?
4'd4 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13071 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13073 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd3 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd3) ?
4'd3 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13072 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13074 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd2 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd2) ?
4'd2 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13073 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13075 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd1 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd1) ?
4'd1 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13074 ;
assign IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13076 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 ==
4'd0 :
IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 ==
4'd0) ?
4'd0 :
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13075 ;
assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
{ (mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[75:72] :
mmio_cRqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
{ (mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
mmio_dataReqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
{ (EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
2'd1 :
((EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
2'd2 :
2'd3),
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[35:32] :
mmio_pRqQ_enqReq_rl[35:32] } ;
assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[66] :
!mmio_pRsQ_enqReq_rl[66]) ?
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[65] :
mmio_pRsQ_enqReq_rl[65],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:33] :
mmio_pRsQ_enqReq_rl[64:33],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[32] :
mmio_pRsQ_enqReq_rl[32],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[31:0] :
mmio_pRsQ_enqReq_rl[31:0] } :
{ 1'h0,
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:0] :
mmio_pRsQ_enqReq_rl[64:0] } ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10098 =
(!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 ||
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 ||
_theResult___fst_exp__h538343 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30382_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8625 =
(!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 ||
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 ||
_theResult___fst_exp__h499542 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard91581_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9335 =
(!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 ||
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 ||
_theResult___fst_exp__h577544 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69583_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ;
assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3__ETC___d13102 =
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ?
4'd0 :
(IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ?
4'd1 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2]) ?
4'd2 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3]) ?
4'd3 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4]) ?
4'd4 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6]) ?
4'd5 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7]) ?
4'd6 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8]) ?
4'd7 :
((IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10]) ?
4'd8 :
4'd9)))))))) ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12180 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12161 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12181 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12161)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12169 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12180 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12182 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12172 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12181 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12205 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12193 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12206 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12193)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12197 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12205 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12207 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12200 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12206 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12363 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12364 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12161)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12363 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12375 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12376 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12193)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12375 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11385 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11366 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11386 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11366)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11374 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11385 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11387 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11377 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11386 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11410 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11398 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11411 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11398)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11402 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11410 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11412 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11405 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11411 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11754 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11755 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11366)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11754 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11766 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11767 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11398)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11766 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8227 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8208 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8228 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8208)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8216 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8227 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8229 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8219 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8228 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8251 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8239 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8252 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8239)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8243 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8251 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8253 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8246 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8252 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8275 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8263 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8276 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8263)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8267 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8275 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8277 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8270 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8276 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8322 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8323 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8208)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8322 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8239)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8263)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } :
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2 } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 =
(!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb$procResp[12]) ?
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 :
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2650_265_ETC___d13703 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13292) &&
fetchStage$pipelines_1_canDeq) ?
fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13700 :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2650_265_ETC___d13711 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13292) &&
fetchStage$pipelines_1_canDeq) ?
IF_NOT_fetchStage_pipelines_1_first__2661_BITS_ETC___d13710 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13708 ;
assign IF_NOT_fetchStage_pipelines_1_first__2661_BITS_ETC___d13633 =
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) ?
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13616 :
((fetchStage$pipelines_1_first[194:192] == 3'd2) ?
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13627 :
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
_0_OR_fetchStage_RDY_pipelines_0_first__2649_36_ETC___d13630) ;
assign IF_NOT_fetchStage_pipelines_1_first__2661_BITS_ETC___d13710 =
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13543 ?
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13708 ;
assign IF_NOT_rob_deqPort_1_deq_data__4609_BIT_25_461_ETC___d14809 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
rob$deqPort_1_deq_data[26] ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
((_theResult___fst_exp__h370030 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) :
((_theResult___fst_exp__h378715 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
((_theResult___fst_exp__h370030 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) :
((_theResult___fst_exp__h378715 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] :
_theResult___fst_exp__h379263 == 8'd255 &&
_theResult___fst_sfd__h379264 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] :
_theResult___fst_exp__h378715 == 8'd0 &&
guard__h370638 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] :
_theResult___fst_exp__h378715 != 8'd255 &&
guard__h370638 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
((_theResult___fst_exp__h415720 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) :
((_theResult___fst_exp__h424405 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
((_theResult___fst_exp__h415720 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) :
((_theResult___fst_exp__h424405 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] :
_theResult___fst_exp__h424953 == 8'd255 &&
_theResult___fst_sfd__h424954 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] :
_theResult___fst_exp__h424405 == 8'd0 &&
guard__h416328 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] :
_theResult___fst_exp__h424405 != 8'd255 &&
guard__h416328 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
((_theResult___fst_exp__h461408 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) :
((_theResult___fst_exp__h470093 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
((_theResult___fst_exp__h461408 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) :
((_theResult___fst_exp__h470093 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] :
_theResult___fst_exp__h470641 == 8'd255 &&
_theResult___fst_sfd__h470642 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] :
_theResult___fst_exp__h470093 == 8'd0 &&
guard__h462016 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] :
_theResult___fst_exp__h470093 != 8'd255 &&
guard__h462016 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10400 =
((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172[10],
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172 }) -
12'd3074 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10441 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 ?
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10393 :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10439) :
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10672 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 ?
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10658 :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10670) :
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10867 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725[2] :
_theResult___fst_exp__h518735 == 11'd2047 &&
_theResult___fst_sfd__h518736 == 52'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10881 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766[2] :
_theResult___fst_exp__h557536 == 11'd2047 &&
_theResult___fst_sfd__h557537 == 52'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10896 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810[2] :
_theResult___fst_exp__h596737 == 11'd2047 &&
_theResult___fst_sfd__h596738 == 52'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10913 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725[1] :
_theResult___fst_exp__h517952 == 11'd0 &&
guard__h509962 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10925 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766[1] :
_theResult___fst_exp__h556753 == 11'd0 &&
guard__h548763 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10938 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810[1] :
_theResult___fst_exp__h595954 == 11'd0 &&
guard__h587964 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10955 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725[0] :
_theResult___fst_exp__h517952 != 11'd2047 &&
guard__h509962 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10967 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766[0] :
_theResult___fst_exp__h556753 != 11'd2047 &&
guard__h548763 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10980 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810[0] :
_theResult___fst_exp__h595954 != 11'd2047 &&
guard__h587964 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8927 =
((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132[10],
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132 }) -
12'd3074 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8968 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 ?
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 ?
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8920 :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8966) :
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9637 =
((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149[10],
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149 }) -
12'd3074 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9678 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 ?
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9630 :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9676) :
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9910 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 ?
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9896 :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9908) :
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_checkForException_2886_BIT_4_2887_THEN_IF_c_ETC___d13025 =
checkForException___d12886[4] ?
CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226 :
4'd2 ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2124_ETC___d12156 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2124_ETC___d12190 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1329_ETC___d11361 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1329_ETC___d11395 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8203 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8236 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8260 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489) :
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097) :
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881) :
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918) ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 =
(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
2'd0) ?
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 =
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066[31:0] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052 =
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
(coreFix_fpuMulDivExe_0_regToExeQ$first[98] ?
6'd2 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[97] ?
6'd3 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[96] ?
6'd4 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[95] ?
6'd5 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[94] ?
6'd6 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[93] ?
6'd7 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[92] ?
6'd8 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[91] ?
6'd9 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[90] ?
6'd10 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[89] ?
6'd11 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[88] ?
6'd12 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[87] ?
6'd13 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[86] ?
6'd14 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[85] ?
6'd15 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[84] ?
6'd16 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[83] ?
6'd17 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[82] ?
6'd18 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[81] ?
6'd19 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[80] ?
6'd20 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[79] ?
6'd21 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[78] ?
6'd22 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[77] ?
6'd23 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[76] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10443 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0 ||
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10098 :
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10441) ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10621 =
{ (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h557548,
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ?
_theResult___snd_fst_sfd__h519437 :
_theResult___fst_sfd__h557552 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10443,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10621 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10674 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0 ||
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10646 :
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10672) ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10729 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 &&
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708[4] :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 &&
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725[4] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10770 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 &&
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749[4] :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 &&
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766[4] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10814 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 &&
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793[4] :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 &&
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810[4] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10829 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 &&
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708[3] :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 &&
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725[3] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10839 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 &&
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749[3] :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 &&
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766[3] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10850 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 &&
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793[3] :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 &&
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810[3] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10869 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 ||
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708[2] :
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 ||
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10867 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10883 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 ||
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749[2] :
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 ||
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10881 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10898 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 ||
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793[2] :
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 ||
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10896 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10915 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 &&
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 ||
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708[1]) :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 &&
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10913 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10927 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 &&
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 ||
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749[1]) :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 &&
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10925 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10940 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 &&
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 ||
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793[1]) :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 &&
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10938 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10957 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 ||
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708[0] :
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 ||
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10955 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10969 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 ||
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749[0] :
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 ||
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10967 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10982 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 ||
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 &&
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793[0] :
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 ||
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10980 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8416 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8382 &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8395 :
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8415 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564 =
((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
(coreFix_fpuMulDivExe_0_regToExeQ$first[162] ?
6'd2 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[161] ?
6'd3 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[160] ?
6'd4 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[159] ?
6'd5 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[158] ?
6'd6 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[157] ?
6'd7 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[156] ?
6'd8 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[155] ?
6'd9 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[154] ?
6'd10 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[153] ?
6'd11 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[152] ?
6'd12 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[151] ?
6'd13 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[150] ?
6'd14 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[149] ?
6'd15 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[148] ?
6'd16 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[147] ?
6'd17 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[146] ?
6'd18 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[145] ?
6'd19 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[144] ?
6'd20 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[143] ?
6'd21 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[142] ?
6'd22 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[141] ?
6'd23 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[140] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8970 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0 ||
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8625 :
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8968) ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9154 =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8970,
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h518747,
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ?
_theResult___snd_fst_sfd__h480495 :
_theResult___fst_sfd__h518751 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9154 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289 =
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
(coreFix_fpuMulDivExe_0_regToExeQ$first[34] ?
6'd2 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[33] ?
6'd3 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[32] ?
6'd4 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[31] ?
6'd5 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[30] ?
6'd6 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[29] ?
6'd7 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[28] ?
6'd8 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[27] ?
6'd9 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[26] ?
6'd10 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[25] ?
6'd11 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[24] ?
6'd12 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[23] ?
6'd13 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[22] ?
6'd14 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[21] ?
6'd15 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[20] ?
6'd16 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[19] ?
6'd17 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[18] ?
6'd18 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[17] ?
6'd19 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[16] ?
6'd20 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[15] ?
6'd21 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[14] ?
6'd22 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[13] ?
6'd23 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[12] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9680 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0 ||
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9335 :
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9678) ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9858 =
{ (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h596749,
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ?
_theResult___snd_fst_sfd__h558638 :
_theResult___fst_sfd__h596753 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9860 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9680,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9858 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9912 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0 ||
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9884 :
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9910) ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9914 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9912,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9858 } ;
assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12593 =
coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
result__h643243 :
w__h643238 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 :
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 =
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd7) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd6) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd5) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd4) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd3) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd2) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd1) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd0) ?
n___1__h196602 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
{ 3'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
3'd5 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
3'd2 :
3'd3) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
58'h155555555555554 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
1'd0 } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 }) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
x__h195199 :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ?
64'd0 :
64'd1) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 =
_theResult_____2__h294593 == v__h294013 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 =
_theResult_____2__h302589 == v__h297358 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 =
EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 &&
(EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
{ EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
x__h300223 } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 =
!MUX_flush_reservation$write_1__SEL_1 &&
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008 =
MUX_flush_reservation$write_1__SEL_1 ?
58'h2AAAAAAAAAAAAAA :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ?
!coreFix_memExe_respLrScAmoQ_full :
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
!coreFix_memExe_respLrScAmoQ_full :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0) ?
!coreFix_memExe_memRespLdQ_full :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 =
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140 =
{ (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } :
65'h10000000000000001 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ?
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
2'd0 :
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 =
{ (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd7) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd6) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd5) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd4) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd3) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd2) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd1) ?
n__h192527 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320 =
EN_dCacheToParent_rqToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 =
_theResult_____2__h308583 == v__h307872 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416 =
EN_dCacheToParent_rsToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 =
_theResult_____2__h316437 == v__h311748 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 =
(coreFix_memExe_dTlb$procResp[105:103] == 3'd3) ?
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
coreFix_memExe_dTlb$procResp[105:103] != 3'd3 &&
!coreFix_memExe_dTlb$procResp[12] :
!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd0 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd0 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd1 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd1 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd2 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd2 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd3 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd3 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd4 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd4 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd5 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd5 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd6 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd6 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd7 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd8 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd8 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd9 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd9 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd10 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd10 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd11 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd11 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd12 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd12 ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 =
_theResult_____2__h330006 == v__h329574 ;
assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
coreFix_memExe_forwardQ_deqReq_rl ;
assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
coreFix_memExe_forwardQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 } :
{ {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359[15]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 } :
{ {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373[7]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 }) ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 } :
{ {48{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407[15]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 } :
{ {56{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420[7]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 }) ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 } :
{ {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348[31]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 }) :
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 } :
{ {32{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398[31]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) :
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 =
_theResult_____2__h326781 == v__h326349 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
coreFix_memExe_memRespLdQ_deqReq_rl ;
assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
csrf_minstret_ehr_data_lat_0$whas ?
rob$deqPort_0_deq_data[95:32] :
csrf_minstret_ehr_data_rl ;
assign IF_fetchStage_RDY_pipelines_0_first__2649_AND__ETC___d13261 =
fetchStage_RDY_pipelines_0_first__2649_AND_NOT_ETC___d13257 ?
fetchStage$RDY_pipelines_0_first :
!regRenamingTable$rename_0_canRename ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13635 =
(fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1)) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13605 :
fetchStage$RDY_pipelines_1_first &&
IF_NOT_fetchStage_pipelines_1_first__2661_BITS_ETC___d13633 ;
assign IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13700 =
(fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
fetchStage_RDY_pipelines_0_first__2649_AND_fet_ETC___d13324 &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13543) ?
IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13635 &&
(IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13748 =
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741 ||
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign IF_fetchStage_pipelines_0_first__2652_BIT_160__ETC___d13918 =
{ fetchStage$pipelines_0_first[159:128],
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13906,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13909 ?
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13912 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13915 } } ;
assign IF_fetchStage_pipelines_0_first__2652_BIT_173__ETC___d12913 =
fetchStage$pipelines_0_first[173] ?
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852 :
12'hCFF ;
assign IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d13121 =
(fetchStage$pipelines_0_first[68] ||
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14]) ?
IF_IF_fetchStage_pipelines_0_first__2652_BIT_6_ETC___d13076 :
CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 ;
assign IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13869 =
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13828 &&
IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13635 &&
(IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13853 ||
rob$RDY_enqPort_1_enq &&
regRenamingTable$RDY_rename_1_claimRename &&
regRenamingTable$RDY_rename_1_getRename &&
fetchStage_RDY_pipelines_1_deq__2664_AND_NOT_f_ETC___d13863) ;
assign IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d14086 =
(fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14033 &&
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14040) ?
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14041 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14042 } ;
assign IF_fetchStage_pipelines_1_first__2661_BIT_160__ETC___d14045 =
{ fetchStage$pipelines_1_first[159:128],
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14039,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14040 ?
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14041 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14042 } } ;
assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[142] :
mmio_cRqQ_enqReq_rl[142] ;
assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[1] :
mmio_cRsQ_enqReq_rl[1] ;
assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[142] :
mmio_dataReqQ_enqReq_rl[142] ;
assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[65] :
mmio_dataRespQ_enqReq_rl[65] ;
assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[39] :
mmio_pRqQ_enqReq_rl[39] ;
assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[67] :
mmio_pRsQ_enqReq_rl[67] ;
assign IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14710 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_snd_snd__h707288 :
64'd0 ;
assign IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14796 =
rob$deqPort_0_canDeq ? y_avValue_snd_fst__h707272 : 5'd0 ;
assign IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14818 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_fst__h707282 :
2'd0 ;
assign IF_rob_deqPort_1_canDeq__4606_THEN_IF_NOT_rob__ETC___d14810 =
rob$deqPort_1_canDeq ?
IF_NOT_rob_deqPort_1_deq_data__4609_BIT_25_461_ETC___d14809 :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
assign IF_sfdin09113_BIT_4_THEN_2_ELSE_0__q131 =
sfdin__h509113[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin15714_BIT_33_THEN_2_ELSE_0__q66 =
sfdin__h415714[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin43636_BIT_33_THEN_2_ELSE_0__q91 =
sfdin__h443636[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin47914_BIT_4_THEN_2_ELSE_0__q171 =
sfdin__h547914[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin52258_BIT_33_THEN_2_ELSE_0__q21 =
sfdin__h352258[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin61402_BIT_33_THEN_2_ELSE_0__q101 =
sfdin__h461402[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin70024_BIT_33_THEN_2_ELSE_0__q31 =
sfdin__h370024[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin87115_BIT_4_THEN_2_ELSE_0__q148 =
sfdin__h587115[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin97948_BIT_33_THEN_2_ELSE_0__q56 =
sfdin__h397948[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd06561_BIT_33_THEN_2_ELSE_0__q58 =
_theResult___snd__h406561[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd17898_BIT_4_THEN_2_ELSE_0__q134 =
_theResult___snd__h517898[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd24351_BIT_33_THEN_2_ELSE_0__q71 =
_theResult___snd__h424351[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd38294_BIT_4_THEN_2_ELSE_0__q167 =
_theResult___snd__h538294[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd52249_BIT_33_THEN_2_ELSE_0__q93 =
_theResult___snd__h452249[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd56699_BIT_4_THEN_2_ELSE_0__q174 =
_theResult___snd__h556699[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd60871_BIT_33_THEN_2_ELSE_0__q23 =
_theResult___snd__h360871[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd70039_BIT_33_THEN_2_ELSE_0__q106 =
_theResult___snd__h470039[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd77495_BIT_4_THEN_2_ELSE_0__q144 =
_theResult___snd__h577495[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd78661_BIT_33_THEN_2_ELSE_0__q36 =
_theResult___snd__h378661[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd95900_BIT_4_THEN_2_ELSE_0__q151 =
_theResult___snd__h595900[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd99493_BIT_4_THEN_2_ELSE_0__q127 =
_theResult___snd__h499493[4] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[0]) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13175 =
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] &&
!checkForException___d12886[4] &&
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13168 &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13249 =
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] &&
!checkForException___d12886[4] &&
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13247 ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13532 =
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] &&
!checkForException___d13505[4] &&
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13530 ;
assign NOT_IF_NOT_rob_deqPort_0_canDeq__4602_4603_OR__ETC___d14815 =
(fflags__h707765 & csrf_fflags_reg) != fflags__h707765 ||
!r__h611009 &&
(IF_rob_deqPort_1_canDeq__4606_THEN_IF_NOT_rob__ETC___d14810 ||
fflags__h707765 != 5'd0) ;
assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13310 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12172 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12161) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12169) ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12200 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12193) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12197) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11377 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11366) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11374) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11405 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11398) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11402) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8219 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8208) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8216) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8246 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8239) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8243) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8270 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8263) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8267) ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10025 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[97] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[96] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[95] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[94] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[93] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[92] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[91] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[90] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[89] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[88] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[87] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[86] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[85] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[84] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[83] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[82] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[81] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[80] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[79] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[78] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[77] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[76] ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10732 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10729 ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10774 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10732 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
(value_BIT_23___h531040 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10770) ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10832 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10829 ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10843 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10832 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
(value_BIT_23___h531040 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10839) ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10872 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10869 ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10887 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10872 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
(value_BIT_23___h531040 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10883) ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10918 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10915 ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10931 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10918 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
(value_BIT_23___h531040 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10927) ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10960 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10957 ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10973 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10960 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
(value_BIT_23___h531040 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10969) ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8415 =
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8537 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[161] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[160] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[159] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[158] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[157] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[156] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[155] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[154] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[153] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[152] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[151] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[150] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[149] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[148] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[147] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[146] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[145] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[144] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[143] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[142] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[141] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[140] ;
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d9262 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[33] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[32] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[31] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[30] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[29] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[28] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[27] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[26] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[25] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[24] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[23] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[22] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[21] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[20] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[19] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[18] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[17] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[16] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[15] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[14] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[13] &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[12] ;
assign NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13644 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] ;
assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591) ;
assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179 =
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176) &&
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149 ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 =
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 =
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351 =
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320 ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447 =
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443) &&
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416 ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 =
!coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923 =
(!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
coreFix_memExe_dMem_perfReqQ_empty) ;
assign NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 =
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 &&
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 &&
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 ;
assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 =
!coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_forwardQ_clearReq_rl ;
assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768 =
(!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
!coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_forwardQ_enqReq_rl[69])) &&
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 ||
coreFix_memExe_forwardQ_empty) ;
assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 =
!coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_memRespLdQ_clearReq_rl ;
assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674 =
(!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
!coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 ||
coreFix_memExe_memRespLdQ_empty) ;
assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 =
!coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLdQ_full_rl ;
assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 =
!coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 =
!coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_clearReq_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585 =
(!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
!coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
!coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
(coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
coreFix_memExe_respLrScAmoQ_empty) ;
assign NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
assign NOT_coreFix_memExe_rsMem_canEnq__3278_3340_OR__ETC___d13645 =
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] ;
assign NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13168 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[199:195] != 5'd13 ||
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13164 &&
!csrf_prv_reg_read__2680_ULT_IF_fetchStage_pipe_ETC___d12918) ;
assign NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13247 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13530 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_1_first[95] ||
!fetchStage$pipelines_1_first[94]) &&
(!fetchStage$pipelines_1_first[88] ||
!fetchStage$pipelines_1_first[87]) &&
!fetchStage$pipelines_1_first[81] &&
(!fetchStage$pipelines_1_first[75] ||
!fetchStage$pipelines_1_first[74])) &&
(fetchStage$pipelines_1_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_prv_reg_read__2680_ULE_1_4236_4300_OR_ETC___d14304 =
!csrf_prv_reg_read__2680_ULE_1___d14236 ||
(commitStage_commitTrap[4] ?
!_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14256 :
!_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14274) ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13616 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2661_BITS_199_TO_ETC___d13602) ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13627 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3230_AND__ETC___d13625 ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2661_BITS_199_TO_ETC___d13602) ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13666 =
!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13660 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13683 =
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343) &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13804 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13660 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13823 =
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13794) &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 &&
(fetchStage$pipelines_1_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13875 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13750 &&
IF_fetchStage_RDY_pipelines_0_first__2649_AND__ETC___d13261) &&
fetchStage$RDY_pipelines_0_first &&
fetchStage_pipelines_0_canDeq__2650_AND_fetchS_ETC___d13873 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 =
(!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291) &&
fetchStage$pipelines_1_canDeq ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13977 =
!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13348 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13988 =
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13985 &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1) &&
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__265_ETC___d13789 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14033 =
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343) &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ;
assign NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14063 =
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13977 &&
specTagManager$canClaim &&
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 &&
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 &&
fetchStage$pipelines_1_first[194:192] == 3'd1 ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13164 =
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
fetchStage$pipelines_0_first[178:174] != 5'd15) &&
rs1__h651591 == 5'd0 &&
imm__h651592 == 32'd0 ||
IF_fetchStage_pipelines_0_first__2652_BIT_173__ETC___d12913[11:10] !=
2'b11 ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 =
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13249 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13292 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291 ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13550 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 &&
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13549 ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13556 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 &&
(!coreFix_aluExe_0_rsAlu$canEnq ||
!coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270) ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13708 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq ;
assign NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13950 =
{ fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13906,
(fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13909) ?
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13912 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13915 },
7'd32,
specTagManager$currentSpecBits } ;
assign NOT_fetchStage_pipelines_0_first__2652_BIT_68__ETC___d13303 =
!fetchStage$pipelines_0_first[68] &&
!checkForException___d12886[4] &&
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13247 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_fetchStage_pipelines_1_canDeq__2658_2659_O_ETC___d12667 =
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(epochManager$checkEpoch_1_check ||
fetchStage$RDY_pipelines_1_deq) ;
assign NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13541 =
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13532 &&
rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13539 ;
assign NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13543 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13348 ||
fetchStage$pipelines_0_first[194:192] != 3'd1) &&
specTagManager$canClaim) &&
regRenamingTable$rename_1_canRename &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13541 ;
assign NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13654 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13648 ||
fetchStage$pipelines_0_first[194:192] != 3'd1) &&
specTagManager$canClaim) &&
regRenamingTable$rename_1_canRename &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13541 ;
assign NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13675 =
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13532 &&
rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13673 ;
assign NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13692 =
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13532 &&
rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13690 ;
assign NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13985 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13977 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 ;
assign NOT_fetchStage_pipelines_1_first__2661_BIT_68__ETC___d13982 =
!fetchStage$pipelines_1_first[68] &&
!checkForException___d13505[4] &&
NOT_csrf_fs_reg_read__1538_EQ_0_2875_2876_OR_N_ETC___d13530 &&
rob$enqPort_1_canEnq &&
epochManager$checkEpoch_1_check ;
assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
!mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
(!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_cRqQ_enqReq_lat_0$whas ?
!mmio_cRqQ_enqReq_lat_0$wget[142] :
!mmio_cRqQ_enqReq_rl[142])) &&
(mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
mmio_cRqQ_empty) ;
assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
!mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
(!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_handlePRq ?
!mmio_cRsQ_enqReq_lat_0$wget[1] :
!mmio_cRsQ_enqReq_rl[1])) &&
(mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
mmio_cRsQ_empty) ;
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt ;
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd ;
assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
(!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
!mmio_dataPendQ_enqReq_lat_0$whas &&
!mmio_dataPendQ_enqReq_rl) &&
(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataPendQ_deqReq_rl) ||
mmio_dataPendQ_empty) ;
assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
!mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataReqQ_clearReq_rl ;
assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
(!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_dataReqQ_enqReq_lat_0$whas ?
!mmio_dataReqQ_enqReq_lat_0$wget[142] :
!mmio_dataReqQ_enqReq_rl[142])) &&
(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
mmio_dataReqQ_empty) ;
assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
!mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataRespQ_clearReq_rl ;
assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
(!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_sendDataResp ?
!mmio_dataRespQ_enqReq_lat_0$wget[65] :
!mmio_dataRespQ_enqReq_rl[65])) &&
(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataRespQ_deqReq_rl) ||
mmio_dataRespQ_empty) ;
assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
!mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
(!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRq_enq ?
!mmio_pRqQ_enqReq_lat_0$wget[39] :
!mmio_pRqQ_enqReq_rl[39])) &&
(mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
mmio_pRqQ_empty) ;
assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
!mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
(!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[67] :
!mmio_pRsQ_enqReq_rl[67])) &&
(mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
(mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) ||
mmio_pRsQ_empty) ;
assign NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
fetchStage_pipelines_0_first__2652_BIT_68_2679_ETC___d13332 ;
assign NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13660 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
fetchStage_pipelines_0_first__2652_BIT_68_2679_ETC___d13332 ;
assign NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[68] ||
checkForException___d12886[4] ||
!rob$enqPort_0_canEnq ;
assign NOT_regRenamingTable_rename_1_canRename__3354__ETC___d13773 =
!regRenamingTable$rename_1_canRename ||
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
fetchStage_pipelines_1_first__2661_BIT_68_3382_ETC___d13771 ;
assign NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_RDY_ETC___d14641 =
(!rob$deqPort_0_canDeq ||
rob$RDY_deqPort_0_deq &&
regRenamingTable$RDY_commit_0_commit) &&
(!rob$deqPort_1_canDeq ||
rob$RDY_deqPort_1_deq_data &&
NOT_rob_deqPort_1_deq_data__4609_BIT_25_4610_4_ETC___d14638) ;
assign NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_deq_ETC___d14789 =
(!rob$deqPort_0_canDeq ||
rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd21 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20) &&
rob$deqPort_1_canDeq ;
assign NOT_rob_deqPort_0_deq_data__4100_BITS_186_TO_1_ETC___d14408 =
rob$deqPort_0_deq_data[186:182] != 5'd13 ||
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 !=
6'd7 ||
csrf_stats_module_writeQ$FULL_N) &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 !=
6'd6 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign NOT_rob_deqPort_1_deq_data__4609_BIT_25_4610_4_ETC___d14638 =
!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20 ||
rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ;
assign NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13794 =
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13660 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13859 =
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934,
x__h289688 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14937 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14893 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14902 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14893,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14911 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14902,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ;
assign SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13605 =
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575 ||
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13319 ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2661_BITS_199_TO_ETC___d13602 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11043 =
b__h600853 * b__h600929 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11056 =
b__h600853 * b__h601042 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63[10],
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28[10],
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98[10],
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10100 =
{ {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168[7]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168 } ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10100 ^
12'h800) <=
12'd3071 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10100 ^
12'h800) <
12'd1026 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8627 =
{ {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128[7]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128 } ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8627 ^
12'h800) <=
12'd3071 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8627 ^
12'h800) <
12'd1026 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9337 =
{ {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145[7]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 } ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9337 ^
12'h800) <=
12'd3071 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9337 ^
12'h800) <
12'd1026 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8627 +
12'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] -
11'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9337 +
12'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] -
11'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10100 +
12'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] -
11'd1023 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 =
{ 3'd0,
_theResult___fst_exp__h352264 == 8'd0 &&
(sfdin__h352258[56:34] == 23'd0 || guard__h344163 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h352861 == 8'd255 &&
_theResult___fst_sfd__h352862 == 23'd0,
1'd0,
_theResult___fst_exp__h352264 != 8'd255 &&
guard__h344163 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 =
{ 3'd0,
_theResult___fst_exp__h397954 == 8'd0 &&
(sfdin__h397948[56:34] == 23'd0 || guard__h389855 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h398551 == 8'd255 &&
_theResult___fst_sfd__h398552 == 23'd0,
1'd0,
_theResult___fst_exp__h397954 != 8'd255 &&
guard__h389855 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 =
{ 3'd0,
_theResult___fst_exp__h443642 == 8'd0 &&
(sfdin__h443636[56:34] == 23'd0 || guard__h435543 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h444239 == 8'd255 &&
_theResult___fst_sfd__h444240 == 23'd0,
1'd0,
_theResult___fst_exp__h443642 != 8'd255 &&
guard__h435543 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10351 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10349 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10725 =
{ 3'd0,
_theResult___fst_exp__h509119 == 11'd0 &&
(sfdin__h509113[56:5] == 52'd0 || guard__h500893 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h509951 == 11'd2047 &&
_theResult___fst_sfd__h509952 == 52'd0,
1'd0,
_theResult___fst_exp__h509119 != 11'd2047 &&
guard__h500893 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10766 =
{ 3'd0,
_theResult___fst_exp__h547920 == 11'd0 &&
(sfdin__h547914[56:5] == 52'd0 || guard__h539694 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h548752 == 11'd2047 &&
_theResult___fst_sfd__h548753 == 52'd0,
1'd0,
_theResult___fst_exp__h547920 != 11'd2047 &&
guard__h539694 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10810 =
{ 3'd0,
_theResult___fst_exp__h587121 == 11'd0 &&
(sfdin__h587115[56:5] == 52'd0 || guard__h578895 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h587953 == 11'd2047 &&
_theResult___fst_sfd__h587954 == 52'd0,
1'd0,
_theResult___fst_exp__h587121 != 11'd2047 &&
guard__h578895 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8878 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8876 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9588 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9586 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 =
{ 3'd0,
_theResult___fst_exp__h370030 == 8'd0 &&
(sfdin__h370024[56:34] == 23'd0 || guard__h361802 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h370627 == 8'd255 &&
_theResult___fst_sfd__h370628 == 23'd0,
1'd0,
_theResult___fst_exp__h370030 != 8'd255 &&
guard__h361802 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 =
{ 3'd0,
_theResult___fst_exp__h415720 == 8'd0 &&
(sfdin__h415714[56:34] == 23'd0 || guard__h407492 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h416317 == 8'd255 &&
_theResult___fst_sfd__h416318 == 23'd0,
1'd0,
_theResult___fst_exp__h415720 != 8'd255 &&
guard__h407492 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 =
{ 3'd0,
_theResult___fst_exp__h461408 == 8'd0 &&
(sfdin__h461402[56:34] == 23'd0 || guard__h453180 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h462005 == 8'd255 &&
_theResult___fst_sfd__h462006 == 23'd0,
1'd0,
_theResult___fst_exp__h461408 != 8'd255 &&
guard__h453180 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 =
{ 3'd0,
_theResult___fst_exp__h360920 == 8'd0 &&
guard__h352872 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h361443 == 8'd255 &&
_theResult___fst_sfd__h361444 == 23'd0,
1'd0,
_theResult___fst_exp__h360920 != 8'd255 &&
guard__h352872 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 =
{ 3'd0,
_theResult___fst_exp__h406610 == 8'd0 &&
guard__h398562 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h407133 == 8'd255 &&
_theResult___fst_sfd__h407134 == 23'd0,
1'd0,
_theResult___fst_exp__h406610 != 8'd255 &&
guard__h398562 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 =
{ 3'd0,
_theResult___fst_exp__h452298 == 8'd0 &&
guard__h444250 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h452821 == 8'd255 &&
_theResult___fst_sfd__h452822 == 23'd0,
1'd0,
_theResult___fst_exp__h452298 != 8'd255 &&
guard__h444250 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10054 =
({ 6'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10401 =
({ 6'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052 } ^
12'h800) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10400 ^
12'h800) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708 =
{ 3'd0,
_theResult___fst_exp__h499542 == 11'd0 &&
guard__h491581 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h500300 == 11'd2047 &&
_theResult___fst_sfd__h500301 == 52'd0,
1'd0,
_theResult___fst_exp__h499542 != 11'd2047 &&
guard__h491581 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 =
{ 3'd0,
_theResult___fst_exp__h538343 == 11'd0 &&
guard__h530382 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h539101 == 11'd2047 &&
_theResult___fst_sfd__h539102 == 52'd0,
1'd0,
_theResult___fst_exp__h538343 != 11'd2047 &&
guard__h530382 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10793 =
{ 3'd0,
_theResult___fst_exp__h577544 == 11'd0 &&
guard__h569583 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h578302 == 11'd2047 &&
_theResult___fst_sfd__h578303 == 52'd0,
1'd0,
_theResult___fst_exp__h577544 != 11'd2047 &&
guard__h569583 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11049 =
b__h601030 * b__h601042 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8566 =
({ 6'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8928 =
({ 6'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564 } ^
12'h800) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8927 ^
12'h800) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9291 =
({ 6'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9638 =
({ 6'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289 } ^
12'h800) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9637 ^
12'h800) ;
assign _0_OR_NOT_fetchStage_pipelines_0_first__2652_BI_ETC___d13722 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_k63183_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2661_BI_ETC___d13807 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_fetchStage_pipelines_0_canDeq__2650_AND_N_ETC__q234 ;
assign _0_OR_fetchStage_RDY_pipelines_0_first__2649_36_ETC___d13630 =
fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13319 ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2661_BITS_199_TO_ETC___d13602 ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 =
sfd__h336548 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 =
sfd__h382243 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 =
sfd__h427931 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10107 =
sfd__h519483 >>
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10103 ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8634 =
sfd__h480541 >>
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8630 ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9344 =
sfd__h558684 >>
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9340 ;
assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14274 =
medeleg_csr__read__h609280[i__h694342] ;
assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14256 =
mideleg_csr__read__h609375[i__h694502] ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[1]) ;
assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10103 =
12'd3074 -
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10100 ;
assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8630 =
12'd3074 -
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8627 ;
assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9340 =
12'd3074 -
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9337 ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8490 =
12'd3970 -
{ 7'd0,
coreFix_fpuMulDivExe_0_regToExeQ$first[162] ?
5'd0 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[161] ?
5'd1 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[160] ?
5'd2 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[159] ?
5'd3 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[158] ?
5'd4 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[157] ?
5'd5 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[156] ?
5'd6 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[155] ?
5'd7 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[154] ?
5'd8 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[153] ?
5'd9 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[152] ?
5'd10 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[151] ?
5'd11 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[150] ?
5'd12 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[149] ?
5'd13 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[148] ?
5'd14 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[147] ?
5'd15 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[146] ?
5'd16 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[145] ?
5'd17 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[144] ?
5'd18 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[143] ?
5'd19 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[142] ?
5'd20 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[141] ?
5'd21 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[140] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 =
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8490 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 =
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8490 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9215 =
12'd3970 -
{ 7'd0,
coreFix_fpuMulDivExe_0_regToExeQ$first[34] ?
5'd0 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[33] ?
5'd1 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[32] ?
5'd2 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[31] ?
5'd3 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[30] ?
5'd4 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[29] ?
5'd5 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[28] ?
5'd6 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[27] ?
5'd7 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[26] ?
5'd8 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[25] ?
5'd9 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[24] ?
5'd10 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[23] ?
5'd11 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[22] ?
5'd12 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[21] ?
5'd13 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[20] ?
5'd14 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[19] ?
5'd15 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[18] ?
5'd16 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[17] ?
5'd17 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[16] ?
5'd18 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[15] ?
5'd19 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[14] ?
5'd20 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[13] ?
5'd21 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[12] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 =
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9215 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 =
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9215 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9978 =
12'd3970 -
{ 7'd0,
coreFix_fpuMulDivExe_0_regToExeQ$first[98] ?
5'd0 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[97] ?
5'd1 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[96] ?
5'd2 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[95] ?
5'd3 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[94] ?
5'd4 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[93] ?
5'd5 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[92] ?
5'd6 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[91] ?
5'd7 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[90] ?
5'd8 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[89] ?
5'd9 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[88] ?
5'd10 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[87] ?
5'd11 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[86] ?
5'd12 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[85] ?
5'd13 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[84] ?
5'd14 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[83] ?
5'd15 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[82] ?
5'd16 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[81] ?
5'd17 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[80] ?
5'd18 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[79] ?
5'd19 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[78] ?
5'd20 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[77] ?
5'd21 :
(coreFix_fpuMulDivExe_0_regToExeQ$first[76] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 =
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9978 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 =
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9978 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ;
assign _dfoo12 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13902 ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14033 &&
fetchStage$pipelines_1_first[199:195] != 5'd14 ;
assign _dfoo18 =
k__h663183 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13884 ||
fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13971 ==
1'd0 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13988 ;
assign _dfoo2 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930 ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14033 &&
fetchStage$pipelines_1_first[191:189] != 3'd0 &&
fetchStage$pipelines_1_first[191:189] != 3'd2 ;
assign _dfoo20 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd20 ;
assign _dfoo26 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 ==
6'd18) ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ;
assign _dfoo7 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922 ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13975 &&
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d14033 &&
(fetchStage$pipelines_1_first[191:189] == 3'd0 ||
fetchStage$pipelines_1_first[191:189] == 3'd2) ;
assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1rf$EN_write_0_wr =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1rf$EN_write_1_wr =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1sbAggr$EN_setReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1sbCons$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1sbCons$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _theResult_____2__h294593 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ?
next_deqP___1__h294872 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
assign _theResult_____2__h302589 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ?
next_deqP___1__h302868 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
assign _theResult_____2__h308583 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ?
next_deqP___1__h309149 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
assign _theResult_____2__h316437 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ?
next_deqP___1__h317003 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
assign _theResult_____2__h326781 =
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ?
next_deqP___1__h327060 :
coreFix_memExe_memRespLdQ_deqP ;
assign _theResult_____2__h330006 =
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ?
next_deqP___1__h330285 :
coreFix_memExe_forwardQ_deqP ;
assign _theResult____h344153 =
(value__h344775 == 54'd0) ? sfd__h336548 : 57'd1 ;
assign _theResult____h361792 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^
12'h800) <
12'd2105) ?
result__h362405 :
_theResult____h344153 ;
assign _theResult____h389845 =
(value__h390465 == 54'd0) ? sfd__h382243 : 57'd1 ;
assign _theResult____h407482 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^
12'h800) <
12'd2105) ?
result__h408095 :
_theResult____h389845 ;
assign _theResult____h435533 =
(value__h436153 == 54'd0) ? sfd__h427931 : 57'd1 ;
assign _theResult____h453170 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^
12'h800) <
12'd2105) ?
result__h453783 :
_theResult____h435533 ;
assign _theResult____h500883 =
((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8630 ^
12'h800) <
12'd2105) ?
result__h501496 :
((value__h485099 == 25'd0) ? sfd__h480541 : 57'd1) ;
assign _theResult____h539684 =
((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10103 ^
12'h800) <
12'd2105) ?
result__h540297 :
((value__h523900 == 25'd0) ? sfd__h519483 : 57'd1) ;
assign _theResult____h578885 =
((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9340 ^
12'h800) <
12'd2105) ?
result__h579498 :
((value__h563101 == 25'd0) ? sfd__h558684 : 57'd1) ;
assign _theResult____h647536 =
(csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
enabled_ints___1__h648033 :
15'd0 ;
assign _theResult___exp__h352780 =
sfd__h352356[24] ?
((_theResult___fst_exp__h352264 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379297) :
((_theResult___fst_exp__h352264 == 8'd0 &&
sfd__h352356[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h352264) ;
assign _theResult___exp__h361362 =
sfd__h360938[24] ?
((_theResult___fst_exp__h360920 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379321) :
((_theResult___fst_exp__h360920 == 8'd0 &&
sfd__h360938[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h360920) ;
assign _theResult___exp__h370546 =
sfd__h370122[24] ?
((_theResult___fst_exp__h370030 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379351) :
((_theResult___fst_exp__h370030 == 8'd0 &&
sfd__h370122[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h370030) ;
assign _theResult___exp__h379182 =
sfd__h378734[24] ?
((_theResult___fst_exp__h378715 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379375) :
((_theResult___fst_exp__h378715 == 8'd0 &&
sfd__h378734[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h378715) ;
assign _theResult___exp__h379284 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h379275 ;
assign _theResult___exp__h398470 =
sfd__h398046[24] ?
((_theResult___fst_exp__h397954 == 8'd254) ?
8'd255 :
din_inc___2_exp__h424987) :
((_theResult___fst_exp__h397954 == 8'd0 &&
sfd__h398046[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h397954) ;
assign _theResult___exp__h407052 =
sfd__h406628[24] ?
((_theResult___fst_exp__h406610 == 8'd254) ?
8'd255 :
din_inc___2_exp__h425011) :
((_theResult___fst_exp__h406610 == 8'd0 &&
sfd__h406628[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h406610) ;
assign _theResult___exp__h416236 =
sfd__h415812[24] ?
((_theResult___fst_exp__h415720 == 8'd254) ?
8'd255 :
din_inc___2_exp__h425041) :
((_theResult___fst_exp__h415720 == 8'd0 &&
sfd__h415812[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h415720) ;
assign _theResult___exp__h424872 =
sfd__h424424[24] ?
((_theResult___fst_exp__h424405 == 8'd254) ?
8'd255 :
din_inc___2_exp__h425065) :
((_theResult___fst_exp__h424405 == 8'd0 &&
sfd__h424424[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h424405) ;
assign _theResult___exp__h424974 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h424965 ;
assign _theResult___exp__h444158 =
sfd__h443734[24] ?
((_theResult___fst_exp__h443642 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470675) :
((_theResult___fst_exp__h443642 == 8'd0 &&
sfd__h443734[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h443642) ;
assign _theResult___exp__h452740 =
sfd__h452316[24] ?
((_theResult___fst_exp__h452298 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470699) :
((_theResult___fst_exp__h452298 == 8'd0 &&
sfd__h452316[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h452298) ;
assign _theResult___exp__h461924 =
sfd__h461500[24] ?
((_theResult___fst_exp__h461408 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470729) :
((_theResult___fst_exp__h461408 == 8'd0 &&
sfd__h461500[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h461408) ;
assign _theResult___exp__h470560 =
sfd__h470112[24] ?
((_theResult___fst_exp__h470093 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470753) :
((_theResult___fst_exp__h470093 == 8'd0 &&
sfd__h470112[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h470093) ;
assign _theResult___exp__h470662 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h470653 ;
assign _theResult___exp__h500197 =
sfd__h499560[53] ?
((_theResult___fst_exp__h499542 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h518792) :
((_theResult___fst_exp__h499542 == 11'd0 &&
sfd__h499560[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h499542) ;
assign _theResult___exp__h509848 =
sfd__h509211[53] ?
((_theResult___fst_exp__h509119 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h518827) :
((_theResult___fst_exp__h509119 == 11'd0 &&
sfd__h509211[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h509119) ;
assign _theResult___exp__h518632 =
sfd__h517971[53] ?
((_theResult___fst_exp__h517952 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h518853) :
((_theResult___fst_exp__h517952 == 11'd0 &&
sfd__h517971[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h517952) ;
assign _theResult___exp__h538998 =
sfd__h538361[53] ?
((_theResult___fst_exp__h538343 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h557593) :
((_theResult___fst_exp__h538343 == 11'd0 &&
sfd__h538361[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h538343) ;
assign _theResult___exp__h548649 =
sfd__h548012[53] ?
((_theResult___fst_exp__h547920 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h557628) :
((_theResult___fst_exp__h547920 == 11'd0 &&
sfd__h548012[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h547920) ;
assign _theResult___exp__h557433 =
sfd__h556772[53] ?
((_theResult___fst_exp__h556753 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h557654) :
((_theResult___fst_exp__h556753 == 11'd0 &&
sfd__h556772[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h556753) ;
assign _theResult___exp__h578199 =
sfd__h577562[53] ?
((_theResult___fst_exp__h577544 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h596794) :
((_theResult___fst_exp__h577544 == 11'd0 &&
sfd__h577562[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h577544) ;
assign _theResult___exp__h587850 =
sfd__h587213[53] ?
((_theResult___fst_exp__h587121 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h596829) :
((_theResult___fst_exp__h587121 == 11'd0 &&
sfd__h587213[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h587121) ;
assign _theResult___exp__h596634 =
sfd__h595973[53] ?
((_theResult___fst_exp__h595954 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h596855) :
((_theResult___fst_exp__h595954 == 11'd0 &&
sfd__h595973[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h595954) ;
assign _theResult___fst__h601253 =
a__h600705[63] ? a___1__h601258 : a__h600705 ;
assign _theResult___fst_exp__h352264 =
_theResult____h344153[56] ?
8'd2 :
_theResult___fst_exp__h352338 ;
assign _theResult___fst_exp__h352329 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ;
assign _theResult___fst_exp__h352335 =
(!_theResult____h344153[56] && !_theResult____h344153[55] &&
!_theResult____h344153[54] &&
!_theResult____h344153[53] &&
!_theResult____h344153[52] &&
!_theResult____h344153[51] &&
!_theResult____h344153[50] &&
!_theResult____h344153[49] &&
!_theResult____h344153[48] &&
!_theResult____h344153[47] &&
!_theResult____h344153[46] &&
!_theResult____h344153[45] &&
!_theResult____h344153[44] &&
!_theResult____h344153[43] &&
!_theResult____h344153[42] &&
!_theResult____h344153[41] &&
!_theResult____h344153[40] &&
!_theResult____h344153[39] &&
!_theResult____h344153[38] &&
!_theResult____h344153[37] &&
!_theResult____h344153[36] &&
!_theResult____h344153[35] &&
!_theResult____h344153[34] &&
!_theResult____h344153[33] &&
!_theResult____h344153[32] &&
!_theResult____h344153[31] &&
!_theResult____h344153[30] &&
!_theResult____h344153[29] &&
!_theResult____h344153[28] &&
!_theResult____h344153[27] &&
!_theResult____h344153[26] &&
!_theResult____h344153[25] &&
!_theResult____h344153[24] &&
!_theResult____h344153[23] &&
!_theResult____h344153[22] &&
!_theResult____h344153[21] &&
!_theResult____h344153[20] &&
!_theResult____h344153[19] &&
!_theResult____h344153[18] &&
!_theResult____h344153[17] &&
!_theResult____h344153[16] &&
!_theResult____h344153[15] &&
!_theResult____h344153[14] &&
!_theResult____h344153[13] &&
!_theResult____h344153[12] &&
!_theResult____h344153[11] &&
!_theResult____h344153[10] &&
!_theResult____h344153[9] &&
!_theResult____h344153[8] &&
!_theResult____h344153[7] &&
!_theResult____h344153[6] &&
!_theResult____h344153[5] &&
!_theResult____h344153[4] &&
!_theResult____h344153[3] &&
!_theResult____h344153[2] &&
!_theResult____h344153[1] &&
!_theResult____h344153[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ?
8'd0 :
_theResult___fst_exp__h352329 ;
assign _theResult___fst_exp__h352338 =
(!_theResult____h344153[56] && _theResult____h344153[55]) ?
8'd1 :
_theResult___fst_exp__h352335 ;
assign _theResult___fst_exp__h352861 =
(_theResult___fst_exp__h352264 == 8'd255) ?
_theResult___fst_exp__h352264 :
_theResult___fst_exp__h352858 ;
assign _theResult___fst_exp__h360911 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ;
assign _theResult___fst_exp__h360917 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ?
8'd0 :
_theResult___fst_exp__h360911 ;
assign _theResult___fst_exp__h360920 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h360917 :
8'd129 ;
assign _theResult___fst_exp__h361443 =
(_theResult___fst_exp__h360920 == 8'd255) ?
_theResult___fst_exp__h360920 :
_theResult___fst_exp__h361440 ;
assign _theResult___fst_exp__h370030 =
_theResult____h361792[56] ?
8'd2 :
_theResult___fst_exp__h370104 ;
assign _theResult___fst_exp__h370095 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ;
assign _theResult___fst_exp__h370101 =
(!_theResult____h361792[56] && !_theResult____h361792[55] &&
!_theResult____h361792[54] &&
!_theResult____h361792[53] &&
!_theResult____h361792[52] &&
!_theResult____h361792[51] &&
!_theResult____h361792[50] &&
!_theResult____h361792[49] &&
!_theResult____h361792[48] &&
!_theResult____h361792[47] &&
!_theResult____h361792[46] &&
!_theResult____h361792[45] &&
!_theResult____h361792[44] &&
!_theResult____h361792[43] &&
!_theResult____h361792[42] &&
!_theResult____h361792[41] &&
!_theResult____h361792[40] &&
!_theResult____h361792[39] &&
!_theResult____h361792[38] &&
!_theResult____h361792[37] &&
!_theResult____h361792[36] &&
!_theResult____h361792[35] &&
!_theResult____h361792[34] &&
!_theResult____h361792[33] &&
!_theResult____h361792[32] &&
!_theResult____h361792[31] &&
!_theResult____h361792[30] &&
!_theResult____h361792[29] &&
!_theResult____h361792[28] &&
!_theResult____h361792[27] &&
!_theResult____h361792[26] &&
!_theResult____h361792[25] &&
!_theResult____h361792[24] &&
!_theResult____h361792[23] &&
!_theResult____h361792[22] &&
!_theResult____h361792[21] &&
!_theResult____h361792[20] &&
!_theResult____h361792[19] &&
!_theResult____h361792[18] &&
!_theResult____h361792[17] &&
!_theResult____h361792[16] &&
!_theResult____h361792[15] &&
!_theResult____h361792[14] &&
!_theResult____h361792[13] &&
!_theResult____h361792[12] &&
!_theResult____h361792[11] &&
!_theResult____h361792[10] &&
!_theResult____h361792[9] &&
!_theResult____h361792[8] &&
!_theResult____h361792[7] &&
!_theResult____h361792[6] &&
!_theResult____h361792[5] &&
!_theResult____h361792[4] &&
!_theResult____h361792[3] &&
!_theResult____h361792[2] &&
!_theResult____h361792[1] &&
!_theResult____h361792[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ?
8'd0 :
_theResult___fst_exp__h370095 ;
assign _theResult___fst_exp__h370104 =
(!_theResult____h361792[56] && _theResult____h361792[55]) ?
8'd1 :
_theResult___fst_exp__h370101 ;
assign _theResult___fst_exp__h370627 =
(_theResult___fst_exp__h370030 == 8'd255) ?
_theResult___fst_exp__h370030 :
_theResult___fst_exp__h370624 ;
assign _theResult___fst_exp__h378667 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ;
assign _theResult___fst_exp__h378706 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ;
assign _theResult___fst_exp__h378712 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ?
8'd0 :
_theResult___fst_exp__h378706 ;
assign _theResult___fst_exp__h378715 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h378712 :
_theResult___fst_exp__h378667 ;
assign _theResult___fst_exp__h379263 =
(_theResult___fst_exp__h378715 == 8'd255) ?
_theResult___fst_exp__h378715 :
_theResult___fst_exp__h379260 ;
assign _theResult___fst_exp__h379272 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
_theResult___snd_fst_exp__h361446 :
_theResult___fst_exp__h344135) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
_theResult___snd_fst_exp__h379266 :
_theResult___fst_exp__h344135) ;
assign _theResult___fst_exp__h379275 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h379272 ;
assign _theResult___fst_exp__h397954 =
_theResult____h389845[56] ?
8'd2 :
_theResult___fst_exp__h398028 ;
assign _theResult___fst_exp__h398019 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ;
assign _theResult___fst_exp__h398025 =
(!_theResult____h389845[56] && !_theResult____h389845[55] &&
!_theResult____h389845[54] &&
!_theResult____h389845[53] &&
!_theResult____h389845[52] &&
!_theResult____h389845[51] &&
!_theResult____h389845[50] &&
!_theResult____h389845[49] &&
!_theResult____h389845[48] &&
!_theResult____h389845[47] &&
!_theResult____h389845[46] &&
!_theResult____h389845[45] &&
!_theResult____h389845[44] &&
!_theResult____h389845[43] &&
!_theResult____h389845[42] &&
!_theResult____h389845[41] &&
!_theResult____h389845[40] &&
!_theResult____h389845[39] &&
!_theResult____h389845[38] &&
!_theResult____h389845[37] &&
!_theResult____h389845[36] &&
!_theResult____h389845[35] &&
!_theResult____h389845[34] &&
!_theResult____h389845[33] &&
!_theResult____h389845[32] &&
!_theResult____h389845[31] &&
!_theResult____h389845[30] &&
!_theResult____h389845[29] &&
!_theResult____h389845[28] &&
!_theResult____h389845[27] &&
!_theResult____h389845[26] &&
!_theResult____h389845[25] &&
!_theResult____h389845[24] &&
!_theResult____h389845[23] &&
!_theResult____h389845[22] &&
!_theResult____h389845[21] &&
!_theResult____h389845[20] &&
!_theResult____h389845[19] &&
!_theResult____h389845[18] &&
!_theResult____h389845[17] &&
!_theResult____h389845[16] &&
!_theResult____h389845[15] &&
!_theResult____h389845[14] &&
!_theResult____h389845[13] &&
!_theResult____h389845[12] &&
!_theResult____h389845[11] &&
!_theResult____h389845[10] &&
!_theResult____h389845[9] &&
!_theResult____h389845[8] &&
!_theResult____h389845[7] &&
!_theResult____h389845[6] &&
!_theResult____h389845[5] &&
!_theResult____h389845[4] &&
!_theResult____h389845[3] &&
!_theResult____h389845[2] &&
!_theResult____h389845[1] &&
!_theResult____h389845[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ?
8'd0 :
_theResult___fst_exp__h398019 ;
assign _theResult___fst_exp__h398028 =
(!_theResult____h389845[56] && _theResult____h389845[55]) ?
8'd1 :
_theResult___fst_exp__h398025 ;
assign _theResult___fst_exp__h398551 =
(_theResult___fst_exp__h397954 == 8'd255) ?
_theResult___fst_exp__h397954 :
_theResult___fst_exp__h398548 ;
assign _theResult___fst_exp__h406601 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ;
assign _theResult___fst_exp__h406607 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ?
8'd0 :
_theResult___fst_exp__h406601 ;
assign _theResult___fst_exp__h406610 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h406607 :
8'd129 ;
assign _theResult___fst_exp__h407133 =
(_theResult___fst_exp__h406610 == 8'd255) ?
_theResult___fst_exp__h406610 :
_theResult___fst_exp__h407130 ;
assign _theResult___fst_exp__h415720 =
_theResult____h407482[56] ?
8'd2 :
_theResult___fst_exp__h415794 ;
assign _theResult___fst_exp__h415785 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ;
assign _theResult___fst_exp__h415791 =
(!_theResult____h407482[56] && !_theResult____h407482[55] &&
!_theResult____h407482[54] &&
!_theResult____h407482[53] &&
!_theResult____h407482[52] &&
!_theResult____h407482[51] &&
!_theResult____h407482[50] &&
!_theResult____h407482[49] &&
!_theResult____h407482[48] &&
!_theResult____h407482[47] &&
!_theResult____h407482[46] &&
!_theResult____h407482[45] &&
!_theResult____h407482[44] &&
!_theResult____h407482[43] &&
!_theResult____h407482[42] &&
!_theResult____h407482[41] &&
!_theResult____h407482[40] &&
!_theResult____h407482[39] &&
!_theResult____h407482[38] &&
!_theResult____h407482[37] &&
!_theResult____h407482[36] &&
!_theResult____h407482[35] &&
!_theResult____h407482[34] &&
!_theResult____h407482[33] &&
!_theResult____h407482[32] &&
!_theResult____h407482[31] &&
!_theResult____h407482[30] &&
!_theResult____h407482[29] &&
!_theResult____h407482[28] &&
!_theResult____h407482[27] &&
!_theResult____h407482[26] &&
!_theResult____h407482[25] &&
!_theResult____h407482[24] &&
!_theResult____h407482[23] &&
!_theResult____h407482[22] &&
!_theResult____h407482[21] &&
!_theResult____h407482[20] &&
!_theResult____h407482[19] &&
!_theResult____h407482[18] &&
!_theResult____h407482[17] &&
!_theResult____h407482[16] &&
!_theResult____h407482[15] &&
!_theResult____h407482[14] &&
!_theResult____h407482[13] &&
!_theResult____h407482[12] &&
!_theResult____h407482[11] &&
!_theResult____h407482[10] &&
!_theResult____h407482[9] &&
!_theResult____h407482[8] &&
!_theResult____h407482[7] &&
!_theResult____h407482[6] &&
!_theResult____h407482[5] &&
!_theResult____h407482[4] &&
!_theResult____h407482[3] &&
!_theResult____h407482[2] &&
!_theResult____h407482[1] &&
!_theResult____h407482[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ?
8'd0 :
_theResult___fst_exp__h415785 ;
assign _theResult___fst_exp__h415794 =
(!_theResult____h407482[56] && _theResult____h407482[55]) ?
8'd1 :
_theResult___fst_exp__h415791 ;
assign _theResult___fst_exp__h416317 =
(_theResult___fst_exp__h415720 == 8'd255) ?
_theResult___fst_exp__h415720 :
_theResult___fst_exp__h416314 ;
assign _theResult___fst_exp__h424357 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ;
assign _theResult___fst_exp__h424396 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ;
assign _theResult___fst_exp__h424402 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ?
8'd0 :
_theResult___fst_exp__h424396 ;
assign _theResult___fst_exp__h424405 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h424402 :
_theResult___fst_exp__h424357 ;
assign _theResult___fst_exp__h424953 =
(_theResult___fst_exp__h424405 == 8'd255) ?
_theResult___fst_exp__h424405 :
_theResult___fst_exp__h424950 ;
assign _theResult___fst_exp__h424962 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
_theResult___snd_fst_exp__h407136 :
_theResult___fst_exp__h389827) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
_theResult___snd_fst_exp__h424956 :
_theResult___fst_exp__h389827) ;
assign _theResult___fst_exp__h424965 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h424962 ;
assign _theResult___fst_exp__h443642 =
_theResult____h435533[56] ?
8'd2 :
_theResult___fst_exp__h443716 ;
assign _theResult___fst_exp__h443707 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ;
assign _theResult___fst_exp__h443713 =
(!_theResult____h435533[56] && !_theResult____h435533[55] &&
!_theResult____h435533[54] &&
!_theResult____h435533[53] &&
!_theResult____h435533[52] &&
!_theResult____h435533[51] &&
!_theResult____h435533[50] &&
!_theResult____h435533[49] &&
!_theResult____h435533[48] &&
!_theResult____h435533[47] &&
!_theResult____h435533[46] &&
!_theResult____h435533[45] &&
!_theResult____h435533[44] &&
!_theResult____h435533[43] &&
!_theResult____h435533[42] &&
!_theResult____h435533[41] &&
!_theResult____h435533[40] &&
!_theResult____h435533[39] &&
!_theResult____h435533[38] &&
!_theResult____h435533[37] &&
!_theResult____h435533[36] &&
!_theResult____h435533[35] &&
!_theResult____h435533[34] &&
!_theResult____h435533[33] &&
!_theResult____h435533[32] &&
!_theResult____h435533[31] &&
!_theResult____h435533[30] &&
!_theResult____h435533[29] &&
!_theResult____h435533[28] &&
!_theResult____h435533[27] &&
!_theResult____h435533[26] &&
!_theResult____h435533[25] &&
!_theResult____h435533[24] &&
!_theResult____h435533[23] &&
!_theResult____h435533[22] &&
!_theResult____h435533[21] &&
!_theResult____h435533[20] &&
!_theResult____h435533[19] &&
!_theResult____h435533[18] &&
!_theResult____h435533[17] &&
!_theResult____h435533[16] &&
!_theResult____h435533[15] &&
!_theResult____h435533[14] &&
!_theResult____h435533[13] &&
!_theResult____h435533[12] &&
!_theResult____h435533[11] &&
!_theResult____h435533[10] &&
!_theResult____h435533[9] &&
!_theResult____h435533[8] &&
!_theResult____h435533[7] &&
!_theResult____h435533[6] &&
!_theResult____h435533[5] &&
!_theResult____h435533[4] &&
!_theResult____h435533[3] &&
!_theResult____h435533[2] &&
!_theResult____h435533[1] &&
!_theResult____h435533[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ?
8'd0 :
_theResult___fst_exp__h443707 ;
assign _theResult___fst_exp__h443716 =
(!_theResult____h435533[56] && _theResult____h435533[55]) ?
8'd1 :
_theResult___fst_exp__h443713 ;
assign _theResult___fst_exp__h444239 =
(_theResult___fst_exp__h443642 == 8'd255) ?
_theResult___fst_exp__h443642 :
_theResult___fst_exp__h444236 ;
assign _theResult___fst_exp__h452289 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ;
assign _theResult___fst_exp__h452295 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ?
8'd0 :
_theResult___fst_exp__h452289 ;
assign _theResult___fst_exp__h452298 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h452295 :
8'd129 ;
assign _theResult___fst_exp__h452821 =
(_theResult___fst_exp__h452298 == 8'd255) ?
_theResult___fst_exp__h452298 :
_theResult___fst_exp__h452818 ;
assign _theResult___fst_exp__h461408 =
_theResult____h453170[56] ?
8'd2 :
_theResult___fst_exp__h461482 ;
assign _theResult___fst_exp__h461473 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ;
assign _theResult___fst_exp__h461479 =
(!_theResult____h453170[56] && !_theResult____h453170[55] &&
!_theResult____h453170[54] &&
!_theResult____h453170[53] &&
!_theResult____h453170[52] &&
!_theResult____h453170[51] &&
!_theResult____h453170[50] &&
!_theResult____h453170[49] &&
!_theResult____h453170[48] &&
!_theResult____h453170[47] &&
!_theResult____h453170[46] &&
!_theResult____h453170[45] &&
!_theResult____h453170[44] &&
!_theResult____h453170[43] &&
!_theResult____h453170[42] &&
!_theResult____h453170[41] &&
!_theResult____h453170[40] &&
!_theResult____h453170[39] &&
!_theResult____h453170[38] &&
!_theResult____h453170[37] &&
!_theResult____h453170[36] &&
!_theResult____h453170[35] &&
!_theResult____h453170[34] &&
!_theResult____h453170[33] &&
!_theResult____h453170[32] &&
!_theResult____h453170[31] &&
!_theResult____h453170[30] &&
!_theResult____h453170[29] &&
!_theResult____h453170[28] &&
!_theResult____h453170[27] &&
!_theResult____h453170[26] &&
!_theResult____h453170[25] &&
!_theResult____h453170[24] &&
!_theResult____h453170[23] &&
!_theResult____h453170[22] &&
!_theResult____h453170[21] &&
!_theResult____h453170[20] &&
!_theResult____h453170[19] &&
!_theResult____h453170[18] &&
!_theResult____h453170[17] &&
!_theResult____h453170[16] &&
!_theResult____h453170[15] &&
!_theResult____h453170[14] &&
!_theResult____h453170[13] &&
!_theResult____h453170[12] &&
!_theResult____h453170[11] &&
!_theResult____h453170[10] &&
!_theResult____h453170[9] &&
!_theResult____h453170[8] &&
!_theResult____h453170[7] &&
!_theResult____h453170[6] &&
!_theResult____h453170[5] &&
!_theResult____h453170[4] &&
!_theResult____h453170[3] &&
!_theResult____h453170[2] &&
!_theResult____h453170[1] &&
!_theResult____h453170[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ?
8'd0 :
_theResult___fst_exp__h461473 ;
assign _theResult___fst_exp__h461482 =
(!_theResult____h453170[56] && _theResult____h453170[55]) ?
8'd1 :
_theResult___fst_exp__h461479 ;
assign _theResult___fst_exp__h462005 =
(_theResult___fst_exp__h461408 == 8'd255) ?
_theResult___fst_exp__h461408 :
_theResult___fst_exp__h462002 ;
assign _theResult___fst_exp__h470045 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ;
assign _theResult___fst_exp__h470084 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ;
assign _theResult___fst_exp__h470090 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ?
8'd0 :
_theResult___fst_exp__h470084 ;
assign _theResult___fst_exp__h470093 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h470090 :
_theResult___fst_exp__h470045 ;
assign _theResult___fst_exp__h470641 =
(_theResult___fst_exp__h470093 == 8'd255) ?
_theResult___fst_exp__h470093 :
_theResult___fst_exp__h470638 ;
assign _theResult___fst_exp__h470650 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
_theResult___snd_fst_exp__h452824 :
_theResult___fst_exp__h435515) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
_theResult___snd_fst_exp__h470644 :
_theResult___fst_exp__h435515) ;
assign _theResult___fst_exp__h470653 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h470650 ;
assign _theResult___fst_exp__h484469 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ;
assign _theResult___fst_exp__h499533 =
11'd897 -
{ 5'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564 } ;
assign _theResult___fst_exp__h499539 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8537 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8566) ?
11'd0 :
_theResult___fst_exp__h499533 ;
assign _theResult___fst_exp__h499542 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_theResult___fst_exp__h499539 :
11'd897 ;
assign _theResult___fst_exp__h500297 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q136 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000 ;
assign _theResult___fst_exp__h500300 =
(_theResult___fst_exp__h499542 == 11'd2047) ?
_theResult___fst_exp__h499542 :
_theResult___fst_exp__h500297 ;
assign _theResult___fst_exp__h509119 =
_theResult____h500883[56] ?
11'd2 :
_theResult___fst_exp__h509193 ;
assign _theResult___fst_exp__h509184 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8876 } ;
assign _theResult___fst_exp__h509190 =
(!_theResult____h500883[56] && !_theResult____h500883[55] &&
!_theResult____h500883[54] &&
!_theResult____h500883[53] &&
!_theResult____h500883[52] &&
!_theResult____h500883[51] &&
!_theResult____h500883[50] &&
!_theResult____h500883[49] &&
!_theResult____h500883[48] &&
!_theResult____h500883[47] &&
!_theResult____h500883[46] &&
!_theResult____h500883[45] &&
!_theResult____h500883[44] &&
!_theResult____h500883[43] &&
!_theResult____h500883[42] &&
!_theResult____h500883[41] &&
!_theResult____h500883[40] &&
!_theResult____h500883[39] &&
!_theResult____h500883[38] &&
!_theResult____h500883[37] &&
!_theResult____h500883[36] &&
!_theResult____h500883[35] &&
!_theResult____h500883[34] &&
!_theResult____h500883[33] &&
!_theResult____h500883[32] &&
!_theResult____h500883[31] &&
!_theResult____h500883[30] &&
!_theResult____h500883[29] &&
!_theResult____h500883[28] &&
!_theResult____h500883[27] &&
!_theResult____h500883[26] &&
!_theResult____h500883[25] &&
!_theResult____h500883[24] &&
!_theResult____h500883[23] &&
!_theResult____h500883[22] &&
!_theResult____h500883[21] &&
!_theResult____h500883[20] &&
!_theResult____h500883[19] &&
!_theResult____h500883[18] &&
!_theResult____h500883[17] &&
!_theResult____h500883[16] &&
!_theResult____h500883[15] &&
!_theResult____h500883[14] &&
!_theResult____h500883[13] &&
!_theResult____h500883[12] &&
!_theResult____h500883[11] &&
!_theResult____h500883[10] &&
!_theResult____h500883[9] &&
!_theResult____h500883[8] &&
!_theResult____h500883[7] &&
!_theResult____h500883[6] &&
!_theResult____h500883[5] &&
!_theResult____h500883[4] &&
!_theResult____h500883[3] &&
!_theResult____h500883[2] &&
!_theResult____h500883[1] &&
!_theResult____h500883[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8878) ?
11'd0 :
_theResult___fst_exp__h509184 ;
assign _theResult___fst_exp__h509193 =
(!_theResult____h500883[56] && _theResult____h500883[55]) ?
11'd1 :
_theResult___fst_exp__h509190 ;
assign _theResult___fst_exp__h509948 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q204 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043 ;
assign _theResult___fst_exp__h509951 =
(_theResult___fst_exp__h509119 == 11'd2047) ?
_theResult___fst_exp__h509119 :
_theResult___fst_exp__h509948 ;
assign _theResult___fst_exp__h517904 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ==
11'd0) ?
11'd1 :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ;
assign _theResult___fst_exp__h517943 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] -
{ 5'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564 } ;
assign _theResult___fst_exp__h517949 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8537 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8928) ?
11'd0 :
_theResult___fst_exp__h517943 ;
assign _theResult___fst_exp__h517952 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_theResult___fst_exp__h517949 :
_theResult___fst_exp__h517904 ;
assign _theResult___fst_exp__h518732 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q206 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074 ;
assign _theResult___fst_exp__h518735 =
(_theResult___fst_exp__h517952 == 11'd2047) ?
_theResult___fst_exp__h517952 :
_theResult___fst_exp__h518732 ;
assign _theResult___fst_exp__h518744 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 ?
_theResult___snd_fst_exp__h500303 :
_theResult___fst_exp__h484469) :
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 ?
_theResult___snd_fst_exp__h518738 :
_theResult___fst_exp__h484469) ;
assign _theResult___fst_exp__h518747 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h518744 ;
assign _theResult___fst_exp__h523270 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ;
assign _theResult___fst_exp__h538334 =
11'd897 -
{ 5'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052 } ;
assign _theResult___fst_exp__h538340 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10025 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10054) ?
11'd0 :
_theResult___fst_exp__h538334 ;
assign _theResult___fst_exp__h538343 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_theResult___fst_exp__h538340 :
11'd897 ;
assign _theResult___fst_exp__h539098 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q176 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473 ;
assign _theResult___fst_exp__h539101 =
(_theResult___fst_exp__h538343 == 11'd2047) ?
_theResult___fst_exp__h538343 :
_theResult___fst_exp__h539098 ;
assign _theResult___fst_exp__h547920 =
_theResult____h539684[56] ?
11'd2 :
_theResult___fst_exp__h547994 ;
assign _theResult___fst_exp__h547985 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10349 } ;
assign _theResult___fst_exp__h547991 =
(!_theResult____h539684[56] && !_theResult____h539684[55] &&
!_theResult____h539684[54] &&
!_theResult____h539684[53] &&
!_theResult____h539684[52] &&
!_theResult____h539684[51] &&
!_theResult____h539684[50] &&
!_theResult____h539684[49] &&
!_theResult____h539684[48] &&
!_theResult____h539684[47] &&
!_theResult____h539684[46] &&
!_theResult____h539684[45] &&
!_theResult____h539684[44] &&
!_theResult____h539684[43] &&
!_theResult____h539684[42] &&
!_theResult____h539684[41] &&
!_theResult____h539684[40] &&
!_theResult____h539684[39] &&
!_theResult____h539684[38] &&
!_theResult____h539684[37] &&
!_theResult____h539684[36] &&
!_theResult____h539684[35] &&
!_theResult____h539684[34] &&
!_theResult____h539684[33] &&
!_theResult____h539684[32] &&
!_theResult____h539684[31] &&
!_theResult____h539684[30] &&
!_theResult____h539684[29] &&
!_theResult____h539684[28] &&
!_theResult____h539684[27] &&
!_theResult____h539684[26] &&
!_theResult____h539684[25] &&
!_theResult____h539684[24] &&
!_theResult____h539684[23] &&
!_theResult____h539684[22] &&
!_theResult____h539684[21] &&
!_theResult____h539684[20] &&
!_theResult____h539684[19] &&
!_theResult____h539684[18] &&
!_theResult____h539684[17] &&
!_theResult____h539684[16] &&
!_theResult____h539684[15] &&
!_theResult____h539684[14] &&
!_theResult____h539684[13] &&
!_theResult____h539684[12] &&
!_theResult____h539684[11] &&
!_theResult____h539684[10] &&
!_theResult____h539684[9] &&
!_theResult____h539684[8] &&
!_theResult____h539684[7] &&
!_theResult____h539684[6] &&
!_theResult____h539684[5] &&
!_theResult____h539684[4] &&
!_theResult____h539684[3] &&
!_theResult____h539684[2] &&
!_theResult____h539684[1] &&
!_theResult____h539684[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10351) ?
11'd0 :
_theResult___fst_exp__h547985 ;
assign _theResult___fst_exp__h547994 =
(!_theResult____h539684[56] && _theResult____h539684[55]) ?
11'd1 :
_theResult___fst_exp__h547991 ;
assign _theResult___fst_exp__h548749 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q178 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511 ;
assign _theResult___fst_exp__h548752 =
(_theResult___fst_exp__h547920 == 11'd2047) ?
_theResult___fst_exp__h547920 :
_theResult___fst_exp__h548749 ;
assign _theResult___fst_exp__h556705 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ==
11'd0) ?
11'd1 :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ;
assign _theResult___fst_exp__h556744 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] -
{ 5'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052 } ;
assign _theResult___fst_exp__h556750 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10025 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10401) ?
11'd0 :
_theResult___fst_exp__h556744 ;
assign _theResult___fst_exp__h556753 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_theResult___fst_exp__h556750 :
_theResult___fst_exp__h556705 ;
assign _theResult___fst_exp__h557533 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q182 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542 ;
assign _theResult___fst_exp__h557536 =
(_theResult___fst_exp__h556753 == 11'd2047) ?
_theResult___fst_exp__h556753 :
_theResult___fst_exp__h557533 ;
assign _theResult___fst_exp__h557545 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 ?
_theResult___snd_fst_exp__h539104 :
_theResult___fst_exp__h523270) :
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 ?
_theResult___snd_fst_exp__h557539 :
_theResult___fst_exp__h523270) ;
assign _theResult___fst_exp__h557548 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h557545 ;
assign _theResult___fst_exp__h562471 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ;
assign _theResult___fst_exp__h577535 =
11'd897 -
{ 5'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289 } ;
assign _theResult___fst_exp__h577541 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d9262 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9291) ?
11'd0 :
_theResult___fst_exp__h577535 ;
assign _theResult___fst_exp__h577544 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_theResult___fst_exp__h577541 :
11'd897 ;
assign _theResult___fst_exp__h578299 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q153 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710 ;
assign _theResult___fst_exp__h578302 =
(_theResult___fst_exp__h577544 == 11'd2047) ?
_theResult___fst_exp__h577544 :
_theResult___fst_exp__h578299 ;
assign _theResult___fst_exp__h587121 =
_theResult____h578885[56] ?
11'd2 :
_theResult___fst_exp__h587195 ;
assign _theResult___fst_exp__h587186 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9586 } ;
assign _theResult___fst_exp__h587192 =
(!_theResult____h578885[56] && !_theResult____h578885[55] &&
!_theResult____h578885[54] &&
!_theResult____h578885[53] &&
!_theResult____h578885[52] &&
!_theResult____h578885[51] &&
!_theResult____h578885[50] &&
!_theResult____h578885[49] &&
!_theResult____h578885[48] &&
!_theResult____h578885[47] &&
!_theResult____h578885[46] &&
!_theResult____h578885[45] &&
!_theResult____h578885[44] &&
!_theResult____h578885[43] &&
!_theResult____h578885[42] &&
!_theResult____h578885[41] &&
!_theResult____h578885[40] &&
!_theResult____h578885[39] &&
!_theResult____h578885[38] &&
!_theResult____h578885[37] &&
!_theResult____h578885[36] &&
!_theResult____h578885[35] &&
!_theResult____h578885[34] &&
!_theResult____h578885[33] &&
!_theResult____h578885[32] &&
!_theResult____h578885[31] &&
!_theResult____h578885[30] &&
!_theResult____h578885[29] &&
!_theResult____h578885[28] &&
!_theResult____h578885[27] &&
!_theResult____h578885[26] &&
!_theResult____h578885[25] &&
!_theResult____h578885[24] &&
!_theResult____h578885[23] &&
!_theResult____h578885[22] &&
!_theResult____h578885[21] &&
!_theResult____h578885[20] &&
!_theResult____h578885[19] &&
!_theResult____h578885[18] &&
!_theResult____h578885[17] &&
!_theResult____h578885[16] &&
!_theResult____h578885[15] &&
!_theResult____h578885[14] &&
!_theResult____h578885[13] &&
!_theResult____h578885[12] &&
!_theResult____h578885[11] &&
!_theResult____h578885[10] &&
!_theResult____h578885[9] &&
!_theResult____h578885[8] &&
!_theResult____h578885[7] &&
!_theResult____h578885[6] &&
!_theResult____h578885[5] &&
!_theResult____h578885[4] &&
!_theResult____h578885[3] &&
!_theResult____h578885[2] &&
!_theResult____h578885[1] &&
!_theResult____h578885[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9588) ?
11'd0 :
_theResult___fst_exp__h587186 ;
assign _theResult___fst_exp__h587195 =
(!_theResult____h578885[56] && _theResult____h578885[55]) ?
11'd1 :
_theResult___fst_exp__h587192 ;
assign _theResult___fst_exp__h587950 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q180 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748 ;
assign _theResult___fst_exp__h587953 =
(_theResult___fst_exp__h587121 == 11'd2047) ?
_theResult___fst_exp__h587121 :
_theResult___fst_exp__h587950 ;
assign _theResult___fst_exp__h595906 =
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ==
11'd0) ?
11'd1 :
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ;
assign _theResult___fst_exp__h595945 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] -
{ 5'd0,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289 } ;
assign _theResult___fst_exp__h595951 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d9262 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9638) ?
11'd0 :
_theResult___fst_exp__h595945 ;
assign _theResult___fst_exp__h595954 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_theResult___fst_exp__h595951 :
_theResult___fst_exp__h595906 ;
assign _theResult___fst_exp__h596734 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q184 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779 ;
assign _theResult___fst_exp__h596737 =
(_theResult___fst_exp__h595954 == 11'd2047) ?
_theResult___fst_exp__h595954 :
_theResult___fst_exp__h596734 ;
assign _theResult___fst_exp__h596746 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 ?
_theResult___snd_fst_exp__h578305 :
_theResult___fst_exp__h562471) :
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 ?
_theResult___snd_fst_exp__h596740 :
_theResult___fst_exp__h562471) ;
assign _theResult___fst_exp__h596749 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
11'd0 :
_theResult___fst_exp__h596746 ;
assign _theResult___fst_sfd__h352862 =
(_theResult___fst_exp__h352264 == 8'd255) ?
sfdin__h352258[56:34] :
_theResult___fst_sfd__h352859 ;
assign _theResult___fst_sfd__h361444 =
(_theResult___fst_exp__h360920 == 8'd255) ?
_theResult___snd__h360871[56:34] :
_theResult___fst_sfd__h361441 ;
assign _theResult___fst_sfd__h370628 =
(_theResult___fst_exp__h370030 == 8'd255) ?
sfdin__h370024[56:34] :
_theResult___fst_sfd__h370625 ;
assign _theResult___fst_sfd__h379264 =
(_theResult___fst_exp__h378715 == 8'd255) ?
_theResult___snd__h378661[56:34] :
_theResult___fst_sfd__h379261 ;
assign _theResult___fst_sfd__h379273 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
_theResult___snd_fst_sfd__h361447 :
_theResult___fst_sfd__h344136) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
_theResult___snd_fst_sfd__h379267 :
_theResult___fst_sfd__h344136) ;
assign _theResult___fst_sfd__h379279 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h379273 ;
assign _theResult___fst_sfd__h398552 =
(_theResult___fst_exp__h397954 == 8'd255) ?
sfdin__h397948[56:34] :
_theResult___fst_sfd__h398549 ;
assign _theResult___fst_sfd__h407134 =
(_theResult___fst_exp__h406610 == 8'd255) ?
_theResult___snd__h406561[56:34] :
_theResult___fst_sfd__h407131 ;
assign _theResult___fst_sfd__h416318 =
(_theResult___fst_exp__h415720 == 8'd255) ?
sfdin__h415714[56:34] :
_theResult___fst_sfd__h416315 ;
assign _theResult___fst_sfd__h424954 =
(_theResult___fst_exp__h424405 == 8'd255) ?
_theResult___snd__h424351[56:34] :
_theResult___fst_sfd__h424951 ;
assign _theResult___fst_sfd__h424963 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
_theResult___snd_fst_sfd__h407137 :
_theResult___fst_sfd__h389828) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
_theResult___snd_fst_sfd__h424957 :
_theResult___fst_sfd__h389828) ;
assign _theResult___fst_sfd__h424969 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h424963 ;
assign _theResult___fst_sfd__h444240 =
(_theResult___fst_exp__h443642 == 8'd255) ?
sfdin__h443636[56:34] :
_theResult___fst_sfd__h444237 ;
assign _theResult___fst_sfd__h452822 =
(_theResult___fst_exp__h452298 == 8'd255) ?
_theResult___snd__h452249[56:34] :
_theResult___fst_sfd__h452819 ;
assign _theResult___fst_sfd__h462006 =
(_theResult___fst_exp__h461408 == 8'd255) ?
sfdin__h461402[56:34] :
_theResult___fst_sfd__h462003 ;
assign _theResult___fst_sfd__h470642 =
(_theResult___fst_exp__h470093 == 8'd255) ?
_theResult___snd__h470039[56:34] :
_theResult___fst_sfd__h470639 ;
assign _theResult___fst_sfd__h470651 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
_theResult___snd_fst_sfd__h452825 :
_theResult___fst_sfd__h435516) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
_theResult___snd_fst_sfd__h470645 :
_theResult___fst_sfd__h435516) ;
assign _theResult___fst_sfd__h470657 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h470651 ;
assign _theResult___fst_sfd__h484470 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ;
assign _theResult___fst_sfd__h500298 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q208 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100 ;
assign _theResult___fst_sfd__h500301 =
(_theResult___fst_exp__h499542 == 11'd2047) ?
_theResult___snd__h499493[56:5] :
_theResult___fst_sfd__h500298 ;
assign _theResult___fst_sfd__h509949 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q212 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127 ;
assign _theResult___fst_sfd__h509952 =
(_theResult___fst_exp__h509119 == 11'd2047) ?
sfdin__h509113[56:5] :
_theResult___fst_sfd__h509949 ;
assign _theResult___fst_sfd__h518733 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q210 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146 ;
assign _theResult___fst_sfd__h518736 =
(_theResult___fst_exp__h517952 == 11'd2047) ?
_theResult___snd__h517898[56:5] :
_theResult___fst_sfd__h518733 ;
assign _theResult___fst_sfd__h518745 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8491 ?
_theResult___snd_fst_sfd__h500304 :
_theResult___fst_sfd__h484470) :
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8628 ?
_theResult___snd_fst_sfd__h518739 :
_theResult___fst_sfd__h484470) ;
assign _theResult___fst_sfd__h518751 =
((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h518745 ;
assign _theResult___fst_sfd__h523271 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ;
assign _theResult___fst_sfd__h539099 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q198 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568 ;
assign _theResult___fst_sfd__h539102 =
(_theResult___fst_exp__h538343 == 11'd2047) ?
_theResult___snd__h538294[56:5] :
_theResult___fst_sfd__h539099 ;
assign _theResult___fst_sfd__h548750 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q200 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594 ;
assign _theResult___fst_sfd__h548753 =
(_theResult___fst_exp__h547920 == 11'd2047) ?
sfdin__h547914[56:5] :
_theResult___fst_sfd__h548750 ;
assign _theResult___fst_sfd__h557534 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q202 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613 ;
assign _theResult___fst_sfd__h557537 =
(_theResult___fst_exp__h556753 == 11'd2047) ?
_theResult___snd__h556699[56:5] :
_theResult___fst_sfd__h557534 ;
assign _theResult___fst_sfd__h557546 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9979 ?
_theResult___snd_fst_sfd__h539105 :
_theResult___fst_sfd__h523271) :
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10101 ?
_theResult___snd_fst_sfd__h557540 :
_theResult___fst_sfd__h523271) ;
assign _theResult___fst_sfd__h557552 =
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h557546 ;
assign _theResult___fst_sfd__h562472 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ;
assign _theResult___fst_sfd__h578300 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q214 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805 ;
assign _theResult___fst_sfd__h578303 =
(_theResult___fst_exp__h577544 == 11'd2047) ?
_theResult___snd__h577495[56:5] :
_theResult___fst_sfd__h578300 ;
assign _theResult___fst_sfd__h587951 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q216 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831 ;
assign _theResult___fst_sfd__h587954 =
(_theResult___fst_exp__h587121 == 11'd2047) ?
sfdin__h587115[56:5] :
_theResult___fst_sfd__h587951 ;
assign _theResult___fst_sfd__h596735 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q218 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850 ;
assign _theResult___fst_sfd__h596738 =
(_theResult___fst_exp__h595954 == 11'd2047) ?
_theResult___snd__h595900[56:5] :
_theResult___fst_sfd__h596735 ;
assign _theResult___fst_sfd__h596747 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9216 ?
_theResult___snd_fst_sfd__h578306 :
_theResult___fst_sfd__h562472) :
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9338 ?
_theResult___snd_fst_sfd__h596741 :
_theResult___fst_sfd__h562472) ;
assign _theResult___fst_sfd__h596753 =
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h596747 ;
assign _theResult___sfd__h352781 =
sfd__h352356[24] ?
((_theResult___fst_exp__h352264 == 8'd254) ?
23'd0 :
sfd__h352356[23:1]) :
sfd__h352356[22:0] ;
assign _theResult___sfd__h361363 =
sfd__h360938[24] ?
((_theResult___fst_exp__h360920 == 8'd254) ?
23'd0 :
sfd__h360938[23:1]) :
sfd__h360938[22:0] ;
assign _theResult___sfd__h370547 =
sfd__h370122[24] ?
((_theResult___fst_exp__h370030 == 8'd254) ?
23'd0 :
sfd__h370122[23:1]) :
sfd__h370122[22:0] ;
assign _theResult___sfd__h379183 =
sfd__h378734[24] ?
((_theResult___fst_exp__h378715 == 8'd254) ?
23'd0 :
sfd__h378734[23:1]) :
sfd__h378734[22:0] ;
assign _theResult___sfd__h379285 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h336498 :
_theResult___fst_sfd__h379279 ;
assign _theResult___sfd__h398471 =
sfd__h398046[24] ?
((_theResult___fst_exp__h397954 == 8'd254) ?
23'd0 :
sfd__h398046[23:1]) :
sfd__h398046[22:0] ;
assign _theResult___sfd__h407053 =
sfd__h406628[24] ?
((_theResult___fst_exp__h406610 == 8'd254) ?
23'd0 :
sfd__h406628[23:1]) :
sfd__h406628[22:0] ;
assign _theResult___sfd__h416237 =
sfd__h415812[24] ?
((_theResult___fst_exp__h415720 == 8'd254) ?
23'd0 :
sfd__h415812[23:1]) :
sfd__h415812[22:0] ;
assign _theResult___sfd__h424873 =
sfd__h424424[24] ?
((_theResult___fst_exp__h424405 == 8'd254) ?
23'd0 :
sfd__h424424[23:1]) :
sfd__h424424[22:0] ;
assign _theResult___sfd__h424975 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h382193 :
_theResult___fst_sfd__h424969 ;
assign _theResult___sfd__h444159 =
sfd__h443734[24] ?
((_theResult___fst_exp__h443642 == 8'd254) ?
23'd0 :
sfd__h443734[23:1]) :
sfd__h443734[22:0] ;
assign _theResult___sfd__h452741 =
sfd__h452316[24] ?
((_theResult___fst_exp__h452298 == 8'd254) ?
23'd0 :
sfd__h452316[23:1]) :
sfd__h452316[22:0] ;
assign _theResult___sfd__h461925 =
sfd__h461500[24] ?
((_theResult___fst_exp__h461408 == 8'd254) ?
23'd0 :
sfd__h461500[23:1]) :
sfd__h461500[22:0] ;
assign _theResult___sfd__h470561 =
sfd__h470112[24] ?
((_theResult___fst_exp__h470093 == 8'd254) ?
23'd0 :
sfd__h470112[23:1]) :
sfd__h470112[22:0] ;
assign _theResult___sfd__h470663 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h427881 :
_theResult___fst_sfd__h470657 ;
assign _theResult___sfd__h500198 =
sfd__h499560[53] ?
((_theResult___fst_exp__h499542 == 11'd2046) ?
52'd0 :
sfd__h499560[52:1]) :
sfd__h499560[51:0] ;
assign _theResult___sfd__h509849 =
sfd__h509211[53] ?
((_theResult___fst_exp__h509119 == 11'd2046) ?
52'd0 :
sfd__h509211[52:1]) :
sfd__h509211[51:0] ;
assign _theResult___sfd__h518633 =
sfd__h517971[53] ?
((_theResult___fst_exp__h517952 == 11'd2046) ?
52'd0 :
sfd__h517971[52:1]) :
sfd__h517971[51:0] ;
assign _theResult___sfd__h538999 =
sfd__h538361[53] ?
((_theResult___fst_exp__h538343 == 11'd2046) ?
52'd0 :
sfd__h538361[52:1]) :
sfd__h538361[51:0] ;
assign _theResult___sfd__h548650 =
sfd__h548012[53] ?
((_theResult___fst_exp__h547920 == 11'd2046) ?
52'd0 :
sfd__h548012[52:1]) :
sfd__h548012[51:0] ;
assign _theResult___sfd__h557434 =
sfd__h556772[53] ?
((_theResult___fst_exp__h556753 == 11'd2046) ?
52'd0 :
sfd__h556772[52:1]) :
sfd__h556772[51:0] ;
assign _theResult___sfd__h578200 =
sfd__h577562[53] ?
((_theResult___fst_exp__h577544 == 11'd2046) ?
52'd0 :
sfd__h577562[52:1]) :
sfd__h577562[51:0] ;
assign _theResult___sfd__h587851 =
sfd__h587213[53] ?
((_theResult___fst_exp__h587121 == 11'd2046) ?
52'd0 :
sfd__h587213[52:1]) :
sfd__h587213[51:0] ;
assign _theResult___sfd__h596635 =
sfd__h595973[53] ?
((_theResult___fst_exp__h595954 == 11'd2046) ?
52'd0 :
sfd__h595973[52:1]) :
sfd__h595973[51:0] ;
assign _theResult___snd__h352275 = { _theResult____h344153[55:0], 1'd0 } ;
assign _theResult___snd__h352286 =
(!_theResult____h344153[56] && _theResult____h344153[55]) ?
_theResult___snd__h352288 :
_theResult___snd__h352298 ;
assign _theResult___snd__h352288 = { _theResult____h344153[54:0], 2'd0 } ;
assign _theResult___snd__h352298 =
(!_theResult____h344153[56] && !_theResult____h344153[55] &&
!_theResult____h344153[54] &&
!_theResult____h344153[53] &&
!_theResult____h344153[52] &&
!_theResult____h344153[51] &&
!_theResult____h344153[50] &&
!_theResult____h344153[49] &&
!_theResult____h344153[48] &&
!_theResult____h344153[47] &&
!_theResult____h344153[46] &&
!_theResult____h344153[45] &&
!_theResult____h344153[44] &&
!_theResult____h344153[43] &&
!_theResult____h344153[42] &&
!_theResult____h344153[41] &&
!_theResult____h344153[40] &&
!_theResult____h344153[39] &&
!_theResult____h344153[38] &&
!_theResult____h344153[37] &&
!_theResult____h344153[36] &&
!_theResult____h344153[35] &&
!_theResult____h344153[34] &&
!_theResult____h344153[33] &&
!_theResult____h344153[32] &&
!_theResult____h344153[31] &&
!_theResult____h344153[30] &&
!_theResult____h344153[29] &&
!_theResult____h344153[28] &&
!_theResult____h344153[27] &&
!_theResult____h344153[26] &&
!_theResult____h344153[25] &&
!_theResult____h344153[24] &&
!_theResult____h344153[23] &&
!_theResult____h344153[22] &&
!_theResult____h344153[21] &&
!_theResult____h344153[20] &&
!_theResult____h344153[19] &&
!_theResult____h344153[18] &&
!_theResult____h344153[17] &&
!_theResult____h344153[16] &&
!_theResult____h344153[15] &&
!_theResult____h344153[14] &&
!_theResult____h344153[13] &&
!_theResult____h344153[12] &&
!_theResult____h344153[11] &&
!_theResult____h344153[10] &&
!_theResult____h344153[9] &&
!_theResult____h344153[8] &&
!_theResult____h344153[7] &&
!_theResult____h344153[6] &&
!_theResult____h344153[5] &&
!_theResult____h344153[4] &&
!_theResult____h344153[3] &&
!_theResult____h344153[2] &&
!_theResult____h344153[1] &&
!_theResult____h344153[0]) ?
_theResult____h344153 :
_theResult___snd__h352304 ;
assign _theResult___snd__h352304 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0],
2'd0 } ;
assign _theResult___snd__h352327 =
_theResult____h344153 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ;
assign _theResult___snd__h360871 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h360880 :
_theResult___snd__h360873 ;
assign _theResult___snd__h360873 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h360880 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ?
sfd__h336548 :
_theResult___snd__h360886 ;
assign _theResult___snd__h360886 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0],
2'd0 } ;
assign _theResult___snd__h360909 =
sfd__h336548 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ;
assign _theResult___snd__h370041 = { _theResult____h361792[55:0], 1'd0 } ;
assign _theResult___snd__h370052 =
(!_theResult____h361792[56] && _theResult____h361792[55]) ?
_theResult___snd__h370054 :
_theResult___snd__h370064 ;
assign _theResult___snd__h370054 = { _theResult____h361792[54:0], 2'd0 } ;
assign _theResult___snd__h370064 =
(!_theResult____h361792[56] && !_theResult____h361792[55] &&
!_theResult____h361792[54] &&
!_theResult____h361792[53] &&
!_theResult____h361792[52] &&
!_theResult____h361792[51] &&
!_theResult____h361792[50] &&
!_theResult____h361792[49] &&
!_theResult____h361792[48] &&
!_theResult____h361792[47] &&
!_theResult____h361792[46] &&
!_theResult____h361792[45] &&
!_theResult____h361792[44] &&
!_theResult____h361792[43] &&
!_theResult____h361792[42] &&
!_theResult____h361792[41] &&
!_theResult____h361792[40] &&
!_theResult____h361792[39] &&
!_theResult____h361792[38] &&
!_theResult____h361792[37] &&
!_theResult____h361792[36] &&
!_theResult____h361792[35] &&
!_theResult____h361792[34] &&
!_theResult____h361792[33] &&
!_theResult____h361792[32] &&
!_theResult____h361792[31] &&
!_theResult____h361792[30] &&
!_theResult____h361792[29] &&
!_theResult____h361792[28] &&
!_theResult____h361792[27] &&
!_theResult____h361792[26] &&
!_theResult____h361792[25] &&
!_theResult____h361792[24] &&
!_theResult____h361792[23] &&
!_theResult____h361792[22] &&
!_theResult____h361792[21] &&
!_theResult____h361792[20] &&
!_theResult____h361792[19] &&
!_theResult____h361792[18] &&
!_theResult____h361792[17] &&
!_theResult____h361792[16] &&
!_theResult____h361792[15] &&
!_theResult____h361792[14] &&
!_theResult____h361792[13] &&
!_theResult____h361792[12] &&
!_theResult____h361792[11] &&
!_theResult____h361792[10] &&
!_theResult____h361792[9] &&
!_theResult____h361792[8] &&
!_theResult____h361792[7] &&
!_theResult____h361792[6] &&
!_theResult____h361792[5] &&
!_theResult____h361792[4] &&
!_theResult____h361792[3] &&
!_theResult____h361792[2] &&
!_theResult____h361792[1] &&
!_theResult____h361792[0]) ?
_theResult____h361792 :
_theResult___snd__h370070 ;
assign _theResult___snd__h370070 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0],
2'd0 } ;
assign _theResult___snd__h370093 =
_theResult____h361792 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ;
assign _theResult___snd__h378661 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h378675 :
_theResult___snd__h360873 ;
assign _theResult___snd__h378675 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ?
sfd__h336548 :
_theResult___snd__h378681 ;
assign _theResult___snd__h378681 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0],
2'd0 } ;
assign _theResult___snd__h378699 =
sfd__h336548 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ;
assign _theResult___snd__h397965 = { _theResult____h389845[55:0], 1'd0 } ;
assign _theResult___snd__h397976 =
(!_theResult____h389845[56] && _theResult____h389845[55]) ?
_theResult___snd__h397978 :
_theResult___snd__h397988 ;
assign _theResult___snd__h397978 = { _theResult____h389845[54:0], 2'd0 } ;
assign _theResult___snd__h397988 =
(!_theResult____h389845[56] && !_theResult____h389845[55] &&
!_theResult____h389845[54] &&
!_theResult____h389845[53] &&
!_theResult____h389845[52] &&
!_theResult____h389845[51] &&
!_theResult____h389845[50] &&
!_theResult____h389845[49] &&
!_theResult____h389845[48] &&
!_theResult____h389845[47] &&
!_theResult____h389845[46] &&
!_theResult____h389845[45] &&
!_theResult____h389845[44] &&
!_theResult____h389845[43] &&
!_theResult____h389845[42] &&
!_theResult____h389845[41] &&
!_theResult____h389845[40] &&
!_theResult____h389845[39] &&
!_theResult____h389845[38] &&
!_theResult____h389845[37] &&
!_theResult____h389845[36] &&
!_theResult____h389845[35] &&
!_theResult____h389845[34] &&
!_theResult____h389845[33] &&
!_theResult____h389845[32] &&
!_theResult____h389845[31] &&
!_theResult____h389845[30] &&
!_theResult____h389845[29] &&
!_theResult____h389845[28] &&
!_theResult____h389845[27] &&
!_theResult____h389845[26] &&
!_theResult____h389845[25] &&
!_theResult____h389845[24] &&
!_theResult____h389845[23] &&
!_theResult____h389845[22] &&
!_theResult____h389845[21] &&
!_theResult____h389845[20] &&
!_theResult____h389845[19] &&
!_theResult____h389845[18] &&
!_theResult____h389845[17] &&
!_theResult____h389845[16] &&
!_theResult____h389845[15] &&
!_theResult____h389845[14] &&
!_theResult____h389845[13] &&
!_theResult____h389845[12] &&
!_theResult____h389845[11] &&
!_theResult____h389845[10] &&
!_theResult____h389845[9] &&
!_theResult____h389845[8] &&
!_theResult____h389845[7] &&
!_theResult____h389845[6] &&
!_theResult____h389845[5] &&
!_theResult____h389845[4] &&
!_theResult____h389845[3] &&
!_theResult____h389845[2] &&
!_theResult____h389845[1] &&
!_theResult____h389845[0]) ?
_theResult____h389845 :
_theResult___snd__h397994 ;
assign _theResult___snd__h397994 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0],
2'd0 } ;
assign _theResult___snd__h398017 =
_theResult____h389845 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ;
assign _theResult___snd__h406561 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h406570 :
_theResult___snd__h406563 ;
assign _theResult___snd__h406563 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h406570 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ?
sfd__h382243 :
_theResult___snd__h406576 ;
assign _theResult___snd__h406576 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0],
2'd0 } ;
assign _theResult___snd__h406599 =
sfd__h382243 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ;
assign _theResult___snd__h415731 = { _theResult____h407482[55:0], 1'd0 } ;
assign _theResult___snd__h415742 =
(!_theResult____h407482[56] && _theResult____h407482[55]) ?
_theResult___snd__h415744 :
_theResult___snd__h415754 ;
assign _theResult___snd__h415744 = { _theResult____h407482[54:0], 2'd0 } ;
assign _theResult___snd__h415754 =
(!_theResult____h407482[56] && !_theResult____h407482[55] &&
!_theResult____h407482[54] &&
!_theResult____h407482[53] &&
!_theResult____h407482[52] &&
!_theResult____h407482[51] &&
!_theResult____h407482[50] &&
!_theResult____h407482[49] &&
!_theResult____h407482[48] &&
!_theResult____h407482[47] &&
!_theResult____h407482[46] &&
!_theResult____h407482[45] &&
!_theResult____h407482[44] &&
!_theResult____h407482[43] &&
!_theResult____h407482[42] &&
!_theResult____h407482[41] &&
!_theResult____h407482[40] &&
!_theResult____h407482[39] &&
!_theResult____h407482[38] &&
!_theResult____h407482[37] &&
!_theResult____h407482[36] &&
!_theResult____h407482[35] &&
!_theResult____h407482[34] &&
!_theResult____h407482[33] &&
!_theResult____h407482[32] &&
!_theResult____h407482[31] &&
!_theResult____h407482[30] &&
!_theResult____h407482[29] &&
!_theResult____h407482[28] &&
!_theResult____h407482[27] &&
!_theResult____h407482[26] &&
!_theResult____h407482[25] &&
!_theResult____h407482[24] &&
!_theResult____h407482[23] &&
!_theResult____h407482[22] &&
!_theResult____h407482[21] &&
!_theResult____h407482[20] &&
!_theResult____h407482[19] &&
!_theResult____h407482[18] &&
!_theResult____h407482[17] &&
!_theResult____h407482[16] &&
!_theResult____h407482[15] &&
!_theResult____h407482[14] &&
!_theResult____h407482[13] &&
!_theResult____h407482[12] &&
!_theResult____h407482[11] &&
!_theResult____h407482[10] &&
!_theResult____h407482[9] &&
!_theResult____h407482[8] &&
!_theResult____h407482[7] &&
!_theResult____h407482[6] &&
!_theResult____h407482[5] &&
!_theResult____h407482[4] &&
!_theResult____h407482[3] &&
!_theResult____h407482[2] &&
!_theResult____h407482[1] &&
!_theResult____h407482[0]) ?
_theResult____h407482 :
_theResult___snd__h415760 ;
assign _theResult___snd__h415760 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0],
2'd0 } ;
assign _theResult___snd__h415783 =
_theResult____h407482 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ;
assign _theResult___snd__h424351 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h424365 :
_theResult___snd__h406563 ;
assign _theResult___snd__h424365 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ?
sfd__h382243 :
_theResult___snd__h424371 ;
assign _theResult___snd__h424371 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0],
2'd0 } ;
assign _theResult___snd__h424389 =
sfd__h382243 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ;
assign _theResult___snd__h443653 = { _theResult____h435533[55:0], 1'd0 } ;
assign _theResult___snd__h443664 =
(!_theResult____h435533[56] && _theResult____h435533[55]) ?
_theResult___snd__h443666 :
_theResult___snd__h443676 ;
assign _theResult___snd__h443666 = { _theResult____h435533[54:0], 2'd0 } ;
assign _theResult___snd__h443676 =
(!_theResult____h435533[56] && !_theResult____h435533[55] &&
!_theResult____h435533[54] &&
!_theResult____h435533[53] &&
!_theResult____h435533[52] &&
!_theResult____h435533[51] &&
!_theResult____h435533[50] &&
!_theResult____h435533[49] &&
!_theResult____h435533[48] &&
!_theResult____h435533[47] &&
!_theResult____h435533[46] &&
!_theResult____h435533[45] &&
!_theResult____h435533[44] &&
!_theResult____h435533[43] &&
!_theResult____h435533[42] &&
!_theResult____h435533[41] &&
!_theResult____h435533[40] &&
!_theResult____h435533[39] &&
!_theResult____h435533[38] &&
!_theResult____h435533[37] &&
!_theResult____h435533[36] &&
!_theResult____h435533[35] &&
!_theResult____h435533[34] &&
!_theResult____h435533[33] &&
!_theResult____h435533[32] &&
!_theResult____h435533[31] &&
!_theResult____h435533[30] &&
!_theResult____h435533[29] &&
!_theResult____h435533[28] &&
!_theResult____h435533[27] &&
!_theResult____h435533[26] &&
!_theResult____h435533[25] &&
!_theResult____h435533[24] &&
!_theResult____h435533[23] &&
!_theResult____h435533[22] &&
!_theResult____h435533[21] &&
!_theResult____h435533[20] &&
!_theResult____h435533[19] &&
!_theResult____h435533[18] &&
!_theResult____h435533[17] &&
!_theResult____h435533[16] &&
!_theResult____h435533[15] &&
!_theResult____h435533[14] &&
!_theResult____h435533[13] &&
!_theResult____h435533[12] &&
!_theResult____h435533[11] &&
!_theResult____h435533[10] &&
!_theResult____h435533[9] &&
!_theResult____h435533[8] &&
!_theResult____h435533[7] &&
!_theResult____h435533[6] &&
!_theResult____h435533[5] &&
!_theResult____h435533[4] &&
!_theResult____h435533[3] &&
!_theResult____h435533[2] &&
!_theResult____h435533[1] &&
!_theResult____h435533[0]) ?
_theResult____h435533 :
_theResult___snd__h443682 ;
assign _theResult___snd__h443682 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0],
2'd0 } ;
assign _theResult___snd__h443705 =
_theResult____h435533 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ;
assign _theResult___snd__h452249 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h452258 :
_theResult___snd__h452251 ;
assign _theResult___snd__h452251 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h452258 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ?
sfd__h427931 :
_theResult___snd__h452264 ;
assign _theResult___snd__h452264 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0],
2'd0 } ;
assign _theResult___snd__h452287 =
sfd__h427931 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ;
assign _theResult___snd__h461419 = { _theResult____h453170[55:0], 1'd0 } ;
assign _theResult___snd__h461430 =
(!_theResult____h453170[56] && _theResult____h453170[55]) ?
_theResult___snd__h461432 :
_theResult___snd__h461442 ;
assign _theResult___snd__h461432 = { _theResult____h453170[54:0], 2'd0 } ;
assign _theResult___snd__h461442 =
(!_theResult____h453170[56] && !_theResult____h453170[55] &&
!_theResult____h453170[54] &&
!_theResult____h453170[53] &&
!_theResult____h453170[52] &&
!_theResult____h453170[51] &&
!_theResult____h453170[50] &&
!_theResult____h453170[49] &&
!_theResult____h453170[48] &&
!_theResult____h453170[47] &&
!_theResult____h453170[46] &&
!_theResult____h453170[45] &&
!_theResult____h453170[44] &&
!_theResult____h453170[43] &&
!_theResult____h453170[42] &&
!_theResult____h453170[41] &&
!_theResult____h453170[40] &&
!_theResult____h453170[39] &&
!_theResult____h453170[38] &&
!_theResult____h453170[37] &&
!_theResult____h453170[36] &&
!_theResult____h453170[35] &&
!_theResult____h453170[34] &&
!_theResult____h453170[33] &&
!_theResult____h453170[32] &&
!_theResult____h453170[31] &&
!_theResult____h453170[30] &&
!_theResult____h453170[29] &&
!_theResult____h453170[28] &&
!_theResult____h453170[27] &&
!_theResult____h453170[26] &&
!_theResult____h453170[25] &&
!_theResult____h453170[24] &&
!_theResult____h453170[23] &&
!_theResult____h453170[22] &&
!_theResult____h453170[21] &&
!_theResult____h453170[20] &&
!_theResult____h453170[19] &&
!_theResult____h453170[18] &&
!_theResult____h453170[17] &&
!_theResult____h453170[16] &&
!_theResult____h453170[15] &&
!_theResult____h453170[14] &&
!_theResult____h453170[13] &&
!_theResult____h453170[12] &&
!_theResult____h453170[11] &&
!_theResult____h453170[10] &&
!_theResult____h453170[9] &&
!_theResult____h453170[8] &&
!_theResult____h453170[7] &&
!_theResult____h453170[6] &&
!_theResult____h453170[5] &&
!_theResult____h453170[4] &&
!_theResult____h453170[3] &&
!_theResult____h453170[2] &&
!_theResult____h453170[1] &&
!_theResult____h453170[0]) ?
_theResult____h453170 :
_theResult___snd__h461448 ;
assign _theResult___snd__h461448 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0],
2'd0 } ;
assign _theResult___snd__h461471 =
_theResult____h453170 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ;
assign _theResult___snd__h470039 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h470053 :
_theResult___snd__h452251 ;
assign _theResult___snd__h470053 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ?
sfd__h427931 :
_theResult___snd__h470059 ;
assign _theResult___snd__h470059 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0],
2'd0 } ;
assign _theResult___snd__h470077 =
sfd__h427931 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ;
assign _theResult___snd__h499493 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_theResult___snd__h499502 :
_theResult___snd__h499495 ;
assign _theResult___snd__h499495 =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ;
assign _theResult___snd__h499502 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8537) ?
sfd__h480541 :
_theResult___snd__h499508 ;
assign _theResult___snd__h499508 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0],
2'd0 } ;
assign _theResult___snd__h499531 =
sfd__h480541 <<
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8564 ;
assign _theResult___snd__h509130 = { _theResult____h500883[55:0], 1'd0 } ;
assign _theResult___snd__h509141 =
(!_theResult____h500883[56] && _theResult____h500883[55]) ?
_theResult___snd__h509143 :
_theResult___snd__h509153 ;
assign _theResult___snd__h509143 = { _theResult____h500883[54:0], 2'd0 } ;
assign _theResult___snd__h509153 =
(!_theResult____h500883[56] && !_theResult____h500883[55] &&
!_theResult____h500883[54] &&
!_theResult____h500883[53] &&
!_theResult____h500883[52] &&
!_theResult____h500883[51] &&
!_theResult____h500883[50] &&
!_theResult____h500883[49] &&
!_theResult____h500883[48] &&
!_theResult____h500883[47] &&
!_theResult____h500883[46] &&
!_theResult____h500883[45] &&
!_theResult____h500883[44] &&
!_theResult____h500883[43] &&
!_theResult____h500883[42] &&
!_theResult____h500883[41] &&
!_theResult____h500883[40] &&
!_theResult____h500883[39] &&
!_theResult____h500883[38] &&
!_theResult____h500883[37] &&
!_theResult____h500883[36] &&
!_theResult____h500883[35] &&
!_theResult____h500883[34] &&
!_theResult____h500883[33] &&
!_theResult____h500883[32] &&
!_theResult____h500883[31] &&
!_theResult____h500883[30] &&
!_theResult____h500883[29] &&
!_theResult____h500883[28] &&
!_theResult____h500883[27] &&
!_theResult____h500883[26] &&
!_theResult____h500883[25] &&
!_theResult____h500883[24] &&
!_theResult____h500883[23] &&
!_theResult____h500883[22] &&
!_theResult____h500883[21] &&
!_theResult____h500883[20] &&
!_theResult____h500883[19] &&
!_theResult____h500883[18] &&
!_theResult____h500883[17] &&
!_theResult____h500883[16] &&
!_theResult____h500883[15] &&
!_theResult____h500883[14] &&
!_theResult____h500883[13] &&
!_theResult____h500883[12] &&
!_theResult____h500883[11] &&
!_theResult____h500883[10] &&
!_theResult____h500883[9] &&
!_theResult____h500883[8] &&
!_theResult____h500883[7] &&
!_theResult____h500883[6] &&
!_theResult____h500883[5] &&
!_theResult____h500883[4] &&
!_theResult____h500883[3] &&
!_theResult____h500883[2] &&
!_theResult____h500883[1] &&
!_theResult____h500883[0]) ?
_theResult____h500883 :
_theResult___snd__h509159 ;
assign _theResult___snd__h509159 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0],
2'd0 } ;
assign _theResult___snd__h509182 =
_theResult____h500883 <<
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8876 ;
assign _theResult___snd__h517898 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
_theResult___snd__h517912 :
_theResult___snd__h499495 ;
assign _theResult___snd__h517912 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d8537) ?
sfd__h480541 :
_theResult___snd__h517918 ;
assign _theResult___snd__h517918 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0],
2'd0 } ;
assign _theResult___snd__h517936 =
sfd__h480541 <<
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8927 ;
assign _theResult___snd__h538294 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_theResult___snd__h538303 :
_theResult___snd__h538296 ;
assign _theResult___snd__h538296 =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ;
assign _theResult___snd__h538303 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10025) ?
sfd__h519483 :
_theResult___snd__h538309 ;
assign _theResult___snd__h538309 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0],
2'd0 } ;
assign _theResult___snd__h538332 =
sfd__h519483 <<
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10052 ;
assign _theResult___snd__h547931 = { _theResult____h539684[55:0], 1'd0 } ;
assign _theResult___snd__h547942 =
(!_theResult____h539684[56] && _theResult____h539684[55]) ?
_theResult___snd__h547944 :
_theResult___snd__h547954 ;
assign _theResult___snd__h547944 = { _theResult____h539684[54:0], 2'd0 } ;
assign _theResult___snd__h547954 =
(!_theResult____h539684[56] && !_theResult____h539684[55] &&
!_theResult____h539684[54] &&
!_theResult____h539684[53] &&
!_theResult____h539684[52] &&
!_theResult____h539684[51] &&
!_theResult____h539684[50] &&
!_theResult____h539684[49] &&
!_theResult____h539684[48] &&
!_theResult____h539684[47] &&
!_theResult____h539684[46] &&
!_theResult____h539684[45] &&
!_theResult____h539684[44] &&
!_theResult____h539684[43] &&
!_theResult____h539684[42] &&
!_theResult____h539684[41] &&
!_theResult____h539684[40] &&
!_theResult____h539684[39] &&
!_theResult____h539684[38] &&
!_theResult____h539684[37] &&
!_theResult____h539684[36] &&
!_theResult____h539684[35] &&
!_theResult____h539684[34] &&
!_theResult____h539684[33] &&
!_theResult____h539684[32] &&
!_theResult____h539684[31] &&
!_theResult____h539684[30] &&
!_theResult____h539684[29] &&
!_theResult____h539684[28] &&
!_theResult____h539684[27] &&
!_theResult____h539684[26] &&
!_theResult____h539684[25] &&
!_theResult____h539684[24] &&
!_theResult____h539684[23] &&
!_theResult____h539684[22] &&
!_theResult____h539684[21] &&
!_theResult____h539684[20] &&
!_theResult____h539684[19] &&
!_theResult____h539684[18] &&
!_theResult____h539684[17] &&
!_theResult____h539684[16] &&
!_theResult____h539684[15] &&
!_theResult____h539684[14] &&
!_theResult____h539684[13] &&
!_theResult____h539684[12] &&
!_theResult____h539684[11] &&
!_theResult____h539684[10] &&
!_theResult____h539684[9] &&
!_theResult____h539684[8] &&
!_theResult____h539684[7] &&
!_theResult____h539684[6] &&
!_theResult____h539684[5] &&
!_theResult____h539684[4] &&
!_theResult____h539684[3] &&
!_theResult____h539684[2] &&
!_theResult____h539684[1] &&
!_theResult____h539684[0]) ?
_theResult____h539684 :
_theResult___snd__h547960 ;
assign _theResult___snd__h547960 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0],
2'd0 } ;
assign _theResult___snd__h547983 =
_theResult____h539684 <<
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10349 ;
assign _theResult___snd__h556699 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
_theResult___snd__h556713 :
_theResult___snd__h538296 ;
assign _theResult___snd__h556713 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10025) ?
sfd__h519483 :
_theResult___snd__h556719 ;
assign _theResult___snd__h556719 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0],
2'd0 } ;
assign _theResult___snd__h556737 =
sfd__h519483 <<
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10400 ;
assign _theResult___snd__h577495 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_theResult___snd__h577504 :
_theResult___snd__h577497 ;
assign _theResult___snd__h577497 =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ;
assign _theResult___snd__h577504 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d9262) ?
sfd__h558684 :
_theResult___snd__h577510 ;
assign _theResult___snd__h577510 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0],
2'd0 } ;
assign _theResult___snd__h577533 =
sfd__h558684 <<
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9289 ;
assign _theResult___snd__h587132 = { _theResult____h578885[55:0], 1'd0 } ;
assign _theResult___snd__h587143 =
(!_theResult____h578885[56] && _theResult____h578885[55]) ?
_theResult___snd__h587145 :
_theResult___snd__h587155 ;
assign _theResult___snd__h587145 = { _theResult____h578885[54:0], 2'd0 } ;
assign _theResult___snd__h587155 =
(!_theResult____h578885[56] && !_theResult____h578885[55] &&
!_theResult____h578885[54] &&
!_theResult____h578885[53] &&
!_theResult____h578885[52] &&
!_theResult____h578885[51] &&
!_theResult____h578885[50] &&
!_theResult____h578885[49] &&
!_theResult____h578885[48] &&
!_theResult____h578885[47] &&
!_theResult____h578885[46] &&
!_theResult____h578885[45] &&
!_theResult____h578885[44] &&
!_theResult____h578885[43] &&
!_theResult____h578885[42] &&
!_theResult____h578885[41] &&
!_theResult____h578885[40] &&
!_theResult____h578885[39] &&
!_theResult____h578885[38] &&
!_theResult____h578885[37] &&
!_theResult____h578885[36] &&
!_theResult____h578885[35] &&
!_theResult____h578885[34] &&
!_theResult____h578885[33] &&
!_theResult____h578885[32] &&
!_theResult____h578885[31] &&
!_theResult____h578885[30] &&
!_theResult____h578885[29] &&
!_theResult____h578885[28] &&
!_theResult____h578885[27] &&
!_theResult____h578885[26] &&
!_theResult____h578885[25] &&
!_theResult____h578885[24] &&
!_theResult____h578885[23] &&
!_theResult____h578885[22] &&
!_theResult____h578885[21] &&
!_theResult____h578885[20] &&
!_theResult____h578885[19] &&
!_theResult____h578885[18] &&
!_theResult____h578885[17] &&
!_theResult____h578885[16] &&
!_theResult____h578885[15] &&
!_theResult____h578885[14] &&
!_theResult____h578885[13] &&
!_theResult____h578885[12] &&
!_theResult____h578885[11] &&
!_theResult____h578885[10] &&
!_theResult____h578885[9] &&
!_theResult____h578885[8] &&
!_theResult____h578885[7] &&
!_theResult____h578885[6] &&
!_theResult____h578885[5] &&
!_theResult____h578885[4] &&
!_theResult____h578885[3] &&
!_theResult____h578885[2] &&
!_theResult____h578885[1] &&
!_theResult____h578885[0]) ?
_theResult____h578885 :
_theResult___snd__h587161 ;
assign _theResult___snd__h587161 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0],
2'd0 } ;
assign _theResult___snd__h587184 =
_theResult____h578885 <<
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9586 ;
assign _theResult___snd__h595900 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
_theResult___snd__h595914 :
_theResult___snd__h577497 ;
assign _theResult___snd__h595914 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d9262) ?
sfd__h558684 :
_theResult___snd__h595920 ;
assign _theResult___snd__h595920 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0],
2'd0 } ;
assign _theResult___snd__h595938 =
sfd__h558684 <<
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9637 ;
assign _theResult___snd__h601254 =
b__h600706[63] ? b___1__h601319 : b__h600706 ;
assign _theResult___snd_fst_exp__h361446 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_theResult___fst_exp__h352861 :
_theResult___fst_exp__h361443 ;
assign _theResult___snd_fst_exp__h379266 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_theResult___fst_exp__h370627 :
_theResult___fst_exp__h379263 ;
assign _theResult___snd_fst_exp__h407136 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_theResult___fst_exp__h398551 :
_theResult___fst_exp__h407133 ;
assign _theResult___snd_fst_exp__h424956 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_theResult___fst_exp__h416317 :
_theResult___fst_exp__h424953 ;
assign _theResult___snd_fst_exp__h452824 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_theResult___fst_exp__h444239 :
_theResult___fst_exp__h452821 ;
assign _theResult___snd_fst_exp__h470644 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_theResult___fst_exp__h462005 :
_theResult___fst_exp__h470641 ;
assign _theResult___snd_fst_exp__h500303 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 ?
11'd0 :
_theResult___fst_exp__h500300 ;
assign _theResult___snd_fst_exp__h518738 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 ?
_theResult___fst_exp__h509951 :
_theResult___fst_exp__h518735 ;
assign _theResult___snd_fst_exp__h539104 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 ?
11'd0 :
_theResult___fst_exp__h539101 ;
assign _theResult___snd_fst_exp__h557539 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
_theResult___fst_exp__h548752 :
_theResult___fst_exp__h557536 ;
assign _theResult___snd_fst_exp__h578305 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 ?
11'd0 :
_theResult___fst_exp__h578302 ;
assign _theResult___snd_fst_exp__h596740 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
_theResult___fst_exp__h587953 :
_theResult___fst_exp__h596737 ;
assign _theResult___snd_fst_sfd__h336498 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h361447 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_theResult___fst_sfd__h352862 :
_theResult___fst_sfd__h361444 ;
assign _theResult___snd_fst_sfd__h379267 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_theResult___fst_sfd__h370628 :
_theResult___fst_sfd__h379264 ;
assign _theResult___snd_fst_sfd__h382193 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h407137 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_theResult___fst_sfd__h398552 :
_theResult___fst_sfd__h407134 ;
assign _theResult___snd_fst_sfd__h424957 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_theResult___fst_sfd__h416318 :
_theResult___fst_sfd__h424954 ;
assign _theResult___snd_fst_sfd__h427881 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h452825 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_theResult___fst_sfd__h444240 :
_theResult___fst_sfd__h452822 ;
assign _theResult___snd_fst_sfd__h470645 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_theResult___fst_sfd__h462006 :
_theResult___fst_sfd__h470642 ;
assign _theResult___snd_fst_sfd__h480495 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h480244 ;
assign _theResult___snd_fst_sfd__h500304 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8493 ?
52'd0 :
_theResult___fst_sfd__h500301 ;
assign _theResult___snd_fst_sfd__h518739 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8629 ?
_theResult___fst_sfd__h509952 :
_theResult___fst_sfd__h518736 ;
assign _theResult___snd_fst_sfd__h519437 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h519186 ;
assign _theResult___snd_fst_sfd__h539105 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9981 ?
52'd0 :
_theResult___fst_sfd__h539102 ;
assign _theResult___snd_fst_sfd__h557540 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10102 ?
_theResult___fst_sfd__h548753 :
_theResult___fst_sfd__h557537 ;
assign _theResult___snd_fst_sfd__h558638 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h558387 ;
assign _theResult___snd_fst_sfd__h578306 =
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9218 ?
52'd0 :
_theResult___fst_sfd__h578303 ;
assign _theResult___snd_fst_sfd__h596741 =
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9339 ?
_theResult___fst_sfd__h587954 :
_theResult___fst_sfd__h596738 ;
assign a___1__h600867 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ;
assign a___1__h601258 = 64'd0 - a__h600705 ;
assign a__h600705 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
a___1__h600867 :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign b___1__h600868 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } :
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
assign b___1__h601319 = 64'd0 - b__h600706 ;
assign b__h600706 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
b___1__h600868 :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign b__h600853 = { {64{a__h600705[63]}}, a__h600705 } ;
assign b__h600929 = { {64{b__h600706[63]}}, b__h600706 } ;
assign b__h601030 = { 64'd0, a__h600705 } ;
assign b__h601042 = { 64'd0, b__h600706 } ;
assign base__h696929 = { csrf_stvec_base_hi_reg, 2'b0 } ;
assign base__h697132 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
assign cause_code__h694327 =
commitStage_commitTrap[4] ? i__h694502 : i__h694342 ;
assign coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12148 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_0_wget__2146_BITS__ETC___d12187 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12161 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2159_BITS__ETC___d12193 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12169 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2167_BITS__ETC___d12197 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_dispToRegQ_first__2125_BIT_13_ETC___d12210 =
(coreFix_aluExe_0_dispToRegQ$first[131] ||
sbCons$lazyLookup_0_get[3] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2124_ETC___d12156 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12182) &&
(sbCons$lazyLookup_0_get[2] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2124_ETC___d12190 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12207) ;
assign coreFix_aluExe_0_exeToFinQ_RDY_first__2537_AND_ETC___d12575 =
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
(coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd9 &&
coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd10 ||
coreFix_trainBPQ_0$FULL_N) ;
assign coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 =
coreFix_aluExe_0_rsAlu$approximateCount <
coreFix_aluExe_1_rsAlu$approximateCount ;
assign coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11353 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_0_wget__1351_BITS__ETC___d11392 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11366 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1364_BITS__ETC___d11398 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11374 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1372_BITS__ETC___d11402 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_dispToRegQ_first__1330_BIT_13_ETC___d11415 =
(coreFix_aluExe_1_dispToRegQ$first[131] ||
sbCons$lazyLookup_1_get[3] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1329_ETC___d11361 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11387) &&
(sbCons$lazyLookup_1_get[2] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1329_ETC___d11395 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11412) ;
assign coreFix_aluExe_1_exeToFinQ_RDY_first__1928_AND_ETC___d11967 =
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
(coreFix_aluExe_1_exeToFinQ$first[325:321] != 5'd9 &&
coreFix_aluExe_1_exeToFinQ$first[325:321] != 5'd10 ||
coreFix_trainBPQ_1$FULL_N) ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8195 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8233 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__193__ETC___d8257 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8208 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8239 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__206__ETC___d8263 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8216 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8243 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__214__ETC___d8267 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8413 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10819 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10774 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10814) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10855 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10843 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10850) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10903 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10887 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10898) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10945 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10931 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10940) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10987 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10973 |
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10982) ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168 =
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] - 8'd127 ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128 =
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] - 8'd127 ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 =
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] - 8'd127 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__37_ETC___d13814 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13794) ;
assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573 =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
y__h252876 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ||
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ||
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
2'd2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rqToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rsToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907 =
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
(!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
coreFix_memExe_dMem_perfReqQ_full ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 =
coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 =
coreFix_memExe_dTlb$procResp[174:114] < 61'd536870912 ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 =
coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 =
coreFix_memExe_dTlb$procResp[174:114] == mmio_fromHostAddr ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 =
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 ||
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 ||
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 ||
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755 =
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ||
(!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!coreFix_memExe_forwardQ_deqReq_rl) &&
coreFix_memExe_forwardQ_full ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661 =
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ||
(!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!coreFix_memExe_memRespLdQ_deqReq_rl) &&
coreFix_memExe_memRespLdQ_full ;
assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 =
coreFix_memExe_regToExeQ$first[189:158] ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570 =
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 ||
(!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
!coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
coreFix_memExe_respLrScAmoQ_full ;
assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14413 =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
rob$RDY_deqPort_0_deq_data &&
rob$RDY_deqPort_0_deq &&
regRenamingTable$RDY_commit_0_commit &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq &&
NOT_rob_deqPort_0_deq_data__4100_BITS_186_TO_1_ETC___d14408 ;
assign csrf_debug_int_pend_read__1696_CONCAT_0b0_2684_ETC___d12689 =
{ csrf_debug_int_pend,
2'b0,
csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
1'd0,
csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ;
assign csrf_debug_int_pend_read__1696_CONCAT_0b0_2684_ETC___d12694 =
{ csrf_debug_int_pend_read__1696_CONCAT_0b0_2684_ETC___d12689,
csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
1'd0,
csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ;
assign csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d12921 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[199:195] == 5'd13 &&
(fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d12916 ||
csrf_prv_reg_read__2680_ULT_IF_fetchStage_pipe_ETC___d12918) ;
assign csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13327 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13594 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_1_first[95] &&
fetchStage$pipelines_1_first[94] ||
fetchStage$pipelines_1_first[88] &&
fetchStage$pipelines_1_first[87] ||
fetchStage$pipelines_1_first[81] ||
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74]) ||
fetchStage$pipelines_1_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_prv_reg_read__2680_ULE_1_4236_AND_IF_comm_ETC___d14276 =
csrf_prv_reg_read__2680_ULE_1___d14236 &&
(commitStage_commitTrap[4] ?
_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14256 :
_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14274) ;
assign csrf_prv_reg_read__2680_ULE_1___d14236 = csrf_prv_reg <= 2'd1 ;
assign csrf_prv_reg_read__2680_ULT_IF_fetchStage_pipe_ETC___d12918 =
csrf_prv_reg <
IF_fetchStage_pipelines_0_first__2652_BIT_173__ETC___d12913[9:8] ;
assign data73346_BITS_31_TO_0__q5 = data__h473346[31:0] ;
assign data___1__h473058 =
{ {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}},
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ;
assign data___1__h473880 =
{ {32{data73346_BITS_31_TO_0__q5[31]}},
data73346_BITS_31_TO_0__q5 } ;
assign data__h473346 =
(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
2'd2) ?
x_quotient__h473246 :
x_remainder__h473247 ;
assign din_inc___2_exp__h379297 = _theResult___fst_exp__h352264 + 8'd1 ;
assign din_inc___2_exp__h379321 = _theResult___fst_exp__h360920 + 8'd1 ;
assign din_inc___2_exp__h379351 = _theResult___fst_exp__h370030 + 8'd1 ;
assign din_inc___2_exp__h379375 = _theResult___fst_exp__h378715 + 8'd1 ;
assign din_inc___2_exp__h424987 = _theResult___fst_exp__h397954 + 8'd1 ;
assign din_inc___2_exp__h425011 = _theResult___fst_exp__h406610 + 8'd1 ;
assign din_inc___2_exp__h425041 = _theResult___fst_exp__h415720 + 8'd1 ;
assign din_inc___2_exp__h425065 = _theResult___fst_exp__h424405 + 8'd1 ;
assign din_inc___2_exp__h470675 = _theResult___fst_exp__h443642 + 8'd1 ;
assign din_inc___2_exp__h470699 = _theResult___fst_exp__h452298 + 8'd1 ;
assign din_inc___2_exp__h470729 = _theResult___fst_exp__h461408 + 8'd1 ;
assign din_inc___2_exp__h470753 = _theResult___fst_exp__h470093 + 8'd1 ;
assign din_inc___2_exp__h518792 = _theResult___fst_exp__h499542 + 11'd1 ;
assign din_inc___2_exp__h518827 = _theResult___fst_exp__h509119 + 11'd1 ;
assign din_inc___2_exp__h518853 = _theResult___fst_exp__h517952 + 11'd1 ;
assign din_inc___2_exp__h557593 = _theResult___fst_exp__h538343 + 11'd1 ;
assign din_inc___2_exp__h557628 = _theResult___fst_exp__h547920 + 11'd1 ;
assign din_inc___2_exp__h557654 = _theResult___fst_exp__h556753 + 11'd1 ;
assign din_inc___2_exp__h596794 = _theResult___fst_exp__h577544 + 11'd1 ;
assign din_inc___2_exp__h596829 = _theResult___fst_exp__h587121 + 11'd1 ;
assign din_inc___2_exp__h596855 = _theResult___fst_exp__h595954 + 11'd1 ;
assign enabled_ints___1__h648033 = pend_ints__h647534 & y__h648045 ;
assign enabled_ints__h648080 =
pend_ints__h647534 &
{ r1__read_BITS_12_TO_0___h648056, csrf_mideleg_1_0_reg } ;
assign fcsr_csr__read__h608288 = { 56'd0, x__h610962 } ;
assign fetchStage_RDY_pipelines_0_first__2649_AND_NOT_ETC___d13257 =
fetchStage$RDY_pipelines_0_first &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 ;
assign fetchStage_RDY_pipelines_0_first__2649_AND_fet_ETC___d13324 =
fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13319 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first &&
IF_fetchStage_RDY_pipelines_0_first__2649_AND__ETC___d13261 ;
assign fetchStage_RDY_pipelines_1_deq__2664_AND_NOT_f_ETC___d13863 =
fetchStage$RDY_pipelines_1_deq &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13859) &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13805 =
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13549 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13804 ;
assign fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13884 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 ;
assign fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13971 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13881 &&
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13549 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13966 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 ;
assign fetchStage_pipelines_0_canDeq__2650_AND_fetchS_ETC___d13873 =
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13756 ||
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(fetchStage_pipelines_1_first__2661_BITS_194_TO_ETC___d13767 ||
NOT_regRenamingTable_rename_1_canRename__3354__ETC___d13773 ||
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13869) &&
IF_fetchStage_RDY_pipelines_1_first__2660_AND__ETC___d13700 ;
assign fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13811 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ;
assign fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13818 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ;
assign fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13839 =
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13811 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13831) ;
assign fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13850 =
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13818 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13334 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13842) ;
assign fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d14076 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d14074 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ;
assign fetchStage_pipelines_0_canDeq__2650_AND_specTa_ETC___d13936 =
fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d12916 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 &&
fetchStage$pipelines_0_first[178:174] == 5'd15 ||
rs1__h651591 != 5'd0 ||
imm__h651592 != 32'd0) &&
IF_fetchStage_pipelines_0_first__2652_BIT_173__ETC___d12913[11:10] ==
2'b11 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13549 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 &&
(!coreFix_aluExe_1_rsAlu$canEnq ||
coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270) ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13570 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2652_BITS_199_TO_ETC___d13563 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13642 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14] ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13750 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13739 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13748 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13756 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 ||
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13755 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13778 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2652_BITS_199_TO_ETC___d13563 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13785 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2652_BITS_199_TO_ETC___d13563 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 ||
coreFix_aluExe_0_rsAlu$canEnq &&
coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 ;
assign fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13966 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[68] ||
checkForException___d12886[4] ||
!rob$enqPort_0_canEnq ;
assign fetchStage_pipelines_0_first__2652_BITS_199_TO_ETC___d13563 =
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d13560 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_0_first__2652_BIT_68_2679_ETC___d13332 =
fetchStage$pipelines_0_first[68] ||
checkForException___d12886[4] ||
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13327 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_1_first__2661_BITS_194_TO_ETC___d13767 =
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13764 ||
!specTagManager$canClaim) ;
assign fetchStage_pipelines_1_first__2661_BITS_199_TO_ETC___d13602 =
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
fetchStage$pipelines_1_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d13596 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first &&
IF_fetchStage_RDY_pipelines_0_first__2649_AND__ETC___d13261 ;
assign fetchStage_pipelines_1_first__2661_BIT_173_340_ETC___d13484 =
{ fetchStage$pipelines_1_first[173],
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 } ;
assign fetchStage_pipelines_1_first__2661_BIT_68_3382_ETC___d13771 =
fetchStage$pipelines_1_first[68] ||
checkForException___d13505[4] ||
csrf_fs_reg_read__1538_EQ_0_2875_AND_fetchStag_ETC___d13594 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13756 ;
assign fflags__h707765 =
NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_deq_ETC___d14789 ?
y_avValue_snd_fst__h707825 :
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14796 ;
assign fflags_csr__read__h608263 = { 59'd0, csrf_fflags_reg } ;
assign frm_csr__read__h608274 = { 61'd0, csrf_frm_reg } ;
assign guard__h344163 =
{ IF_sfdin52258_BIT_33_THEN_2_ELSE_0__q21[1],
{ sfdin__h352258[32:0], 23'd0 } != 56'd0 } ;
assign guard__h352872 =
{ IF_theResult___snd60871_BIT_33_THEN_2_ELSE_0__q23[1],
{ _theResult___snd__h360871[32:0], 23'd0 } != 56'd0 } ;
assign guard__h361802 =
{ IF_sfdin70024_BIT_33_THEN_2_ELSE_0__q31[1],
{ sfdin__h370024[32:0], 23'd0 } != 56'd0 } ;
assign guard__h362400 = x__h362502 != 57'd0 ;
assign guard__h370638 =
{ IF_theResult___snd78661_BIT_33_THEN_2_ELSE_0__q36[1],
{ _theResult___snd__h378661[32:0], 23'd0 } != 56'd0 } ;
assign guard__h389855 =
{ IF_sfdin97948_BIT_33_THEN_2_ELSE_0__q56[1],
{ sfdin__h397948[32:0], 23'd0 } != 56'd0 } ;
assign guard__h398562 =
{ IF_theResult___snd06561_BIT_33_THEN_2_ELSE_0__q58[1],
{ _theResult___snd__h406561[32:0], 23'd0 } != 56'd0 } ;
assign guard__h407492 =
{ IF_sfdin15714_BIT_33_THEN_2_ELSE_0__q66[1],
{ sfdin__h415714[32:0], 23'd0 } != 56'd0 } ;
assign guard__h408090 = x__h408192 != 57'd0 ;
assign guard__h416328 =
{ IF_theResult___snd24351_BIT_33_THEN_2_ELSE_0__q71[1],
{ _theResult___snd__h424351[32:0], 23'd0 } != 56'd0 } ;
assign guard__h435543 =
{ IF_sfdin43636_BIT_33_THEN_2_ELSE_0__q91[1],
{ sfdin__h443636[32:0], 23'd0 } != 56'd0 } ;
assign guard__h444250 =
{ IF_theResult___snd52249_BIT_33_THEN_2_ELSE_0__q93[1],
{ _theResult___snd__h452249[32:0], 23'd0 } != 56'd0 } ;
assign guard__h453180 =
{ IF_sfdin61402_BIT_33_THEN_2_ELSE_0__q101[1],
{ sfdin__h461402[32:0], 23'd0 } != 56'd0 } ;
assign guard__h453778 = x__h453880 != 57'd0 ;
assign guard__h462016 =
{ IF_theResult___snd70039_BIT_33_THEN_2_ELSE_0__q106[1],
{ _theResult___snd__h470039[32:0], 23'd0 } != 56'd0 } ;
assign guard__h491581 =
{ IF_theResult___snd99493_BIT_4_THEN_2_ELSE_0__q127[1],
{ _theResult___snd__h499493[3:0], 52'd0 } != 56'd0 } ;
assign guard__h500893 =
{ IF_sfdin09113_BIT_4_THEN_2_ELSE_0__q131[1],
{ sfdin__h509113[3:0], 52'd0 } != 56'd0 } ;
assign guard__h501491 = x__h501591 != 57'd0 ;
assign guard__h509962 =
{ IF_theResult___snd17898_BIT_4_THEN_2_ELSE_0__q134[1],
{ _theResult___snd__h517898[3:0], 52'd0 } != 56'd0 } ;
assign guard__h530382 =
{ IF_theResult___snd38294_BIT_4_THEN_2_ELSE_0__q167[1],
{ _theResult___snd__h538294[3:0], 52'd0 } != 56'd0 } ;
assign guard__h539694 =
{ IF_sfdin47914_BIT_4_THEN_2_ELSE_0__q171[1],
{ sfdin__h547914[3:0], 52'd0 } != 56'd0 } ;
assign guard__h540292 = x__h540392 != 57'd0 ;
assign guard__h548763 =
{ IF_theResult___snd56699_BIT_4_THEN_2_ELSE_0__q174[1],
{ _theResult___snd__h556699[3:0], 52'd0 } != 56'd0 } ;
assign guard__h569583 =
{ IF_theResult___snd77495_BIT_4_THEN_2_ELSE_0__q144[1],
{ _theResult___snd__h577495[3:0], 52'd0 } != 56'd0 } ;
assign guard__h578895 =
{ IF_sfdin87115_BIT_4_THEN_2_ELSE_0__q148[1],
{ sfdin__h587115[3:0], 52'd0 } != 56'd0 } ;
assign guard__h579493 = x__h579593 != 57'd0 ;
assign guard__h587964 =
{ IF_theResult___snd95900_BIT_4_THEN_2_ELSE_0__q151[1],
{ _theResult___snd__h595900[3:0], 52'd0 } != 56'd0 } ;
assign idx__h677617 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13550 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13570) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 ;
assign imm__h651592 =
fetchStage$pipelines_0_first[160] ?
fetchStage$pipelines_0_first[159:128] :
32'd0 ;
assign k__h663183 =
!coreFix_aluExe_0_rsAlu$canEnq ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3268__ETC___d13270 ;
assign mcause_csr__read__h609935 =
{ r1__read__h612502, csrf_mcause_code_reg } ;
assign mcounteren_csr__read__h609680 =
{ r1__read__h612489, csrf_mcounteren_cy_reg } ;
assign medeleg_csr__read__h609280 =
{ r1__read__h612325, csrf_medeleg_9_0_reg } ;
assign mideleg_csr__read__h609375 =
{ r1__read__h612342, csrf_mideleg_1_0_reg } ;
assign mie_csr__read__h609506 =
{ r1__read__h612366, csrf_software_int_en_vec_0 } ;
assign mip_csr__read__h610175 =
{ r1__read__h612508, csrf_software_int_pend_vec_0 } ;
assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
(!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
mmio_cRqQ_full ;
assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
(!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
mmio_cRsQ_full ;
assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
(mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
(!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataPendQ_deqReq_rl) &&
mmio_dataPendQ_full ;
assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
(!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
mmio_dataReqQ_full ;
assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
(!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataRespQ_deqReq_rl) &&
mmio_dataRespQ_full ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12932 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
(fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12928) &&
rob$isEmpty ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13194 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13175 &&
(fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20) ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13878 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_268_ETC___d13249 &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 ;
assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
(!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
mmio_pRqQ_full ;
assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
(!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
!mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) &&
mmio_pRsQ_full ;
assign msip__h75409 = csrf_software_int_pend_vec_3 ;
assign mstatus_csr__read__h609132 = { r1__read__h612188, csrf_ie_vec_0 } ;
assign mtvec_csr__read__h609588 =
{ r1__read__h612484, csrf_mtvec_mode_low_reg } ;
assign n___1__h196602 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
x__h195199[63:56],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
x__h195199[55:48],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
x__h195199[47:40],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
x__h195199[39:32],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
x__h195199[31:24],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
x__h195199[23:16],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
x__h195199[15:8],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
x__h195199[7:0] } ;
assign n__read__h610279 =
(csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
csrf_mcycle_ehr_data_rl :
64'd0 ;
assign n__read__h610470 =
(csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
csrf_minstret_ehr_data_rl :
64'd0 ;
assign n__read__h6134 =
csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
(csrf_mcycle_ehr_data_lat_0$whas ?
rob$deqPort_0_deq_data[95:32] :
csrf_mcycle_ehr_data_rl) :
64'd0 ;
assign n__read__h705337 =
csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
64'd0 ;
assign next_deqP___1__h294872 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
3'd1 ;
assign next_deqP___1__h302868 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
assign next_deqP___1__h309149 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
assign next_deqP___1__h317003 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
assign next_deqP___1__h327060 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
assign next_deqP___1__h330285 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
assign next_pc__h704680 =
(rob$deqPort_0_deq_data[97:96] == 2'd0) ?
rob$deqPort_0_deq_data[95:32] :
rob$deqPort_0_deq_data[282:219] + 64'd4 ;
assign out___1_sfd__h480244 =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ;
assign out___1_sfd__h519186 =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ;
assign out___1_sfd__h558387 =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ;
assign out_exp__h352783 =
sfdin__h352258[34] ?
_theResult___exp__h352780 :
_theResult___fst_exp__h352264 ;
assign out_exp__h361365 =
_theResult___snd__h360871[34] ?
_theResult___exp__h361362 :
_theResult___fst_exp__h360920 ;
assign out_exp__h370549 =
sfdin__h370024[34] ?
_theResult___exp__h370546 :
_theResult___fst_exp__h370030 ;
assign out_exp__h379185 =
_theResult___snd__h378661[34] ?
_theResult___exp__h379182 :
_theResult___fst_exp__h378715 ;
assign out_exp__h398473 =
sfdin__h397948[34] ?
_theResult___exp__h398470 :
_theResult___fst_exp__h397954 ;
assign out_exp__h407055 =
_theResult___snd__h406561[34] ?
_theResult___exp__h407052 :
_theResult___fst_exp__h406610 ;
assign out_exp__h416239 =
sfdin__h415714[34] ?
_theResult___exp__h416236 :
_theResult___fst_exp__h415720 ;
assign out_exp__h424875 =
_theResult___snd__h424351[34] ?
_theResult___exp__h424872 :
_theResult___fst_exp__h424405 ;
assign out_exp__h444161 =
sfdin__h443636[34] ?
_theResult___exp__h444158 :
_theResult___fst_exp__h443642 ;
assign out_exp__h452743 =
_theResult___snd__h452249[34] ?
_theResult___exp__h452740 :
_theResult___fst_exp__h452298 ;
assign out_exp__h461927 =
sfdin__h461402[34] ?
_theResult___exp__h461924 :
_theResult___fst_exp__h461408 ;
assign out_exp__h470563 =
_theResult___snd__h470039[34] ?
_theResult___exp__h470560 :
_theResult___fst_exp__h470093 ;
assign out_exp__h500200 =
_theResult___snd__h499493[5] ?
_theResult___exp__h500197 :
_theResult___fst_exp__h499542 ;
assign out_exp__h509851 =
sfdin__h509113[5] ?
_theResult___exp__h509848 :
_theResult___fst_exp__h509119 ;
assign out_exp__h518635 =
_theResult___snd__h517898[5] ?
_theResult___exp__h518632 :
_theResult___fst_exp__h517952 ;
assign out_exp__h539001 =
_theResult___snd__h538294[5] ?
_theResult___exp__h538998 :
_theResult___fst_exp__h538343 ;
assign out_exp__h548652 =
sfdin__h547914[5] ?
_theResult___exp__h548649 :
_theResult___fst_exp__h547920 ;
assign out_exp__h557436 =
_theResult___snd__h556699[5] ?
_theResult___exp__h557433 :
_theResult___fst_exp__h556753 ;
assign out_exp__h578202 =
_theResult___snd__h577495[5] ?
_theResult___exp__h578199 :
_theResult___fst_exp__h577544 ;
assign out_exp__h587853 =
sfdin__h587115[5] ?
_theResult___exp__h587850 :
_theResult___fst_exp__h587121 ;
assign out_exp__h596637 =
_theResult___snd__h595900[5] ?
_theResult___exp__h596634 :
_theResult___fst_exp__h595954 ;
assign out_f_exp__h379561 =
(_theResult___exp__h379284 == 8'd255 &&
_theResult___sfd__h379285 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h379275 ;
assign out_f_exp__h425251 =
(_theResult___exp__h424974 == 8'd255 &&
_theResult___sfd__h424975 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h424965 ;
assign out_f_exp__h470939 =
(_theResult___exp__h470662 == 8'd255 &&
_theResult___sfd__h470663 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h470653 ;
assign out_f_sfd__h379562 =
(_theResult___exp__h379284 == 8'd255 &&
_theResult___sfd__h379285 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h379285 ;
assign out_f_sfd__h425252 =
(_theResult___exp__h424974 == 8'd255 &&
_theResult___sfd__h424975 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h424975 ;
assign out_f_sfd__h470940 =
(_theResult___exp__h470662 == 8'd255 &&
_theResult___sfd__h470663 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h470663 ;
assign out_sfd__h352784 =
sfdin__h352258[34] ?
_theResult___sfd__h352781 :
sfdin__h352258[56:34] ;
assign out_sfd__h361366 =
_theResult___snd__h360871[34] ?
_theResult___sfd__h361363 :
_theResult___snd__h360871[56:34] ;
assign out_sfd__h370550 =
sfdin__h370024[34] ?
_theResult___sfd__h370547 :
sfdin__h370024[56:34] ;
assign out_sfd__h379186 =
_theResult___snd__h378661[34] ?
_theResult___sfd__h379183 :
_theResult___snd__h378661[56:34] ;
assign out_sfd__h398474 =
sfdin__h397948[34] ?
_theResult___sfd__h398471 :
sfdin__h397948[56:34] ;
assign out_sfd__h407056 =
_theResult___snd__h406561[34] ?
_theResult___sfd__h407053 :
_theResult___snd__h406561[56:34] ;
assign out_sfd__h416240 =
sfdin__h415714[34] ?
_theResult___sfd__h416237 :
sfdin__h415714[56:34] ;
assign out_sfd__h424876 =
_theResult___snd__h424351[34] ?
_theResult___sfd__h424873 :
_theResult___snd__h424351[56:34] ;
assign out_sfd__h444162 =
sfdin__h443636[34] ?
_theResult___sfd__h444159 :
sfdin__h443636[56:34] ;
assign out_sfd__h452744 =
_theResult___snd__h452249[34] ?
_theResult___sfd__h452741 :
_theResult___snd__h452249[56:34] ;
assign out_sfd__h461928 =
sfdin__h461402[34] ?
_theResult___sfd__h461925 :
sfdin__h461402[56:34] ;
assign out_sfd__h470564 =
_theResult___snd__h470039[34] ?
_theResult___sfd__h470561 :
_theResult___snd__h470039[56:34] ;
assign out_sfd__h500201 =
_theResult___snd__h499493[5] ?
_theResult___sfd__h500198 :
_theResult___snd__h499493[56:5] ;
assign out_sfd__h509852 =
sfdin__h509113[5] ?
_theResult___sfd__h509849 :
sfdin__h509113[56:5] ;
assign out_sfd__h518636 =
_theResult___snd__h517898[5] ?
_theResult___sfd__h518633 :
_theResult___snd__h517898[56:5] ;
assign out_sfd__h539002 =
_theResult___snd__h538294[5] ?
_theResult___sfd__h538999 :
_theResult___snd__h538294[56:5] ;
assign out_sfd__h548653 =
sfdin__h547914[5] ?
_theResult___sfd__h548650 :
sfdin__h547914[56:5] ;
assign out_sfd__h557437 =
_theResult___snd__h556699[5] ?
_theResult___sfd__h557434 :
_theResult___snd__h556699[56:5] ;
assign out_sfd__h578203 =
_theResult___snd__h577495[5] ?
_theResult___sfd__h578200 :
_theResult___snd__h577495[56:5] ;
assign out_sfd__h587854 =
sfdin__h587115[5] ?
_theResult___sfd__h587851 :
sfdin__h587115[56:5] ;
assign out_sfd__h596638 =
_theResult___snd__h595900[5] ?
_theResult___sfd__h596635 :
_theResult___snd__h595900[56:5] ;
assign pend_ints__h647534 =
{ csrf_debug_int_pend_read__1696_CONCAT_0b0_2684_ETC___d12694,
csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
1'd0,
csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ;
assign prv__h709280 = csrf_prv_reg ;
assign prv__h709324 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
assign q___1__h473956 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ;
assign q__h601833 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] /
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ;
assign r1__read_BITS_12_TO_0___h648056 =
{ 3'd0,
csrf_mideleg_11_reg,
1'b0,
csrf_mideleg_9_7_reg,
1'b0,
csrf_mideleg_5_3_reg,
1'b0 } ;
assign r1__read_BITS_13_TO_12___h651460 = csrf_fs_reg ;
assign r1__read_BIT_20___h652088 = csrf_tw_reg ;
assign r1__read__h610977 = { r1__read__h610979, csrf_ie_vec_1 } ;
assign r1__read__h610979 = { r1__read__h610981, 2'b0 } ;
assign r1__read__h610981 = { r1__read__h610983, csrf_prev_ie_vec_0 } ;
assign r1__read__h610983 = { r1__read__h610985, csrf_prev_ie_vec_1 } ;
assign r1__read__h610985 = { r1__read__h610987, 2'b0 } ;
assign r1__read__h610987 = { r1__read__h610989, csrf_spp_reg } ;
assign r1__read__h610989 = { r1__read__h610991, 4'b0 } ;
assign r1__read__h610991 = { r1__read__h610993, csrf_fs_reg } ;
assign r1__read__h610993 = { r1__read__h610995, 2'd0 } ;
assign r1__read__h610995 = { r1__read__h610997, 1'b0 } ;
assign r1__read__h610997 = { r1__read__h610999, csrf_sum_reg } ;
assign r1__read__h610999 = { r1__read__h611001, csrf_mxr_reg } ;
assign r1__read__h611001 = { r1__read__h611003, 12'b0 } ;
assign r1__read__h611003 = { r1__read__h611005, 2'b10 } ;
assign r1__read__h611005 = { r__h611009, 29'b0 } ;
assign r1__read__h611381 =
{ r1__read__h611383, csrf_software_int_en_vec_1 } ;
assign r1__read__h611383 = { r1__read__h611385, 2'b0 } ;
assign r1__read__h611385 = { r1__read__h611387, csrf_timer_int_en_vec_0 } ;
assign r1__read__h611387 = { r1__read__h611389, csrf_timer_int_en_vec_1 } ;
assign r1__read__h611389 = { r1__read__h611391, 2'b0 } ;
assign r1__read__h611391 =
{ r1__read__h611393, csrf_external_int_en_vec_0 } ;
assign r1__read__h611393 = { 54'b0, csrf_external_int_en_vec_1 } ;
assign r1__read__h611911 = { csrf_stvec_base_hi_reg, 1'b0 } ;
assign r1__read__h611916 = { r1__read__h611918, csrf_scounteren_tm_reg } ;
assign r1__read__h611918 = { 61'd0, csrf_scounteren_ir_reg } ;
assign r1__read__h611929 = { csrf_scause_interrupt_reg, 59'b0 } ;
assign r1__read__h611935 =
{ r1__read__h611937, csrf_software_int_pend_vec_1 } ;
assign r1__read__h611937 = { r1__read__h611939, 2'b0 } ;
assign r1__read__h611939 =
{ r1__read__h611941, csrf_timer_int_pend_vec_0 } ;
assign r1__read__h611941 =
{ r1__read__h611943, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h611943 = { r1__read__h611945, 2'b0 } ;
assign r1__read__h611945 =
{ r1__read__h611947, csrf_external_int_pend_vec_0 } ;
assign r1__read__h611947 = { 54'b0, csrf_external_int_pend_vec_1 } ;
assign r1__read__h612165 = { vm_mode_reg__read__h612171, 16'd0 } ;
assign r1__read__h612188 = { r1__read__h612190, csrf_ie_vec_1 } ;
assign r1__read__h612190 = { r1__read__h612192, 1'b0 } ;
assign r1__read__h612192 = { r1__read__h612194, csrf_ie_vec_3 } ;
assign r1__read__h612194 = { r1__read__h612196, csrf_prev_ie_vec_0 } ;
assign r1__read__h612196 = { r1__read__h612198, csrf_prev_ie_vec_1 } ;
assign r1__read__h612198 = { r1__read__h612200, 1'b0 } ;
assign r1__read__h612200 = { r1__read__h612202, csrf_prev_ie_vec_3 } ;
assign r1__read__h612202 = { r1__read__h612204, csrf_spp_reg } ;
assign r1__read__h612204 = { r1__read__h612206, 2'b0 } ;
assign r1__read__h612206 = { r1__read__h612208, csrf_mpp_reg } ;
assign r1__read__h612208 = { r1__read__h612210, csrf_fs_reg } ;
assign r1__read__h612210 = { r1__read__h612212, 2'd0 } ;
assign r1__read__h612212 = { r1__read__h612214, csrf_mprv_reg } ;
assign r1__read__h612214 = { r1__read__h612216, csrf_sum_reg } ;
assign r1__read__h612216 = { r1__read__h612218, csrf_mxr_reg } ;
assign r1__read__h612218 = { r1__read__h612220, csrf_tvm_reg } ;
assign r1__read__h612220 = { r1__read__h612222, csrf_tw_reg } ;
assign r1__read__h612222 = { r1__read__h612224, csrf_tsr_reg } ;
assign r1__read__h612224 = { r1__read__h612226, 9'b0 } ;
assign r1__read__h612226 = { r1__read__h612228, 2'b10 } ;
assign r1__read__h612228 = { r1__read__h612230, 2'b10 } ;
assign r1__read__h612230 = { r__h611009, 27'b0 } ;
assign r1__read__h612325 = { r1__read__h612327, 1'b0 } ;
assign r1__read__h612327 = { r1__read__h612329, csrf_medeleg_13_11_reg } ;
assign r1__read__h612329 = { r1__read__h612331, 1'b0 } ;
assign r1__read__h612331 = { 48'b0, csrf_medeleg_15_reg } ;
assign r1__read__h612342 = { r1__read__h612344, 1'b0 } ;
assign r1__read__h612344 = { r1__read__h612346, csrf_mideleg_5_3_reg } ;
assign r1__read__h612346 = { r1__read__h612348, 1'b0 } ;
assign r1__read__h612348 = { r1__read__h612350, csrf_mideleg_9_7_reg } ;
assign r1__read__h612350 = { r1__read__h612352, 1'b0 } ;
assign r1__read__h612352 = { 52'b0, csrf_mideleg_11_reg } ;
assign r1__read__h612366 =
{ r1__read__h612368, csrf_software_int_en_vec_1 } ;
assign r1__read__h612368 = { r1__read__h612370, 1'b0 } ;
assign r1__read__h612370 =
{ r1__read__h612372, csrf_software_int_en_vec_3 } ;
assign r1__read__h612372 = { r1__read__h612374, csrf_timer_int_en_vec_0 } ;
assign r1__read__h612374 = { r1__read__h612376, csrf_timer_int_en_vec_1 } ;
assign r1__read__h612376 = { r1__read__h612378, 1'b0 } ;
assign r1__read__h612378 = { r1__read__h612380, csrf_timer_int_en_vec_3 } ;
assign r1__read__h612380 =
{ r1__read__h612382, csrf_external_int_en_vec_0 } ;
assign r1__read__h612382 =
{ r1__read__h612384, csrf_external_int_en_vec_1 } ;
assign r1__read__h612384 = { r1__read__h612386, 1'b0 } ;
assign r1__read__h612386 = { 52'd4, csrf_external_int_en_vec_3 } ;
assign r1__read__h612484 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
assign r1__read__h612489 = { r1__read__h612491, csrf_mcounteren_tm_reg } ;
assign r1__read__h612491 = { 61'd0, csrf_mcounteren_ir_reg } ;
assign r1__read__h612502 = { csrf_mcause_interrupt_reg, 59'b0 } ;
assign r1__read__h612508 =
{ r1__read__h612510, csrf_software_int_pend_vec_1 } ;
assign r1__read__h612510 = { r1__read__h612512, 1'b0 } ;
assign r1__read__h612512 =
{ r1__read__h612514, csrf_software_int_pend_vec_3 } ;
assign r1__read__h612514 =
{ r1__read__h612516, csrf_timer_int_pend_vec_0 } ;
assign r1__read__h612516 =
{ r1__read__h612518, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h612518 = { r1__read__h612520, 1'b0 } ;
assign r1__read__h612520 =
{ r1__read__h612522, csrf_timer_int_pend_vec_3 } ;
assign r1__read__h612522 =
{ r1__read__h612524, csrf_external_int_pend_vec_0 } ;
assign r1__read__h612524 =
{ r1__read__h612526, csrf_external_int_pend_vec_1 } ;
assign r1__read__h612526 = { r1__read__h612528, 1'b0 } ;
assign r1__read__h612528 =
{ r1__read__h612530, csrf_external_int_pend_vec_3 } ;
assign r1__read__h612530 = { r1__read__h612532, 2'b0 } ;
assign r1__read__h612532 = { 49'b0, csrf_debug_int_pend } ;
assign rVal1__h479827 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign rVal2__h479828 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign r___1__h473983 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ;
assign r__h601834 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] %
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ;
assign r__h611009 = csrf_fs_reg == 2'b11 ;
assign regRenamingTable_RDY_rename_0_getRename__3134__ETC___d13735 =
regRenamingTable$RDY_rename_0_getRename &&
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 &&
(fetchStage$pipelines_0_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign regRenamingTable_RDY_rename_1_getRename__3791__ETC___d13809 =
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3228_3318_OR_NOT__ETC___d13794) &&
_0_OR_NOT_fetchStage_pipelines_1_first__2661_BI_ETC___d13807 ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_0_first__2652_BIT_68__ETC___d13303 ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13319 =
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ||
!specTagManager$canClaim ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13625 =
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13764 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13762 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13896 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13902 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 &&
fetchStage$pipelines_0_first[199:195] != 5'd14 ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13922 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 &&
(fetchStage$pipelines_0_first[191:189] == 3'd0 ||
fetchStage$pipelines_0_first[191:189] == 3'd2) ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d13930 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 &&
fetchStage$pipelines_0_first[191:189] != 3'd0 &&
fetchStage$pipelines_0_first[191:189] != 3'd2 ;
assign regRenamingTable_rename_0_canRename__3230_AND__ETC___d14074 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12886[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 ;
assign regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_1_first__2661_BIT_68__ETC___d13982 ;
assign regRenamingTable_rename_1_canRename__3354_AND__ETC___d14028 =
regRenamingTable_rename_1_canRename__3354_AND__ETC___d13984 &&
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) &&
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3230__ETC___d13715 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign renaming_spec_bits__h677486 =
fetchStage$pipelines_0_canDeq ?
y_avValue_snd_fst__h674252 :
specTagManager$currentSpecBits ;
assign res_data__h335940 = { 32'd0, x__h335952 } ;
assign res_data__h335945 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
assign res_data__h381635 = { 32'd0, x__h381647 } ;
assign res_data__h381640 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
assign res_data__h427323 = { 32'd0, x__h427335 } ;
assign res_data__h427328 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
assign res_fflags__h335941 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ;
assign res_fflags__h381636 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399220 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399220 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399220 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399220 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399220 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ;
assign res_fflags__h427324 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ;
assign resp_addr__h290043 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
assign result__h362405 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] |
guard__h362400 } ;
assign result__h408095 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] |
guard__h408090 } ;
assign result__h453783 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] |
guard__h453778 } ;
assign result__h501496 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8634[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8634[0] |
guard__h501491 } ;
assign result__h540297 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10107[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10107[0] |
guard__h540292 } ;
assign result__h579498 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9344[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9344[0] |
guard__h579493 } ;
assign result__h643243 = w__h643238 & y__h643272 ;
assign result__h643294 = ~x__h643293 ;
assign rob_RDY_enqPort_0_enq__2674_AND_regRenamingTab_ETC___d13142 =
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
coreFix_aluExe_0_rsAlu$RDY_enq) ;
assign rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13539 =
rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291) ;
assign rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13673 =
rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13669) ;
assign rob_enqPort_1_canEnq__3534_AND_epochManager_ch_ETC___d13690 =
rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3230_AND__ETC___d13305 &&
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13686) ;
assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 =
rob$deqPort_0_deq_data[95:32] ;
assign rs1__h651591 =
(fetchStage$pipelines_0_first[88] &&
!fetchStage$pipelines_0_first[87]) ?
fetchStage$pipelines_0_first[86:82] :
5'd0 ;
assign satp_csr__read__h608989 = { r1__read__h612165, csrf_ppn_reg } ;
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8280 =
(sbCons$lazyLookup_2_get[2] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8236 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8253) &&
(sbCons$lazyLookup_2_get[1] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8260 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8277) ;
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8281 =
(sbCons$lazyLookup_2_get[3] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8203 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8229) &&
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8280 ;
assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 =
(sbCons$lazyLookup_3_get[3] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604) &&
(sbCons$lazyLookup_3_get[2] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ;
assign sbIdx__h157159 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
coreFix_memExe_reqStQ_data_0_rl[65:64]) :
2'd0 ;
assign scause_csr__read__h608787 =
{ r1__read__h611929, csrf_scause_code_reg } ;
assign scounteren_csr__read__h608649 =
{ r1__read__h611916, csrf_scounteren_cy_reg } ;
assign sfd__h336548 = { value__h344775, 3'd0 } ;
assign sfd__h352356 =
{ 1'b0,
_theResult___fst_exp__h352264 != 8'd0,
sfdin__h352258[56:34] } +
25'd1 ;
assign sfd__h360938 =
{ 1'b0,
_theResult___fst_exp__h360920 != 8'd0,
_theResult___snd__h360871[56:34] } +
25'd1 ;
assign sfd__h370122 =
{ 1'b0,
_theResult___fst_exp__h370030 != 8'd0,
sfdin__h370024[56:34] } +
25'd1 ;
assign sfd__h378734 =
{ 1'b0,
_theResult___fst_exp__h378715 != 8'd0,
_theResult___snd__h378661[56:34] } +
25'd1 ;
assign sfd__h382243 = { value__h390465, 3'd0 } ;
assign sfd__h398046 =
{ 1'b0,
_theResult___fst_exp__h397954 != 8'd0,
sfdin__h397948[56:34] } +
25'd1 ;
assign sfd__h406628 =
{ 1'b0,
_theResult___fst_exp__h406610 != 8'd0,
_theResult___snd__h406561[56:34] } +
25'd1 ;
assign sfd__h415812 =
{ 1'b0,
_theResult___fst_exp__h415720 != 8'd0,
sfdin__h415714[56:34] } +
25'd1 ;
assign sfd__h424424 =
{ 1'b0,
_theResult___fst_exp__h424405 != 8'd0,
_theResult___snd__h424351[56:34] } +
25'd1 ;
assign sfd__h427931 = { value__h436153, 3'd0 } ;
assign sfd__h443734 =
{ 1'b0,
_theResult___fst_exp__h443642 != 8'd0,
sfdin__h443636[56:34] } +
25'd1 ;
assign sfd__h452316 =
{ 1'b0,
_theResult___fst_exp__h452298 != 8'd0,
_theResult___snd__h452249[56:34] } +
25'd1 ;
assign sfd__h461500 =
{ 1'b0,
_theResult___fst_exp__h461408 != 8'd0,
sfdin__h461402[56:34] } +
25'd1 ;
assign sfd__h470112 =
{ 1'b0,
_theResult___fst_exp__h470093 != 8'd0,
_theResult___snd__h470039[56:34] } +
25'd1 ;
assign sfd__h480541 = { value__h485099, 32'd0 } ;
assign sfd__h499560 =
{ 1'b0,
_theResult___fst_exp__h499542 != 11'd0,
_theResult___snd__h499493[56:5] } +
54'd1 ;
assign sfd__h509211 =
{ 1'b0,
_theResult___fst_exp__h509119 != 11'd0,
sfdin__h509113[56:5] } +
54'd1 ;
assign sfd__h517971 =
{ 1'b0,
_theResult___fst_exp__h517952 != 11'd0,
_theResult___snd__h517898[56:5] } +
54'd1 ;
assign sfd__h519483 = { value__h523900, 32'd0 } ;
assign sfd__h538361 =
{ 1'b0,
_theResult___fst_exp__h538343 != 11'd0,
_theResult___snd__h538294[56:5] } +
54'd1 ;
assign sfd__h548012 =
{ 1'b0,
_theResult___fst_exp__h547920 != 11'd0,
sfdin__h547914[56:5] } +
54'd1 ;
assign sfd__h556772 =
{ 1'b0,
_theResult___fst_exp__h556753 != 11'd0,
_theResult___snd__h556699[56:5] } +
54'd1 ;
assign sfd__h558684 = { value__h563101, 32'd0 } ;
assign sfd__h577562 =
{ 1'b0,
_theResult___fst_exp__h577544 != 11'd0,
_theResult___snd__h577495[56:5] } +
54'd1 ;
assign sfd__h587213 =
{ 1'b0,
_theResult___fst_exp__h587121 != 11'd0,
sfdin__h587115[56:5] } +
54'd1 ;
assign sfd__h595973 =
{ 1'b0,
_theResult___fst_exp__h595954 != 11'd0,
_theResult___snd__h595900[56:5] } +
54'd1 ;
assign sfdin__h352258 =
_theResult____h344153[56] ?
_theResult___snd__h352275 :
_theResult___snd__h352286 ;
assign sfdin__h370024 =
_theResult____h361792[56] ?
_theResult___snd__h370041 :
_theResult___snd__h370052 ;
assign sfdin__h397948 =
_theResult____h389845[56] ?
_theResult___snd__h397965 :
_theResult___snd__h397976 ;
assign sfdin__h415714 =
_theResult____h407482[56] ?
_theResult___snd__h415731 :
_theResult___snd__h415742 ;
assign sfdin__h443636 =
_theResult____h435533[56] ?
_theResult___snd__h443653 :
_theResult___snd__h443664 ;
assign sfdin__h461402 =
_theResult____h453170[56] ?
_theResult___snd__h461419 :
_theResult___snd__h461430 ;
assign sfdin__h509113 =
_theResult____h500883[56] ?
_theResult___snd__h509130 :
_theResult___snd__h509141 ;
assign sfdin__h547914 =
_theResult____h539684[56] ?
_theResult___snd__h547931 :
_theResult___snd__h547942 ;
assign sfdin__h587115 =
_theResult____h578885[56] ?
_theResult___snd__h587132 :
_theResult___snd__h587143 ;
assign shiftData__h181366 =
coreFix_memExe_regToExeQ$first[75:12] << x__h181498 ;
assign sie_csr__read__h608553 =
{ r1__read__h611381, csrf_software_int_en_vec_0 } ;
assign sip_csr__read__h608926 =
{ r1__read__h611935, csrf_software_int_pend_vec_0 } ;
assign spec_bits__h680581 = specTagManager$currentSpecBits | y__h680594 ;
assign sstatus_csr__read__h608484 = { r1__read__h610977, csrf_ie_vec_0 } ;
assign stvec_csr__read__h608596 =
{ r1__read__h611911, csrf_stvec_mode_low_reg } ;
assign upd__h3639 =
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
assign upd__h4956 = n__read__h6134 + 64'd1 ;
assign v__h294013 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ?
v__h294244 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
assign v__h294244 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
3'd1 ;
assign v__h297358 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ?
v__h297876 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
assign v__h297876 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
assign v__h307872 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ?
v__h308103 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
assign v__h308103 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
assign v__h311748 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ?
v__h311979 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
assign v__h311979 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
assign v__h326349 =
(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ?
v__h326580 :
coreFix_memExe_memRespLdQ_enqP ;
assign v__h326580 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
assign v__h329574 =
(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ?
v__h329805 :
coreFix_memExe_forwardQ_enqP ;
assign v__h329805 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
assign v__h601904 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
v__h601914 :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
assign v__h601914 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
assign v__h602945 = v__h601904 - 2'd1 ;
assign v__h606895 =
sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h607800 ;
assign v__h630583 =
sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h631336 ;
assign vaddr__h181361 =
coreFix_memExe_regToExeQ$first[139:76] +
{ {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}},
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ;
assign value_BIT_23___h531040 =
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 ;
assign value_BIT_52___h399220 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ;
assign value__h344775 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
assign value__h390465 =
{ 1'b0,
value_BIT_52___h399220,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
assign value__h436153 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
assign value__h485099 =
{ 1'b0,
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0,
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ;
assign value__h523900 =
{ 1'b0,
value_BIT_23___h531040,
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ;
assign value__h563101 =
{ 1'b0,
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0,
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ;
assign vm_mode_reg__read__h612171 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
assign w__h643238 =
coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
result__h643294 :
12'd4095 ;
assign x__h153733 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
5'd0 ;
assign x__h153739 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h157280 = { 3'd0, sbIdx__h157159 } ;
assign x__h157286 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqStQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h160096 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h160100 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h161948 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h17672 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
mmio_dataReqQ_enqReq_rl[141:78] ;
assign x__h181275 =
sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180363 ;
assign x__h181276 =
sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180969 ;
assign x__h181498 = { vaddr__h181361[2:0], 3'b0 } ;
assign x__h191752 =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
curData__h190989[63:32] :
curData__h190989[31:0] ;
assign x__h20210 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
mmio_dataReqQ_enqReq_rl[63:0] ;
assign x__h285351 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h285363 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h287217 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h300223 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
assign x__h335952 =
{ (_theResult___exp__h379284 != 8'd255 ||
_theResult___sfd__h379285 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136,
out_f_exp__h379561,
out_f_sfd__h379562 } ;
assign x__h362502 =
sfd__h336548 << (x__h362535[11] ? 12'hAAA : x__h362535) ;
assign x__h362535 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ;
assign x__h381647 =
{ (_theResult___exp__h424974 != 8'd255 ||
_theResult___sfd__h424975 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528,
out_f_exp__h425251,
out_f_sfd__h425252 } ;
assign x__h408192 =
sfd__h382243 << (x__h408225[11] ? 12'hAAA : x__h408225) ;
assign x__h408225 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ;
assign x__h427335 =
{ (_theResult___exp__h470662 != 8'd255 ||
_theResult___sfd__h470663 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920,
out_f_exp__h470939,
out_f_sfd__h470940 } ;
assign x__h453880 =
sfd__h427931 << (x__h453913[11] ? 12'hAAA : x__h453913) ;
assign x__h453913 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ;
assign x__h45579 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[141:78] :
mmio_cRqQ_enqReq_rl[141:78] ;
assign x__h479736 =
sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476872 ;
assign x__h479737 =
sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h477480 ;
assign x__h479738 =
sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h478082 ;
assign x__h48115 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[63:0] :
mmio_cRqQ_enqReq_rl[63:0] ;
assign x__h501591 = sfd__h480541 << x__h501624 ;
assign x__h501624 =
12'd57 -
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8630 ;
assign x__h540392 = sfd__h519483 << x__h540425 ;
assign x__h540425 =
12'd57 -
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10103 ;
assign x__h579593 = sfd__h558684 << x__h579626 ;
assign x__h579626 =
12'd57 -
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9340 ;
assign x__h601242 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___fst__h601253 :
a__h600705 ;
assign x__h601268 = a__h600705[63] ^ b__h600706[63] ;
assign x__h601842 = { q__h601833, r__h601834 } ;
assign x__h610962 = { csrf_frm_reg, csrf_fflags_reg } ;
assign x__h615173 =
coreFix_aluExe_1_dispToRegQ$first[131] ?
rVal1__h608010 :
v__h606895 ;
assign x__h615174 =
sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h613062 ;
assign x__h636394 =
coreFix_aluExe_0_dispToRegQ$first[131] ?
rVal1__h631544 :
v__h630583 ;
assign x__h636395 =
sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h634293 ;
assign x__h643242 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
assign x__h643293 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
assign x__h690863 =
(!rob$deqPort_0_deq_data[166] &&
(rob$deqPort_0_deq_data[165:162] == 4'd1 ||
rob$deqPort_0_deq_data[165:162] == 4'd12)) ?
rob$deqPort_0_deq_data[161:98] :
rob$deqPort_0_deq_data[95:32] ;
assign x__h696944 = { cause_code__h694327, 2'b0 } ;
assign x__h704740 = { 1'b0, csrf_spp_reg } ;
assign x__h708013 =
NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_deq_ETC___d14789 ?
y_avValue_snd_snd_snd_fst__h707835 :
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14818 ;
assign x__h75524 = mmio_pRqQ_data_0[31:0] ;
assign x_addr__h312146 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
assign x_data__h65373 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[31:0] :
mmio_pRqQ_enqReq_rl[31:0] ;
assign x_data_imm__h670087 = fetchStage$pipelines_0_first[159:128] ;
assign x_data_imm__h684830 = fetchStage$pipelines_1_first[159:128] ;
assign x_decodeInfo_frm__h651275 = csrf_frm_reg ;
assign x_quotient__h473246 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ?
64'hFFFFFFFFFFFFFFFF :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ?
q___1__h473956 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ;
assign x_reg_ifc__read__h608393 = { 63'd0, csrf_stats_module_doStats } ;
assign x_remainder__h473247 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ?
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ?
r___1__h473983 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ;
assign y__h252876 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
assign y__h643272 = ~x__h643242 ;
assign y__h648045 =
{ 3'd7,
~csrf_mideleg_11_reg,
1'd1,
~csrf_mideleg_9_7_reg,
1'd1,
~csrf_mideleg_5_3_reg,
1'd1,
~csrf_mideleg_1_0_reg } ;
assign y__h680594 = 12'd1 << specTagManager$nextSpecTag ;
assign y__h707788 =
NOT_rob_deqPort_0_canDeq__4602_4603_OR_rob_deq_ETC___d14789 ?
y_avValue_snd_snd_snd_snd_snd__h707841 :
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14710 ;
assign y_avValue__h180363 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ;
assign y_avValue__h180969 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ;
assign y_avValue__h476872 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8219 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8323 ;
assign y_avValue__h477480 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8246 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ;
assign y_avValue__h478082 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8270 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ;
assign y_avValue__h607800 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11377 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11755 ;
assign y_avValue__h613062 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1350_1_ETC___d11405 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__135_ETC___d11767 ;
assign y_avValue__h631336 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12172 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12364 ;
assign y_avValue__h634293 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2145_2_ETC___d12200 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__214_ETC___d12376 ;
assign y_avValue__h695205 =
(csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ?
base__h696929 + { 58'd0, x__h696944 } :
base__h696929 ;
assign y_avValue__h696966 =
(csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ?
base__h697132 + { 58'd0, x__h696944 } :
base__h697132 ;
assign y_avValue_fst__h673978 =
(fetchStage$pipelines_0_first[194:192] == 3'd1) ?
spec_bits__h680581 :
specTagManager$currentSpecBits ;
assign y_avValue_snd_fst__h674252 =
((fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254) ?
y_avValue_snd_fst__h674287 :
specTagManager$currentSpecBits ;
assign y_avValue_snd_fst__h674287 =
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 ?
y_avValue_fst__h673978 :
specTagManager$currentSpecBits ;
assign y_avValue_snd_fst__h707272 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ?
5'd0 :
rob$deqPort_0_deq_data[31:27] ;
assign y_avValue_snd_fst__h707825 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14796 :
y_avValue_snd_fst__h707854 ;
assign y_avValue_snd_fst__h707854 =
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14796 |
rob$deqPort_1_deq_data[31:27] ;
assign y_avValue_snd_snd_snd_fst__h707282 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ?
2'd0 :
2'd1 ;
assign y_avValue_snd_snd_snd_fst__h707835 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14818 :
y_avValue_snd_snd_snd_fst__h707864 ;
assign y_avValue_snd_snd_snd_fst__h707864 =
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14818 +
2'd1 ;
assign y_avValue_snd_snd_snd_snd_snd__h707288 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ?
64'd0 :
64'd1 ;
assign y_avValue_snd_snd_snd_snd_snd__h707841 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14710 :
y_avValue_snd_snd_snd_snd_snd__h707870 ;
assign y_avValue_snd_snd_snd_snd_snd__h707870 =
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14710 +
64'd1 ;
always@(mmio_cRqQ_data_0)
begin
case (mmio_cRqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 =
mmio_cRqQ_data_0[77:72];
2'd3:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 =
{ 2'd3, mmio_cRqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
3'd0:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
x__h195199 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
3'd0:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
3'd1:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
3'd2:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
3'd3:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
3'd4:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
3'd5:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
3'd6:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
3'd7:
x__h283918 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
addr__h288139 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
1'd1:
addr__h288139 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
3'd0:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
curData__h190989 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0, 4'd3: trap_val__h695358 = commitStage_commitTrap[132:69];
default: trap_val__h695358 =
(commitStage_commitTrap[3:0] != 4'd2 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11) ?
commitStage_commitTrap[68:5] :
64'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
x__h289688 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
1'd1:
x__h289688 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
fflags_csr__read__h608263 or
frm_csr__read__h608274 or
fcsr_csr__read__h608288 or
sstatus_csr__read__h608484 or
sie_csr__read__h608553 or
stvec_csr__read__h608596 or
scounteren_csr__read__h608649 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h608787 or
csrf_stval_csr or
sip_csr__read__h608926 or
satp_csr__read__h608989 or
mstatus_csr__read__h609132 or
medeleg_csr__read__h609280 or
mideleg_csr__read__h609375 or
mie_csr__read__h609506 or
mtvec_csr__read__h609588 or
mcounteren_csr__read__h609680 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h609935 or
csrf_mtval_csr or
mip_csr__read__h610175 or
x_reg_ifc__read__h608393 or
n__read__h610279 or n__read__h610470 or csrf_time_reg)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1: rVal1__h608010 = fflags_csr__read__h608263;
12'd2: rVal1__h608010 = frm_csr__read__h608274;
12'd3: rVal1__h608010 = fcsr_csr__read__h608288;
12'd256: rVal1__h608010 = sstatus_csr__read__h608484;
12'd260: rVal1__h608010 = sie_csr__read__h608553;
12'd261: rVal1__h608010 = stvec_csr__read__h608596;
12'd262: rVal1__h608010 = scounteren_csr__read__h608649;
12'd320: rVal1__h608010 = csrf_sscratch_csr;
12'd321: rVal1__h608010 = csrf_sepc_csr;
12'd322: rVal1__h608010 = scause_csr__read__h608787;
12'd323: rVal1__h608010 = csrf_stval_csr;
12'd324: rVal1__h608010 = sip_csr__read__h608926;
12'd384: rVal1__h608010 = satp_csr__read__h608989;
12'd768: rVal1__h608010 = mstatus_csr__read__h609132;
12'd769: rVal1__h608010 = 64'h8000000000141129;
12'd770: rVal1__h608010 = medeleg_csr__read__h609280;
12'd771: rVal1__h608010 = mideleg_csr__read__h609375;
12'd772: rVal1__h608010 = mie_csr__read__h609506;
12'd773: rVal1__h608010 = mtvec_csr__read__h609588;
12'd774: rVal1__h608010 = mcounteren_csr__read__h609680;
12'd832: rVal1__h608010 = csrf_mscratch_csr;
12'd833: rVal1__h608010 = csrf_mepc_csr;
12'd834: rVal1__h608010 = mcause_csr__read__h609935;
12'd835: rVal1__h608010 = csrf_mtval_csr;
12'd836: rVal1__h608010 = mip_csr__read__h610175;
12'd2048: rVal1__h608010 = 64'd0;
12'd2049: rVal1__h608010 = x_reg_ifc__read__h608393;
12'd2816, 12'd3072: rVal1__h608010 = n__read__h610279;
12'd2818, 12'd3074: rVal1__h608010 = n__read__h610470;
12'd3073: rVal1__h608010 = csrf_time_reg;
default: rVal1__h608010 = 64'd0;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
fflags_csr__read__h608263 or
frm_csr__read__h608274 or
fcsr_csr__read__h608288 or
sstatus_csr__read__h608484 or
sie_csr__read__h608553 or
stvec_csr__read__h608596 or
scounteren_csr__read__h608649 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h608787 or
csrf_stval_csr or
sip_csr__read__h608926 or
satp_csr__read__h608989 or
mstatus_csr__read__h609132 or
medeleg_csr__read__h609280 or
mideleg_csr__read__h609375 or
mie_csr__read__h609506 or
mtvec_csr__read__h609588 or
mcounteren_csr__read__h609680 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h609935 or
csrf_mtval_csr or
mip_csr__read__h610175 or
x_reg_ifc__read__h608393 or
n__read__h610279 or n__read__h610470 or csrf_time_reg)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1: rVal1__h631544 = fflags_csr__read__h608263;
12'd2: rVal1__h631544 = frm_csr__read__h608274;
12'd3: rVal1__h631544 = fcsr_csr__read__h608288;
12'd256: rVal1__h631544 = sstatus_csr__read__h608484;
12'd260: rVal1__h631544 = sie_csr__read__h608553;
12'd261: rVal1__h631544 = stvec_csr__read__h608596;
12'd262: rVal1__h631544 = scounteren_csr__read__h608649;
12'd320: rVal1__h631544 = csrf_sscratch_csr;
12'd321: rVal1__h631544 = csrf_sepc_csr;
12'd322: rVal1__h631544 = scause_csr__read__h608787;
12'd323: rVal1__h631544 = csrf_stval_csr;
12'd324: rVal1__h631544 = sip_csr__read__h608926;
12'd384: rVal1__h631544 = satp_csr__read__h608989;
12'd768: rVal1__h631544 = mstatus_csr__read__h609132;
12'd769: rVal1__h631544 = 64'h8000000000141129;
12'd770: rVal1__h631544 = medeleg_csr__read__h609280;
12'd771: rVal1__h631544 = mideleg_csr__read__h609375;
12'd772: rVal1__h631544 = mie_csr__read__h609506;
12'd773: rVal1__h631544 = mtvec_csr__read__h609588;
12'd774: rVal1__h631544 = mcounteren_csr__read__h609680;
12'd832: rVal1__h631544 = csrf_mscratch_csr;
12'd833: rVal1__h631544 = csrf_mepc_csr;
12'd834: rVal1__h631544 = mcause_csr__read__h609935;
12'd835: rVal1__h631544 = csrf_mtval_csr;
12'd836: rVal1__h631544 = mip_csr__read__h610175;
12'd2048: rVal1__h631544 = 64'd0;
12'd2049: rVal1__h631544 = x_reg_ifc__read__h608393;
12'd2816, 12'd3072: rVal1__h631544 = n__read__h610279;
12'd2818, 12'd3074: rVal1__h631544 = n__read__h610470;
12'd3073: rVal1__h631544 = csrf_time_reg;
default: rVal1__h631544 = 64'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h389827 = 8'd255;
3'd2:
_theResult___fst_exp__h389827 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h389827 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h389827 = 8'd254;
default: _theResult___fst_exp__h389827 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h344135 = 8'd255;
3'd2:
_theResult___fst_exp__h344135 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h344135 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h344135 = 8'd254;
default: _theResult___fst_exp__h344135 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h344136 = 23'd0;
3'd2:
_theResult___fst_sfd__h344136 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h344136 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h344136 = 23'd8388607;
default: _theResult___fst_sfd__h344136 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h389828 = 23'd0;
3'd2:
_theResult___fst_sfd__h389828 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h389828 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h389828 = 23'd8388607;
default: _theResult___fst_sfd__h389828 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h435515 = 8'd255;
3'd2:
_theResult___fst_exp__h435515 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h435515 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h435515 = 8'd254;
default: _theResult___fst_exp__h435515 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h435516 = 23'd0;
3'd2:
_theResult___fst_sfd__h435516 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h435516 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h435516 = 23'd8388607;
default: _theResult___fst_sfd__h435516 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 52'd0;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
i__h694342 = commitStage_commitTrap[3:0];
default: i__h694342 = 4'd15;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
i__h694502 = commitStage_commitTrap[3:0];
default: i__h694502 = 4'd14;
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[15:0];
2'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[31:16];
2'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[47:32];
2'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
coreFix_memExe_respLrScAmoQ_data_0[31:0];
1'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
coreFix_memExe_respLrScAmoQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[7:0];
3'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[15:8];
3'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[23:16];
3'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[31:24];
3'd4:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[39:32];
3'd5:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[47:40];
3'd6:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[55:48];
3'd7:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
mmio_dataRespQ_data_0[31:0];
1'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
mmio_dataRespQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[15:0];
2'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[31:16];
2'd2:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[47:32];
2'd3:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[7:0];
3'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[15:8];
3'd2:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[23:16];
3'd3:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[31:24];
3'd4:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[39:32];
3'd5:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[47:40];
3'd6:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[55:48];
3'd7:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[105:103])
3'd0, 3'd2:
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 = 4'd4;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 = 4'd6;
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[109:106])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 =
coreFix_memExe_dTlb$procResp[109:106];
4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd10;
4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd11;
4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd12;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd13;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
1'd1:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h352872 or
_theResult___fst_exp__h360920 or
out_exp__h361365 or _theResult___exp__h361362)
begin
case (guard__h352872)
2'b0, 2'b01:
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q24 =
_theResult___fst_exp__h360920;
2'b10:
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q24 =
out_exp__h361365;
2'b11:
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q24 =
_theResult___exp__h361362;
endcase
end
always@(guard__h352872 or
_theResult___fst_exp__h360920 or _theResult___exp__h361362)
begin
case (guard__h352872)
2'b0:
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q25 =
_theResult___fst_exp__h360920;
2'b01, 2'b10, 2'b11:
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q25 =
_theResult___exp__h361362;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q24 or
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q25 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or
_theResult___fst_exp__h360920)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h361440 =
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q24;
3'd1:
_theResult___fst_exp__h361440 =
CASE_guard52872_0b0_theResult___fst_exp60920_0_ETC__q25;
3'd2:
_theResult___fst_exp__h361440 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528;
3'd3:
_theResult___fst_exp__h361440 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530;
3'd4: _theResult___fst_exp__h361440 = _theResult___fst_exp__h360920;
default: _theResult___fst_exp__h361440 = 8'd0;
endcase
end
always@(guard__h344163 or
_theResult___fst_exp__h352264 or
out_exp__h352783 or _theResult___exp__h352780)
begin
case (guard__h344163)
2'b0, 2'b01:
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q26 =
_theResult___fst_exp__h352264;
2'b10:
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q26 =
out_exp__h352783;
2'b11:
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q26 =
_theResult___exp__h352780;
endcase
end
always@(guard__h344163 or
_theResult___fst_exp__h352264 or _theResult___exp__h352780)
begin
case (guard__h344163)
2'b0:
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q27 =
_theResult___fst_exp__h352264;
2'b01, 2'b10, 2'b11:
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q27 =
_theResult___exp__h352780;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q26 or
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q27 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or
_theResult___fst_exp__h352264)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h352858 =
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q26;
3'd1:
_theResult___fst_exp__h352858 =
CASE_guard44163_0b0_theResult___fst_exp52264_0_ETC__q27;
3'd2:
_theResult___fst_exp__h352858 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306;
3'd3:
_theResult___fst_exp__h352858 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309;
3'd4: _theResult___fst_exp__h352858 = _theResult___fst_exp__h352264;
default: _theResult___fst_exp__h352858 = 8'd0;
endcase
end
always@(guard__h361802 or
_theResult___fst_exp__h370030 or
out_exp__h370549 or _theResult___exp__h370546)
begin
case (guard__h361802)
2'b0, 2'b01:
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q32 =
_theResult___fst_exp__h370030;
2'b10:
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q32 =
out_exp__h370549;
2'b11:
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q32 =
_theResult___exp__h370546;
endcase
end
always@(guard__h361802 or
_theResult___fst_exp__h370030 or _theResult___exp__h370546)
begin
case (guard__h361802)
2'b0:
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q33 =
_theResult___fst_exp__h370030;
2'b01, 2'b10, 2'b11:
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q33 =
_theResult___exp__h370546;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q32 or
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q33 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or
_theResult___fst_exp__h370030)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h370624 =
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q32;
3'd1:
_theResult___fst_exp__h370624 =
CASE_guard61802_0b0_theResult___fst_exp70030_0_ETC__q33;
3'd2:
_theResult___fst_exp__h370624 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853;
3'd3:
_theResult___fst_exp__h370624 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855;
3'd4: _theResult___fst_exp__h370624 = _theResult___fst_exp__h370030;
default: _theResult___fst_exp__h370624 = 8'd0;
endcase
end
always@(guard__h370638 or
_theResult___fst_exp__h378715 or
out_exp__h379185 or _theResult___exp__h379182)
begin
case (guard__h370638)
2'b0, 2'b01:
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q37 =
_theResult___fst_exp__h378715;
2'b10:
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q37 =
out_exp__h379185;
2'b11:
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q37 =
_theResult___exp__h379182;
endcase
end
always@(guard__h370638 or
_theResult___fst_exp__h378715 or _theResult___exp__h379182)
begin
case (guard__h370638)
2'b0:
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q38 =
_theResult___fst_exp__h378715;
2'b01, 2'b10, 2'b11:
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q38 =
_theResult___exp__h379182;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q37 or
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q38 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or
_theResult___fst_exp__h378715)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h379260 =
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q37;
3'd1:
_theResult___fst_exp__h379260 =
CASE_guard70638_0b0_theResult___fst_exp78715_0_ETC__q38;
3'd2:
_theResult___fst_exp__h379260 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922;
3'd3:
_theResult___fst_exp__h379260 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924;
3'd4: _theResult___fst_exp__h379260 = _theResult___fst_exp__h378715;
default: _theResult___fst_exp__h379260 = 8'd0;
endcase
end
always@(guard__h352872 or
_theResult___snd__h360871 or
out_sfd__h361366 or _theResult___sfd__h361363)
begin
case (guard__h352872)
2'b0, 2'b01:
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q39 =
_theResult___snd__h360871[56:34];
2'b10:
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q39 =
out_sfd__h361366;
2'b11:
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q39 =
_theResult___sfd__h361363;
endcase
end
always@(guard__h352872 or
_theResult___snd__h360871 or _theResult___sfd__h361363)
begin
case (guard__h352872)
2'b0:
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q40 =
_theResult___snd__h360871[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q40 =
_theResult___sfd__h361363;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q39 or
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q40 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or
_theResult___snd__h360871)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h361441 =
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q39;
3'd1:
_theResult___fst_sfd__h361441 =
CASE_guard52872_0b0_theResult___snd60871_BITS__ETC__q40;
3'd2:
_theResult___fst_sfd__h361441 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972;
3'd3:
_theResult___fst_sfd__h361441 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974;
3'd4: _theResult___fst_sfd__h361441 = _theResult___snd__h360871[56:34];
default: _theResult___fst_sfd__h361441 = 23'd0;
endcase
end
always@(guard__h344163 or
sfdin__h352258 or out_sfd__h352784 or _theResult___sfd__h352781)
begin
case (guard__h344163)
2'b0, 2'b01:
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q41 =
sfdin__h352258[56:34];
2'b10:
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q41 =
out_sfd__h352784;
2'b11:
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q41 =
_theResult___sfd__h352781;
endcase
end
always@(guard__h344163 or sfdin__h352258 or _theResult___sfd__h352781)
begin
case (guard__h344163)
2'b0:
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q42 =
sfdin__h352258[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q42 =
_theResult___sfd__h352781;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q41 or
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q42 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or
sfdin__h352258)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h352859 =
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q41;
3'd1:
_theResult___fst_sfd__h352859 =
CASE_guard44163_0b0_sfdin52258_BITS_56_TO_34_0_ETC__q42;
3'd2:
_theResult___fst_sfd__h352859 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953;
3'd3:
_theResult___fst_sfd__h352859 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955;
3'd4: _theResult___fst_sfd__h352859 = sfdin__h352258[56:34];
default: _theResult___fst_sfd__h352859 = 23'd0;
endcase
end
always@(guard__h361802 or
sfdin__h370024 or out_sfd__h370550 or _theResult___sfd__h370547)
begin
case (guard__h361802)
2'b0, 2'b01:
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q43 =
sfdin__h370024[56:34];
2'b10:
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q43 =
out_sfd__h370550;
2'b11:
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q43 =
_theResult___sfd__h370547;
endcase
end
always@(guard__h361802 or sfdin__h370024 or _theResult___sfd__h370547)
begin
case (guard__h361802)
2'b0:
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q44 =
sfdin__h370024[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q44 =
_theResult___sfd__h370547;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q43 or
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q44 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or
sfdin__h370024)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h370625 =
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q43;
3'd1:
_theResult___fst_sfd__h370625 =
CASE_guard61802_0b0_sfdin70024_BITS_56_TO_34_0_ETC__q44;
3'd2:
_theResult___fst_sfd__h370625 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999;
3'd3:
_theResult___fst_sfd__h370625 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001;
3'd4: _theResult___fst_sfd__h370625 = sfdin__h370024[56:34];
default: _theResult___fst_sfd__h370625 = 23'd0;
endcase
end
always@(guard__h370638 or
_theResult___snd__h378661 or
out_sfd__h379186 or _theResult___sfd__h379183)
begin
case (guard__h370638)
2'b0, 2'b01:
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q45 =
_theResult___snd__h378661[56:34];
2'b10:
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q45 =
out_sfd__h379186;
2'b11:
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q45 =
_theResult___sfd__h379183;
endcase
end
always@(guard__h370638 or
_theResult___snd__h378661 or _theResult___sfd__h379183)
begin
case (guard__h370638)
2'b0:
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q46 =
_theResult___snd__h378661[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q46 =
_theResult___sfd__h379183;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q45 or
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q46 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or
_theResult___snd__h378661)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h379261 =
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q45;
3'd1:
_theResult___fst_sfd__h379261 =
CASE_guard70638_0b0_theResult___snd78661_BITS__ETC__q46;
3'd2:
_theResult___fst_sfd__h379261 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018;
3'd3:
_theResult___fst_sfd__h379261 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020;
3'd4: _theResult___fst_sfd__h379261 = _theResult___snd__h378661[56:34];
default: _theResult___fst_sfd__h379261 = 23'd0;
endcase
end
always@(guard__h344163 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h344163)
2'b0, 2'b01, 2'b10:
CASE_guard44163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard44163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 =
guard__h344163 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard44163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or
guard__h344163)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
CASE_guard44163_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
(guard__h344163 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h344163 == 2'b01 || guard__h344163 == 2'b10 ||
guard__h344163 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h344163 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h344163)
2'b0, 2'b01, 2'b10:
CASE_guard44163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard44163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 =
guard__h344163 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard44163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 or
guard__h344163)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
CASE_guard44163_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
(guard__h344163 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h344163 != 2'b01 && guard__h344163 != 2'b10 &&
guard__h344163 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h352872 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h352872)
2'b0, 2'b01, 2'b10:
CASE_guard52872_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard52872_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 =
guard__h352872 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard52872_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 or
guard__h352872)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
CASE_guard52872_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
(guard__h352872 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h352872 == 2'b01 || guard__h352872 == 2'b10 ||
guard__h352872 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h352872 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h352872)
2'b0, 2'b01, 2'b10:
CASE_guard52872_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard52872_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 =
guard__h352872 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard52872_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or
guard__h352872)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
CASE_guard52872_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
(guard__h352872 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h352872 != 2'b01 && guard__h352872 != 2'b10 &&
guard__h352872 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h361802 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h361802)
2'b0, 2'b01, 2'b10:
CASE_guard61802_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard61802_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 =
guard__h361802 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard61802_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51 or
guard__h361802)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
CASE_guard61802_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q51;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
(guard__h361802 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h361802 == 2'b01 || guard__h361802 == 2'b10 ||
guard__h361802 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h361802 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h361802)
2'b0, 2'b01, 2'b10:
CASE_guard61802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q52 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard61802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q52 =
guard__h361802 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard61802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q52 or
guard__h361802)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
CASE_guard61802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q52;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
(guard__h361802 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h361802 != 2'b01 && guard__h361802 != 2'b10 &&
guard__h361802 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h370638 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h370638)
2'b0, 2'b01, 2'b10:
CASE_guard70638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard70638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 =
guard__h370638 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard70638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or
guard__h370638)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
CASE_guard70638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
(guard__h370638 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h370638 == 2'b01 || guard__h370638 == 2'b10 ||
guard__h370638 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h370638 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h370638)
2'b0, 2'b01, 2'b10:
CASE_guard70638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard70638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 =
guard__h370638 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard70638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54 or
guard__h370638)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
CASE_guard70638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q54;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
(guard__h370638 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h370638 != 2'b01 && guard__h370638 != 2'b10 &&
guard__h370638 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h398562 or
_theResult___fst_exp__h406610 or
out_exp__h407055 or _theResult___exp__h407052)
begin
case (guard__h398562)
2'b0, 2'b01:
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q59 =
_theResult___fst_exp__h406610;
2'b10:
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q59 =
out_exp__h407055;
2'b11:
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q59 =
_theResult___exp__h407052;
endcase
end
always@(guard__h398562 or
_theResult___fst_exp__h406610 or _theResult___exp__h407052)
begin
case (guard__h398562)
2'b0:
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q60 =
_theResult___fst_exp__h406610;
2'b01, 2'b10, 2'b11:
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q60 =
_theResult___exp__h407052;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q59 or
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q60 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or
_theResult___fst_exp__h406610)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h407130 =
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q59;
3'd1:
_theResult___fst_exp__h407130 =
CASE_guard98562_0b0_theResult___fst_exp06610_0_ETC__q60;
3'd2:
_theResult___fst_exp__h407130 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920;
3'd3:
_theResult___fst_exp__h407130 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922;
3'd4: _theResult___fst_exp__h407130 = _theResult___fst_exp__h406610;
default: _theResult___fst_exp__h407130 = 8'd0;
endcase
end
always@(guard__h389855 or
_theResult___fst_exp__h397954 or
out_exp__h398473 or _theResult___exp__h398470)
begin
case (guard__h389855)
2'b0, 2'b01:
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q61 =
_theResult___fst_exp__h397954;
2'b10:
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q61 =
out_exp__h398473;
2'b11:
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q61 =
_theResult___exp__h398470;
endcase
end
always@(guard__h389855 or
_theResult___fst_exp__h397954 or _theResult___exp__h398470)
begin
case (guard__h389855)
2'b0:
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q62 =
_theResult___fst_exp__h397954;
2'b01, 2'b10, 2'b11:
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q62 =
_theResult___exp__h398470;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q61 or
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q62 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or
_theResult___fst_exp__h397954)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h398548 =
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q61;
3'd1:
_theResult___fst_exp__h398548 =
CASE_guard89855_0b0_theResult___fst_exp97954_0_ETC__q62;
3'd2:
_theResult___fst_exp__h398548 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698;
3'd3:
_theResult___fst_exp__h398548 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701;
3'd4: _theResult___fst_exp__h398548 = _theResult___fst_exp__h397954;
default: _theResult___fst_exp__h398548 = 8'd0;
endcase
end
always@(guard__h407492 or
_theResult___fst_exp__h415720 or
out_exp__h416239 or _theResult___exp__h416236)
begin
case (guard__h407492)
2'b0, 2'b01:
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q67 =
_theResult___fst_exp__h415720;
2'b10:
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q67 =
out_exp__h416239;
2'b11:
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q67 =
_theResult___exp__h416236;
endcase
end
always@(guard__h407492 or
_theResult___fst_exp__h415720 or _theResult___exp__h416236)
begin
case (guard__h407492)
2'b0:
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q68 =
_theResult___fst_exp__h415720;
2'b01, 2'b10, 2'b11:
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q68 =
_theResult___exp__h416236;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q67 or
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q68 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or
_theResult___fst_exp__h415720)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h416314 =
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q67;
3'd1:
_theResult___fst_exp__h416314 =
CASE_guard07492_0b0_theResult___fst_exp15720_0_ETC__q68;
3'd2:
_theResult___fst_exp__h416314 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245;
3'd3:
_theResult___fst_exp__h416314 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247;
3'd4: _theResult___fst_exp__h416314 = _theResult___fst_exp__h415720;
default: _theResult___fst_exp__h416314 = 8'd0;
endcase
end
always@(guard__h416328 or
_theResult___fst_exp__h424405 or
out_exp__h424875 or _theResult___exp__h424872)
begin
case (guard__h416328)
2'b0, 2'b01:
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q72 =
_theResult___fst_exp__h424405;
2'b10:
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q72 =
out_exp__h424875;
2'b11:
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q72 =
_theResult___exp__h424872;
endcase
end
always@(guard__h416328 or
_theResult___fst_exp__h424405 or _theResult___exp__h424872)
begin
case (guard__h416328)
2'b0:
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q73 =
_theResult___fst_exp__h424405;
2'b01, 2'b10, 2'b11:
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q73 =
_theResult___exp__h424872;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q72 or
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q73 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or
_theResult___fst_exp__h424405)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h424950 =
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q72;
3'd1:
_theResult___fst_exp__h424950 =
CASE_guard16328_0b0_theResult___fst_exp24405_0_ETC__q73;
3'd2:
_theResult___fst_exp__h424950 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314;
3'd3:
_theResult___fst_exp__h424950 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316;
3'd4: _theResult___fst_exp__h424950 = _theResult___fst_exp__h424405;
default: _theResult___fst_exp__h424950 = 8'd0;
endcase
end
always@(guard__h398562 or
_theResult___snd__h406561 or
out_sfd__h407056 or _theResult___sfd__h407053)
begin
case (guard__h398562)
2'b0, 2'b01:
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q74 =
_theResult___snd__h406561[56:34];
2'b10:
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q74 =
out_sfd__h407056;
2'b11:
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q74 =
_theResult___sfd__h407053;
endcase
end
always@(guard__h398562 or
_theResult___snd__h406561 or _theResult___sfd__h407053)
begin
case (guard__h398562)
2'b0:
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q75 =
_theResult___snd__h406561[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q75 =
_theResult___sfd__h407053;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q74 or
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q75 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or
_theResult___snd__h406561)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h407131 =
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q74;
3'd1:
_theResult___fst_sfd__h407131 =
CASE_guard98562_0b0_theResult___snd06561_BITS__ETC__q75;
3'd2:
_theResult___fst_sfd__h407131 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364;
3'd3:
_theResult___fst_sfd__h407131 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366;
3'd4: _theResult___fst_sfd__h407131 = _theResult___snd__h406561[56:34];
default: _theResult___fst_sfd__h407131 = 23'd0;
endcase
end
always@(guard__h389855 or
sfdin__h397948 or out_sfd__h398474 or _theResult___sfd__h398471)
begin
case (guard__h389855)
2'b0, 2'b01:
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q76 =
sfdin__h397948[56:34];
2'b10:
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q76 =
out_sfd__h398474;
2'b11:
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q76 =
_theResult___sfd__h398471;
endcase
end
always@(guard__h389855 or sfdin__h397948 or _theResult___sfd__h398471)
begin
case (guard__h389855)
2'b0:
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q77 =
sfdin__h397948[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q77 =
_theResult___sfd__h398471;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q76 or
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q77 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or
sfdin__h397948)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h398549 =
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q76;
3'd1:
_theResult___fst_sfd__h398549 =
CASE_guard89855_0b0_sfdin97948_BITS_56_TO_34_0_ETC__q77;
3'd2:
_theResult___fst_sfd__h398549 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345;
3'd3:
_theResult___fst_sfd__h398549 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347;
3'd4: _theResult___fst_sfd__h398549 = sfdin__h397948[56:34];
default: _theResult___fst_sfd__h398549 = 23'd0;
endcase
end
always@(guard__h407492 or
sfdin__h415714 or out_sfd__h416240 or _theResult___sfd__h416237)
begin
case (guard__h407492)
2'b0, 2'b01:
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q78 =
sfdin__h415714[56:34];
2'b10:
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q78 =
out_sfd__h416240;
2'b11:
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q78 =
_theResult___sfd__h416237;
endcase
end
always@(guard__h407492 or sfdin__h415714 or _theResult___sfd__h416237)
begin
case (guard__h407492)
2'b0:
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q79 =
sfdin__h415714[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q79 =
_theResult___sfd__h416237;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q78 or
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q79 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or
sfdin__h415714)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h416315 =
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q78;
3'd1:
_theResult___fst_sfd__h416315 =
CASE_guard07492_0b0_sfdin15714_BITS_56_TO_34_0_ETC__q79;
3'd2:
_theResult___fst_sfd__h416315 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391;
3'd3:
_theResult___fst_sfd__h416315 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393;
3'd4: _theResult___fst_sfd__h416315 = sfdin__h415714[56:34];
default: _theResult___fst_sfd__h416315 = 23'd0;
endcase
end
always@(guard__h416328 or
_theResult___snd__h424351 or
out_sfd__h424876 or _theResult___sfd__h424873)
begin
case (guard__h416328)
2'b0, 2'b01:
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q80 =
_theResult___snd__h424351[56:34];
2'b10:
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q80 =
out_sfd__h424876;
2'b11:
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q80 =
_theResult___sfd__h424873;
endcase
end
always@(guard__h416328 or
_theResult___snd__h424351 or _theResult___sfd__h424873)
begin
case (guard__h416328)
2'b0:
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q81 =
_theResult___snd__h424351[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q81 =
_theResult___sfd__h424873;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q80 or
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q81 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or
_theResult___snd__h424351)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h424951 =
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q80;
3'd1:
_theResult___fst_sfd__h424951 =
CASE_guard16328_0b0_theResult___snd24351_BITS__ETC__q81;
3'd2:
_theResult___fst_sfd__h424951 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410;
3'd3:
_theResult___fst_sfd__h424951 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412;
3'd4: _theResult___fst_sfd__h424951 = _theResult___snd__h424351[56:34];
default: _theResult___fst_sfd__h424951 = 23'd0;
endcase
end
always@(guard__h389855 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h389855)
2'b0, 2'b01, 2'b10:
CASE_guard89855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard89855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 =
guard__h389855 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard89855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82 or
guard__h389855)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
CASE_guard89855_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q82;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
(guard__h389855 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h389855 == 2'b01 || guard__h389855 == 2'b10 ||
guard__h389855 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h389855 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h389855)
2'b0, 2'b01, 2'b10:
CASE_guard89855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard89855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 =
guard__h389855 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard89855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83 or
guard__h389855)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
CASE_guard89855_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q83;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
(guard__h389855 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h389855 != 2'b01 && guard__h389855 != 2'b10 &&
guard__h389855 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h398562 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h398562)
2'b0, 2'b01, 2'b10:
CASE_guard98562_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard98562_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 =
guard__h398562 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard98562_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or
guard__h398562)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
CASE_guard98562_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
(guard__h398562 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h398562 == 2'b01 || guard__h398562 == 2'b10 ||
guard__h398562 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h398562 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h398562)
2'b0, 2'b01, 2'b10:
CASE_guard98562_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard98562_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 =
guard__h398562 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard98562_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or
guard__h398562)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
CASE_guard98562_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
(guard__h398562 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h398562 != 2'b01 && guard__h398562 != 2'b10 &&
guard__h398562 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h407492 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h407492)
2'b0, 2'b01, 2'b10:
CASE_guard07492_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard07492_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 =
guard__h407492 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard07492_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or
guard__h407492)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
CASE_guard07492_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
(guard__h407492 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h407492 == 2'b01 || guard__h407492 == 2'b10 ||
guard__h407492 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h407492 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h407492)
2'b0, 2'b01, 2'b10:
CASE_guard07492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard07492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 =
guard__h407492 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard07492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or
guard__h407492)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
CASE_guard07492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
(guard__h407492 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h407492 != 2'b01 && guard__h407492 != 2'b10 &&
guard__h407492 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h416328 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h416328)
2'b0, 2'b01, 2'b10:
CASE_guard16328_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard16328_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 =
guard__h416328 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard16328_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or
guard__h416328)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
CASE_guard16328_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
(guard__h416328 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h416328 == 2'b01 || guard__h416328 == 2'b10 ||
guard__h416328 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h416328 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h416328)
2'b0, 2'b01, 2'b10:
CASE_guard16328_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard16328_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 =
guard__h416328 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard16328_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or
guard__h416328)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
CASE_guard16328_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
(guard__h416328 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h416328 != 2'b01 && guard__h416328 != 2'b10 &&
guard__h416328 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h444250 or
_theResult___fst_exp__h452298 or
out_exp__h452743 or _theResult___exp__h452740)
begin
case (guard__h444250)
2'b0, 2'b01:
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q94 =
_theResult___fst_exp__h452298;
2'b10:
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q94 =
out_exp__h452743;
2'b11:
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q94 =
_theResult___exp__h452740;
endcase
end
always@(guard__h444250 or
_theResult___fst_exp__h452298 or _theResult___exp__h452740)
begin
case (guard__h444250)
2'b0:
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q95 =
_theResult___fst_exp__h452298;
2'b01, 2'b10, 2'b11:
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q95 =
_theResult___exp__h452740;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q94 or
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q95 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or
_theResult___fst_exp__h452298)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h452818 =
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q94;
3'd1:
_theResult___fst_exp__h452818 =
CASE_guard44250_0b0_theResult___fst_exp52298_0_ETC__q95;
3'd2:
_theResult___fst_exp__h452818 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312;
3'd3:
_theResult___fst_exp__h452818 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314;
3'd4: _theResult___fst_exp__h452818 = _theResult___fst_exp__h452298;
default: _theResult___fst_exp__h452818 = 8'd0;
endcase
end
always@(guard__h435543 or
_theResult___fst_exp__h443642 or
out_exp__h444161 or _theResult___exp__h444158)
begin
case (guard__h435543)
2'b0, 2'b01:
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q96 =
_theResult___fst_exp__h443642;
2'b10:
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q96 =
out_exp__h444161;
2'b11:
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q96 =
_theResult___exp__h444158;
endcase
end
always@(guard__h435543 or
_theResult___fst_exp__h443642 or _theResult___exp__h444158)
begin
case (guard__h435543)
2'b0:
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q97 =
_theResult___fst_exp__h443642;
2'b01, 2'b10, 2'b11:
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q97 =
_theResult___exp__h444158;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q96 or
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q97 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or
_theResult___fst_exp__h443642)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h444236 =
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q96;
3'd1:
_theResult___fst_exp__h444236 =
CASE_guard35543_0b0_theResult___fst_exp43642_0_ETC__q97;
3'd2:
_theResult___fst_exp__h444236 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090;
3'd3:
_theResult___fst_exp__h444236 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093;
3'd4: _theResult___fst_exp__h444236 = _theResult___fst_exp__h443642;
default: _theResult___fst_exp__h444236 = 8'd0;
endcase
end
always@(guard__h453180 or
_theResult___fst_exp__h461408 or
out_exp__h461927 or _theResult___exp__h461924)
begin
case (guard__h453180)
2'b0, 2'b01:
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q102 =
_theResult___fst_exp__h461408;
2'b10:
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q102 =
out_exp__h461927;
2'b11:
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q102 =
_theResult___exp__h461924;
endcase
end
always@(guard__h453180 or
_theResult___fst_exp__h461408 or _theResult___exp__h461924)
begin
case (guard__h453180)
2'b0:
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q103 =
_theResult___fst_exp__h461408;
2'b01, 2'b10, 2'b11:
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q103 =
_theResult___exp__h461924;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q102 or
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q103 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or
_theResult___fst_exp__h461408)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h462002 =
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q102;
3'd1:
_theResult___fst_exp__h462002 =
CASE_guard53180_0b0_theResult___fst_exp61408_0_ETC__q103;
3'd2:
_theResult___fst_exp__h462002 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637;
3'd3:
_theResult___fst_exp__h462002 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639;
3'd4: _theResult___fst_exp__h462002 = _theResult___fst_exp__h461408;
default: _theResult___fst_exp__h462002 = 8'd0;
endcase
end
always@(guard__h462016 or
_theResult___fst_exp__h470093 or
out_exp__h470563 or _theResult___exp__h470560)
begin
case (guard__h462016)
2'b0, 2'b01:
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q107 =
_theResult___fst_exp__h470093;
2'b10:
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q107 =
out_exp__h470563;
2'b11:
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q107 =
_theResult___exp__h470560;
endcase
end
always@(guard__h462016 or
_theResult___fst_exp__h470093 or _theResult___exp__h470560)
begin
case (guard__h462016)
2'b0:
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q108 =
_theResult___fst_exp__h470093;
2'b01, 2'b10, 2'b11:
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q108 =
_theResult___exp__h470560;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q107 or
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q108 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or
_theResult___fst_exp__h470093)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h470638 =
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q107;
3'd1:
_theResult___fst_exp__h470638 =
CASE_guard62016_0b0_theResult___fst_exp70093_0_ETC__q108;
3'd2:
_theResult___fst_exp__h470638 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706;
3'd3:
_theResult___fst_exp__h470638 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708;
3'd4: _theResult___fst_exp__h470638 = _theResult___fst_exp__h470093;
default: _theResult___fst_exp__h470638 = 8'd0;
endcase
end
always@(guard__h444250 or
_theResult___snd__h452249 or
out_sfd__h452744 or _theResult___sfd__h452741)
begin
case (guard__h444250)
2'b0, 2'b01:
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q109 =
_theResult___snd__h452249[56:34];
2'b10:
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q109 =
out_sfd__h452744;
2'b11:
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q109 =
_theResult___sfd__h452741;
endcase
end
always@(guard__h444250 or
_theResult___snd__h452249 or _theResult___sfd__h452741)
begin
case (guard__h444250)
2'b0:
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q110 =
_theResult___snd__h452249[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q110 =
_theResult___sfd__h452741;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q109 or
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q110 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or
_theResult___snd__h452249)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h452819 =
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q109;
3'd1:
_theResult___fst_sfd__h452819 =
CASE_guard44250_0b0_theResult___snd52249_BITS__ETC__q110;
3'd2:
_theResult___fst_sfd__h452819 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756;
3'd3:
_theResult___fst_sfd__h452819 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758;
3'd4: _theResult___fst_sfd__h452819 = _theResult___snd__h452249[56:34];
default: _theResult___fst_sfd__h452819 = 23'd0;
endcase
end
always@(guard__h435543 or
sfdin__h443636 or out_sfd__h444162 or _theResult___sfd__h444159)
begin
case (guard__h435543)
2'b0, 2'b01:
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q111 =
sfdin__h443636[56:34];
2'b10:
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q111 =
out_sfd__h444162;
2'b11:
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q111 =
_theResult___sfd__h444159;
endcase
end
always@(guard__h435543 or sfdin__h443636 or _theResult___sfd__h444159)
begin
case (guard__h435543)
2'b0:
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q112 =
sfdin__h443636[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q112 =
_theResult___sfd__h444159;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q111 or
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q112 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or
sfdin__h443636)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h444237 =
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q111;
3'd1:
_theResult___fst_sfd__h444237 =
CASE_guard35543_0b0_sfdin43636_BITS_56_TO_34_0_ETC__q112;
3'd2:
_theResult___fst_sfd__h444237 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737;
3'd3:
_theResult___fst_sfd__h444237 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739;
3'd4: _theResult___fst_sfd__h444237 = sfdin__h443636[56:34];
default: _theResult___fst_sfd__h444237 = 23'd0;
endcase
end
always@(guard__h453180 or
sfdin__h461402 or out_sfd__h461928 or _theResult___sfd__h461925)
begin
case (guard__h453180)
2'b0, 2'b01:
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q113 =
sfdin__h461402[56:34];
2'b10:
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q113 =
out_sfd__h461928;
2'b11:
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q113 =
_theResult___sfd__h461925;
endcase
end
always@(guard__h453180 or sfdin__h461402 or _theResult___sfd__h461925)
begin
case (guard__h453180)
2'b0:
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q114 =
sfdin__h461402[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q114 =
_theResult___sfd__h461925;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q113 or
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q114 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or
sfdin__h461402)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h462003 =
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q113;
3'd1:
_theResult___fst_sfd__h462003 =
CASE_guard53180_0b0_sfdin61402_BITS_56_TO_34_0_ETC__q114;
3'd2:
_theResult___fst_sfd__h462003 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783;
3'd3:
_theResult___fst_sfd__h462003 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785;
3'd4: _theResult___fst_sfd__h462003 = sfdin__h461402[56:34];
default: _theResult___fst_sfd__h462003 = 23'd0;
endcase
end
always@(guard__h462016 or
_theResult___snd__h470039 or
out_sfd__h470564 or _theResult___sfd__h470561)
begin
case (guard__h462016)
2'b0, 2'b01:
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q115 =
_theResult___snd__h470039[56:34];
2'b10:
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q115 =
out_sfd__h470564;
2'b11:
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q115 =
_theResult___sfd__h470561;
endcase
end
always@(guard__h462016 or
_theResult___snd__h470039 or _theResult___sfd__h470561)
begin
case (guard__h462016)
2'b0:
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q116 =
_theResult___snd__h470039[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q116 =
_theResult___sfd__h470561;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q115 or
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q116 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or
_theResult___snd__h470039)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h470639 =
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q115;
3'd1:
_theResult___fst_sfd__h470639 =
CASE_guard62016_0b0_theResult___snd70039_BITS__ETC__q116;
3'd2:
_theResult___fst_sfd__h470639 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802;
3'd3:
_theResult___fst_sfd__h470639 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804;
3'd4: _theResult___fst_sfd__h470639 = _theResult___snd__h470039[56:34];
default: _theResult___fst_sfd__h470639 = 23'd0;
endcase
end
always@(guard__h435543 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h435543)
2'b0, 2'b01, 2'b10:
CASE_guard35543_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard35543_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 =
guard__h435543 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard35543_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or
guard__h435543)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
CASE_guard35543_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
(guard__h435543 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h435543 == 2'b01 || guard__h435543 == 2'b10 ||
guard__h435543 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h435543 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h435543)
2'b0, 2'b01, 2'b10:
CASE_guard35543_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard35543_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 =
guard__h435543 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard35543_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or
guard__h435543)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
CASE_guard35543_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
(guard__h435543 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h435543 != 2'b01 && guard__h435543 != 2'b10 &&
guard__h435543 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h444250 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h444250)
2'b0, 2'b01, 2'b10:
CASE_guard44250_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard44250_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 =
guard__h444250 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard44250_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or
guard__h444250)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
CASE_guard44250_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
(guard__h444250 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h444250 == 2'b01 || guard__h444250 == 2'b10 ||
guard__h444250 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h444250 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h444250)
2'b0, 2'b01, 2'b10:
CASE_guard44250_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard44250_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 =
guard__h444250 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard44250_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or
guard__h444250)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
CASE_guard44250_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
(guard__h444250 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h444250 != 2'b01 && guard__h444250 != 2'b10 &&
guard__h444250 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h453180 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h453180)
2'b0, 2'b01, 2'b10:
CASE_guard53180_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard53180_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 =
guard__h453180 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard53180_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or
guard__h453180)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
CASE_guard53180_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
(guard__h453180 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h453180 == 2'b01 || guard__h453180 == 2'b10 ||
guard__h453180 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h453180 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h453180)
2'b0, 2'b01, 2'b10:
CASE_guard53180_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard53180_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 =
guard__h453180 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard53180_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or
guard__h453180)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
CASE_guard53180_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
(guard__h453180 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h453180 != 2'b01 && guard__h453180 != 2'b10 &&
guard__h453180 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h462016 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h462016)
2'b0, 2'b01, 2'b10:
CASE_guard62016_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard62016_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 =
guard__h462016 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard62016_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or
guard__h462016)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
CASE_guard62016_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
(guard__h462016 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h462016 == 2'b01 || guard__h462016 == 2'b10 ||
guard__h462016 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h462016 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h462016)
2'b0, 2'b01, 2'b10:
CASE_guard62016_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard62016_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 =
guard__h462016 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard62016_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or
guard__h462016)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
CASE_guard62016_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
(guard__h462016 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h462016 != 2'b01 && guard__h462016 != 2'b10 &&
guard__h462016 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8382 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8382 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8382 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8382 =
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
endcase
end
always@(guard__h491581 or
_theResult___fst_exp__h499542 or _theResult___exp__h500197)
begin
case (guard__h491581)
2'b0:
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q135 =
_theResult___fst_exp__h499542;
2'b01, 2'b10, 2'b11:
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q135 =
_theResult___exp__h500197;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h499542 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8996 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8994 or
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q135)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000 =
_theResult___fst_exp__h499542;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8996;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8994;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000 =
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q135;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9000 =
11'd0;
endcase
end
always@(guard__h491581 or
_theResult___fst_exp__h499542 or
out_exp__h500200 or _theResult___exp__h500197)
begin
case (guard__h491581)
2'b0, 2'b01:
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q136 =
_theResult___fst_exp__h499542;
2'b10:
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q136 =
out_exp__h500200;
2'b11:
CASE_guard91581_0b0_theResult___fst_exp99542_0_ETC__q136 =
_theResult___exp__h500197;
endcase
end
always@(guard__h491581 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h491581)
2'b0, 2'b01, 2'b10:
CASE_guard91581_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard91581_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 =
guard__h491581 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h491581)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
(guard__h491581 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h491581 == 2'b01 || guard__h491581 == 2'b10 ||
guard__h491581 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h500893 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h500893)
2'b0, 2'b01, 2'b10:
CASE_guard00893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard00893_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 =
guard__h500893 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500893)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
(guard__h500893 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h500893 == 2'b01 || guard__h500893 == 2'b10 ||
guard__h500893 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h509962 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h509962)
2'b0, 2'b01, 2'b10:
CASE_guard09962_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard09962_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 =
guard__h509962 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509962)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
(guard__h509962 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h509962 == 2'b01 || guard__h509962 == 2'b10 ||
guard__h509962 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h569583 or
_theResult___fst_exp__h577544 or _theResult___exp__h578199)
begin
case (guard__h569583)
2'b0:
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q152 =
_theResult___fst_exp__h577544;
2'b01, 2'b10, 2'b11:
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q152 =
_theResult___exp__h578199;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h577544 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9706 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9704 or
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q152)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710 =
_theResult___fst_exp__h577544;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9706;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9704;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710 =
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q152;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9710 =
11'd0;
endcase
end
always@(guard__h569583 or
_theResult___fst_exp__h577544 or
out_exp__h578202 or _theResult___exp__h578199)
begin
case (guard__h569583)
2'b0, 2'b01:
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q153 =
_theResult___fst_exp__h577544;
2'b10:
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q153 =
out_exp__h578202;
2'b11:
CASE_guard69583_0b0_theResult___fst_exp77544_0_ETC__q153 =
_theResult___exp__h578199;
endcase
end
always@(guard__h569583 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h569583)
2'b0, 2'b01, 2'b10:
CASE_guard69583_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard69583_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 =
guard__h569583 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569583)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
(guard__h569583 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h569583 == 2'b01 || guard__h569583 == 2'b10 ||
guard__h569583 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h578895 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h578895)
2'b0, 2'b01, 2'b10:
CASE_guard78895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard78895_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 =
guard__h578895 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578895)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
(guard__h578895 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h578895 == 2'b01 || guard__h578895 == 2'b10 ||
guard__h578895 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h587964 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h587964)
2'b0, 2'b01, 2'b10:
CASE_guard87964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard87964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 =
guard__h587964 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587964)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
(guard__h587964 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h587964 == 2'b01 || guard__h587964 == 2'b10 ||
guard__h587964 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h578895 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h578895)
2'b0, 2'b01, 2'b10:
CASE_guard78895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard78895_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 =
guard__h578895 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578895)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
(guard__h578895 == 2'b0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h578895 != 2'b01 && guard__h578895 != 2'b10 &&
guard__h578895 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h587964 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h587964)
2'b0, 2'b01, 2'b10:
CASE_guard87964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard87964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 =
guard__h587964 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587964)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
(guard__h587964 == 2'b0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h587964 != 2'b01 && guard__h587964 != 2'b10 &&
guard__h587964 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h569583 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h569583)
2'b0, 2'b01, 2'b10:
CASE_guard69583_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard69583_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 =
guard__h569583 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569583)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
(guard__h569583 == 2'b0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h569583 != 2'b01 && guard__h569583 != 2'b10 &&
guard__h569583 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h530382 or
_theResult___fst_exp__h538343 or _theResult___exp__h538998)
begin
case (guard__h530382)
2'b0:
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q175 =
_theResult___fst_exp__h538343;
2'b01, 2'b10, 2'b11:
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q175 =
_theResult___exp__h538998;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h538343 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10469 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467 or
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q175)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473 =
_theResult___fst_exp__h538343;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10469;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473 =
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q175;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10473 =
11'd0;
endcase
end
always@(guard__h530382 or
_theResult___fst_exp__h538343 or
out_exp__h539001 or _theResult___exp__h538998)
begin
case (guard__h530382)
2'b0, 2'b01:
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q176 =
_theResult___fst_exp__h538343;
2'b10:
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q176 =
out_exp__h539001;
2'b11:
CASE_guard30382_0b0_theResult___fst_exp38343_0_ETC__q176 =
_theResult___exp__h538998;
endcase
end
always@(guard__h539694 or
_theResult___fst_exp__h547920 or _theResult___exp__h548649)
begin
case (guard__h539694)
2'b0:
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q177 =
_theResult___fst_exp__h547920;
2'b01, 2'b10, 2'b11:
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q177 =
_theResult___exp__h548649;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h547920 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505 or
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q177)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511 =
_theResult___fst_exp__h547920;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10507;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10505;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511 =
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q177;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10511 =
11'd0;
endcase
end
always@(guard__h539694 or
_theResult___fst_exp__h547920 or
out_exp__h548652 or _theResult___exp__h548649)
begin
case (guard__h539694)
2'b0, 2'b01:
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q178 =
_theResult___fst_exp__h547920;
2'b10:
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q178 =
out_exp__h548652;
2'b11:
CASE_guard39694_0b0_theResult___fst_exp47920_0_ETC__q178 =
_theResult___exp__h548649;
endcase
end
always@(guard__h578895 or
_theResult___fst_exp__h587121 or _theResult___exp__h587850)
begin
case (guard__h578895)
2'b0:
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q179 =
_theResult___fst_exp__h587121;
2'b01, 2'b10, 2'b11:
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q179 =
_theResult___exp__h587850;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h587121 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9744 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9742 or
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q179)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748 =
_theResult___fst_exp__h587121;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9744;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9742;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748 =
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q179;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9748 =
11'd0;
endcase
end
always@(guard__h578895 or
_theResult___fst_exp__h587121 or
out_exp__h587853 or _theResult___exp__h587850)
begin
case (guard__h578895)
2'b0, 2'b01:
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q180 =
_theResult___fst_exp__h587121;
2'b10:
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q180 =
out_exp__h587853;
2'b11:
CASE_guard78895_0b0_theResult___fst_exp87121_0_ETC__q180 =
_theResult___exp__h587850;
endcase
end
always@(guard__h548763 or
_theResult___fst_exp__h556753 or _theResult___exp__h557433)
begin
case (guard__h548763)
2'b0:
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q181 =
_theResult___fst_exp__h556753;
2'b01, 2'b10, 2'b11:
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q181 =
_theResult___exp__h557433;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h556753 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10538 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10536 or
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q181)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542 =
_theResult___fst_exp__h556753;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10538;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10536;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542 =
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q181;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10542 =
11'd0;
endcase
end
always@(guard__h548763 or
_theResult___fst_exp__h556753 or
out_exp__h557436 or _theResult___exp__h557433)
begin
case (guard__h548763)
2'b0, 2'b01:
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q182 =
_theResult___fst_exp__h556753;
2'b10:
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q182 =
out_exp__h557436;
2'b11:
CASE_guard48763_0b0_theResult___fst_exp56753_0_ETC__q182 =
_theResult___exp__h557433;
endcase
end
always@(guard__h587964 or
_theResult___fst_exp__h595954 or _theResult___exp__h596634)
begin
case (guard__h587964)
2'b0:
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q183 =
_theResult___fst_exp__h595954;
2'b01, 2'b10, 2'b11:
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q183 =
_theResult___exp__h596634;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h595954 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9775 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9773 or
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q183)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779 =
_theResult___fst_exp__h595954;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9775;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9773;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779 =
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q183;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9779 =
11'd0;
endcase
end
always@(guard__h587964 or
_theResult___fst_exp__h595954 or
out_exp__h596637 or _theResult___exp__h596634)
begin
case (guard__h587964)
2'b0, 2'b01:
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q184 =
_theResult___fst_exp__h595954;
2'b10:
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q184 =
out_exp__h596637;
2'b11:
CASE_guard87964_0b0_theResult___fst_exp95954_0_ETC__q184 =
_theResult___exp__h596634;
endcase
end
always@(guard__h530382 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h530382)
2'b0, 2'b01, 2'b10:
CASE_guard30382_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard30382_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 =
guard__h530382 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530382)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
(guard__h530382 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h530382 == 2'b01 || guard__h530382 == 2'b10 ||
guard__h530382 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h539694 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h539694)
2'b0, 2'b01, 2'b10:
CASE_guard39694_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard39694_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 =
guard__h539694 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539694)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
(guard__h539694 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h539694 == 2'b01 || guard__h539694 == 2'b10 ||
guard__h539694 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h548763 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h548763)
2'b0, 2'b01, 2'b10:
CASE_guard48763_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard48763_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 =
guard__h548763 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548763)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
(guard__h548763 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h548763 == 2'b01 || guard__h548763 == 2'b10 ||
guard__h548763 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h539694 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h539694)
2'b0, 2'b01, 2'b10:
CASE_guard39694_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard39694_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 =
guard__h539694 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539694)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
(guard__h539694 == 2'b0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h539694 != 2'b01 && guard__h539694 != 2'b10 &&
guard__h539694 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h548763 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h548763)
2'b0, 2'b01, 2'b10:
CASE_guard48763_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard48763_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 =
guard__h548763 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548763)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
(guard__h548763 == 2'b0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h548763 != 2'b01 && guard__h548763 != 2'b10 &&
guard__h548763 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h530382 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h530382)
2'b0, 2'b01, 2'b10:
CASE_guard30382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard30382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 =
guard__h530382 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530382)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
(guard__h530382 == 2'b0) ?
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h530382 != 2'b01 && guard__h530382 != 2'b10 &&
guard__h530382 != 2'b11 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h530382 or
_theResult___snd__h538294 or _theResult___sfd__h538999)
begin
case (guard__h530382)
2'b0:
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q197 =
_theResult___snd__h538294[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q197 =
_theResult___sfd__h538999;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h538294 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10564 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10562 or
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q197)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568 =
_theResult___snd__h538294[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10564;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10562;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568 =
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q197;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10568 =
52'd0;
endcase
end
always@(guard__h530382 or
_theResult___snd__h538294 or
out_sfd__h539002 or _theResult___sfd__h538999)
begin
case (guard__h530382)
2'b0, 2'b01:
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q198 =
_theResult___snd__h538294[56:5];
2'b10:
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q198 =
out_sfd__h539002;
2'b11:
CASE_guard30382_0b0_theResult___snd38294_BITS__ETC__q198 =
_theResult___sfd__h538999;
endcase
end
always@(guard__h539694 or sfdin__h547914 or _theResult___sfd__h548650)
begin
case (guard__h539694)
2'b0:
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q199 =
sfdin__h547914[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q199 =
_theResult___sfd__h548650;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h547914 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10590 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10588 or
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q199)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594 =
sfdin__h547914[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10590;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10588;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594 =
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q199;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10594 =
52'd0;
endcase
end
always@(guard__h539694 or
sfdin__h547914 or out_sfd__h548653 or _theResult___sfd__h548650)
begin
case (guard__h539694)
2'b0, 2'b01:
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q200 =
sfdin__h547914[56:5];
2'b10:
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q200 =
out_sfd__h548653;
2'b11:
CASE_guard39694_0b0_sfdin47914_BITS_56_TO_5_0b_ETC__q200 =
_theResult___sfd__h548650;
endcase
end
always@(guard__h548763 or
_theResult___snd__h556699 or _theResult___sfd__h557434)
begin
case (guard__h548763)
2'b0:
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q201 =
_theResult___snd__h556699[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q201 =
_theResult___sfd__h557434;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h556699 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10609 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10607 or
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q201)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613 =
_theResult___snd__h556699[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10609;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10607;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613 =
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q201;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10613 =
52'd0;
endcase
end
always@(guard__h548763 or
_theResult___snd__h556699 or
out_sfd__h557437 or _theResult___sfd__h557434)
begin
case (guard__h548763)
2'b0, 2'b01:
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q202 =
_theResult___snd__h556699[56:5];
2'b10:
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q202 =
out_sfd__h557437;
2'b11:
CASE_guard48763_0b0_theResult___snd56699_BITS__ETC__q202 =
_theResult___sfd__h557434;
endcase
end
always@(guard__h500893 or
_theResult___fst_exp__h509119 or _theResult___exp__h509848)
begin
case (guard__h500893)
2'b0:
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q203 =
_theResult___fst_exp__h509119;
2'b01, 2'b10, 2'b11:
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q203 =
_theResult___exp__h509848;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h509119 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9039 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9037 or
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q203)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043 =
_theResult___fst_exp__h509119;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9039;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9037;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043 =
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q203;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9043 =
11'd0;
endcase
end
always@(guard__h500893 or
_theResult___fst_exp__h509119 or
out_exp__h509851 or _theResult___exp__h509848)
begin
case (guard__h500893)
2'b0, 2'b01:
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q204 =
_theResult___fst_exp__h509119;
2'b10:
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q204 =
out_exp__h509851;
2'b11:
CASE_guard00893_0b0_theResult___fst_exp09119_0_ETC__q204 =
_theResult___exp__h509848;
endcase
end
always@(guard__h509962 or
_theResult___fst_exp__h517952 or _theResult___exp__h518632)
begin
case (guard__h509962)
2'b0:
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q205 =
_theResult___fst_exp__h517952;
2'b01, 2'b10, 2'b11:
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q205 =
_theResult___exp__h518632;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h517952 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9070 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9068 or
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q205)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074 =
_theResult___fst_exp__h517952;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9070;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9068;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074 =
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q205;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9074 =
11'd0;
endcase
end
always@(guard__h509962 or
_theResult___fst_exp__h517952 or
out_exp__h518635 or _theResult___exp__h518632)
begin
case (guard__h509962)
2'b0, 2'b01:
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q206 =
_theResult___fst_exp__h517952;
2'b10:
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q206 =
out_exp__h518635;
2'b11:
CASE_guard09962_0b0_theResult___fst_exp17952_0_ETC__q206 =
_theResult___exp__h518632;
endcase
end
always@(guard__h491581 or
_theResult___snd__h499493 or _theResult___sfd__h500198)
begin
case (guard__h491581)
2'b0:
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q207 =
_theResult___snd__h499493[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q207 =
_theResult___sfd__h500198;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h499493 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9094 or
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q207)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100 =
_theResult___snd__h499493[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9094;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100 =
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q207;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9100 =
52'd0;
endcase
end
always@(guard__h491581 or
_theResult___snd__h499493 or
out_sfd__h500201 or _theResult___sfd__h500198)
begin
case (guard__h491581)
2'b0, 2'b01:
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q208 =
_theResult___snd__h499493[56:5];
2'b10:
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q208 =
out_sfd__h500201;
2'b11:
CASE_guard91581_0b0_theResult___snd99493_BITS__ETC__q208 =
_theResult___sfd__h500198;
endcase
end
always@(guard__h509962 or
_theResult___snd__h517898 or _theResult___sfd__h518633)
begin
case (guard__h509962)
2'b0:
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q209 =
_theResult___snd__h517898[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q209 =
_theResult___sfd__h518633;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h517898 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9142 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9140 or
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q209)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146 =
_theResult___snd__h517898[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9142;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9140;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146 =
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q209;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9146 =
52'd0;
endcase
end
always@(guard__h509962 or
_theResult___snd__h517898 or
out_sfd__h518636 or _theResult___sfd__h518633)
begin
case (guard__h509962)
2'b0, 2'b01:
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q210 =
_theResult___snd__h517898[56:5];
2'b10:
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q210 =
out_sfd__h518636;
2'b11:
CASE_guard09962_0b0_theResult___snd17898_BITS__ETC__q210 =
_theResult___sfd__h518633;
endcase
end
always@(guard__h500893 or sfdin__h509113 or _theResult___sfd__h509849)
begin
case (guard__h500893)
2'b0:
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q211 =
sfdin__h509113[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q211 =
_theResult___sfd__h509849;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h509113 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9123 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9121 or
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q211)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127 =
sfdin__h509113[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9123;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9121;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127 =
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q211;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9127 =
52'd0;
endcase
end
always@(guard__h500893 or
sfdin__h509113 or out_sfd__h509852 or _theResult___sfd__h509849)
begin
case (guard__h500893)
2'b0, 2'b01:
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q212 =
sfdin__h509113[56:5];
2'b10:
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q212 =
out_sfd__h509852;
2'b11:
CASE_guard00893_0b0_sfdin09113_BITS_56_TO_5_0b_ETC__q212 =
_theResult___sfd__h509849;
endcase
end
always@(guard__h569583 or
_theResult___snd__h577495 or _theResult___sfd__h578200)
begin
case (guard__h569583)
2'b0:
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q213 =
_theResult___snd__h577495[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q213 =
_theResult___sfd__h578200;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h577495 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9801 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9799 or
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q213)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805 =
_theResult___snd__h577495[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9801;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9799;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805 =
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q213;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9805 =
52'd0;
endcase
end
always@(guard__h569583 or
_theResult___snd__h577495 or
out_sfd__h578203 or _theResult___sfd__h578200)
begin
case (guard__h569583)
2'b0, 2'b01:
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q214 =
_theResult___snd__h577495[56:5];
2'b10:
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q214 =
out_sfd__h578203;
2'b11:
CASE_guard69583_0b0_theResult___snd77495_BITS__ETC__q214 =
_theResult___sfd__h578200;
endcase
end
always@(guard__h578895 or sfdin__h587115 or _theResult___sfd__h587851)
begin
case (guard__h578895)
2'b0:
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q215 =
sfdin__h587115[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q215 =
_theResult___sfd__h587851;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h587115 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9827 or
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9825 or
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q215)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831 =
sfdin__h587115[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9827;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831 =
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9825;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831 =
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q215;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9831 =
52'd0;
endcase
end
always@(guard__h578895 or
sfdin__h587115 or out_sfd__h587854 or _theResult___sfd__h587851)
begin
case (guard__h578895)
2'b0, 2'b01:
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q216 =
sfdin__h587115[56:5];
2'b10:
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q216 =
out_sfd__h587854;
2'b11:
CASE_guard78895_0b0_sfdin87115_BITS_56_TO_5_0b_ETC__q216 =
_theResult___sfd__h587851;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10855 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10843 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10832)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10857 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10843;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10857 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10832;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10857 =
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10855;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10819 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10774 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10732)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10821 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10774;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10821 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10732;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10821 =
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10819;
endcase
end
always@(guard__h587964 or
_theResult___snd__h595900 or _theResult___sfd__h596635)
begin
case (guard__h587964)
2'b0:
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q217 =
_theResult___snd__h595900[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q217 =
_theResult___sfd__h596635;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h595900 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9846 or
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9844 or
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q217)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850 =
_theResult___snd__h595900[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9846;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850 =
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9844;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850 =
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q217;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9850 =
52'd0;
endcase
end
always@(guard__h587964 or
_theResult___snd__h595900 or
out_sfd__h596638 or _theResult___sfd__h596635)
begin
case (guard__h587964)
2'b0, 2'b01:
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q218 =
_theResult___snd__h595900[56:5];
2'b10:
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q218 =
out_sfd__h596638;
2'b11:
CASE_guard87964_0b0_theResult___snd95900_BITS__ETC__q218 =
_theResult___sfd__h596635;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10903 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10887 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10872)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10905 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10887;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10905 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10872;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10905 =
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10903;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10945 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10931 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10918)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10947 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10931;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10947 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10918;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10947 =
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10945;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10987 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10973 or
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10960)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10989 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10973;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10989 =
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__35_ETC___d10960;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10989 =
coreFix_fpuMulDivExe_0_regToExeQ_first__357_BI_ETC___d10987;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 =
coreFix_aluExe_1_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first or
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219)
begin
case (coreFix_aluExe_1_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 =
coreFix_aluExe_1_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 =
{ coreFix_aluExe_1_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_1_regToExeQ$first[404:400],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219,
coreFix_aluExe_1_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[394:383])
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 =
coreFix_aluExe_1_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 =
coreFix_aluExe_0_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first or
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222)
begin
case (coreFix_aluExe_0_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 =
coreFix_aluExe_0_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 =
{ coreFix_aluExe_0_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_0_regToExeQ$first[404:400],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222,
coreFix_aluExe_0_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[394:383])
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 =
coreFix_aluExe_0_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852 =
fetchStage$pipelines_0_first[172:161];
default: IF_fetchStage_pipelines_0_first__2652_BITS_172_ETC___d12852 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[67:64])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 =
fetchStage$pipelines_0_first[67:64];
4'd11:
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 = 4'd10;
4'd12:
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 = 4'd11;
4'd13:
IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 = 4'd12;
default: IF_fetchStage_pipelines_0_first__2652_BIT_68_2_ETC___d12996 =
4'd13;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 =
fetchStage$pipelines_0_first[177:175];
default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = 3'd7;
endcase
end
always@(fetchStage$pipelines_0_first or
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778 =
fetchStage$pipelines_0_first[194:174];
3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778 =
{ fetchStage$pipelines_0_first[194:192],
9'h0AA,
fetchStage$pipelines_0_first[182:178],
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225,
fetchStage$pipelines_0_first[174] };
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d12778 =
21'd1485482;
endcase
end
always@(checkForException___d12886)
begin
case (checkForException___d12886[3:0])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226 =
checkForException___d12886[3:0];
4'd11: CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226 = 4'd10;
4'd12: CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226 = 4'd11;
4'd13: CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226 = 4'd12;
default: CASE_checkForException_2886_BITS_3_TO_0_0_chec_ETC__q226 =
4'd13;
endcase
end
always@(IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3__ETC___d13102)
begin
case (IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3__ETC___d13102)
4'd0, 4'd1:
CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 =
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3__ETC___d13102;
4'd2: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd3;
4'd3: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd4;
4'd4: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd5;
4'd5: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd7;
4'd6: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd8;
4'd7: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd9;
4'd8: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 = 4'd11;
default: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2680__ETC__q227 =
4'd14;
endcase
end
always@(k__h663183 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h663183)
1'd0:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 =
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 =
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 =
coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13291 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287;
endcase
end
always@(k__h663183 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h663183)
1'd0:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 =
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 =
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
regRenamingTable$rename_0_canRename or
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254 or
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13310 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 =
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13310;
3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 =
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13315 =
regRenamingTable$rename_0_canRename &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13254;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 =
!coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13348 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13348 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13348 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343);
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 =
fetchStage$pipelines_1_first[177:175];
default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = 3'd7;
endcase
end
always@(fetchStage$pipelines_1_first or
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408 =
fetchStage$pipelines_1_first[194:174];
3'd4:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408 =
{ fetchStage$pipelines_1_first[194:192],
9'h0AA,
fetchStage$pipelines_1_first[182:178],
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228,
fetchStage$pipelines_1_first[174] };
default: IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13408 =
21'd1485482;
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 =
fetchStage$pipelines_1_first[172:161];
default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 =
12'd2303;
endcase
end
always@(idx__h677617 or
fetchStage$pipelines_0_canDeq or
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13550 or
coreFix_aluExe_0_rsAlu$canEnq or
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13556 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h677617)
1'd0:
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13550 ||
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2652_BITS_19_ETC___d13556 ||
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 =
!coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 or
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13642 or
NOT_coreFix_memExe_rsMem_canEnq__3278_3340_OR__ETC___d13645 or
NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13644)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13648 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 ||
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13642;
3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13648 =
NOT_coreFix_memExe_rsMem_canEnq__3278_3340_OR__ETC___d13645;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13648 =
NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13644;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13648 =
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[0] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[1] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[2] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[3] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[4] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[5] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[6] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[7] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[8] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[9] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[10] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[11] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[12] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[13] ||
IF_IF_NOT_csrf_prv_reg_read__2680_EQ_3_2681_26_ETC___d12721[14];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13669 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13669 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287;
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13686 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13686 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13686 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 =
coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_1_first or
regRenamingTable$rename_1_canRename or
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13541 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575 or
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13654 or
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13683 or
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13692 or
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13666 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13675)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 =
!SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575 &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13654;
3'd2:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 =
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13683 &&
regRenamingTable$rename_1_canRename &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13692;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 =
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13666 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable$rename_1_canRename &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13675;
default: IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13697 =
regRenamingTable$rename_1_canRename &&
NOT_fetchStage_pipelines_1_first__2661_BITS_19_ETC___d13541;
endcase
end
always@(k__h663183 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (k__h663183)
1'd0:
CASE_k63183_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_k63183_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13741 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 or
regRenamingTable_RDY_rename_0_getRename__3134__ETC___d13735 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 or
regRenamingTable$RDY_rename_0_getRename or
_0_OR_NOT_fetchStage_pipelines_0_first__2652_BI_ETC___d13722 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13739 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 ||
regRenamingTable$RDY_rename_0_getRename &&
_0_OR_NOT_fetchStage_pipelines_0_first__2652_BI_ETC___d13722;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13739 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_0_getRename;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13739 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 ||
regRenamingTable_RDY_rename_0_getRename__3134__ETC___d13735;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13755 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13755 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13755 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13762 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__326_ETC___d13308 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim);
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13762 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13762 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13287;
endcase
end
always@(idx__h677617 or
fetchStage$pipelines_0_canDeq or
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13778 or
coreFix_aluExe_0_rsAlu$canEnq or
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13785 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h677617)
1'd0:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__265_ETC___d13789 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13778) &&
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__265_ETC___d13789 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2652_BITS_194_TO_ETC___d13785) &&
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13805 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (fetchStage_pipelines_0_canDeq__2650_AND_NOT_fe_ETC___d13805)
1'd0:
CASE_fetchStage_pipelines_0_canDeq__2650_AND_N_ETC__q234 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_fetchStage_pipelines_0_canDeq__2650_AND_N_ETC__q234 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13831 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13831 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343);
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13842 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3264_co_ETC___d13274;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13842 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2652_BITS_194_ETC___d13842 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13343;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13850 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575 or
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13839)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13853 =
SEL_ARR_fetchStage_pipelines_0_canDeq__2650_AN_ETC___d13575;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13853 =
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13839;
default: IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13853 =
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13850;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13818 or
regRenamingTable$RDY_rename_1_getRename or
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13823 or
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__265_ETC___d13789 or
regRenamingTable_RDY_rename_1_getRename__3791__ETC___d13809 or
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13811 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__37_ETC___d13814)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13828 =
!SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__265_ETC___d13789 ||
regRenamingTable_RDY_rename_1_getRename__3791__ETC___d13809;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13828 =
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13811 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__37_ETC___d13814;
default: IF_fetchStage_pipelines_1_first__2661_BITS_194_ETC___d13828 =
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2650_AND_regRen_ETC___d13818 ||
regRenamingTable$RDY_rename_1_getRename &&
NOT_fetchStage_pipelines_0_canDeq__2650_2651_O_ETC___d13823;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13909 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13909 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13906 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13906 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13915 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13915 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13912 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_0_first__2652_BITS_191_ETC___d13912 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14042 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14042 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14040 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14040 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14039 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14039 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14041 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_1_first__2661_BITS_191_ETC___d14041 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd0;
12'd2:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd1;
12'd3:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd2;
12'd256:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd8;
12'd260:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd9;
12'd261:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd10;
12'd262:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd11;
12'd320:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd12;
12'd321:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd13;
12'd322:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd14;
12'd323:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd15;
12'd324:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd16;
12'd384:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd17;
12'd768:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd18;
12'd769:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd19;
12'd770:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd20;
12'd771:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd21;
12'd772:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd22;
12'd773:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd23;
12'd774:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd24;
12'd832:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd25;
12'd833:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd26;
12'd834:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd27;
12'd835:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd28;
12'd836:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd29;
12'd2048:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd6;
12'd2049:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd7;
12'd2816:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd30;
12'd2818:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd31;
12'd3072:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd3;
12'd3073:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd4;
12'd3074:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd5;
12'd3857:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd32;
12'd3858:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd33;
12'd3859:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd34;
12'd3860:
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 = 6'd35;
default: IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 =
6'd36;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd0:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 = 3'd4;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 = 3'd3;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 = 3'd2;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 = 3'd1;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10684 =
3'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
coreFix_memExe_stb$deq or
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 or
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
3'd0, 3'd2, 3'd4:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
3'd1:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
{ coreFix_memExe_stb$deq[575] ?
coreFix_memExe_stb$deq[511:504] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
coreFix_memExe_stb$deq[574] ?
coreFix_memExe_stb$deq[503:496] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
coreFix_memExe_stb$deq[573] ?
coreFix_memExe_stb$deq[495:488] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
coreFix_memExe_stb$deq[572] ?
coreFix_memExe_stb$deq[487:480] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
coreFix_memExe_stb$deq[571] ?
coreFix_memExe_stb$deq[479:472] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
coreFix_memExe_stb$deq[570] ?
coreFix_memExe_stb$deq[471:464] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
coreFix_memExe_stb$deq[569] ?
coreFix_memExe_stb$deq[463:456] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
coreFix_memExe_stb$deq[568] ?
coreFix_memExe_stb$deq[455:448] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
coreFix_memExe_stb$deq[567] ?
coreFix_memExe_stb$deq[447:440] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
coreFix_memExe_stb$deq[566] ?
coreFix_memExe_stb$deq[439:432] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
coreFix_memExe_stb$deq[565] ?
coreFix_memExe_stb$deq[431:424] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
coreFix_memExe_stb$deq[564] ?
coreFix_memExe_stb$deq[423:416] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
coreFix_memExe_stb$deq[563] ?
coreFix_memExe_stb$deq[415:408] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
coreFix_memExe_stb$deq[562] ?
coreFix_memExe_stb$deq[407:400] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
coreFix_memExe_stb$deq[561] ?
coreFix_memExe_stb$deq[399:392] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
coreFix_memExe_stb$deq[560] ?
coreFix_memExe_stb$deq[391:384] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
coreFix_memExe_stb$deq[559] ?
coreFix_memExe_stb$deq[383:376] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
coreFix_memExe_stb$deq[558] ?
coreFix_memExe_stb$deq[375:368] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
coreFix_memExe_stb$deq[557] ?
coreFix_memExe_stb$deq[367:360] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
coreFix_memExe_stb$deq[556] ?
coreFix_memExe_stb$deq[359:352] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
coreFix_memExe_stb$deq[555] ?
coreFix_memExe_stb$deq[351:344] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
coreFix_memExe_stb$deq[554] ?
coreFix_memExe_stb$deq[343:336] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
coreFix_memExe_stb$deq[553] ?
coreFix_memExe_stb$deq[335:328] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
coreFix_memExe_stb$deq[552] ?
coreFix_memExe_stb$deq[327:320] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
coreFix_memExe_stb$deq[551] ?
coreFix_memExe_stb$deq[319:312] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
coreFix_memExe_stb$deq[550] ?
coreFix_memExe_stb$deq[311:304] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
coreFix_memExe_stb$deq[549] ?
coreFix_memExe_stb$deq[303:296] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
coreFix_memExe_stb$deq[548] ?
coreFix_memExe_stb$deq[295:288] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
coreFix_memExe_stb$deq[547] ?
coreFix_memExe_stb$deq[287:280] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
coreFix_memExe_stb$deq[546] ?
coreFix_memExe_stb$deq[279:272] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
coreFix_memExe_stb$deq[545] ?
coreFix_memExe_stb$deq[271:264] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
coreFix_memExe_stb$deq[544] ?
coreFix_memExe_stb$deq[263:256] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
coreFix_memExe_stb$deq[543] ?
coreFix_memExe_stb$deq[255:248] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
coreFix_memExe_stb$deq[542] ?
coreFix_memExe_stb$deq[247:240] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
coreFix_memExe_stb$deq[541] ?
coreFix_memExe_stb$deq[239:232] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
coreFix_memExe_stb$deq[540] ?
coreFix_memExe_stb$deq[231:224] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
coreFix_memExe_stb$deq[539] ?
coreFix_memExe_stb$deq[223:216] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
coreFix_memExe_stb$deq[538] ?
coreFix_memExe_stb$deq[215:208] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
coreFix_memExe_stb$deq[537] ?
coreFix_memExe_stb$deq[207:200] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
coreFix_memExe_stb$deq[536] ?
coreFix_memExe_stb$deq[199:192] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
coreFix_memExe_stb$deq[535] ?
coreFix_memExe_stb$deq[191:184] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
coreFix_memExe_stb$deq[534] ?
coreFix_memExe_stb$deq[183:176] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
coreFix_memExe_stb$deq[533] ?
coreFix_memExe_stb$deq[175:168] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
coreFix_memExe_stb$deq[532] ?
coreFix_memExe_stb$deq[167:160] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
coreFix_memExe_stb$deq[531] ?
coreFix_memExe_stb$deq[159:152] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
coreFix_memExe_stb$deq[530] ?
coreFix_memExe_stb$deq[151:144] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
coreFix_memExe_stb$deq[529] ?
coreFix_memExe_stb$deq[143:136] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
coreFix_memExe_stb$deq[528] ?
coreFix_memExe_stb$deq[135:128] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
coreFix_memExe_stb$deq[527] ?
coreFix_memExe_stb$deq[127:120] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
coreFix_memExe_stb$deq[526] ?
coreFix_memExe_stb$deq[119:112] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
coreFix_memExe_stb$deq[525] ?
coreFix_memExe_stb$deq[111:104] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
coreFix_memExe_stb$deq[524] ?
coreFix_memExe_stb$deq[103:96] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
coreFix_memExe_stb$deq[523] ?
coreFix_memExe_stb$deq[95:88] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
coreFix_memExe_stb$deq[522] ?
coreFix_memExe_stb$deq[87:80] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
coreFix_memExe_stb$deq[521] ?
coreFix_memExe_stb$deq[79:72] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
coreFix_memExe_stb$deq[520] ?
coreFix_memExe_stb$deq[71:64] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
coreFix_memExe_stb$deq[519] ?
coreFix_memExe_stb$deq[63:56] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
coreFix_memExe_stb$deq[518] ?
coreFix_memExe_stb$deq[55:48] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
coreFix_memExe_stb$deq[517] ?
coreFix_memExe_stb$deq[47:40] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
coreFix_memExe_stb$deq[516] ?
coreFix_memExe_stb$deq[39:32] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
coreFix_memExe_stb$deq[515] ?
coreFix_memExe_stb$deq[31:24] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
coreFix_memExe_stb$deq[514] ?
coreFix_memExe_stb$deq[23:16] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
coreFix_memExe_stb$deq[513] ?
coreFix_memExe_stb$deq[15:8] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
coreFix_memExe_stb$deq[512] ?
coreFix_memExe_stb$deq[7:0] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
3'd3:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ?
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9860 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9914)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9918 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155;
5'd25:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9918 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9860;
5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9918 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9914;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9918 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9860;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8395 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8395 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8395 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d8395 =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8413 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
2'd0, 2'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8413;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 =
4'd14;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 =
4'd15;
endcase
end
always@(mmio_dataReqQ_data_0)
begin
case (mmio_dataReqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263 =
mmio_dataReqQ_data_0[77:72];
2'd3:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263 =
{ 2'd3, mmio_dataReqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_lsq$firstSt)
begin
case (coreFix_memExe_lsq$firstSt[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 =
coreFix_memExe_lsq$firstSt[3:0];
default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 =
4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstLd)
begin
case (coreFix_memExe_lsq$firstLd[6:3])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 =
coreFix_memExe_lsq$firstLd[6:3];
default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 =
4'd15;
endcase
end
always@(mmioToPlatform_pRq_enq_x)
begin
case (mmioToPlatform_pRq_enq_x[37:36])
2'd0, 2'd1, 2'd2:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266 =
mmioToPlatform_pRq_enq_x[37:32];
2'd3:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266 =
{ 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 =
coreFix_aluExe_0_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData or
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
coreFix_aluExe_0_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
{ coreFix_aluExe_0_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_0_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267,
coreFix_aluExe_0_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 =
coreFix_aluExe_0_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270 =
coreFix_aluExe_0_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270)
begin
case (coreFix_aluExe_0_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271 =
coreFix_aluExe_0_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271 =
{ coreFix_aluExe_0_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_0_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270,
coreFix_aluExe_0_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272 =
coreFix_aluExe_0_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 =
coreFix_aluExe_1_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData or
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
coreFix_aluExe_1_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
{ coreFix_aluExe_1_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_1_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273,
coreFix_aluExe_1_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 =
coreFix_aluExe_1_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276 =
coreFix_aluExe_1_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276)
begin
case (coreFix_aluExe_1_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277 =
coreFix_aluExe_1_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277 =
{ coreFix_aluExe_1_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_1_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276,
coreFix_aluExe_1_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278 =
coreFix_aluExe_1_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278 =
12'd2303;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 =
{ coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
9'h0AA,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 =
21'd1485482;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10674 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10621)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623;
5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10674,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10621 };
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d9155;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 =
64'h3FF0000000000000;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__357_ETC___d10623;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 =
{ coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
9'h0AA,
coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283,
coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 =
21'd1485482;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_instret <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
4'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
2'd3;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
4'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
66'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
started <= `BSV_ASSIGNMENT_DELAY 1'd0;
update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (commitStage_commitTrap$EN)
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
commitStage_commitTrap$D_IN;
if (commitStage_rg_instret$EN)
commitStage_rg_instret <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_instret$D_IN;
if (coreFix_doStatsReg$EN)
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_empty$EN)
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_empty$D_IN;
if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_full$EN)
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_full$D_IN;
if (coreFix_memExe_forwardQ_clearReq_rl$EN)
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_clearReq_rl$D_IN;
if (coreFix_memExe_forwardQ_data_0$EN)
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_0$D_IN;
if (coreFix_memExe_forwardQ_data_1$EN)
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_1$D_IN;
if (coreFix_memExe_forwardQ_deqP$EN)
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqP$D_IN;
if (coreFix_memExe_forwardQ_deqReq_rl$EN)
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_empty$EN)
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_empty$D_IN;
if (coreFix_memExe_forwardQ_enqP$EN)
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqP$D_IN;
if (coreFix_memExe_forwardQ_enqReq_rl$EN)
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_full$EN)
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_full$D_IN;
if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_data_0$EN)
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_0$D_IN;
if (coreFix_memExe_memRespLdQ_data_1$EN)
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_1$D_IN;
if (coreFix_memExe_memRespLdQ_deqP$EN)
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqP$D_IN;
if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_empty$EN)
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_empty$D_IN;
if (coreFix_memExe_memRespLdQ_enqP$EN)
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqP$D_IN;
if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_full$EN)
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_full$D_IN;
if (coreFix_memExe_reqLdQ_data_0_rl$EN)
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLdQ_empty_rl$EN)
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_empty_rl$D_IN;
if (coreFix_memExe_reqLdQ_full_rl$EN)
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_full_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
if (coreFix_memExe_reqStQ_data_0_rl$EN)
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_data_0_rl$D_IN;
if (coreFix_memExe_reqStQ_empty_rl$EN)
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_empty_rl$D_IN;
if (coreFix_memExe_reqStQ_full_rl$EN)
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_full_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_data_0$EN)
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_data_0$D_IN;
if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_empty$EN)
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_empty$D_IN;
if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_full$EN)
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_full$D_IN;
if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
if (csrInstOrInterruptInflight_rl$EN)
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
csrInstOrInterruptInflight_rl$D_IN;
if (csrf_debug_int_pend$EN)
csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY
csrf_debug_int_pend$D_IN;
if (csrf_external_int_en_vec_0$EN)
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_0$D_IN;
if (csrf_external_int_en_vec_1$EN)
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_1$D_IN;
if (csrf_external_int_en_vec_3$EN)
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_3$D_IN;
if (csrf_external_int_pend_vec_0$EN)
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_0$D_IN;
if (csrf_external_int_pend_vec_1$EN)
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_1$D_IN;
if (csrf_external_int_pend_vec_3$EN)
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_3$D_IN;
if (csrf_fflags_reg$EN)
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
if (csrf_frm_reg$EN)
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
if (csrf_fs_reg$EN)
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
if (csrf_ie_vec_0$EN)
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
if (csrf_ie_vec_1$EN)
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
if (csrf_ie_vec_3$EN)
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
if (csrf_mcause_code_reg$EN)
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_code_reg$D_IN;
if (csrf_mcause_interrupt_reg$EN)
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_interrupt_reg$D_IN;
if (csrf_mcounteren_cy_reg$EN)
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_cy_reg$D_IN;
if (csrf_mcounteren_ir_reg$EN)
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_ir_reg$D_IN;
if (csrf_mcounteren_tm_reg$EN)
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_tm_reg$D_IN;
if (csrf_mcycle_ehr_data_rl$EN)
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_mcycle_ehr_data_rl$D_IN;
if (csrf_medeleg_13_11_reg$EN)
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_13_11_reg$D_IN;
if (csrf_medeleg_15_reg$EN)
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_15_reg$D_IN;
if (csrf_medeleg_9_0_reg$EN)
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_9_0_reg$D_IN;
if (csrf_mepc_csr$EN)
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
if (csrf_mideleg_11_reg$EN)
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_11_reg$D_IN;
if (csrf_mideleg_1_0_reg$EN)
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_1_0_reg$D_IN;
if (csrf_mideleg_5_3_reg$EN)
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_5_3_reg$D_IN;
if (csrf_mideleg_9_7_reg$EN)
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_9_7_reg$D_IN;
if (csrf_minstret_ehr_data_rl$EN)
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_minstret_ehr_data_rl$D_IN;
if (csrf_mpp_reg$EN)
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
if (csrf_mprv_reg$EN)
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
if (csrf_mscratch_csr$EN)
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
if (csrf_mtval_csr$EN)
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
if (csrf_mtvec_base_hi_reg$EN)
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_base_hi_reg$D_IN;
if (csrf_mtvec_mode_low_reg$EN)
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_mode_low_reg$D_IN;
if (csrf_mxr_reg$EN)
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
if (csrf_ppn_reg$EN)
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
if (csrf_prev_ie_vec_0$EN)
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
if (csrf_prev_ie_vec_1$EN)
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
if (csrf_prev_ie_vec_3$EN)
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
if (csrf_prv_reg$EN)
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
if (csrf_scause_code_reg$EN)
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_code_reg$D_IN;
if (csrf_scause_interrupt_reg$EN)
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_interrupt_reg$D_IN;
if (csrf_scounteren_cy_reg$EN)
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_cy_reg$D_IN;
if (csrf_scounteren_ir_reg$EN)
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_ir_reg$D_IN;
if (csrf_scounteren_tm_reg$EN)
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_tm_reg$D_IN;
if (csrf_sepc_csr$EN)
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
if (csrf_software_int_en_vec_0$EN)
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_0$D_IN;
if (csrf_software_int_en_vec_1$EN)
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_1$D_IN;
if (csrf_software_int_en_vec_3$EN)
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_3$D_IN;
if (csrf_software_int_pend_vec_0$EN)
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_0$D_IN;
if (csrf_software_int_pend_vec_1$EN)
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_1$D_IN;
if (csrf_software_int_pend_vec_3$EN)
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_3$D_IN;
if (csrf_spp_reg$EN)
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
if (csrf_sscratch_csr$EN)
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
if (csrf_stats_module_doStats$EN)
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
csrf_stats_module_doStats$D_IN;
if (csrf_stval_csr$EN)
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
if (csrf_stvec_base_hi_reg$EN)
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_base_hi_reg$D_IN;
if (csrf_stvec_mode_low_reg$EN)
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_mode_low_reg$D_IN;
if (csrf_sum_reg$EN)
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
if (csrf_time_reg$EN)
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
if (csrf_timer_int_en_vec_0$EN)
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_0$D_IN;
if (csrf_timer_int_en_vec_1$EN)
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_1$D_IN;
if (csrf_timer_int_en_vec_3$EN)
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_3$D_IN;
if (csrf_timer_int_pend_vec_0$EN)
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_0$D_IN;
if (csrf_timer_int_pend_vec_1$EN)
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_1$D_IN;
if (csrf_timer_int_pend_vec_3$EN)
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_3$D_IN;
if (csrf_tsr_reg$EN)
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
if (csrf_tvm_reg$EN)
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
if (csrf_tw_reg$EN)
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
if (csrf_vm_mode_sv39_reg$EN)
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
csrf_vm_mode_sv39_reg$D_IN;
if (flush_reservation$EN)
flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
if (flush_tlbs$EN)
flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
if (mmio_cRqQ_clearReq_rl$EN)
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_clearReq_rl$D_IN;
if (mmio_cRqQ_data_0$EN)
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
if (mmio_cRqQ_deqReq_rl$EN)
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_deqReq_rl$D_IN;
if (mmio_cRqQ_empty$EN)
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
if (mmio_cRqQ_enqReq_rl$EN)
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_enqReq_rl$D_IN;
if (mmio_cRqQ_full$EN)
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
if (mmio_cRsQ_clearReq_rl$EN)
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_clearReq_rl$D_IN;
if (mmio_cRsQ_data_0$EN)
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
if (mmio_cRsQ_deqReq_rl$EN)
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_deqReq_rl$D_IN;
if (mmio_cRsQ_empty$EN)
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
if (mmio_cRsQ_enqReq_rl$EN)
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_enqReq_rl$D_IN;
if (mmio_cRsQ_full$EN)
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
if (mmio_dataPendQ_clearReq_rl$EN)
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_clearReq_rl$D_IN;
if (mmio_dataPendQ_deqReq_rl$EN)
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_deqReq_rl$D_IN;
if (mmio_dataPendQ_empty$EN)
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_empty$D_IN;
if (mmio_dataPendQ_enqReq_rl$EN)
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_enqReq_rl$D_IN;
if (mmio_dataPendQ_full$EN)
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_full$D_IN;
if (mmio_dataReqQ_clearReq_rl$EN)
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_clearReq_rl$D_IN;
if (mmio_dataReqQ_data_0$EN)
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_data_0$D_IN;
if (mmio_dataReqQ_deqReq_rl$EN)
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_deqReq_rl$D_IN;
if (mmio_dataReqQ_empty$EN)
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_empty$D_IN;
if (mmio_dataReqQ_enqReq_rl$EN)
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_enqReq_rl$D_IN;
if (mmio_dataReqQ_full$EN)
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
if (mmio_dataRespQ_clearReq_rl$EN)
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_clearReq_rl$D_IN;
if (mmio_dataRespQ_data_0$EN)
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_data_0$D_IN;
if (mmio_dataRespQ_deqReq_rl$EN)
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_deqReq_rl$D_IN;
if (mmio_dataRespQ_empty$EN)
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_empty$D_IN;
if (mmio_dataRespQ_enqReq_rl$EN)
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_enqReq_rl$D_IN;
if (mmio_dataRespQ_full$EN)
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_full$D_IN;
if (mmio_fromHostAddr$EN)
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
if (mmio_pRqQ_clearReq_rl$EN)
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_clearReq_rl$D_IN;
if (mmio_pRqQ_data_0$EN)
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
if (mmio_pRqQ_deqReq_rl$EN)
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_deqReq_rl$D_IN;
if (mmio_pRqQ_empty$EN)
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
if (mmio_pRqQ_enqReq_rl$EN)
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_enqReq_rl$D_IN;
if (mmio_pRqQ_full$EN)
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
if (mmio_pRsQ_clearReq_rl$EN)
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_clearReq_rl$D_IN;
if (mmio_pRsQ_data_0$EN)
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
if (mmio_pRsQ_deqReq_rl$EN)
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_deqReq_rl$D_IN;
if (mmio_pRsQ_empty$EN)
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
if (mmio_pRsQ_enqReq_rl$EN)
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_enqReq_rl$D_IN;
if (mmio_pRsQ_full$EN)
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
if (mmio_toHostAddr$EN)
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
if (outOfReset$EN)
outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
if (update_vm_info$EN)
update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
commitStage_commitTrap = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_instret = 64'hAAAAAAAAAAAAAAAA;
coreFix_doStatsReg = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
coreFix_memExe_dMem_perfReqQ_full = 1'h0;
coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_deqP = 1'h0;
coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
coreFix_memExe_forwardQ_empty = 1'h0;
coreFix_memExe_forwardQ_enqP = 1'h0;
coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full = 1'h0;
coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_deqP = 1'h0;
coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_empty = 1'h0;
coreFix_memExe_memRespLdQ_enqP = 1'h0;
coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full = 1'h0;
coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl = 1'h0;
coreFix_memExe_reqLdQ_full_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl = 1'h0;
coreFix_memExe_reqStQ_full_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_empty = 1'h0;
coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full = 1'h0;
coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
csrInstOrInterruptInflight_rl = 1'h0;
csrf_debug_int_pend = 1'h0;
csrf_external_int_en_vec_0 = 1'h0;
csrf_external_int_en_vec_1 = 1'h0;
csrf_external_int_en_vec_3 = 1'h0;
csrf_external_int_pend_vec_0 = 1'h0;
csrf_external_int_pend_vec_1 = 1'h0;
csrf_external_int_pend_vec_3 = 1'h0;
csrf_fflags_reg = 5'h0A;
csrf_frm_reg = 3'h2;
csrf_fs_reg = 2'h2;
csrf_ie_vec_0 = 1'h0;
csrf_ie_vec_1 = 1'h0;
csrf_ie_vec_3 = 1'h0;
csrf_mcause_code_reg = 4'hA;
csrf_mcause_interrupt_reg = 1'h0;
csrf_mcounteren_cy_reg = 1'h0;
csrf_mcounteren_ir_reg = 1'h0;
csrf_mcounteren_tm_reg = 1'h0;
csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_medeleg_13_11_reg = 3'h2;
csrf_medeleg_15_reg = 1'h0;
csrf_medeleg_9_0_reg = 10'h2AA;
csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mideleg_11_reg = 1'h0;
csrf_mideleg_1_0_reg = 2'h2;
csrf_mideleg_5_3_reg = 3'h2;
csrf_mideleg_9_7_reg = 3'h2;
csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_mpp_reg = 2'h2;
csrf_mprv_reg = 1'h0;
csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_mtvec_mode_low_reg = 1'h0;
csrf_mxr_reg = 1'h0;
csrf_ppn_reg = 44'hAAAAAAAAAAA;
csrf_prev_ie_vec_0 = 1'h0;
csrf_prev_ie_vec_1 = 1'h0;
csrf_prev_ie_vec_3 = 1'h0;
csrf_prv_reg = 2'h2;
csrf_scause_code_reg = 4'hA;
csrf_scause_interrupt_reg = 1'h0;
csrf_scounteren_cy_reg = 1'h0;
csrf_scounteren_ir_reg = 1'h0;
csrf_scounteren_tm_reg = 1'h0;
csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_software_int_en_vec_0 = 1'h0;
csrf_software_int_en_vec_1 = 1'h0;
csrf_software_int_en_vec_3 = 1'h0;
csrf_software_int_pend_vec_0 = 1'h0;
csrf_software_int_pend_vec_1 = 1'h0;
csrf_software_int_pend_vec_3 = 1'h0;
csrf_spp_reg = 1'h0;
csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stats_module_doStats = 1'h0;
csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_stvec_mode_low_reg = 1'h0;
csrf_sum_reg = 1'h0;
csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
csrf_timer_int_en_vec_0 = 1'h0;
csrf_timer_int_en_vec_1 = 1'h0;
csrf_timer_int_en_vec_3 = 1'h0;
csrf_timer_int_pend_vec_0 = 1'h0;
csrf_timer_int_pend_vec_1 = 1'h0;
csrf_timer_int_pend_vec_3 = 1'h0;
csrf_tsr_reg = 1'h0;
csrf_tvm_reg = 1'h0;
csrf_tw_reg = 1'h0;
csrf_vm_mode_sv39_reg = 1'h0;
flush_reservation = 1'h0;
flush_tlbs = 1'h0;
mmio_cRqQ_clearReq_rl = 1'h0;
mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_deqReq_rl = 1'h0;
mmio_cRqQ_empty = 1'h0;
mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full = 1'h0;
mmio_cRsQ_clearReq_rl = 1'h0;
mmio_cRsQ_data_0 = 1'h0;
mmio_cRsQ_deqReq_rl = 1'h0;
mmio_cRsQ_empty = 1'h0;
mmio_cRsQ_enqReq_rl = 2'h2;
mmio_cRsQ_full = 1'h0;
mmio_dataPendQ_clearReq_rl = 1'h0;
mmio_dataPendQ_deqReq_rl = 1'h0;
mmio_dataPendQ_empty = 1'h0;
mmio_dataPendQ_enqReq_rl = 1'h0;
mmio_dataPendQ_full = 1'h0;
mmio_dataReqQ_clearReq_rl = 1'h0;
mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_deqReq_rl = 1'h0;
mmio_dataReqQ_empty = 1'h0;
mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full = 1'h0;
mmio_dataRespQ_clearReq_rl = 1'h0;
mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_deqReq_rl = 1'h0;
mmio_dataRespQ_empty = 1'h0;
mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full = 1'h0;
mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmio_pRqQ_clearReq_rl = 1'h0;
mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
mmio_pRqQ_deqReq_rl = 1'h0;
mmio_pRqQ_empty = 1'h0;
mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
mmio_pRqQ_full = 1'h0;
mmio_pRsQ_clearReq_rl = 1'h0;
mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_deqReq_rl = 1'h0;
mmio_pRsQ_empty = 1'h0;
mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
mmio_pRsQ_full = 1'h0;
mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
outOfReset = 1'h0;
started = 1'h0;
update_vm_info = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_outOfReset)
$fwrite(32'h80000002, "mkProc came out of reset\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_instret,
rob$deqPort_0_deq_data[282:219],
rob$deqPort_0_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd1 &&
rob$deqPort_0_deq_data[186:182] != 5'd2 &&
rob$deqPort_0_deq_data[186:182] != 5'd3 &&
rob$deqPort_0_deq_data[186:182] != 5'd4 &&
rob$deqPort_0_deq_data[186:182] != 5'd5 &&
rob$deqPort_0_deq_data[186:182] != 5'd6 &&
rob$deqPort_0_deq_data[186:182] != 5'd7 &&
rob$deqPort_0_deq_data[186:182] != 5'd8 &&
rob$deqPort_0_deq_data[186:182] != 5'd9 &&
rob$deqPort_0_deq_data[186:182] != 5'd10 &&
rob$deqPort_0_deq_data[186:182] != 5'd11 &&
rob$deqPort_0_deq_data[186:182] != 5'd12 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd14 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write(" [doCommitTrap]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_instret,
rob$deqPort_0_deq_data[282:219],
rob$deqPort_0_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd1 &&
rob$deqPort_0_deq_data[186:182] != 5'd2 &&
rob$deqPort_0_deq_data[186:182] != 5'd3 &&
rob$deqPort_0_deq_data[186:182] != 5'd4 &&
rob$deqPort_0_deq_data[186:182] != 5'd5 &&
rob$deqPort_0_deq_data[186:182] != 5'd6 &&
rob$deqPort_0_deq_data[186:182] != 5'd7 &&
rob$deqPort_0_deq_data[186:182] != 5'd8 &&
rob$deqPort_0_deq_data[186:182] != 5'd9 &&
rob$deqPort_0_deq_data[186:182] != 5'd10 &&
rob$deqPort_0_deq_data[186:182] != 5'd11 &&
rob$deqPort_0_deq_data[186:182] != 5'd12 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd14 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write(" [doCommitSystemInst]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4100_BIT_181_4324_T_ETC___d14398 == 6'd6)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
rob$deqPort_0_deq_data[95:32]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_instret,
rob$deqPort_0_deq_data[282:219],
rob$deqPort_0_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] != 5'd1 &&
rob$deqPort_0_deq_data[186:182] != 5'd2 &&
rob$deqPort_0_deq_data[186:182] != 5'd3 &&
rob$deqPort_0_deq_data[186:182] != 5'd4 &&
rob$deqPort_0_deq_data[186:182] != 5'd5 &&
rob$deqPort_0_deq_data[186:182] != 5'd6 &&
rob$deqPort_0_deq_data[186:182] != 5'd7 &&
rob$deqPort_0_deq_data[186:182] != 5'd8 &&
rob$deqPort_0_deq_data[186:182] != 5'd9 &&
rob$deqPort_0_deq_data[186:182] != 5'd10 &&
rob$deqPort_0_deq_data[186:182] != 5'd11 &&
rob$deqPort_0_deq_data[186:182] != 5'd12 &&
rob$deqPort_0_deq_data[186:182] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd0), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_instret +
IF_rob_deqPort_0_canDeq__4602_THEN_IF_NOT_rob__ETC___d14710,
rob$deqPort_1_deq_data[282:219],
rob$deqPort_1_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 &&
rob$deqPort_1_deq_data[186:182] != 5'd1 &&
rob$deqPort_1_deq_data[186:182] != 5'd2 &&
rob$deqPort_1_deq_data[186:182] != 5'd3 &&
rob$deqPort_1_deq_data[186:182] != 5'd4 &&
rob$deqPort_1_deq_data[186:182] != 5'd5 &&
rob$deqPort_1_deq_data[186:182] != 5'd6 &&
rob$deqPort_1_deq_data[186:182] != 5'd7 &&
rob$deqPort_1_deq_data[186:182] != 5'd8 &&
rob$deqPort_1_deq_data[186:182] != 5'd9 &&
rob$deqPort_1_deq_data[186:182] != 5'd10 &&
rob$deqPort_1_deq_data[186:182] != 5'd11 &&
rob$deqPort_1_deq_data[186:182] != 5'd12 &&
rob$deqPort_1_deq_data[186:182] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd1), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
v__h601904 == 2'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
end
// synopsys translate_on
endmodule // mkCore
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