10108 lines
400 KiB
Verilog
10108 lines
400 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
|
|
//
|
|
// On Mon Jul 13 18:47:23 BST 2020
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// flush_done O 1
|
|
// RDY_flush_done O 1 const
|
|
// RDY_flush O 1
|
|
// RDY_updateVMInfo O 1 const
|
|
// noPendingReq O 1
|
|
// RDY_noPendingReq O 1 const
|
|
// RDY_procReq O 1
|
|
// procResp O 561
|
|
// RDY_procResp O 1
|
|
// RDY_deqProcResp O 1
|
|
// toParent_rqToP_notEmpty O 1
|
|
// RDY_toParent_rqToP_notEmpty O 1 const
|
|
// RDY_toParent_rqToP_deq O 1
|
|
// toParent_rqToP_first O 29
|
|
// RDY_toParent_rqToP_first O 1
|
|
// toParent_ldTransRsFromP_notFull O 1
|
|
// RDY_toParent_ldTransRsFromP_notFull O 1 const
|
|
// RDY_toParent_ldTransRsFromP_enq O 1
|
|
// RDY_toParent_flush_request_get O 1
|
|
// RDY_toParent_flush_response_put O 1
|
|
// RDY_specUpdate_incorrectSpeculation O 1 const
|
|
// RDY_specUpdate_correctSpeculation O 1 const
|
|
// RDY_perf_setStatus O 1 const
|
|
// RDY_perf_req O 1
|
|
// perf_resp O 67
|
|
// RDY_perf_resp O 1
|
|
// perf_respValid O 1
|
|
// RDY_perf_respValid O 1 const
|
|
// CLK I 1 clock
|
|
// RST_N I 1 reset
|
|
// updateVMInfo_vm I 49 reg
|
|
// procReq_req I 491
|
|
// toParent_ldTransRsFromP_enq_x I 83
|
|
// specUpdate_incorrectSpeculation_kill_all I 1
|
|
// specUpdate_incorrectSpeculation_kill_tag I 4
|
|
// specUpdate_correctSpeculation_mask I 12
|
|
// perf_setStatus_doStats I 1 unused
|
|
// perf_req_r I 3
|
|
// EN_flush I 1
|
|
// EN_updateVMInfo I 1
|
|
// EN_procReq I 1
|
|
// EN_deqProcResp I 1
|
|
// EN_toParent_rqToP_deq I 1
|
|
// EN_toParent_ldTransRsFromP_enq I 1
|
|
// EN_toParent_flush_request_get I 1
|
|
// EN_toParent_flush_response_put I 1
|
|
// EN_specUpdate_incorrectSpeculation I 1
|
|
// EN_specUpdate_correctSpeculation I 1
|
|
// EN_perf_setStatus I 1 unused
|
|
// EN_perf_req I 1
|
|
// EN_perf_resp I 1
|
|
//
|
|
// No combinational paths from inputs to outputs
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module mkDTlbSynth(CLK,
|
|
RST_N,
|
|
|
|
flush_done,
|
|
RDY_flush_done,
|
|
|
|
EN_flush,
|
|
RDY_flush,
|
|
|
|
updateVMInfo_vm,
|
|
EN_updateVMInfo,
|
|
RDY_updateVMInfo,
|
|
|
|
noPendingReq,
|
|
RDY_noPendingReq,
|
|
|
|
procReq_req,
|
|
EN_procReq,
|
|
RDY_procReq,
|
|
|
|
procResp,
|
|
RDY_procResp,
|
|
|
|
EN_deqProcResp,
|
|
RDY_deqProcResp,
|
|
|
|
toParent_rqToP_notEmpty,
|
|
RDY_toParent_rqToP_notEmpty,
|
|
|
|
EN_toParent_rqToP_deq,
|
|
RDY_toParent_rqToP_deq,
|
|
|
|
toParent_rqToP_first,
|
|
RDY_toParent_rqToP_first,
|
|
|
|
toParent_ldTransRsFromP_notFull,
|
|
RDY_toParent_ldTransRsFromP_notFull,
|
|
|
|
toParent_ldTransRsFromP_enq_x,
|
|
EN_toParent_ldTransRsFromP_enq,
|
|
RDY_toParent_ldTransRsFromP_enq,
|
|
|
|
EN_toParent_flush_request_get,
|
|
RDY_toParent_flush_request_get,
|
|
|
|
EN_toParent_flush_response_put,
|
|
RDY_toParent_flush_response_put,
|
|
|
|
specUpdate_incorrectSpeculation_kill_all,
|
|
specUpdate_incorrectSpeculation_kill_tag,
|
|
EN_specUpdate_incorrectSpeculation,
|
|
RDY_specUpdate_incorrectSpeculation,
|
|
|
|
specUpdate_correctSpeculation_mask,
|
|
EN_specUpdate_correctSpeculation,
|
|
RDY_specUpdate_correctSpeculation,
|
|
|
|
perf_setStatus_doStats,
|
|
EN_perf_setStatus,
|
|
RDY_perf_setStatus,
|
|
|
|
perf_req_r,
|
|
EN_perf_req,
|
|
RDY_perf_req,
|
|
|
|
EN_perf_resp,
|
|
perf_resp,
|
|
RDY_perf_resp,
|
|
|
|
perf_respValid,
|
|
RDY_perf_respValid);
|
|
input CLK;
|
|
input RST_N;
|
|
|
|
// value method flush_done
|
|
output flush_done;
|
|
output RDY_flush_done;
|
|
|
|
// action method flush
|
|
input EN_flush;
|
|
output RDY_flush;
|
|
|
|
// action method updateVMInfo
|
|
input [48 : 0] updateVMInfo_vm;
|
|
input EN_updateVMInfo;
|
|
output RDY_updateVMInfo;
|
|
|
|
// value method noPendingReq
|
|
output noPendingReq;
|
|
output RDY_noPendingReq;
|
|
|
|
// action method procReq
|
|
input [490 : 0] procReq_req;
|
|
input EN_procReq;
|
|
output RDY_procReq;
|
|
|
|
// value method procResp
|
|
output [560 : 0] procResp;
|
|
output RDY_procResp;
|
|
|
|
// action method deqProcResp
|
|
input EN_deqProcResp;
|
|
output RDY_deqProcResp;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
output toParent_rqToP_notEmpty;
|
|
output RDY_toParent_rqToP_notEmpty;
|
|
|
|
// action method toParent_rqToP_deq
|
|
input EN_toParent_rqToP_deq;
|
|
output RDY_toParent_rqToP_deq;
|
|
|
|
// value method toParent_rqToP_first
|
|
output [28 : 0] toParent_rqToP_first;
|
|
output RDY_toParent_rqToP_first;
|
|
|
|
// value method toParent_ldTransRsFromP_notFull
|
|
output toParent_ldTransRsFromP_notFull;
|
|
output RDY_toParent_ldTransRsFromP_notFull;
|
|
|
|
// action method toParent_ldTransRsFromP_enq
|
|
input [82 : 0] toParent_ldTransRsFromP_enq_x;
|
|
input EN_toParent_ldTransRsFromP_enq;
|
|
output RDY_toParent_ldTransRsFromP_enq;
|
|
|
|
// action method toParent_flush_request_get
|
|
input EN_toParent_flush_request_get;
|
|
output RDY_toParent_flush_request_get;
|
|
|
|
// action method toParent_flush_response_put
|
|
input EN_toParent_flush_response_put;
|
|
output RDY_toParent_flush_response_put;
|
|
|
|
// action method specUpdate_incorrectSpeculation
|
|
input specUpdate_incorrectSpeculation_kill_all;
|
|
input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
|
|
input EN_specUpdate_incorrectSpeculation;
|
|
output RDY_specUpdate_incorrectSpeculation;
|
|
|
|
// action method specUpdate_correctSpeculation
|
|
input [11 : 0] specUpdate_correctSpeculation_mask;
|
|
input EN_specUpdate_correctSpeculation;
|
|
output RDY_specUpdate_correctSpeculation;
|
|
|
|
// action method perf_setStatus
|
|
input perf_setStatus_doStats;
|
|
input EN_perf_setStatus;
|
|
output RDY_perf_setStatus;
|
|
|
|
// action method perf_req
|
|
input [2 : 0] perf_req_r;
|
|
input EN_perf_req;
|
|
output RDY_perf_req;
|
|
|
|
// actionvalue method perf_resp
|
|
input EN_perf_resp;
|
|
output [66 : 0] perf_resp;
|
|
output RDY_perf_resp;
|
|
|
|
// value method perf_respValid
|
|
output perf_respValid;
|
|
output RDY_perf_respValid;
|
|
|
|
// signals for module outputs
|
|
wire [560 : 0] procResp;
|
|
wire [66 : 0] perf_resp;
|
|
wire [28 : 0] toParent_rqToP_first;
|
|
wire RDY_deqProcResp,
|
|
RDY_flush,
|
|
RDY_flush_done,
|
|
RDY_noPendingReq,
|
|
RDY_perf_req,
|
|
RDY_perf_resp,
|
|
RDY_perf_respValid,
|
|
RDY_perf_setStatus,
|
|
RDY_procReq,
|
|
RDY_procResp,
|
|
RDY_specUpdate_correctSpeculation,
|
|
RDY_specUpdate_incorrectSpeculation,
|
|
RDY_toParent_flush_request_get,
|
|
RDY_toParent_flush_response_put,
|
|
RDY_toParent_ldTransRsFromP_enq,
|
|
RDY_toParent_ldTransRsFromP_notFull,
|
|
RDY_toParent_rqToP_deq,
|
|
RDY_toParent_rqToP_first,
|
|
RDY_toParent_rqToP_notEmpty,
|
|
RDY_updateVMInfo,
|
|
flush_done,
|
|
noPendingReq,
|
|
perf_respValid,
|
|
toParent_ldTransRsFromP_notFull,
|
|
toParent_rqToP_notEmpty;
|
|
|
|
// inlined wires
|
|
reg [2 : 0] m_freeQ_enqReq_lat_0$wget;
|
|
wire [83 : 0] m_ldTransRsFromPQ_enqReq_lat_0$wget;
|
|
wire [29 : 0] m_rqToPQ_enqReq_lat_0$wget;
|
|
wire [5 : 0] m_tlb_m_updRepIdx_lat_1$wget;
|
|
wire [3 : 0] m_perfReqQ_enqReq_lat_0$wget;
|
|
wire m_freeQ_enqReq_lat_0$whas,
|
|
m_ldTransRsFromPQ_deqReq_lat_0$whas,
|
|
m_pendValid_0_lat_0$whas,
|
|
m_pendValid_1_lat_0$whas,
|
|
m_pendValid_2_lat_0$whas,
|
|
m_pendValid_3_lat_0$whas,
|
|
m_rqToPQ_enqReq_lat_0$whas,
|
|
m_tlb_m_lruBit_lat_0$whas,
|
|
m_tlb_m_updRepIdx_lat_0$whas,
|
|
m_tlb_m_updRepIdx_lat_1$whas;
|
|
|
|
// register m_flushRqToPQ_clearReq_rl
|
|
reg m_flushRqToPQ_clearReq_rl;
|
|
wire m_flushRqToPQ_clearReq_rl$D_IN, m_flushRqToPQ_clearReq_rl$EN;
|
|
|
|
// register m_flushRqToPQ_deqReq_rl
|
|
reg m_flushRqToPQ_deqReq_rl;
|
|
wire m_flushRqToPQ_deqReq_rl$D_IN, m_flushRqToPQ_deqReq_rl$EN;
|
|
|
|
// register m_flushRqToPQ_empty
|
|
reg m_flushRqToPQ_empty;
|
|
wire m_flushRqToPQ_empty$D_IN, m_flushRqToPQ_empty$EN;
|
|
|
|
// register m_flushRqToPQ_enqReq_rl
|
|
reg m_flushRqToPQ_enqReq_rl;
|
|
wire m_flushRqToPQ_enqReq_rl$D_IN, m_flushRqToPQ_enqReq_rl$EN;
|
|
|
|
// register m_flushRqToPQ_full
|
|
reg m_flushRqToPQ_full;
|
|
wire m_flushRqToPQ_full$D_IN, m_flushRqToPQ_full$EN;
|
|
|
|
// register m_flushRsFromPQ_clearReq_rl
|
|
reg m_flushRsFromPQ_clearReq_rl;
|
|
wire m_flushRsFromPQ_clearReq_rl$D_IN, m_flushRsFromPQ_clearReq_rl$EN;
|
|
|
|
// register m_flushRsFromPQ_deqReq_rl
|
|
reg m_flushRsFromPQ_deqReq_rl;
|
|
wire m_flushRsFromPQ_deqReq_rl$D_IN, m_flushRsFromPQ_deqReq_rl$EN;
|
|
|
|
// register m_flushRsFromPQ_empty
|
|
reg m_flushRsFromPQ_empty;
|
|
wire m_flushRsFromPQ_empty$D_IN, m_flushRsFromPQ_empty$EN;
|
|
|
|
// register m_flushRsFromPQ_enqReq_rl
|
|
reg m_flushRsFromPQ_enqReq_rl;
|
|
wire m_flushRsFromPQ_enqReq_rl$D_IN, m_flushRsFromPQ_enqReq_rl$EN;
|
|
|
|
// register m_flushRsFromPQ_full
|
|
reg m_flushRsFromPQ_full;
|
|
wire m_flushRsFromPQ_full$D_IN, m_flushRsFromPQ_full$EN;
|
|
|
|
// register m_freeQInitIdx
|
|
reg [1 : 0] m_freeQInitIdx;
|
|
wire [1 : 0] m_freeQInitIdx$D_IN;
|
|
wire m_freeQInitIdx$EN;
|
|
|
|
// register m_freeQInited
|
|
reg m_freeQInited;
|
|
wire m_freeQInited$D_IN, m_freeQInited$EN;
|
|
|
|
// register m_freeQ_clearReq_rl
|
|
reg m_freeQ_clearReq_rl;
|
|
wire m_freeQ_clearReq_rl$D_IN, m_freeQ_clearReq_rl$EN;
|
|
|
|
// register m_freeQ_data_0
|
|
reg [1 : 0] m_freeQ_data_0;
|
|
wire [1 : 0] m_freeQ_data_0$D_IN;
|
|
wire m_freeQ_data_0$EN;
|
|
|
|
// register m_freeQ_data_1
|
|
reg [1 : 0] m_freeQ_data_1;
|
|
wire [1 : 0] m_freeQ_data_1$D_IN;
|
|
wire m_freeQ_data_1$EN;
|
|
|
|
// register m_freeQ_data_2
|
|
reg [1 : 0] m_freeQ_data_2;
|
|
wire [1 : 0] m_freeQ_data_2$D_IN;
|
|
wire m_freeQ_data_2$EN;
|
|
|
|
// register m_freeQ_data_3
|
|
reg [1 : 0] m_freeQ_data_3;
|
|
wire [1 : 0] m_freeQ_data_3$D_IN;
|
|
wire m_freeQ_data_3$EN;
|
|
|
|
// register m_freeQ_deqP
|
|
reg [1 : 0] m_freeQ_deqP;
|
|
wire [1 : 0] m_freeQ_deqP$D_IN;
|
|
wire m_freeQ_deqP$EN;
|
|
|
|
// register m_freeQ_deqReq_rl
|
|
reg m_freeQ_deqReq_rl;
|
|
wire m_freeQ_deqReq_rl$D_IN, m_freeQ_deqReq_rl$EN;
|
|
|
|
// register m_freeQ_empty
|
|
reg m_freeQ_empty;
|
|
wire m_freeQ_empty$D_IN, m_freeQ_empty$EN;
|
|
|
|
// register m_freeQ_enqP
|
|
reg [1 : 0] m_freeQ_enqP;
|
|
wire [1 : 0] m_freeQ_enqP$D_IN;
|
|
wire m_freeQ_enqP$EN;
|
|
|
|
// register m_freeQ_enqReq_rl
|
|
reg [2 : 0] m_freeQ_enqReq_rl;
|
|
wire [2 : 0] m_freeQ_enqReq_rl$D_IN;
|
|
wire m_freeQ_enqReq_rl$EN;
|
|
|
|
// register m_freeQ_full
|
|
reg m_freeQ_full;
|
|
wire m_freeQ_full$D_IN, m_freeQ_full$EN;
|
|
|
|
// register m_ldTransRsFromPQ_clearReq_rl
|
|
reg m_ldTransRsFromPQ_clearReq_rl;
|
|
wire m_ldTransRsFromPQ_clearReq_rl$D_IN, m_ldTransRsFromPQ_clearReq_rl$EN;
|
|
|
|
// register m_ldTransRsFromPQ_data_0
|
|
reg [82 : 0] m_ldTransRsFromPQ_data_0;
|
|
wire [82 : 0] m_ldTransRsFromPQ_data_0$D_IN;
|
|
wire m_ldTransRsFromPQ_data_0$EN;
|
|
|
|
// register m_ldTransRsFromPQ_data_1
|
|
reg [82 : 0] m_ldTransRsFromPQ_data_1;
|
|
wire [82 : 0] m_ldTransRsFromPQ_data_1$D_IN;
|
|
wire m_ldTransRsFromPQ_data_1$EN;
|
|
|
|
// register m_ldTransRsFromPQ_deqP
|
|
reg m_ldTransRsFromPQ_deqP;
|
|
wire m_ldTransRsFromPQ_deqP$D_IN, m_ldTransRsFromPQ_deqP$EN;
|
|
|
|
// register m_ldTransRsFromPQ_deqReq_rl
|
|
reg m_ldTransRsFromPQ_deqReq_rl;
|
|
wire m_ldTransRsFromPQ_deqReq_rl$D_IN, m_ldTransRsFromPQ_deqReq_rl$EN;
|
|
|
|
// register m_ldTransRsFromPQ_empty
|
|
reg m_ldTransRsFromPQ_empty;
|
|
wire m_ldTransRsFromPQ_empty$D_IN, m_ldTransRsFromPQ_empty$EN;
|
|
|
|
// register m_ldTransRsFromPQ_enqP
|
|
reg m_ldTransRsFromPQ_enqP;
|
|
wire m_ldTransRsFromPQ_enqP$D_IN, m_ldTransRsFromPQ_enqP$EN;
|
|
|
|
// register m_ldTransRsFromPQ_enqReq_rl
|
|
reg [83 : 0] m_ldTransRsFromPQ_enqReq_rl;
|
|
wire [83 : 0] m_ldTransRsFromPQ_enqReq_rl$D_IN;
|
|
wire m_ldTransRsFromPQ_enqReq_rl$EN;
|
|
|
|
// register m_ldTransRsFromPQ_full
|
|
reg m_ldTransRsFromPQ_full;
|
|
wire m_ldTransRsFromPQ_full$D_IN, m_ldTransRsFromPQ_full$EN;
|
|
|
|
// register m_needFlush
|
|
reg m_needFlush;
|
|
wire m_needFlush$D_IN, m_needFlush$EN;
|
|
|
|
// register m_pendInst_0
|
|
reg [478 : 0] m_pendInst_0;
|
|
wire [478 : 0] m_pendInst_0$D_IN;
|
|
wire m_pendInst_0$EN;
|
|
|
|
// register m_pendInst_1
|
|
reg [478 : 0] m_pendInst_1;
|
|
wire [478 : 0] m_pendInst_1$D_IN;
|
|
wire m_pendInst_1$EN;
|
|
|
|
// register m_pendInst_2
|
|
reg [478 : 0] m_pendInst_2;
|
|
wire [478 : 0] m_pendInst_2$D_IN;
|
|
wire m_pendInst_2$EN;
|
|
|
|
// register m_pendInst_3
|
|
reg [478 : 0] m_pendInst_3;
|
|
wire [478 : 0] m_pendInst_3$D_IN;
|
|
wire m_pendInst_3$EN;
|
|
|
|
// register m_pendPoisoned_0
|
|
reg m_pendPoisoned_0;
|
|
wire m_pendPoisoned_0$D_IN, m_pendPoisoned_0$EN;
|
|
|
|
// register m_pendPoisoned_1
|
|
reg m_pendPoisoned_1;
|
|
wire m_pendPoisoned_1$D_IN, m_pendPoisoned_1$EN;
|
|
|
|
// register m_pendPoisoned_2
|
|
reg m_pendPoisoned_2;
|
|
wire m_pendPoisoned_2$D_IN, m_pendPoisoned_2$EN;
|
|
|
|
// register m_pendPoisoned_3
|
|
reg m_pendPoisoned_3;
|
|
wire m_pendPoisoned_3$D_IN, m_pendPoisoned_3$EN;
|
|
|
|
// register m_pendResp_0
|
|
reg [69 : 0] m_pendResp_0;
|
|
wire [69 : 0] m_pendResp_0$D_IN;
|
|
wire m_pendResp_0$EN;
|
|
|
|
// register m_pendResp_1
|
|
reg [69 : 0] m_pendResp_1;
|
|
wire [69 : 0] m_pendResp_1$D_IN;
|
|
wire m_pendResp_1$EN;
|
|
|
|
// register m_pendResp_2
|
|
reg [69 : 0] m_pendResp_2;
|
|
wire [69 : 0] m_pendResp_2$D_IN;
|
|
wire m_pendResp_2$EN;
|
|
|
|
// register m_pendResp_3
|
|
reg [69 : 0] m_pendResp_3;
|
|
wire [69 : 0] m_pendResp_3$D_IN;
|
|
wire m_pendResp_3$EN;
|
|
|
|
// register m_pendSpecBits_0_rl
|
|
reg [11 : 0] m_pendSpecBits_0_rl;
|
|
wire [11 : 0] m_pendSpecBits_0_rl$D_IN;
|
|
wire m_pendSpecBits_0_rl$EN;
|
|
|
|
// register m_pendSpecBits_1_rl
|
|
reg [11 : 0] m_pendSpecBits_1_rl;
|
|
wire [11 : 0] m_pendSpecBits_1_rl$D_IN;
|
|
wire m_pendSpecBits_1_rl$EN;
|
|
|
|
// register m_pendSpecBits_2_rl
|
|
reg [11 : 0] m_pendSpecBits_2_rl;
|
|
wire [11 : 0] m_pendSpecBits_2_rl$D_IN;
|
|
wire m_pendSpecBits_2_rl$EN;
|
|
|
|
// register m_pendSpecBits_3_rl
|
|
reg [11 : 0] m_pendSpecBits_3_rl;
|
|
wire [11 : 0] m_pendSpecBits_3_rl$D_IN;
|
|
wire m_pendSpecBits_3_rl$EN;
|
|
|
|
// register m_pendValid_0_rl
|
|
reg m_pendValid_0_rl;
|
|
wire m_pendValid_0_rl$D_IN, m_pendValid_0_rl$EN;
|
|
|
|
// register m_pendValid_1_rl
|
|
reg m_pendValid_1_rl;
|
|
wire m_pendValid_1_rl$D_IN, m_pendValid_1_rl$EN;
|
|
|
|
// register m_pendValid_2_rl
|
|
reg m_pendValid_2_rl;
|
|
wire m_pendValid_2_rl$D_IN, m_pendValid_2_rl$EN;
|
|
|
|
// register m_pendValid_3_rl
|
|
reg m_pendValid_3_rl;
|
|
wire m_pendValid_3_rl$D_IN, m_pendValid_3_rl$EN;
|
|
|
|
// register m_pendWait_0
|
|
reg [3 : 0] m_pendWait_0;
|
|
wire [3 : 0] m_pendWait_0$D_IN;
|
|
wire m_pendWait_0$EN;
|
|
|
|
// register m_pendWait_1
|
|
reg [3 : 0] m_pendWait_1;
|
|
wire [3 : 0] m_pendWait_1$D_IN;
|
|
wire m_pendWait_1$EN;
|
|
|
|
// register m_pendWait_2
|
|
reg [3 : 0] m_pendWait_2;
|
|
wire [3 : 0] m_pendWait_2$D_IN;
|
|
wire m_pendWait_2$EN;
|
|
|
|
// register m_pendWait_3
|
|
reg [3 : 0] m_pendWait_3;
|
|
wire [3 : 0] m_pendWait_3$D_IN;
|
|
wire m_pendWait_3$EN;
|
|
|
|
// register m_perfReqQ_clearReq_rl
|
|
reg m_perfReqQ_clearReq_rl;
|
|
wire m_perfReqQ_clearReq_rl$D_IN, m_perfReqQ_clearReq_rl$EN;
|
|
|
|
// register m_perfReqQ_data_0
|
|
reg [2 : 0] m_perfReqQ_data_0;
|
|
wire [2 : 0] m_perfReqQ_data_0$D_IN;
|
|
wire m_perfReqQ_data_0$EN;
|
|
|
|
// register m_perfReqQ_deqReq_rl
|
|
reg m_perfReqQ_deqReq_rl;
|
|
wire m_perfReqQ_deqReq_rl$D_IN, m_perfReqQ_deqReq_rl$EN;
|
|
|
|
// register m_perfReqQ_empty
|
|
reg m_perfReqQ_empty;
|
|
wire m_perfReqQ_empty$D_IN, m_perfReqQ_empty$EN;
|
|
|
|
// register m_perfReqQ_enqReq_rl
|
|
reg [3 : 0] m_perfReqQ_enqReq_rl;
|
|
wire [3 : 0] m_perfReqQ_enqReq_rl$D_IN;
|
|
wire m_perfReqQ_enqReq_rl$EN;
|
|
|
|
// register m_perfReqQ_full
|
|
reg m_perfReqQ_full;
|
|
wire m_perfReqQ_full$D_IN, m_perfReqQ_full$EN;
|
|
|
|
// register m_respForOtherReq
|
|
reg [2 : 0] m_respForOtherReq;
|
|
wire [2 : 0] m_respForOtherReq$D_IN;
|
|
wire m_respForOtherReq$EN;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
reg m_rqToPQ_clearReq_rl;
|
|
wire m_rqToPQ_clearReq_rl$D_IN, m_rqToPQ_clearReq_rl$EN;
|
|
|
|
// register m_rqToPQ_data_0
|
|
reg [28 : 0] m_rqToPQ_data_0;
|
|
wire [28 : 0] m_rqToPQ_data_0$D_IN;
|
|
wire m_rqToPQ_data_0$EN;
|
|
|
|
// register m_rqToPQ_data_1
|
|
reg [28 : 0] m_rqToPQ_data_1;
|
|
wire [28 : 0] m_rqToPQ_data_1$D_IN;
|
|
wire m_rqToPQ_data_1$EN;
|
|
|
|
// register m_rqToPQ_data_2
|
|
reg [28 : 0] m_rqToPQ_data_2;
|
|
wire [28 : 0] m_rqToPQ_data_2$D_IN;
|
|
wire m_rqToPQ_data_2$EN;
|
|
|
|
// register m_rqToPQ_data_3
|
|
reg [28 : 0] m_rqToPQ_data_3;
|
|
wire [28 : 0] m_rqToPQ_data_3$D_IN;
|
|
wire m_rqToPQ_data_3$EN;
|
|
|
|
// register m_rqToPQ_deqP
|
|
reg [1 : 0] m_rqToPQ_deqP;
|
|
wire [1 : 0] m_rqToPQ_deqP$D_IN;
|
|
wire m_rqToPQ_deqP$EN;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
reg m_rqToPQ_deqReq_rl;
|
|
wire m_rqToPQ_deqReq_rl$D_IN, m_rqToPQ_deqReq_rl$EN;
|
|
|
|
// register m_rqToPQ_empty
|
|
reg m_rqToPQ_empty;
|
|
wire m_rqToPQ_empty$D_IN, m_rqToPQ_empty$EN;
|
|
|
|
// register m_rqToPQ_enqP
|
|
reg [1 : 0] m_rqToPQ_enqP;
|
|
wire [1 : 0] m_rqToPQ_enqP$D_IN;
|
|
wire m_rqToPQ_enqP$EN;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
reg [29 : 0] m_rqToPQ_enqReq_rl;
|
|
wire [29 : 0] m_rqToPQ_enqReq_rl$D_IN;
|
|
wire m_rqToPQ_enqReq_rl$EN;
|
|
|
|
// register m_rqToPQ_full
|
|
reg m_rqToPQ_full;
|
|
wire m_rqToPQ_full$D_IN, m_rqToPQ_full$EN;
|
|
|
|
// register m_tlb_m_entryVec_0
|
|
reg [79 : 0] m_tlb_m_entryVec_0;
|
|
wire [79 : 0] m_tlb_m_entryVec_0$D_IN;
|
|
wire m_tlb_m_entryVec_0$EN;
|
|
|
|
// register m_tlb_m_entryVec_1
|
|
reg [79 : 0] m_tlb_m_entryVec_1;
|
|
wire [79 : 0] m_tlb_m_entryVec_1$D_IN;
|
|
wire m_tlb_m_entryVec_1$EN;
|
|
|
|
// register m_tlb_m_entryVec_10
|
|
reg [79 : 0] m_tlb_m_entryVec_10;
|
|
wire [79 : 0] m_tlb_m_entryVec_10$D_IN;
|
|
wire m_tlb_m_entryVec_10$EN;
|
|
|
|
// register m_tlb_m_entryVec_11
|
|
reg [79 : 0] m_tlb_m_entryVec_11;
|
|
wire [79 : 0] m_tlb_m_entryVec_11$D_IN;
|
|
wire m_tlb_m_entryVec_11$EN;
|
|
|
|
// register m_tlb_m_entryVec_12
|
|
reg [79 : 0] m_tlb_m_entryVec_12;
|
|
wire [79 : 0] m_tlb_m_entryVec_12$D_IN;
|
|
wire m_tlb_m_entryVec_12$EN;
|
|
|
|
// register m_tlb_m_entryVec_13
|
|
reg [79 : 0] m_tlb_m_entryVec_13;
|
|
wire [79 : 0] m_tlb_m_entryVec_13$D_IN;
|
|
wire m_tlb_m_entryVec_13$EN;
|
|
|
|
// register m_tlb_m_entryVec_14
|
|
reg [79 : 0] m_tlb_m_entryVec_14;
|
|
wire [79 : 0] m_tlb_m_entryVec_14$D_IN;
|
|
wire m_tlb_m_entryVec_14$EN;
|
|
|
|
// register m_tlb_m_entryVec_15
|
|
reg [79 : 0] m_tlb_m_entryVec_15;
|
|
wire [79 : 0] m_tlb_m_entryVec_15$D_IN;
|
|
wire m_tlb_m_entryVec_15$EN;
|
|
|
|
// register m_tlb_m_entryVec_16
|
|
reg [79 : 0] m_tlb_m_entryVec_16;
|
|
wire [79 : 0] m_tlb_m_entryVec_16$D_IN;
|
|
wire m_tlb_m_entryVec_16$EN;
|
|
|
|
// register m_tlb_m_entryVec_17
|
|
reg [79 : 0] m_tlb_m_entryVec_17;
|
|
wire [79 : 0] m_tlb_m_entryVec_17$D_IN;
|
|
wire m_tlb_m_entryVec_17$EN;
|
|
|
|
// register m_tlb_m_entryVec_18
|
|
reg [79 : 0] m_tlb_m_entryVec_18;
|
|
wire [79 : 0] m_tlb_m_entryVec_18$D_IN;
|
|
wire m_tlb_m_entryVec_18$EN;
|
|
|
|
// register m_tlb_m_entryVec_19
|
|
reg [79 : 0] m_tlb_m_entryVec_19;
|
|
wire [79 : 0] m_tlb_m_entryVec_19$D_IN;
|
|
wire m_tlb_m_entryVec_19$EN;
|
|
|
|
// register m_tlb_m_entryVec_2
|
|
reg [79 : 0] m_tlb_m_entryVec_2;
|
|
wire [79 : 0] m_tlb_m_entryVec_2$D_IN;
|
|
wire m_tlb_m_entryVec_2$EN;
|
|
|
|
// register m_tlb_m_entryVec_20
|
|
reg [79 : 0] m_tlb_m_entryVec_20;
|
|
wire [79 : 0] m_tlb_m_entryVec_20$D_IN;
|
|
wire m_tlb_m_entryVec_20$EN;
|
|
|
|
// register m_tlb_m_entryVec_21
|
|
reg [79 : 0] m_tlb_m_entryVec_21;
|
|
wire [79 : 0] m_tlb_m_entryVec_21$D_IN;
|
|
wire m_tlb_m_entryVec_21$EN;
|
|
|
|
// register m_tlb_m_entryVec_22
|
|
reg [79 : 0] m_tlb_m_entryVec_22;
|
|
wire [79 : 0] m_tlb_m_entryVec_22$D_IN;
|
|
wire m_tlb_m_entryVec_22$EN;
|
|
|
|
// register m_tlb_m_entryVec_23
|
|
reg [79 : 0] m_tlb_m_entryVec_23;
|
|
wire [79 : 0] m_tlb_m_entryVec_23$D_IN;
|
|
wire m_tlb_m_entryVec_23$EN;
|
|
|
|
// register m_tlb_m_entryVec_24
|
|
reg [79 : 0] m_tlb_m_entryVec_24;
|
|
wire [79 : 0] m_tlb_m_entryVec_24$D_IN;
|
|
wire m_tlb_m_entryVec_24$EN;
|
|
|
|
// register m_tlb_m_entryVec_25
|
|
reg [79 : 0] m_tlb_m_entryVec_25;
|
|
wire [79 : 0] m_tlb_m_entryVec_25$D_IN;
|
|
wire m_tlb_m_entryVec_25$EN;
|
|
|
|
// register m_tlb_m_entryVec_26
|
|
reg [79 : 0] m_tlb_m_entryVec_26;
|
|
wire [79 : 0] m_tlb_m_entryVec_26$D_IN;
|
|
wire m_tlb_m_entryVec_26$EN;
|
|
|
|
// register m_tlb_m_entryVec_27
|
|
reg [79 : 0] m_tlb_m_entryVec_27;
|
|
wire [79 : 0] m_tlb_m_entryVec_27$D_IN;
|
|
wire m_tlb_m_entryVec_27$EN;
|
|
|
|
// register m_tlb_m_entryVec_28
|
|
reg [79 : 0] m_tlb_m_entryVec_28;
|
|
wire [79 : 0] m_tlb_m_entryVec_28$D_IN;
|
|
wire m_tlb_m_entryVec_28$EN;
|
|
|
|
// register m_tlb_m_entryVec_29
|
|
reg [79 : 0] m_tlb_m_entryVec_29;
|
|
wire [79 : 0] m_tlb_m_entryVec_29$D_IN;
|
|
wire m_tlb_m_entryVec_29$EN;
|
|
|
|
// register m_tlb_m_entryVec_3
|
|
reg [79 : 0] m_tlb_m_entryVec_3;
|
|
wire [79 : 0] m_tlb_m_entryVec_3$D_IN;
|
|
wire m_tlb_m_entryVec_3$EN;
|
|
|
|
// register m_tlb_m_entryVec_30
|
|
reg [79 : 0] m_tlb_m_entryVec_30;
|
|
wire [79 : 0] m_tlb_m_entryVec_30$D_IN;
|
|
wire m_tlb_m_entryVec_30$EN;
|
|
|
|
// register m_tlb_m_entryVec_31
|
|
reg [79 : 0] m_tlb_m_entryVec_31;
|
|
wire [79 : 0] m_tlb_m_entryVec_31$D_IN;
|
|
wire m_tlb_m_entryVec_31$EN;
|
|
|
|
// register m_tlb_m_entryVec_4
|
|
reg [79 : 0] m_tlb_m_entryVec_4;
|
|
wire [79 : 0] m_tlb_m_entryVec_4$D_IN;
|
|
wire m_tlb_m_entryVec_4$EN;
|
|
|
|
// register m_tlb_m_entryVec_5
|
|
reg [79 : 0] m_tlb_m_entryVec_5;
|
|
wire [79 : 0] m_tlb_m_entryVec_5$D_IN;
|
|
wire m_tlb_m_entryVec_5$EN;
|
|
|
|
// register m_tlb_m_entryVec_6
|
|
reg [79 : 0] m_tlb_m_entryVec_6;
|
|
wire [79 : 0] m_tlb_m_entryVec_6$D_IN;
|
|
wire m_tlb_m_entryVec_6$EN;
|
|
|
|
// register m_tlb_m_entryVec_7
|
|
reg [79 : 0] m_tlb_m_entryVec_7;
|
|
wire [79 : 0] m_tlb_m_entryVec_7$D_IN;
|
|
wire m_tlb_m_entryVec_7$EN;
|
|
|
|
// register m_tlb_m_entryVec_8
|
|
reg [79 : 0] m_tlb_m_entryVec_8;
|
|
wire [79 : 0] m_tlb_m_entryVec_8$D_IN;
|
|
wire m_tlb_m_entryVec_8$EN;
|
|
|
|
// register m_tlb_m_entryVec_9
|
|
reg [79 : 0] m_tlb_m_entryVec_9;
|
|
wire [79 : 0] m_tlb_m_entryVec_9$D_IN;
|
|
wire m_tlb_m_entryVec_9$EN;
|
|
|
|
// register m_tlb_m_lruBit_rl
|
|
reg [31 : 0] m_tlb_m_lruBit_rl;
|
|
wire [31 : 0] m_tlb_m_lruBit_rl$D_IN;
|
|
wire m_tlb_m_lruBit_rl$EN;
|
|
|
|
// register m_tlb_m_randIdx
|
|
reg [4 : 0] m_tlb_m_randIdx;
|
|
wire [4 : 0] m_tlb_m_randIdx$D_IN;
|
|
wire m_tlb_m_randIdx$EN;
|
|
|
|
// register m_tlb_m_updRepIdx_rl
|
|
reg [5 : 0] m_tlb_m_updRepIdx_rl;
|
|
wire [5 : 0] m_tlb_m_updRepIdx_rl$D_IN;
|
|
wire m_tlb_m_updRepIdx_rl$EN;
|
|
|
|
// register m_tlb_m_validVec_0
|
|
reg m_tlb_m_validVec_0;
|
|
wire m_tlb_m_validVec_0$D_IN, m_tlb_m_validVec_0$EN;
|
|
|
|
// register m_tlb_m_validVec_1
|
|
reg m_tlb_m_validVec_1;
|
|
wire m_tlb_m_validVec_1$D_IN, m_tlb_m_validVec_1$EN;
|
|
|
|
// register m_tlb_m_validVec_10
|
|
reg m_tlb_m_validVec_10;
|
|
wire m_tlb_m_validVec_10$D_IN, m_tlb_m_validVec_10$EN;
|
|
|
|
// register m_tlb_m_validVec_11
|
|
reg m_tlb_m_validVec_11;
|
|
wire m_tlb_m_validVec_11$D_IN, m_tlb_m_validVec_11$EN;
|
|
|
|
// register m_tlb_m_validVec_12
|
|
reg m_tlb_m_validVec_12;
|
|
wire m_tlb_m_validVec_12$D_IN, m_tlb_m_validVec_12$EN;
|
|
|
|
// register m_tlb_m_validVec_13
|
|
reg m_tlb_m_validVec_13;
|
|
wire m_tlb_m_validVec_13$D_IN, m_tlb_m_validVec_13$EN;
|
|
|
|
// register m_tlb_m_validVec_14
|
|
reg m_tlb_m_validVec_14;
|
|
wire m_tlb_m_validVec_14$D_IN, m_tlb_m_validVec_14$EN;
|
|
|
|
// register m_tlb_m_validVec_15
|
|
reg m_tlb_m_validVec_15;
|
|
wire m_tlb_m_validVec_15$D_IN, m_tlb_m_validVec_15$EN;
|
|
|
|
// register m_tlb_m_validVec_16
|
|
reg m_tlb_m_validVec_16;
|
|
wire m_tlb_m_validVec_16$D_IN, m_tlb_m_validVec_16$EN;
|
|
|
|
// register m_tlb_m_validVec_17
|
|
reg m_tlb_m_validVec_17;
|
|
wire m_tlb_m_validVec_17$D_IN, m_tlb_m_validVec_17$EN;
|
|
|
|
// register m_tlb_m_validVec_18
|
|
reg m_tlb_m_validVec_18;
|
|
wire m_tlb_m_validVec_18$D_IN, m_tlb_m_validVec_18$EN;
|
|
|
|
// register m_tlb_m_validVec_19
|
|
reg m_tlb_m_validVec_19;
|
|
wire m_tlb_m_validVec_19$D_IN, m_tlb_m_validVec_19$EN;
|
|
|
|
// register m_tlb_m_validVec_2
|
|
reg m_tlb_m_validVec_2;
|
|
wire m_tlb_m_validVec_2$D_IN, m_tlb_m_validVec_2$EN;
|
|
|
|
// register m_tlb_m_validVec_20
|
|
reg m_tlb_m_validVec_20;
|
|
wire m_tlb_m_validVec_20$D_IN, m_tlb_m_validVec_20$EN;
|
|
|
|
// register m_tlb_m_validVec_21
|
|
reg m_tlb_m_validVec_21;
|
|
wire m_tlb_m_validVec_21$D_IN, m_tlb_m_validVec_21$EN;
|
|
|
|
// register m_tlb_m_validVec_22
|
|
reg m_tlb_m_validVec_22;
|
|
wire m_tlb_m_validVec_22$D_IN, m_tlb_m_validVec_22$EN;
|
|
|
|
// register m_tlb_m_validVec_23
|
|
reg m_tlb_m_validVec_23;
|
|
wire m_tlb_m_validVec_23$D_IN, m_tlb_m_validVec_23$EN;
|
|
|
|
// register m_tlb_m_validVec_24
|
|
reg m_tlb_m_validVec_24;
|
|
wire m_tlb_m_validVec_24$D_IN, m_tlb_m_validVec_24$EN;
|
|
|
|
// register m_tlb_m_validVec_25
|
|
reg m_tlb_m_validVec_25;
|
|
wire m_tlb_m_validVec_25$D_IN, m_tlb_m_validVec_25$EN;
|
|
|
|
// register m_tlb_m_validVec_26
|
|
reg m_tlb_m_validVec_26;
|
|
wire m_tlb_m_validVec_26$D_IN, m_tlb_m_validVec_26$EN;
|
|
|
|
// register m_tlb_m_validVec_27
|
|
reg m_tlb_m_validVec_27;
|
|
wire m_tlb_m_validVec_27$D_IN, m_tlb_m_validVec_27$EN;
|
|
|
|
// register m_tlb_m_validVec_28
|
|
reg m_tlb_m_validVec_28;
|
|
wire m_tlb_m_validVec_28$D_IN, m_tlb_m_validVec_28$EN;
|
|
|
|
// register m_tlb_m_validVec_29
|
|
reg m_tlb_m_validVec_29;
|
|
wire m_tlb_m_validVec_29$D_IN, m_tlb_m_validVec_29$EN;
|
|
|
|
// register m_tlb_m_validVec_3
|
|
reg m_tlb_m_validVec_3;
|
|
wire m_tlb_m_validVec_3$D_IN, m_tlb_m_validVec_3$EN;
|
|
|
|
// register m_tlb_m_validVec_30
|
|
reg m_tlb_m_validVec_30;
|
|
wire m_tlb_m_validVec_30$D_IN, m_tlb_m_validVec_30$EN;
|
|
|
|
// register m_tlb_m_validVec_31
|
|
reg m_tlb_m_validVec_31;
|
|
wire m_tlb_m_validVec_31$D_IN, m_tlb_m_validVec_31$EN;
|
|
|
|
// register m_tlb_m_validVec_4
|
|
reg m_tlb_m_validVec_4;
|
|
wire m_tlb_m_validVec_4$D_IN, m_tlb_m_validVec_4$EN;
|
|
|
|
// register m_tlb_m_validVec_5
|
|
reg m_tlb_m_validVec_5;
|
|
wire m_tlb_m_validVec_5$D_IN, m_tlb_m_validVec_5$EN;
|
|
|
|
// register m_tlb_m_validVec_6
|
|
reg m_tlb_m_validVec_6;
|
|
wire m_tlb_m_validVec_6$D_IN, m_tlb_m_validVec_6$EN;
|
|
|
|
// register m_tlb_m_validVec_7
|
|
reg m_tlb_m_validVec_7;
|
|
wire m_tlb_m_validVec_7$D_IN, m_tlb_m_validVec_7$EN;
|
|
|
|
// register m_tlb_m_validVec_8
|
|
reg m_tlb_m_validVec_8;
|
|
wire m_tlb_m_validVec_8$D_IN, m_tlb_m_validVec_8$EN;
|
|
|
|
// register m_tlb_m_validVec_9
|
|
reg m_tlb_m_validVec_9;
|
|
wire m_tlb_m_validVec_9$D_IN, m_tlb_m_validVec_9$EN;
|
|
|
|
// register m_vm_info
|
|
reg [48 : 0] m_vm_info;
|
|
wire [48 : 0] m_vm_info$D_IN;
|
|
wire m_vm_info$EN;
|
|
|
|
// register m_waitFlushP
|
|
reg m_waitFlushP;
|
|
wire m_waitFlushP$D_IN, m_waitFlushP$EN;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_m_doFinishFlush,
|
|
CAN_FIRE_RL_m_doInitFreeQ,
|
|
CAN_FIRE_RL_m_doPRs,
|
|
CAN_FIRE_RL_m_doPoisonedProcResp,
|
|
CAN_FIRE_RL_m_doStartFlush,
|
|
CAN_FIRE_RL_m_flushRqToPQ_canonicalize,
|
|
CAN_FIRE_RL_m_flushRqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_flushRqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_flushRqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_flushRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_freeQ_canonicalize,
|
|
CAN_FIRE_RL_m_freeQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_freeQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_freeQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_0_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_1_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_2_canon,
|
|
CAN_FIRE_RL_m_pendSpecBits_3_canon,
|
|
CAN_FIRE_RL_m_pendValid_0_canon,
|
|
CAN_FIRE_RL_m_pendValid_1_canon,
|
|
CAN_FIRE_RL_m_pendValid_2_canon,
|
|
CAN_FIRE_RL_m_pendValid_3_canon,
|
|
CAN_FIRE_RL_m_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_m_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_m_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_m_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_m_tlb_m_doUpdateRep,
|
|
CAN_FIRE_RL_m_tlb_m_incRandIdx,
|
|
CAN_FIRE_RL_m_tlb_m_lruBit_canon,
|
|
CAN_FIRE_RL_m_tlb_m_updRepIdx_canon,
|
|
CAN_FIRE_deqProcResp,
|
|
CAN_FIRE_flush,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_procReq,
|
|
CAN_FIRE_specUpdate_correctSpeculation,
|
|
CAN_FIRE_specUpdate_incorrectSpeculation,
|
|
CAN_FIRE_toParent_flush_request_get,
|
|
CAN_FIRE_toParent_flush_response_put,
|
|
CAN_FIRE_toParent_ldTransRsFromP_enq,
|
|
CAN_FIRE_toParent_rqToP_deq,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_m_doFinishFlush,
|
|
WILL_FIRE_RL_m_doInitFreeQ,
|
|
WILL_FIRE_RL_m_doPRs,
|
|
WILL_FIRE_RL_m_doPoisonedProcResp,
|
|
WILL_FIRE_RL_m_doStartFlush,
|
|
WILL_FIRE_RL_m_flushRqToPQ_canonicalize,
|
|
WILL_FIRE_RL_m_flushRqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_flushRqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_flushRqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_flushRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_freeQ_canonicalize,
|
|
WILL_FIRE_RL_m_freeQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_freeQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_freeQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_0_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_1_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_2_canon,
|
|
WILL_FIRE_RL_m_pendSpecBits_3_canon,
|
|
WILL_FIRE_RL_m_pendValid_0_canon,
|
|
WILL_FIRE_RL_m_pendValid_1_canon,
|
|
WILL_FIRE_RL_m_pendValid_2_canon,
|
|
WILL_FIRE_RL_m_pendValid_3_canon,
|
|
WILL_FIRE_RL_m_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_m_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_m_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_m_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep,
|
|
WILL_FIRE_RL_m_tlb_m_incRandIdx,
|
|
WILL_FIRE_RL_m_tlb_m_lruBit_canon,
|
|
WILL_FIRE_RL_m_tlb_m_updRepIdx_canon,
|
|
WILL_FIRE_deqProcResp,
|
|
WILL_FIRE_flush,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_procReq,
|
|
WILL_FIRE_specUpdate_correctSpeculation,
|
|
WILL_FIRE_specUpdate_incorrectSpeculation,
|
|
WILL_FIRE_toParent_flush_request_get,
|
|
WILL_FIRE_toParent_flush_response_put,
|
|
WILL_FIRE_toParent_ldTransRsFromP_enq,
|
|
WILL_FIRE_toParent_rqToP_deq,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [69 : 0] MUX_m_pendResp_0$write_1__VAL_1,
|
|
MUX_m_pendResp_0$write_1__VAL_2,
|
|
MUX_m_pendResp_1$write_1__VAL_1,
|
|
MUX_m_pendResp_1$write_1__VAL_2,
|
|
MUX_m_pendResp_2$write_1__VAL_1,
|
|
MUX_m_pendResp_2$write_1__VAL_2,
|
|
MUX_m_pendResp_3$write_1__VAL_1,
|
|
MUX_m_pendResp_3$write_1__VAL_2;
|
|
wire [31 : 0] MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [5 : 0] MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire [3 : 0] MUX_m_pendWait_0$write_1__VAL_1,
|
|
MUX_m_pendWait_1$write_1__VAL_1,
|
|
MUX_m_pendWait_2$write_1__VAL_1,
|
|
MUX_m_pendWait_3$write_1__VAL_1;
|
|
wire [2 : 0] MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2,
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3;
|
|
wire MUX_m_pendPoisoned_0$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_0$write_1__SEL_2,
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_1$write_1__SEL_2,
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_2$write_1__SEL_2,
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1,
|
|
MUX_m_pendPoisoned_3$write_1__SEL_2,
|
|
MUX_m_pendResp_0$write_1__SEL_1,
|
|
MUX_m_pendResp_1$write_1__SEL_1,
|
|
MUX_m_pendResp_2$write_1__SEL_1,
|
|
MUX_m_pendResp_3$write_1__SEL_1,
|
|
MUX_m_pendWait_0$write_1__SEL_1,
|
|
MUX_m_pendWait_1$write_1__SEL_1,
|
|
MUX_m_pendWait_2$write_1__SEL_1,
|
|
MUX_m_pendWait_3$write_1__SEL_1,
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_0$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_1$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_10$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_11$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_12$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_13$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_14$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_15$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_16$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_17$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_18$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_19$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_2$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_20$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_21$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_22$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_23$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_24$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_25$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_26$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_27$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_28$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_29$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_3$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_30$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_31$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_4$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_5$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_6$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_7$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_8$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_9$write_1__SEL_1,
|
|
MUX_m_waitFlushP$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [65 : 0] SEL_ARR_m_pendInst_0_84_BITS_440_TO_375_705_m__ETC___d3115,
|
|
x__h70397;
|
|
reg [64 : 0] x__h104309, x__h104336;
|
|
reg [63 : 0] x__h104272, x__h104327, x__h94088;
|
|
reg [55 : 0] x__h70310, x__h91666;
|
|
reg [43 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650,
|
|
ppn__h91662;
|
|
reg [26 : 0] CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3,
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11,
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12,
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13,
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14,
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15,
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16,
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17,
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18,
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19,
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20,
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1,
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21,
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22,
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23,
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24,
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25,
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26,
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27,
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28,
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29,
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30,
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q2,
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31,
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32,
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4,
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5,
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6,
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7,
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8,
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9,
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697,
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_28_TO_2_738_m_ETC___d3746;
|
|
reg [17 : 0] SEL_ARR_m_pendInst_0_84_BITS_341_TO_324_218_m__ETC___d3223;
|
|
reg [13 : 0] SEL_ARR_m_pendInst_0_84_BITS_374_TO_361_116_m__ETC___d3121,
|
|
x__h100777,
|
|
x__h100786;
|
|
reg [11 : 0] SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3722;
|
|
reg [5 : 0] SEL_ARR_m_pendInst_0_84_BITS_135_TO_130_689_m__ETC___d3694,
|
|
SEL_ARR_m_pendInst_0_84_BITS_276_TO_271_309_m__ETC___d3314,
|
|
SEL_ARR_m_pendInst_0_84_BITS_322_TO_317_230_m__ETC___d3235,
|
|
SEL_ARR_m_pendInst_0_84_BITS_469_TO_464_973_m__ETC___d2978;
|
|
reg [4 : 0] CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q37,
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361,
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409,
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457,
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505,
|
|
SEL_ARR_m_pendInst_0_84_BITS_462_TO_458_991_m__ETC___d2996,
|
|
SEL_ARR_m_pendInst_0_84_BITS_474_TO_470_967_m__ETC___d2972;
|
|
reg [3 : 0] SEL_ARR_m_pendInst_0_84_BITS_360_TO_357_122_m__ETC___d3127,
|
|
SEL_ARR_m_pendInst_0_84_BITS_461_TO_458_997_m__ETC___d3002;
|
|
reg [2 : 0] SEL_ARR_m_pendInst_0_84_BITS_288_TO_286_253_m__ETC___d3258,
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d2960,
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593;
|
|
reg [1 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577,
|
|
SEL_ARR_m_pendInst_0_84_BITS_280_TO_279_283_m__ETC___d3288,
|
|
SEL_ARR_m_pendInst_0_84_BITS_282_TO_281_277_m__ETC___d3282,
|
|
SEL_ARR_m_pendInst_0_84_BITS_343_TO_342_212_m__ETC___d3217,
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_1_TO_0_747_m__ETC___d3752,
|
|
idx__h73988,
|
|
level__h38292,
|
|
level__h86706;
|
|
reg CASE_IF_m_respForOtherReq_69_BIT_2_70_THEN_m_r_ETC___d1260,
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33,
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34,
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3508,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3514,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3520,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3526,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3532,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3538,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3544,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3550,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3556,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3562,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3568,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3574,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3580,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3586,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3592,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3598,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3604,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3610,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3616,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3622,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3628,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3634,
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3640,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d607,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d615,
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_265_666_667_NO_ETC___d3675,
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_277_298_299_NO_ETC___d3307,
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989,
|
|
SEL_ARR_NOT_m_pendResp_0_827_BIT_5_845_846_NOT_ETC___d2854,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_17_m_ETC___d675,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708,
|
|
SEL_ARR_m_pendInst_0_84_BIT_0_707_m_pendInst_1_ETC___d3712,
|
|
SEL_ARR_m_pendInst_0_84_BIT_278_292_m_pendInst_ETC___d3297,
|
|
SEL_ARR_m_pendInst_0_84_BIT_283_271_m_pendInst_ETC___d3276,
|
|
SEL_ARR_m_pendInst_0_84_BIT_284_265_m_pendInst_ETC___d3270,
|
|
SEL_ARR_m_pendInst_0_84_BIT_285_259_m_pendInst_ETC___d3264,
|
|
SEL_ARR_m_pendInst_0_84_BIT_323_224_m_pendInst_ETC___d3229,
|
|
SEL_ARR_m_pendInst_0_84_BIT_344_206_m_pendInst_ETC___d3211,
|
|
SEL_ARR_m_pendInst_0_84_BIT_345_194_m_pendInst_ETC___d3199,
|
|
SEL_ARR_m_pendInst_0_84_BIT_346_188_m_pendInst_ETC___d3193,
|
|
SEL_ARR_m_pendInst_0_84_BIT_347_182_m_pendInst_ETC___d3187,
|
|
SEL_ARR_m_pendInst_0_84_BIT_348_176_m_pendInst_ETC___d3181,
|
|
SEL_ARR_m_pendInst_0_84_BIT_349_170_m_pendInst_ETC___d3175,
|
|
SEL_ARR_m_pendInst_0_84_BIT_350_164_m_pendInst_ETC___d3169,
|
|
SEL_ARR_m_pendInst_0_84_BIT_351_158_m_pendInst_ETC___d3163,
|
|
SEL_ARR_m_pendInst_0_84_BIT_352_152_m_pendInst_ETC___d3157,
|
|
SEL_ARR_m_pendInst_0_84_BIT_353_146_m_pendInst_ETC___d3151,
|
|
SEL_ARR_m_pendInst_0_84_BIT_354_140_m_pendInst_ETC___d3145,
|
|
SEL_ARR_m_pendInst_0_84_BIT_355_134_m_pendInst_ETC___d3139,
|
|
SEL_ARR_m_pendInst_0_84_BIT_356_128_m_pendInst_ETC___d3133,
|
|
SEL_ARR_m_pendInst_0_84_BIT_441_109_m_pendInst_ETC___d3114,
|
|
SEL_ARR_m_pendInst_0_84_BIT_442_102_m_pendInst_ETC___d3107,
|
|
SEL_ARR_m_pendInst_0_84_BIT_443_096_m_pendInst_ETC___d3101,
|
|
SEL_ARR_m_pendInst_0_84_BIT_444_089_m_pendInst_ETC___d3094,
|
|
SEL_ARR_m_pendInst_0_84_BIT_445_083_m_pendInst_ETC___d3088,
|
|
SEL_ARR_m_pendInst_0_84_BIT_446_076_m_pendInst_ETC___d3081,
|
|
SEL_ARR_m_pendInst_0_84_BIT_447_070_m_pendInst_ETC___d3075,
|
|
SEL_ARR_m_pendInst_0_84_BIT_448_063_m_pendInst_ETC___d3068,
|
|
SEL_ARR_m_pendInst_0_84_BIT_449_057_m_pendInst_ETC___d3062,
|
|
SEL_ARR_m_pendInst_0_84_BIT_450_050_m_pendInst_ETC___d3055,
|
|
SEL_ARR_m_pendInst_0_84_BIT_451_044_m_pendInst_ETC___d3049,
|
|
SEL_ARR_m_pendInst_0_84_BIT_452_037_m_pendInst_ETC___d3042,
|
|
SEL_ARR_m_pendInst_0_84_BIT_453_031_m_pendInst_ETC___d3036,
|
|
SEL_ARR_m_pendInst_0_84_BIT_454_024_m_pendInst_ETC___d3029,
|
|
SEL_ARR_m_pendInst_0_84_BIT_455_018_m_pendInst_ETC___d3023,
|
|
SEL_ARR_m_pendInst_0_84_BIT_456_011_m_pendInst_ETC___d3016,
|
|
SEL_ARR_m_pendInst_0_84_BIT_457_005_m_pendInst_ETC___d3010,
|
|
SEL_ARR_m_pendInst_0_84_BIT_475_961_m_pendInst_ETC___d2966,
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_0__ETC___d2865,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_11_ETC___d2925,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_12_ETC___d2931,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_13_ETC___d2937,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_15_ETC___d2943,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_1__ETC___d2871,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_2__ETC___d2877,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_3__ETC___d2883,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_4__ETC___d2889,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_5__ETC___d2895,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_6__ETC___d2901,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_7__ETC___d2907,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_8__ETC___d2913,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_9__ETC___d2919,
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700,
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691,
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572,
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608;
|
|
wire [463 : 0] NOT_SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_98_ETC___d3719;
|
|
wire [69 : 0] DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1767,
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2766;
|
|
wire [63 : 0] x__h70301, x__h91657;
|
|
wire [31 : 0] INV_n__read0928__q35,
|
|
n__read__h50928,
|
|
upd__h50955,
|
|
val__h5329,
|
|
x__h5387;
|
|
wire [11 : 0] n__read__h106143,
|
|
n__read__h106274,
|
|
n__read__h106405,
|
|
n__read__h106536,
|
|
upd__h10027,
|
|
upd__h8992,
|
|
upd__h9337,
|
|
upd__h9682;
|
|
wire [8 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_10_02__ETC___d1699;
|
|
wire [5 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_9_10_m_ETC___d1698;
|
|
wire [4 : 0] IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2372,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2374,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2376,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2378,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2380,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2382,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2384,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2386,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2388,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2390,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2392,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2394,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2396,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2398,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2400,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3643,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3645,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3647,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3649,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3651,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3653,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3655,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3657,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3659,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3661,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3663,
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2946,
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2948,
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2950,
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2952,
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2954,
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2956,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27,
|
|
IF_m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec__ETC___d1420,
|
|
IF_m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec__ETC___d1421,
|
|
IF_m_tlb_m_validVec_12_90_AND_m_tlb_m_validVec_ETC___d1410,
|
|
IF_m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_ETC___d1405,
|
|
IF_m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_ETC___d1406,
|
|
IF_m_tlb_m_validVec_20_018_AND_m_tlb_m_validVe_ETC___d1402,
|
|
IF_m_tlb_m_validVec_24_082_AND_m_tlb_m_validVe_ETC___d1398,
|
|
IF_m_tlb_m_validVec_24_082_AND_m_tlb_m_validVe_ETC___d1399,
|
|
IF_m_tlb_m_validVec_28_146_AND_m_tlb_m_validVe_ETC___d1395,
|
|
IF_m_tlb_m_validVec_4_62_AND_m_tlb_m_validVec__ETC___d1417,
|
|
IF_m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec__ETC___d1413,
|
|
IF_m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec__ETC___d1414,
|
|
addIdx__h55557,
|
|
addIdx__h60407,
|
|
idx__h86667,
|
|
v__h45375,
|
|
v__h50192,
|
|
v__h51720;
|
|
wire [3 : 0] _2_CONCAT_IF_NOT_m_pendWait_0_264_BITS_3_TO_2_2_ETC___d2799,
|
|
_dfoo26,
|
|
_dfoo28,
|
|
_dfoo30,
|
|
_dfoo32;
|
|
wire [1 : 0] IF_NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_2_ETC___d2797,
|
|
IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1801,
|
|
_theResult_____2__h13508,
|
|
_theResult_____2__h17468,
|
|
idx__h37917,
|
|
idx__h73600,
|
|
idx__h94435,
|
|
next_deqP___1__h13697,
|
|
next_deqP___1__h17657,
|
|
v__h13028,
|
|
v__h13179,
|
|
v__h16896,
|
|
v__h17047,
|
|
x_id__h21371;
|
|
wire IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2697,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2705,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2747,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2754,
|
|
IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2694,
|
|
IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2702,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172,
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357,
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d1261,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d1760,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d684,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1831,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1832,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1833,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3727,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3728,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3729,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2266,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2267,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2268,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2269,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2270,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2271,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2272,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2273,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2274,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2275,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2276,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2277,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2278,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2279,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2280,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2281,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2282,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2283,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2284,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2285,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2286,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2287,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2288,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2289,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2290,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2291,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2292,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2293,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2294,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2295,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_ldTra_ETC___d1258,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1629,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1631,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1633,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1635,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1637,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1639,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1641,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1643,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1645,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1647,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1649,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1651,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1653,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1655,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1657,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1659,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1661,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1663,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1665,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1667,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1669,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1671,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1673,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1675,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1677,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1679,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1681,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1683,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1685,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1687,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1689,
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1691,
|
|
IF_NOT_m_tlb_m_validVec_10_58_59_OR_NOT_m_tlb__ETC___d1238,
|
|
IF_NOT_m_tlb_m_validVec_11_74_75_OR_NOT_m_tlb__ETC___d1236,
|
|
IF_NOT_m_tlb_m_validVec_12_90_91_OR_NOT_m_tlb__ETC___d1234,
|
|
IF_NOT_m_tlb_m_validVec_13_06_07_OR_NOT_m_tlb__ETC___d1232,
|
|
IF_NOT_m_tlb_m_validVec_14_22_23_OR_NOT_m_tlb__ETC___d1230,
|
|
IF_NOT_m_tlb_m_validVec_15_38_39_OR_NOT_m_tlb__ETC___d1228,
|
|
IF_NOT_m_tlb_m_validVec_16_54_55_OR_NOT_m_tlb__ETC___d1226,
|
|
IF_NOT_m_tlb_m_validVec_17_70_71_OR_NOT_m_tlb__ETC___d1224,
|
|
IF_NOT_m_tlb_m_validVec_18_86_87_OR_NOT_m_tlb__ETC___d1222,
|
|
IF_NOT_m_tlb_m_validVec_19_002_003_OR_NOT_m_tl_ETC___d1220,
|
|
IF_NOT_m_tlb_m_validVec_1_14_15_OR_NOT_m_tlb_m_ETC___d1256,
|
|
IF_NOT_m_tlb_m_validVec_20_018_019_OR_NOT_m_tl_ETC___d1218,
|
|
IF_NOT_m_tlb_m_validVec_21_034_035_OR_NOT_m_tl_ETC___d1216,
|
|
IF_NOT_m_tlb_m_validVec_22_050_051_OR_NOT_m_tl_ETC___d1214,
|
|
IF_NOT_m_tlb_m_validVec_23_066_067_OR_NOT_m_tl_ETC___d1212,
|
|
IF_NOT_m_tlb_m_validVec_24_082_083_OR_NOT_m_tl_ETC___d1210,
|
|
IF_NOT_m_tlb_m_validVec_25_098_099_OR_NOT_m_tl_ETC___d1208,
|
|
IF_NOT_m_tlb_m_validVec_26_114_115_OR_NOT_m_tl_ETC___d1206,
|
|
IF_NOT_m_tlb_m_validVec_27_130_131_OR_NOT_m_tl_ETC___d1204,
|
|
IF_NOT_m_tlb_m_validVec_28_146_147_OR_NOT_m_tl_ETC___d1202,
|
|
IF_NOT_m_tlb_m_validVec_29_162_163_OR_NOT_m_tl_ETC___d1200,
|
|
IF_NOT_m_tlb_m_validVec_2_30_31_OR_NOT_m_tlb_m_ETC___d1254,
|
|
IF_NOT_m_tlb_m_validVec_30_178_179_OR_NOT_m_tl_ETC___d1198,
|
|
IF_NOT_m_tlb_m_validVec_3_46_47_OR_NOT_m_tlb_m_ETC___d1252,
|
|
IF_NOT_m_tlb_m_validVec_4_62_63_OR_NOT_m_tlb_m_ETC___d1250,
|
|
IF_NOT_m_tlb_m_validVec_5_78_79_OR_NOT_m_tlb_m_ETC___d1248,
|
|
IF_NOT_m_tlb_m_validVec_6_94_95_OR_NOT_m_tlb_m_ETC___d1246,
|
|
IF_NOT_m_tlb_m_validVec_7_10_11_OR_NOT_m_tlb_m_ETC___d1244,
|
|
IF_NOT_m_tlb_m_validVec_8_26_27_OR_NOT_m_tlb_m_ETC___d1242,
|
|
IF_NOT_m_tlb_m_validVec_9_42_43_OR_NOT_m_tlb_m_ETC___d1240,
|
|
IF_NOT_procReq_req_BITS_490_TO_488_297_EQ_1_29_ETC___d2707,
|
|
IF_NOT_procReq_req_BITS_490_TO_488_297_EQ_1_29_ETC___d2756,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1750,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1758,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d672,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d682,
|
|
IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134,
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108,
|
|
IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333,
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284,
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291,
|
|
IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1315,
|
|
IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1332,
|
|
IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1704,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1724,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1725,
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1727,
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222,
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196,
|
|
IF_m_tlb_m_entryVec_10_61_BITS_1_TO_0_65_EQ_0__ETC___d2024,
|
|
IF_m_tlb_m_entryVec_11_77_BITS_1_TO_0_81_EQ_0__ETC___d2034,
|
|
IF_m_tlb_m_entryVec_12_93_BITS_1_TO_0_97_EQ_0__ETC___d2044,
|
|
IF_m_tlb_m_entryVec_13_09_BITS_1_TO_0_13_EQ_0__ETC___d2054,
|
|
IF_m_tlb_m_entryVec_14_25_BITS_1_TO_0_29_EQ_0__ETC___d2064,
|
|
IF_m_tlb_m_entryVec_15_41_BITS_1_TO_0_45_EQ_0__ETC___d2074,
|
|
IF_m_tlb_m_entryVec_16_57_BITS_1_TO_0_61_EQ_0__ETC___d2084,
|
|
IF_m_tlb_m_entryVec_17_73_BITS_1_TO_0_77_EQ_0__ETC___d2094,
|
|
IF_m_tlb_m_entryVec_18_89_BITS_1_TO_0_93_EQ_0__ETC___d2104,
|
|
IF_m_tlb_m_entryVec_19_005_BITS_1_TO_0_009_EQ__ETC___d2114,
|
|
IF_m_tlb_m_entryVec_1_17_BITS_1_TO_0_21_EQ_0_9_ETC___d1934,
|
|
IF_m_tlb_m_entryVec_20_021_BITS_1_TO_0_025_EQ__ETC___d2124,
|
|
IF_m_tlb_m_entryVec_21_037_BITS_1_TO_0_041_EQ__ETC___d2134,
|
|
IF_m_tlb_m_entryVec_22_053_BITS_1_TO_0_057_EQ__ETC___d2144,
|
|
IF_m_tlb_m_entryVec_23_069_BITS_1_TO_0_073_EQ__ETC___d2154,
|
|
IF_m_tlb_m_entryVec_24_085_BITS_1_TO_0_089_EQ__ETC___d2164,
|
|
IF_m_tlb_m_entryVec_25_101_BITS_1_TO_0_105_EQ__ETC___d2174,
|
|
IF_m_tlb_m_entryVec_26_117_BITS_1_TO_0_121_EQ__ETC___d2184,
|
|
IF_m_tlb_m_entryVec_27_133_BITS_1_TO_0_137_EQ__ETC___d2194,
|
|
IF_m_tlb_m_entryVec_28_149_BITS_1_TO_0_153_EQ__ETC___d2204,
|
|
IF_m_tlb_m_entryVec_29_165_BITS_1_TO_0_169_EQ__ETC___d2214,
|
|
IF_m_tlb_m_entryVec_2_33_BITS_1_TO_0_37_EQ_0_9_ETC___d1944,
|
|
IF_m_tlb_m_entryVec_30_181_BITS_1_TO_0_185_EQ__ETC___d2224,
|
|
IF_m_tlb_m_entryVec_31_582_BITS_1_TO_0_586_EQ__ETC___d2234,
|
|
IF_m_tlb_m_entryVec_3_49_BITS_1_TO_0_53_EQ_0_9_ETC___d1954,
|
|
IF_m_tlb_m_entryVec_4_65_BITS_1_TO_0_69_EQ_0_9_ETC___d1964,
|
|
IF_m_tlb_m_entryVec_5_81_BITS_1_TO_0_85_EQ_0_9_ETC___d1974,
|
|
IF_m_tlb_m_entryVec_6_97_BITS_1_TO_0_01_EQ_0_9_ETC___d1984,
|
|
IF_m_tlb_m_entryVec_7_13_BITS_1_TO_0_17_EQ_0_9_ETC___d1994,
|
|
IF_m_tlb_m_entryVec_8_29_BITS_1_TO_0_33_EQ_0_9_ETC___d2004,
|
|
IF_m_tlb_m_entryVec_9_45_BITS_1_TO_0_49_EQ_0_0_ETC___d2014,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17,
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2744,
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2751,
|
|
NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BI_ETC___d673,
|
|
NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_47_ETC___d2698,
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1747,
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1755,
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626,
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686,
|
|
NOT_m_ldTransRsFromPQ_empty_68_90_AND_NOT_m_pe_ETC___d1313,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1820,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1824,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2838,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2840,
|
|
NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266__ETC___d1784,
|
|
NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266__ETC___d1798,
|
|
NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267__ETC___d2795,
|
|
NOT_m_tlb_m_entryVec_0_92_BITS_79_TO_53_93_EQ__ETC___d711,
|
|
NOT_m_tlb_m_entryVec_10_61_BITS_79_TO_53_62_EQ_ETC___d872,
|
|
NOT_m_tlb_m_entryVec_11_77_BITS_79_TO_53_78_EQ_ETC___d888,
|
|
NOT_m_tlb_m_entryVec_12_93_BITS_79_TO_53_94_EQ_ETC___d904,
|
|
NOT_m_tlb_m_entryVec_13_09_BITS_79_TO_53_10_EQ_ETC___d920,
|
|
NOT_m_tlb_m_entryVec_14_25_BITS_79_TO_53_26_EQ_ETC___d936,
|
|
NOT_m_tlb_m_entryVec_15_41_BITS_79_TO_53_42_EQ_ETC___d952,
|
|
NOT_m_tlb_m_entryVec_16_57_BITS_79_TO_53_58_EQ_ETC___d968,
|
|
NOT_m_tlb_m_entryVec_17_73_BITS_79_TO_53_74_EQ_ETC___d984,
|
|
NOT_m_tlb_m_entryVec_18_89_BITS_79_TO_53_90_EQ_ETC___d1000,
|
|
NOT_m_tlb_m_entryVec_19_005_BITS_79_TO_53_006__ETC___d1016,
|
|
NOT_m_tlb_m_entryVec_1_17_BITS_79_TO_53_18_EQ__ETC___d728,
|
|
NOT_m_tlb_m_entryVec_20_021_BITS_79_TO_53_022__ETC___d1032,
|
|
NOT_m_tlb_m_entryVec_21_037_BITS_79_TO_53_038__ETC___d1048,
|
|
NOT_m_tlb_m_entryVec_22_053_BITS_79_TO_53_054__ETC___d1064,
|
|
NOT_m_tlb_m_entryVec_23_069_BITS_79_TO_53_070__ETC___d1080,
|
|
NOT_m_tlb_m_entryVec_24_085_BITS_79_TO_53_086__ETC___d1096,
|
|
NOT_m_tlb_m_entryVec_25_101_BITS_79_TO_53_102__ETC___d1112,
|
|
NOT_m_tlb_m_entryVec_26_117_BITS_79_TO_53_118__ETC___d1128,
|
|
NOT_m_tlb_m_entryVec_27_133_BITS_79_TO_53_134__ETC___d1144,
|
|
NOT_m_tlb_m_entryVec_28_149_BITS_79_TO_53_150__ETC___d1160,
|
|
NOT_m_tlb_m_entryVec_29_165_BITS_79_TO_53_166__ETC___d1176,
|
|
NOT_m_tlb_m_entryVec_2_33_BITS_79_TO_53_34_EQ__ETC___d744,
|
|
NOT_m_tlb_m_entryVec_30_181_BITS_79_TO_53_182__ETC___d1192,
|
|
NOT_m_tlb_m_entryVec_3_49_BITS_79_TO_53_50_EQ__ETC___d760,
|
|
NOT_m_tlb_m_entryVec_4_65_BITS_79_TO_53_66_EQ__ETC___d776,
|
|
NOT_m_tlb_m_entryVec_5_81_BITS_79_TO_53_82_EQ__ETC___d792,
|
|
NOT_m_tlb_m_entryVec_6_97_BITS_79_TO_53_98_EQ__ETC___d808,
|
|
NOT_m_tlb_m_entryVec_7_13_BITS_79_TO_53_14_EQ__ETC___d824,
|
|
NOT_m_tlb_m_entryVec_8_29_BITS_79_TO_53_30_EQ__ETC___d840,
|
|
NOT_m_tlb_m_entryVec_9_45_BITS_79_TO_53_46_EQ__ETC___d856,
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d687,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2227,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806,
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_va_ETC___d1342,
|
|
NOT_m_tlb_m_validVec_11_74_75_OR_NOT_m_tlb_m_e_ETC___d1614,
|
|
NOT_m_tlb_m_validVec_13_06_07_OR_NOT_m_tlb_m_e_ETC___d1612,
|
|
NOT_m_tlb_m_validVec_15_38_39_OR_NOT_m_tlb_m_e_ETC___d1610,
|
|
NOT_m_tlb_m_validVec_16_54_55_OR_NOT_m_tlb_m_v_ETC___d1357,
|
|
NOT_m_tlb_m_validVec_17_70_71_OR_NOT_m_tlb_m_e_ETC___d1608,
|
|
NOT_m_tlb_m_validVec_19_002_003_OR_NOT_m_tlb_m_ETC___d1606,
|
|
NOT_m_tlb_m_validVec_1_14_15_OR_NOT_m_tlb_m_en_ETC___d1624,
|
|
NOT_m_tlb_m_validVec_21_034_035_OR_NOT_m_tlb_m_ETC___d1604,
|
|
NOT_m_tlb_m_validVec_23_066_067_OR_NOT_m_tlb_m_ETC___d1602,
|
|
NOT_m_tlb_m_validVec_24_082_083_OR_NOT_m_tlb_m_ETC___d1364,
|
|
NOT_m_tlb_m_validVec_25_098_099_OR_NOT_m_tlb_m_ETC___d1600,
|
|
NOT_m_tlb_m_validVec_27_130_131_OR_NOT_m_tlb_m_ETC___d1598,
|
|
NOT_m_tlb_m_validVec_29_162_163_OR_NOT_m_tlb_m_ETC___d1596,
|
|
NOT_m_tlb_m_validVec_3_46_47_OR_NOT_m_tlb_m_en_ETC___d1622,
|
|
NOT_m_tlb_m_validVec_5_78_79_OR_NOT_m_tlb_m_en_ETC___d1620,
|
|
NOT_m_tlb_m_validVec_7_10_11_OR_NOT_m_tlb_m_en_ETC___d1618,
|
|
NOT_m_tlb_m_validVec_8_26_27_OR_NOT_m_tlb_m_va_ETC___d1349,
|
|
NOT_m_tlb_m_validVec_9_42_43_OR_NOT_m_tlb_m_en_ETC___d1616,
|
|
NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d1751,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2748,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2713,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2714,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2715,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2716,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2761,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2762,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2763,
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2764,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d667,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d679,
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d1762,
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d1263,
|
|
_dfoo1,
|
|
_dfoo11,
|
|
_dfoo13,
|
|
_dfoo15,
|
|
_dfoo25,
|
|
_dfoo27,
|
|
_dfoo29,
|
|
_dfoo3,
|
|
_dfoo31,
|
|
_dfoo49,
|
|
_dfoo5,
|
|
_dfoo51,
|
|
_dfoo53,
|
|
_dfoo55,
|
|
_dfoo57,
|
|
_dfoo59,
|
|
_dfoo61,
|
|
_dfoo63,
|
|
_dfoo7,
|
|
_dfoo9,
|
|
_theResult_____2__h22136,
|
|
m_pendWait_0_264_BITS_1_TO_0_284_EQ_SEL_ARR_m__ETC___d1285,
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1283,
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1292,
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1318,
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267_AND__ETC___d2780,
|
|
m_pendWait_1_270_BITS_1_TO_0_276_EQ_SEL_ARR_m__ETC___d1277,
|
|
m_pendWait_1_270_BITS_3_TO_2_271_EQ_0_272_OR_m_ETC___d1281,
|
|
m_pendWait_2_294_BITS_1_TO_0_300_EQ_SEL_ARR_m__ETC___d1301,
|
|
m_pendWait_3_320_BITS_1_TO_0_326_EQ_SEL_ARR_m__ETC___d1327,
|
|
m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec_1_1_ETC___d1373,
|
|
m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_17_ETC___d1388,
|
|
m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec_9_4_ETC___d1380,
|
|
next_deqP___1__h22325,
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2771,
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2774,
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2778,
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2782,
|
|
procReq_req_BITS_490_TO_488_297_EQ_1_298_OR_pr_ETC___d2758,
|
|
v__h21066,
|
|
v__h21217;
|
|
|
|
// value method flush_done
|
|
assign flush_done = !m_needFlush ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = !m_needFlush ;
|
|
assign CAN_FIRE_flush = !m_needFlush ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// value method noPendingReq
|
|
assign noPendingReq =
|
|
!m_pendValid_0_rl && !m_pendValid_1_rl && !m_pendValid_2_rl &&
|
|
!m_pendValid_3_rl ;
|
|
assign RDY_noPendingReq = 1'd1 ;
|
|
|
|
// action method procReq
|
|
assign RDY_procReq =
|
|
!m_freeQ_empty && !m_needFlush && m_ldTransRsFromPQ_empty &&
|
|
!m_rqToPQ_full &&
|
|
m_freeQInited &&
|
|
(!m_vm_info[46] ||
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d687) ;
|
|
assign CAN_FIRE_procReq = RDY_procReq ;
|
|
assign WILL_FIRE_procReq = EN_procReq ;
|
|
|
|
// value method procResp
|
|
assign procResp =
|
|
{ x__h94088,
|
|
!SEL_ARR_NOT_m_pendResp_0_827_BIT_5_845_846_NOT_ETC___d2854,
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_0__ETC___d2865 ?
|
|
5'd0 :
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2956,
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d2960,
|
|
SEL_ARR_m_pendInst_0_84_BIT_475_961_m_pendInst_ETC___d2966,
|
|
SEL_ARR_m_pendInst_0_84_BITS_474_TO_470_967_m__ETC___d2972,
|
|
SEL_ARR_m_pendInst_0_84_BITS_469_TO_464_973_m__ETC___d2978,
|
|
NOT_SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_98_ETC___d3719,
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3722 } ;
|
|
assign RDY_procResp =
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3729 &&
|
|
m_freeQInited ;
|
|
|
|
// action method deqProcResp
|
|
assign RDY_deqProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3729 &&
|
|
m_freeQInited ;
|
|
assign CAN_FIRE_deqProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3729 &&
|
|
m_freeQInited ;
|
|
assign WILL_FIRE_deqProcResp = EN_deqProcResp ;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
assign toParent_rqToP_notEmpty = !m_rqToPQ_empty ;
|
|
assign RDY_toParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method toParent_rqToP_deq
|
|
assign RDY_toParent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_rqToP_deq = EN_toParent_rqToP_deq ;
|
|
|
|
// value method toParent_rqToP_first
|
|
assign toParent_rqToP_first =
|
|
{ SEL_ARR_m_rqToPQ_data_0_737_BITS_28_TO_2_738_m_ETC___d3746,
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_1_TO_0_747_m__ETC___d3752 } ;
|
|
assign RDY_toParent_rqToP_first = !m_rqToPQ_empty ;
|
|
|
|
// value method toParent_ldTransRsFromP_notFull
|
|
assign toParent_ldTransRsFromP_notFull = !m_ldTransRsFromPQ_full ;
|
|
assign RDY_toParent_ldTransRsFromP_notFull = 1'd1 ;
|
|
|
|
// action method toParent_ldTransRsFromP_enq
|
|
assign RDY_toParent_ldTransRsFromP_enq = !m_ldTransRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_ldTransRsFromP_enq = !m_ldTransRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_ldTransRsFromP_enq =
|
|
EN_toParent_ldTransRsFromP_enq ;
|
|
|
|
// action method toParent_flush_request_get
|
|
assign RDY_toParent_flush_request_get = !m_flushRqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_flush_request_get = !m_flushRqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_flush_request_get =
|
|
EN_toParent_flush_request_get ;
|
|
|
|
// action method toParent_flush_response_put
|
|
assign RDY_toParent_flush_response_put = !m_flushRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_flush_response_put = !m_flushRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_flush_response_put =
|
|
EN_toParent_flush_response_put ;
|
|
|
|
// action method specUpdate_incorrectSpeculation
|
|
assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_incorrectSpeculation =
|
|
EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// action method specUpdate_correctSpeculation
|
|
assign RDY_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_correctSpeculation =
|
|
EN_specUpdate_correctSpeculation ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !m_perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !m_perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { m_perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !m_perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !m_perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !m_perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// rule RL_m_doStartFlush
|
|
assign CAN_FIRE_RL_m_doStartFlush =
|
|
!m_flushRqToPQ_full && m_needFlush && !m_waitFlushP &&
|
|
!m_pendValid_0_rl &&
|
|
!m_pendValid_1_rl &&
|
|
!m_pendValid_2_rl &&
|
|
!m_pendValid_3_rl ;
|
|
assign WILL_FIRE_RL_m_doStartFlush = CAN_FIRE_RL_m_doStartFlush ;
|
|
|
|
// rule RL_m_doFinishFlush
|
|
assign CAN_FIRE_RL_m_doFinishFlush =
|
|
!m_flushRsFromPQ_empty && m_needFlush && m_waitFlushP ;
|
|
assign WILL_FIRE_RL_m_doFinishFlush = CAN_FIRE_RL_m_doFinishFlush ;
|
|
|
|
// rule RL_m_doInitFreeQ
|
|
assign CAN_FIRE_RL_m_doInitFreeQ = !m_freeQ_full && !m_freeQInited ;
|
|
assign WILL_FIRE_RL_m_doInitFreeQ = CAN_FIRE_RL_m_doInitFreeQ ;
|
|
|
|
// rule RL_m_doPoisonedProcResp
|
|
assign CAN_FIRE_RL_m_doPoisonedProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1833 &&
|
|
m_freeQInited ;
|
|
assign WILL_FIRE_RL_m_doPoisonedProcResp =
|
|
CAN_FIRE_RL_m_doPoisonedProcResp &&
|
|
!EN_specUpdate_incorrectSpeculation &&
|
|
!EN_deqProcResp ;
|
|
|
|
// rule RL_m_tlb_m_doUpdateRep
|
|
assign CAN_FIRE_RL_m_tlb_m_doUpdateRep =
|
|
!CAN_FIRE_RL_m_doStartFlush && m_tlb_m_updRepIdx_rl[5] ;
|
|
assign WILL_FIRE_RL_m_tlb_m_doUpdateRep =
|
|
CAN_FIRE_RL_m_tlb_m_doUpdateRep && !WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// rule RL_m_doPRs
|
|
assign CAN_FIRE_RL_m_doPRs =
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d1263 &&
|
|
IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1315 &&
|
|
IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1332 &&
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign WILL_FIRE_RL_m_doPRs =
|
|
CAN_FIRE_RL_m_doPRs && !WILL_FIRE_RL_m_doStartFlush &&
|
|
!EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// rule RL_m_tlb_m_incRandIdx
|
|
assign CAN_FIRE_RL_m_tlb_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_m_tlb_m_lruBit_canon
|
|
assign CAN_FIRE_RL_m_tlb_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_m_tlb_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_m_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_0_canon
|
|
assign CAN_FIRE_RL_m_pendValid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_1_canon
|
|
assign CAN_FIRE_RL_m_pendValid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_2_canon
|
|
assign CAN_FIRE_RL_m_pendValid_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_3_canon
|
|
assign CAN_FIRE_RL_m_pendValid_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_0_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_1_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_2_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_3_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_canonicalize
|
|
assign CAN_FIRE_RL_m_freeQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_m_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_pendPoisoned_0$write_1__SEL_1 =
|
|
EN_procReq && idx__h73988 == 2'd0 ;
|
|
assign MUX_m_pendPoisoned_0$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_1$write_1__SEL_1 =
|
|
EN_procReq && idx__h73988 == 2'd1 ;
|
|
assign MUX_m_pendPoisoned_1$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_2$write_1__SEL_1 =
|
|
EN_procReq && idx__h73988 == 2'd2 ;
|
|
assign MUX_m_pendPoisoned_2$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_2_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_3$write_1__SEL_1 =
|
|
EN_procReq && idx__h73988 == 2'd3 ;
|
|
assign MUX_m_pendPoisoned_3$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_3_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendResp_0$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo15 ;
|
|
assign MUX_m_pendResp_1$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo13 ;
|
|
assign MUX_m_pendResp_2$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo11 ;
|
|
assign MUX_m_pendResp_3$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo9 ;
|
|
assign MUX_m_pendWait_0$write_1__SEL_1 = EN_procReq && _dfoo63 ;
|
|
assign MUX_m_pendWait_1$write_1__SEL_1 = EN_procReq && _dfoo61 ;
|
|
assign MUX_m_pendWait_2$write_1__SEL_1 = EN_procReq && _dfoo59 ;
|
|
assign MUX_m_pendWait_3$write_1__SEL_1 = EN_procReq && _dfoo57 ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign MUX_m_tlb_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1629 ;
|
|
assign MUX_m_tlb_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1631 ;
|
|
assign MUX_m_tlb_m_validVec_10$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1649 ;
|
|
assign MUX_m_tlb_m_validVec_11$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1651 ;
|
|
assign MUX_m_tlb_m_validVec_12$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1653 ;
|
|
assign MUX_m_tlb_m_validVec_13$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1655 ;
|
|
assign MUX_m_tlb_m_validVec_14$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1657 ;
|
|
assign MUX_m_tlb_m_validVec_15$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1659 ;
|
|
assign MUX_m_tlb_m_validVec_16$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1661 ;
|
|
assign MUX_m_tlb_m_validVec_17$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1663 ;
|
|
assign MUX_m_tlb_m_validVec_18$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1665 ;
|
|
assign MUX_m_tlb_m_validVec_19$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1667 ;
|
|
assign MUX_m_tlb_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1633 ;
|
|
assign MUX_m_tlb_m_validVec_20$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1669 ;
|
|
assign MUX_m_tlb_m_validVec_21$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1671 ;
|
|
assign MUX_m_tlb_m_validVec_22$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1673 ;
|
|
assign MUX_m_tlb_m_validVec_23$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1675 ;
|
|
assign MUX_m_tlb_m_validVec_24$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1677 ;
|
|
assign MUX_m_tlb_m_validVec_25$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1679 ;
|
|
assign MUX_m_tlb_m_validVec_26$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1681 ;
|
|
assign MUX_m_tlb_m_validVec_27$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1683 ;
|
|
assign MUX_m_tlb_m_validVec_28$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1685 ;
|
|
assign MUX_m_tlb_m_validVec_29$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1687 ;
|
|
assign MUX_m_tlb_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1635 ;
|
|
assign MUX_m_tlb_m_validVec_30$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1689 ;
|
|
assign MUX_m_tlb_m_validVec_31$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1691 ;
|
|
assign MUX_m_tlb_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1637 ;
|
|
assign MUX_m_tlb_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1639 ;
|
|
assign MUX_m_tlb_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1641 ;
|
|
assign MUX_m_tlb_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1643 ;
|
|
assign MUX_m_tlb_m_validVec_8$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1645 ;
|
|
assign MUX_m_tlb_m_validVec_9$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1647 ;
|
|
assign MUX_m_waitFlushP$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doFinishFlush || EN_flush ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, m_freeQInitIdx } ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, idx__h73600 } ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, idx__h94435 } ;
|
|
assign MUX_m_pendResp_0$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1704 ?
|
|
{ x__h70301, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1767 ;
|
|
assign MUX_m_pendResp_0$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2713 ?
|
|
{ x__h91657, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2761 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2766 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendResp_1$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1724 ?
|
|
{ x__h70301, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1767 ;
|
|
assign MUX_m_pendResp_1$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2714 ?
|
|
{ x__h91657, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2762 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2766 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendResp_2$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1725 ?
|
|
{ x__h70301, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1767 ;
|
|
assign MUX_m_pendResp_2$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2715 ?
|
|
{ x__h91657, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2763 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2766 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendResp_3$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1727 ?
|
|
{ x__h70301, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1767 ;
|
|
assign MUX_m_pendResp_3$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2716 ?
|
|
{ x__h91657, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2764 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2766 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendWait_0$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2713 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2761 ?
|
|
4'd2 :
|
|
_dfoo32) ;
|
|
assign MUX_m_pendWait_1$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2714 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2762 ?
|
|
4'd2 :
|
|
_dfoo30) ;
|
|
assign MUX_m_pendWait_2$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2715 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2763 ?
|
|
4'd2 :
|
|
_dfoo28) ;
|
|
assign MUX_m_pendWait_3$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2716 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2764 ?
|
|
4'd2 :
|
|
_dfoo26) ;
|
|
assign MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h5329 == 32'hFFFFFFFF) ? x__h5387 : val__h5329 ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, v__h45375 } ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, idx__h86667 } ;
|
|
|
|
// inlined wires
|
|
assign m_tlb_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep || WILL_FIRE_RL_m_doStartFlush ;
|
|
assign m_tlb_m_updRepIdx_lat_0$whas =
|
|
WILL_FIRE_RL_m_doStartFlush || WILL_FIRE_RL_m_tlb_m_doUpdateRep ;
|
|
assign m_tlb_m_updRepIdx_lat_1$wget =
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign m_tlb_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ||
|
|
EN_procReq && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709 ;
|
|
assign m_pendValid_0_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73600 == 2'd0 ||
|
|
EN_deqProcResp && idx__h94435 == 2'd0 ;
|
|
assign m_pendValid_1_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73600 == 2'd1 ||
|
|
EN_deqProcResp && idx__h94435 == 2'd1 ;
|
|
assign m_pendValid_2_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73600 == 2'd2 ||
|
|
EN_deqProcResp && idx__h94435 == 2'd2 ;
|
|
assign m_pendValid_3_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h73600 == 2'd3 ||
|
|
EN_deqProcResp && idx__h94435 == 2'd3 ;
|
|
always@(WILL_FIRE_RL_m_doInitFreeQ or
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1 or
|
|
WILL_FIRE_RL_m_doPoisonedProcResp or
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2 or
|
|
EN_deqProcResp or MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_m_doInitFreeQ:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1;
|
|
WILL_FIRE_RL_m_doPoisonedProcResp:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2;
|
|
EN_deqProcResp:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3;
|
|
default: m_freeQ_enqReq_lat_0$wget = 3'b010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign m_freeQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_doInitFreeQ ||
|
|
WILL_FIRE_RL_m_doPoisonedProcResp ||
|
|
EN_deqProcResp ;
|
|
assign m_rqToPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, procReq_req[425:399], idx__h73988 } ;
|
|
assign m_rqToPQ_enqReq_lat_0$whas =
|
|
EN_procReq && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806 ;
|
|
assign m_ldTransRsFromPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, toParent_ldTransRsFromP_enq_x } ;
|
|
assign m_ldTransRsFromPQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1318 &&
|
|
(m_pendWait_3[3:2] == 2'd0 || m_pendWait_3[3:2] == 2'd1 ||
|
|
!m_pendWait_3_320_BITS_1_TO_0_326_EQ_SEL_ARR_m__ETC___d1327 ||
|
|
idx__h37917 == 2'd3) ;
|
|
assign m_perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
|
|
// register m_flushRqToPQ_clearReq_rl
|
|
assign m_flushRqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_deqReq_rl
|
|
assign m_flushRqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_empty
|
|
assign m_flushRqToPQ_empty$D_IN =
|
|
m_flushRqToPQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_m_doStartFlush && !m_flushRqToPQ_enqReq_rl &&
|
|
(EN_toParent_flush_request_get || m_flushRqToPQ_deqReq_rl ||
|
|
m_flushRqToPQ_empty) ;
|
|
assign m_flushRqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_enqReq_rl
|
|
assign m_flushRqToPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_full
|
|
assign m_flushRqToPQ_full$D_IN =
|
|
!m_flushRqToPQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_m_doStartFlush || m_flushRqToPQ_enqReq_rl ||
|
|
!EN_toParent_flush_request_get && !m_flushRqToPQ_deqReq_rl &&
|
|
m_flushRqToPQ_full) ;
|
|
assign m_flushRqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_clearReq_rl
|
|
assign m_flushRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_deqReq_rl
|
|
assign m_flushRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_empty
|
|
assign m_flushRsFromPQ_empty$D_IN =
|
|
m_flushRsFromPQ_clearReq_rl ||
|
|
!EN_toParent_flush_response_put && !m_flushRsFromPQ_enqReq_rl &&
|
|
(CAN_FIRE_RL_m_doFinishFlush || m_flushRsFromPQ_deqReq_rl ||
|
|
m_flushRsFromPQ_empty) ;
|
|
assign m_flushRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_enqReq_rl
|
|
assign m_flushRsFromPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_full
|
|
assign m_flushRsFromPQ_full$D_IN =
|
|
!m_flushRsFromPQ_clearReq_rl &&
|
|
(EN_toParent_flush_response_put || m_flushRsFromPQ_enqReq_rl ||
|
|
!CAN_FIRE_RL_m_doFinishFlush && !m_flushRsFromPQ_deqReq_rl &&
|
|
m_flushRsFromPQ_full) ;
|
|
assign m_flushRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_freeQInitIdx
|
|
assign m_freeQInitIdx$D_IN = m_freeQInitIdx + 2'd1 ;
|
|
assign m_freeQInitIdx$EN = CAN_FIRE_RL_m_doInitFreeQ ;
|
|
|
|
// register m_freeQInited
|
|
assign m_freeQInited$D_IN = 1'd1 ;
|
|
assign m_freeQInited$EN =
|
|
WILL_FIRE_RL_m_doInitFreeQ && m_freeQInitIdx == 2'd3 ;
|
|
|
|
// register m_freeQ_clearReq_rl
|
|
assign m_freeQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_freeQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_data_0
|
|
assign m_freeQ_data_0$D_IN =
|
|
m_freeQ_enqReq_lat_0$whas ?
|
|
m_freeQ_enqReq_lat_0$wget[1:0] :
|
|
m_freeQ_enqReq_rl[1:0] ;
|
|
assign m_freeQ_data_0$EN =
|
|
m_freeQ_enqP == 2'd0 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_1
|
|
assign m_freeQ_data_1$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_1$EN =
|
|
m_freeQ_enqP == 2'd1 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_2
|
|
assign m_freeQ_data_2$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_2$EN =
|
|
m_freeQ_enqP == 2'd2 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_3
|
|
assign m_freeQ_data_3$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_3$EN =
|
|
m_freeQ_enqP == 2'd3 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_deqP
|
|
assign m_freeQ_deqP$D_IN =
|
|
m_freeQ_clearReq_rl ? 2'd0 : _theResult_____2__h13508 ;
|
|
assign m_freeQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_deqReq_rl
|
|
assign m_freeQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_freeQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_empty
|
|
assign m_freeQ_empty$D_IN =
|
|
m_freeQ_clearReq_rl ||
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172 ;
|
|
assign m_freeQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_enqP
|
|
assign m_freeQ_enqP$D_IN = m_freeQ_clearReq_rl ? 2'd0 : v__h13028 ;
|
|
assign m_freeQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_enqReq_rl
|
|
assign m_freeQ_enqReq_rl$D_IN = 3'b010 ;
|
|
assign m_freeQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_full
|
|
assign m_freeQ_full$D_IN =
|
|
!m_freeQ_clearReq_rl &&
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167 ;
|
|
assign m_freeQ_full$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_clearReq_rl
|
|
assign m_ldTransRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_ldTransRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_data_0
|
|
assign m_ldTransRsFromPQ_data_0$D_IN =
|
|
{ IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 ||
|
|
(EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[82] :
|
|
m_ldTransRsFromPQ_enqReq_rl[82]),
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[81:2] :
|
|
m_ldTransRsFromPQ_enqReq_rl[81:2],
|
|
x_id__h21371 } ;
|
|
assign m_ldTransRsFromPQ_data_0$EN =
|
|
m_ldTransRsFromPQ_enqP == 1'd0 &&
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ;
|
|
|
|
// register m_ldTransRsFromPQ_data_1
|
|
assign m_ldTransRsFromPQ_data_1$D_IN = m_ldTransRsFromPQ_data_0$D_IN ;
|
|
assign m_ldTransRsFromPQ_data_1$EN =
|
|
m_ldTransRsFromPQ_enqP == 1'd1 &&
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ;
|
|
|
|
// register m_ldTransRsFromPQ_deqP
|
|
assign m_ldTransRsFromPQ_deqP$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl && _theResult_____2__h22136 ;
|
|
assign m_ldTransRsFromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_deqReq_rl
|
|
assign m_ldTransRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_ldTransRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_empty
|
|
assign m_ldTransRsFromPQ_empty$D_IN =
|
|
m_ldTransRsFromPQ_clearReq_rl ||
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 &&
|
|
(IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 ||
|
|
m_ldTransRsFromPQ_empty) ;
|
|
assign m_ldTransRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_enqP
|
|
assign m_ldTransRsFromPQ_enqP$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl && v__h21066 ;
|
|
assign m_ldTransRsFromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_enqReq_rl
|
|
assign m_ldTransRsFromPQ_enqReq_rl$D_IN = 84'h2AAAAAAAAAAAAAAAAAAAA ;
|
|
assign m_ldTransRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_full
|
|
assign m_ldTransRsFromPQ_full$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366 ;
|
|
assign m_ldTransRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_needFlush
|
|
assign m_needFlush$D_IN = !WILL_FIRE_RL_m_doFinishFlush ;
|
|
assign m_needFlush$EN = MUX_m_waitFlushP$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_0
|
|
assign m_pendInst_0$D_IN =
|
|
{ procReq_req[490:283],
|
|
CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q37,
|
|
procReq_req[277:12] } ;
|
|
assign m_pendInst_0$EN = MUX_m_pendPoisoned_0$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_1
|
|
assign m_pendInst_1$D_IN = m_pendInst_0$D_IN ;
|
|
assign m_pendInst_1$EN = MUX_m_pendPoisoned_1$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_2
|
|
assign m_pendInst_2$D_IN = m_pendInst_0$D_IN ;
|
|
assign m_pendInst_2$EN = MUX_m_pendPoisoned_2$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_3
|
|
assign m_pendInst_3$D_IN = m_pendInst_0$D_IN ;
|
|
assign m_pendInst_3$EN = MUX_m_pendPoisoned_3$write_1__SEL_1 ;
|
|
|
|
// register m_pendPoisoned_0
|
|
assign m_pendPoisoned_0$D_IN = !MUX_m_pendPoisoned_0$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_0$EN =
|
|
EN_procReq && idx__h73988 == 2'd0 ||
|
|
MUX_m_pendPoisoned_0$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_1
|
|
assign m_pendPoisoned_1$D_IN = !MUX_m_pendPoisoned_1$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_1$EN =
|
|
EN_procReq && idx__h73988 == 2'd1 ||
|
|
MUX_m_pendPoisoned_1$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_2
|
|
assign m_pendPoisoned_2$D_IN = !MUX_m_pendPoisoned_2$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_2$EN =
|
|
EN_procReq && idx__h73988 == 2'd2 ||
|
|
MUX_m_pendPoisoned_2$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_3
|
|
assign m_pendPoisoned_3$D_IN = !MUX_m_pendPoisoned_3$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_3$EN =
|
|
EN_procReq && idx__h73988 == 2'd3 ||
|
|
MUX_m_pendPoisoned_3$write_1__SEL_2 ;
|
|
|
|
// register m_pendResp_0
|
|
assign m_pendResp_0$D_IN =
|
|
MUX_m_pendResp_0$write_1__SEL_1 ?
|
|
MUX_m_pendResp_0$write_1__VAL_1 :
|
|
MUX_m_pendResp_0$write_1__VAL_2 ;
|
|
assign m_pendResp_0$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo15 || EN_procReq && _dfoo55 ;
|
|
|
|
// register m_pendResp_1
|
|
assign m_pendResp_1$D_IN =
|
|
MUX_m_pendResp_1$write_1__SEL_1 ?
|
|
MUX_m_pendResp_1$write_1__VAL_1 :
|
|
MUX_m_pendResp_1$write_1__VAL_2 ;
|
|
assign m_pendResp_1$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo13 || EN_procReq && _dfoo53 ;
|
|
|
|
// register m_pendResp_2
|
|
assign m_pendResp_2$D_IN =
|
|
MUX_m_pendResp_2$write_1__SEL_1 ?
|
|
MUX_m_pendResp_2$write_1__VAL_1 :
|
|
MUX_m_pendResp_2$write_1__VAL_2 ;
|
|
assign m_pendResp_2$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo11 || EN_procReq && _dfoo51 ;
|
|
|
|
// register m_pendResp_3
|
|
assign m_pendResp_3$D_IN =
|
|
MUX_m_pendResp_3$write_1__SEL_1 ?
|
|
MUX_m_pendResp_3$write_1__VAL_1 :
|
|
MUX_m_pendResp_3$write_1__VAL_2 ;
|
|
assign m_pendResp_3$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo9 || EN_procReq && _dfoo49 ;
|
|
|
|
// register m_pendSpecBits_0_rl
|
|
assign m_pendSpecBits_0_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h8992 :
|
|
n__read__h106143 ;
|
|
assign m_pendSpecBits_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_1_rl
|
|
assign m_pendSpecBits_1_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h9337 :
|
|
n__read__h106274 ;
|
|
assign m_pendSpecBits_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_2_rl
|
|
assign m_pendSpecBits_2_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h9682 :
|
|
n__read__h106405 ;
|
|
assign m_pendSpecBits_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_3_rl
|
|
assign m_pendSpecBits_3_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h10027 :
|
|
n__read__h106536 ;
|
|
assign m_pendSpecBits_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_0_rl
|
|
assign m_pendValid_0_rl$D_IN =
|
|
MUX_m_pendPoisoned_0$write_1__SEL_1 ||
|
|
(m_pendValid_0_lat_0$whas ? 1'd0 : m_pendValid_0_rl) ;
|
|
assign m_pendValid_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_1_rl
|
|
assign m_pendValid_1_rl$D_IN =
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1 ||
|
|
(m_pendValid_1_lat_0$whas ? 1'd0 : m_pendValid_1_rl) ;
|
|
assign m_pendValid_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_2_rl
|
|
assign m_pendValid_2_rl$D_IN =
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1 ||
|
|
(m_pendValid_2_lat_0$whas ? 1'd0 : m_pendValid_2_rl) ;
|
|
assign m_pendValid_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_3_rl
|
|
assign m_pendValid_3_rl$D_IN =
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1 ||
|
|
(m_pendValid_3_lat_0$whas ? 1'd0 : m_pendValid_3_rl) ;
|
|
assign m_pendValid_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendWait_0
|
|
assign m_pendWait_0$D_IN =
|
|
MUX_m_pendWait_0$write_1__SEL_1 ?
|
|
MUX_m_pendWait_0$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_0$EN =
|
|
EN_procReq && _dfoo63 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd0 ;
|
|
|
|
// register m_pendWait_1
|
|
assign m_pendWait_1$D_IN =
|
|
MUX_m_pendWait_1$write_1__SEL_1 ?
|
|
MUX_m_pendWait_1$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_1$EN =
|
|
EN_procReq && _dfoo61 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd1 ;
|
|
|
|
// register m_pendWait_2
|
|
assign m_pendWait_2$D_IN =
|
|
MUX_m_pendWait_2$write_1__SEL_1 ?
|
|
MUX_m_pendWait_2$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_2$EN =
|
|
EN_procReq && _dfoo59 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd2 ;
|
|
|
|
// register m_pendWait_3
|
|
assign m_pendWait_3$D_IN =
|
|
MUX_m_pendWait_3$write_1__SEL_1 ?
|
|
MUX_m_pendWait_3$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_3$EN =
|
|
EN_procReq && _dfoo57 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd3 ;
|
|
|
|
// register m_perfReqQ_clearReq_rl
|
|
assign m_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_data_0
|
|
assign m_perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
m_perfReqQ_enqReq_lat_0$wget[2:0] :
|
|
m_perfReqQ_enqReq_rl[2:0] ;
|
|
assign m_perfReqQ_data_0$EN =
|
|
!m_perfReqQ_clearReq_rl &&
|
|
IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 ;
|
|
|
|
// register m_perfReqQ_deqReq_rl
|
|
assign m_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_empty
|
|
assign m_perfReqQ_empty$D_IN =
|
|
m_perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!m_perfReqQ_enqReq_lat_0$wget[3] :
|
|
!m_perfReqQ_enqReq_rl[3]) &&
|
|
(EN_perf_resp || m_perfReqQ_deqReq_rl || m_perfReqQ_empty) ;
|
|
assign m_perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_enqReq_rl
|
|
assign m_perfReqQ_enqReq_rl$D_IN = 4'b0010 ;
|
|
assign m_perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_full
|
|
assign m_perfReqQ_full$D_IN =
|
|
!m_perfReqQ_clearReq_rl &&
|
|
(IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 ||
|
|
!EN_perf_resp && !m_perfReqQ_deqReq_rl && m_perfReqQ_full) ;
|
|
assign m_perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register m_respForOtherReq
|
|
assign m_respForOtherReq$D_IN =
|
|
{ NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266__ETC___d1798,
|
|
IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1801 } ;
|
|
assign m_respForOtherReq$EN = WILL_FIRE_RL_m_doPRs ;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
assign m_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_data_0
|
|
assign m_rqToPQ_data_0$D_IN =
|
|
m_rqToPQ_enqReq_lat_0$whas ?
|
|
m_rqToPQ_enqReq_lat_0$wget[28:0] :
|
|
m_rqToPQ_enqReq_rl[28:0] ;
|
|
assign m_rqToPQ_data_0$EN =
|
|
m_rqToPQ_enqP == 2'd0 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_1
|
|
assign m_rqToPQ_data_1$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_1$EN =
|
|
m_rqToPQ_enqP == 2'd1 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_2
|
|
assign m_rqToPQ_data_2$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_2$EN =
|
|
m_rqToPQ_enqP == 2'd2 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_3
|
|
assign m_rqToPQ_data_3$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_3$EN =
|
|
m_rqToPQ_enqP == 2'd3 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_deqP
|
|
assign m_rqToPQ_deqP$D_IN =
|
|
m_rqToPQ_clearReq_rl ? 2'd0 : _theResult_____2__h17468 ;
|
|
assign m_rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
assign m_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_empty
|
|
assign m_rqToPQ_empty$D_IN =
|
|
m_rqToPQ_clearReq_rl ||
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260 ;
|
|
assign m_rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqP
|
|
assign m_rqToPQ_enqP$D_IN = m_rqToPQ_clearReq_rl ? 2'd0 : v__h16896 ;
|
|
assign m_rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
assign m_rqToPQ_enqReq_rl$D_IN = 30'b001010101010101010101010101010 ;
|
|
assign m_rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_full
|
|
assign m_rqToPQ_full$D_IN =
|
|
!m_rqToPQ_clearReq_rl &&
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255 ;
|
|
assign m_rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_entryVec_0
|
|
assign m_tlb_m_entryVec_0$D_IN =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_10_02__ETC___d1699 } ;
|
|
assign m_tlb_m_entryVec_0$EN = MUX_m_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_1
|
|
assign m_tlb_m_entryVec_1$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_1$EN = MUX_m_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_10
|
|
assign m_tlb_m_entryVec_10$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_10$EN = MUX_m_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_11
|
|
assign m_tlb_m_entryVec_11$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_11$EN = MUX_m_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_12
|
|
assign m_tlb_m_entryVec_12$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_12$EN = MUX_m_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_13
|
|
assign m_tlb_m_entryVec_13$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_13$EN = MUX_m_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_14
|
|
assign m_tlb_m_entryVec_14$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_14$EN = MUX_m_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_15
|
|
assign m_tlb_m_entryVec_15$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_15$EN = MUX_m_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_16
|
|
assign m_tlb_m_entryVec_16$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_16$EN = MUX_m_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_17
|
|
assign m_tlb_m_entryVec_17$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_17$EN = MUX_m_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_18
|
|
assign m_tlb_m_entryVec_18$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_18$EN = MUX_m_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_19
|
|
assign m_tlb_m_entryVec_19$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_19$EN = MUX_m_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_2
|
|
assign m_tlb_m_entryVec_2$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_2$EN = MUX_m_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_20
|
|
assign m_tlb_m_entryVec_20$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_20$EN = MUX_m_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_21
|
|
assign m_tlb_m_entryVec_21$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_21$EN = MUX_m_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_22
|
|
assign m_tlb_m_entryVec_22$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_22$EN = MUX_m_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_23
|
|
assign m_tlb_m_entryVec_23$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_23$EN = MUX_m_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_24
|
|
assign m_tlb_m_entryVec_24$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_24$EN = MUX_m_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_25
|
|
assign m_tlb_m_entryVec_25$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_25$EN = MUX_m_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_26
|
|
assign m_tlb_m_entryVec_26$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_26$EN = MUX_m_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_27
|
|
assign m_tlb_m_entryVec_27$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_27$EN = MUX_m_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_28
|
|
assign m_tlb_m_entryVec_28$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_28$EN = MUX_m_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_29
|
|
assign m_tlb_m_entryVec_29$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_29$EN = MUX_m_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_3
|
|
assign m_tlb_m_entryVec_3$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_3$EN = MUX_m_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_30
|
|
assign m_tlb_m_entryVec_30$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_30$EN = MUX_m_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_31
|
|
assign m_tlb_m_entryVec_31$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_31$EN = MUX_m_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_4
|
|
assign m_tlb_m_entryVec_4$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_4$EN = MUX_m_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_5
|
|
assign m_tlb_m_entryVec_5$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_5$EN = MUX_m_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_6
|
|
assign m_tlb_m_entryVec_6$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_6$EN = MUX_m_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_7
|
|
assign m_tlb_m_entryVec_7$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_7$EN = MUX_m_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_8
|
|
assign m_tlb_m_entryVec_8$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_8$EN = MUX_m_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_9
|
|
assign m_tlb_m_entryVec_9$D_IN = m_tlb_m_entryVec_0$D_IN ;
|
|
assign m_tlb_m_entryVec_9$EN = MUX_m_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_lruBit_rl
|
|
assign m_tlb_m_lruBit_rl$D_IN = n__read__h50928 ;
|
|
assign m_tlb_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_randIdx
|
|
assign m_tlb_m_randIdx$D_IN = m_tlb_m_randIdx + 5'd1 ;
|
|
assign m_tlb_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_updRepIdx_rl
|
|
assign m_tlb_m_updRepIdx_rl$D_IN =
|
|
{ IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27 } ;
|
|
assign m_tlb_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_validVec_0
|
|
assign m_tlb_m_validVec_0$D_IN = MUX_m_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_0$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1629 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_1
|
|
assign m_tlb_m_validVec_1$D_IN = MUX_m_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_1$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1631 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_10
|
|
assign m_tlb_m_validVec_10$D_IN = MUX_m_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_10$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1649 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_11
|
|
assign m_tlb_m_validVec_11$D_IN = MUX_m_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_11$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1651 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_12
|
|
assign m_tlb_m_validVec_12$D_IN = MUX_m_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_12$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1653 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_13
|
|
assign m_tlb_m_validVec_13$D_IN = MUX_m_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_13$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1655 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_14
|
|
assign m_tlb_m_validVec_14$D_IN = MUX_m_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_14$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1657 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_15
|
|
assign m_tlb_m_validVec_15$D_IN = MUX_m_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_15$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1659 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_16
|
|
assign m_tlb_m_validVec_16$D_IN = MUX_m_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_16$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1661 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_17
|
|
assign m_tlb_m_validVec_17$D_IN = MUX_m_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_17$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1663 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_18
|
|
assign m_tlb_m_validVec_18$D_IN = MUX_m_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_18$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1665 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_19
|
|
assign m_tlb_m_validVec_19$D_IN = MUX_m_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_19$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1667 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_2
|
|
assign m_tlb_m_validVec_2$D_IN = MUX_m_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_2$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1633 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_20
|
|
assign m_tlb_m_validVec_20$D_IN = MUX_m_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_20$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1669 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_21
|
|
assign m_tlb_m_validVec_21$D_IN = MUX_m_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_21$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1671 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_22
|
|
assign m_tlb_m_validVec_22$D_IN = MUX_m_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_22$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1673 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_23
|
|
assign m_tlb_m_validVec_23$D_IN = MUX_m_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_23$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1675 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_24
|
|
assign m_tlb_m_validVec_24$D_IN = MUX_m_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_24$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1677 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_25
|
|
assign m_tlb_m_validVec_25$D_IN = MUX_m_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_25$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1679 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_26
|
|
assign m_tlb_m_validVec_26$D_IN = MUX_m_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_26$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1681 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_27
|
|
assign m_tlb_m_validVec_27$D_IN = MUX_m_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_27$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1683 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_28
|
|
assign m_tlb_m_validVec_28$D_IN = MUX_m_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_28$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1685 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_29
|
|
assign m_tlb_m_validVec_29$D_IN = MUX_m_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_29$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1687 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_3
|
|
assign m_tlb_m_validVec_3$D_IN = MUX_m_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_3$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1635 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_30
|
|
assign m_tlb_m_validVec_30$D_IN = MUX_m_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_30$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1689 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_31
|
|
assign m_tlb_m_validVec_31$D_IN = MUX_m_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_31$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1691 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_4
|
|
assign m_tlb_m_validVec_4$D_IN = MUX_m_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_4$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1637 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_5
|
|
assign m_tlb_m_validVec_5$D_IN = MUX_m_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_5$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1639 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_6
|
|
assign m_tlb_m_validVec_6$D_IN = MUX_m_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_6$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1641 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_7
|
|
assign m_tlb_m_validVec_7$D_IN = MUX_m_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_7$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1643 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_8
|
|
assign m_tlb_m_validVec_8$D_IN = MUX_m_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_8$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1645 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_9
|
|
assign m_tlb_m_validVec_9$D_IN = MUX_m_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_9$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1647 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_vm_info
|
|
assign m_vm_info$D_IN = updateVMInfo_vm ;
|
|
assign m_vm_info$EN = EN_updateVMInfo ;
|
|
|
|
// register m_waitFlushP
|
|
assign m_waitFlushP$D_IN = !MUX_m_waitFlushP$write_1__SEL_1 ;
|
|
assign m_waitFlushP$EN =
|
|
WILL_FIRE_RL_m_doFinishFlush || EN_flush ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1767 =
|
|
{ 65'h15555555555555555,
|
|
(SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd4) ?
|
|
5'd13 :
|
|
5'd15 } ;
|
|
assign DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2766 =
|
|
{ 65'h15555555555555555,
|
|
(procReq_req[490:488] != 3'd1 &&
|
|
procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
5'd13 :
|
|
5'd15 } ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2697 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2694 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2694 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2705 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2702 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2702 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2747 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2744 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2744 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2754 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2751 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2751 ;
|
|
assign IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2694 =
|
|
(level__h86706 == 2'd0 ||
|
|
((level__h86706 == 2'd1) ?
|
|
ppn__h91662[8:0] == 9'd0 :
|
|
level__h86706 == 2'd2 && ppn__h91662[17:0] == 18'd0)) &&
|
|
(!SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 ||
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537) ;
|
|
assign IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_ETC___d2702 =
|
|
(level__h86706 == 2'd0 ||
|
|
((level__h86706 == 2'd1) ?
|
|
ppn__h91662[8:0] == 9'd0 :
|
|
level__h86706 == 2'd2 && ppn__h91662[17:0] == 18'd0)) &&
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 =
|
|
_theResult_____2__h13508 == v__h13028 ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167 =
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 &&
|
|
(IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ||
|
|
!EN_procReq && !m_freeQ_deqReq_rl && m_freeQ_full) ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172 =
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 &&
|
|
(m_freeQ_enqReq_lat_0$whas ?
|
|
!m_freeQ_enqReq_lat_0$wget[2] :
|
|
!m_freeQ_enqReq_rl[2]) &&
|
|
(IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 ||
|
|
m_freeQ_empty) ;
|
|
assign IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 =
|
|
_theResult_____2__h22136 == v__h21066 ;
|
|
assign IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366 =
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 &&
|
|
(IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ||
|
|
!m_ldTransRsFromPQ_deqReq_lat_0$whas &&
|
|
!m_ldTransRsFromPQ_deqReq_rl &&
|
|
m_ldTransRsFromPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 =
|
|
_theResult_____2__h17468 == v__h16896 ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 &&
|
|
(IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ||
|
|
!EN_toParent_rqToP_deq && !m_rqToPQ_deqReq_rl &&
|
|
m_rqToPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 &&
|
|
(m_rqToPQ_enqReq_lat_0$whas ?
|
|
!m_rqToPQ_enqReq_lat_0$wget[29] :
|
|
!m_rqToPQ_enqReq_rl[29]) &&
|
|
(IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 ||
|
|
m_rqToPQ_empty) ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d1261 =
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 ?
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d687 &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_ldTra_ETC___d1258 :
|
|
CASE_IF_m_respForOtherReq_69_BIT_2_70_THEN_m_r_ETC___d1260 ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d1760 =
|
|
(SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd4) ?
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d1751 :
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_17_m_ETC___d675 ||
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662 ||
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1758 ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d684 =
|
|
(SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd4) ?
|
|
NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BI_ETC___d673 :
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_17_m_ETC___d675 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662 &&
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d682 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1831 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) ?
|
|
m_pendValid_1_rl && m_pendWait_1[3:2] == 2'd0 &&
|
|
m_pendPoisoned_1 :
|
|
m_pendValid_0_rl ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1832 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1820 ?
|
|
m_pendValid_2_rl && m_pendWait_2[3:2] == 2'd0 &&
|
|
m_pendPoisoned_2 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1831 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1833 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1824 ?
|
|
m_pendValid_3_rl && m_pendWait_3[3:2] == 2'd0 &&
|
|
m_pendPoisoned_3 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1832 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3727 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) ?
|
|
m_pendValid_1_rl && m_pendWait_1[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_1 :
|
|
m_pendValid_0_rl ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3728 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2838 ?
|
|
m_pendValid_2_rl && m_pendWait_2[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_2 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3727 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3729 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2840 ?
|
|
m_pendValid_3_rl && m_pendWait_3[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_3 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3728 ;
|
|
assign IF_NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_2_ETC___d2797 =
|
|
((m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2771) &&
|
|
(m_pendWait_1[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2774)) ?
|
|
2'd2 :
|
|
((m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2771) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2266 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927 ?
|
|
m_tlb_m_validVec_1 &&
|
|
IF_m_tlb_m_entryVec_1_17_BITS_1_TO_0_21_EQ_0_9_ETC___d1934 :
|
|
m_tlb_m_validVec_0 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2267 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_17_BITS_1_TO_0_21_EQ_0_9_ETC___d1934)) ?
|
|
m_tlb_m_validVec_2 &&
|
|
IF_m_tlb_m_entryVec_2_33_BITS_1_TO_0_37_EQ_0_9_ETC___d1944 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2266 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2268 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947 ?
|
|
m_tlb_m_validVec_3 &&
|
|
IF_m_tlb_m_entryVec_3_49_BITS_1_TO_0_53_EQ_0_9_ETC___d1954 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2267 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2269 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_49_BITS_1_TO_0_53_EQ_0_9_ETC___d1954)) ?
|
|
m_tlb_m_validVec_4 &&
|
|
IF_m_tlb_m_entryVec_4_65_BITS_1_TO_0_69_EQ_0_9_ETC___d1964 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2268 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2270 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967 ?
|
|
m_tlb_m_validVec_5 &&
|
|
IF_m_tlb_m_entryVec_5_81_BITS_1_TO_0_85_EQ_0_9_ETC___d1974 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2269 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2271 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_81_BITS_1_TO_0_85_EQ_0_9_ETC___d1974)) ?
|
|
m_tlb_m_validVec_6 &&
|
|
IF_m_tlb_m_entryVec_6_97_BITS_1_TO_0_01_EQ_0_9_ETC___d1984 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2270 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2272 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987 ?
|
|
m_tlb_m_validVec_7 &&
|
|
IF_m_tlb_m_entryVec_7_13_BITS_1_TO_0_17_EQ_0_9_ETC___d1994 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2271 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2273 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_13_BITS_1_TO_0_17_EQ_0_9_ETC___d1994)) ?
|
|
m_tlb_m_validVec_8 &&
|
|
IF_m_tlb_m_entryVec_8_29_BITS_1_TO_0_33_EQ_0_9_ETC___d2004 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2272 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2274 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007 ?
|
|
m_tlb_m_validVec_9 &&
|
|
IF_m_tlb_m_entryVec_9_45_BITS_1_TO_0_49_EQ_0_0_ETC___d2014 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2273 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2275 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_45_BITS_1_TO_0_49_EQ_0_0_ETC___d2014)) ?
|
|
m_tlb_m_validVec_10 &&
|
|
IF_m_tlb_m_entryVec_10_61_BITS_1_TO_0_65_EQ_0__ETC___d2024 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2274 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2276 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027 ?
|
|
m_tlb_m_validVec_11 &&
|
|
IF_m_tlb_m_entryVec_11_77_BITS_1_TO_0_81_EQ_0__ETC___d2034 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2275 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2277 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_77_BITS_1_TO_0_81_EQ_0__ETC___d2034)) ?
|
|
m_tlb_m_validVec_12 &&
|
|
IF_m_tlb_m_entryVec_12_93_BITS_1_TO_0_97_EQ_0__ETC___d2044 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2276 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2278 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047 ?
|
|
m_tlb_m_validVec_13 &&
|
|
IF_m_tlb_m_entryVec_13_09_BITS_1_TO_0_13_EQ_0__ETC___d2054 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2277 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2279 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_09_BITS_1_TO_0_13_EQ_0__ETC___d2054)) ?
|
|
m_tlb_m_validVec_14 &&
|
|
IF_m_tlb_m_entryVec_14_25_BITS_1_TO_0_29_EQ_0__ETC___d2064 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2278 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2280 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067 ?
|
|
m_tlb_m_validVec_15 &&
|
|
IF_m_tlb_m_entryVec_15_41_BITS_1_TO_0_45_EQ_0__ETC___d2074 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2279 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2281 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_41_BITS_1_TO_0_45_EQ_0__ETC___d2074)) ?
|
|
m_tlb_m_validVec_16 &&
|
|
IF_m_tlb_m_entryVec_16_57_BITS_1_TO_0_61_EQ_0__ETC___d2084 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2280 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2282 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087 ?
|
|
m_tlb_m_validVec_17 &&
|
|
IF_m_tlb_m_entryVec_17_73_BITS_1_TO_0_77_EQ_0__ETC___d2094 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2281 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2283 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_73_BITS_1_TO_0_77_EQ_0__ETC___d2094)) ?
|
|
m_tlb_m_validVec_18 &&
|
|
IF_m_tlb_m_entryVec_18_89_BITS_1_TO_0_93_EQ_0__ETC___d2104 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2282 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2284 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107 ?
|
|
m_tlb_m_validVec_19 &&
|
|
IF_m_tlb_m_entryVec_19_005_BITS_1_TO_0_009_EQ__ETC___d2114 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2283 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2285 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_005_BITS_1_TO_0_009_EQ__ETC___d2114)) ?
|
|
m_tlb_m_validVec_20 &&
|
|
IF_m_tlb_m_entryVec_20_021_BITS_1_TO_0_025_EQ__ETC___d2124 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2284 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2286 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127 ?
|
|
m_tlb_m_validVec_21 &&
|
|
IF_m_tlb_m_entryVec_21_037_BITS_1_TO_0_041_EQ__ETC___d2134 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2285 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2287 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_037_BITS_1_TO_0_041_EQ__ETC___d2134)) ?
|
|
m_tlb_m_validVec_22 &&
|
|
IF_m_tlb_m_entryVec_22_053_BITS_1_TO_0_057_EQ__ETC___d2144 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2286 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2288 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147 ?
|
|
m_tlb_m_validVec_23 &&
|
|
IF_m_tlb_m_entryVec_23_069_BITS_1_TO_0_073_EQ__ETC___d2154 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2287 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2289 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_069_BITS_1_TO_0_073_EQ__ETC___d2154)) ?
|
|
m_tlb_m_validVec_24 &&
|
|
IF_m_tlb_m_entryVec_24_085_BITS_1_TO_0_089_EQ__ETC___d2164 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2288 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2290 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167 ?
|
|
m_tlb_m_validVec_25 &&
|
|
IF_m_tlb_m_entryVec_25_101_BITS_1_TO_0_105_EQ__ETC___d2174 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2289 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2291 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_101_BITS_1_TO_0_105_EQ__ETC___d2174)) ?
|
|
m_tlb_m_validVec_26 &&
|
|
IF_m_tlb_m_entryVec_26_117_BITS_1_TO_0_121_EQ__ETC___d2184 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2290 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2292 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187 ?
|
|
m_tlb_m_validVec_27 &&
|
|
IF_m_tlb_m_entryVec_27_133_BITS_1_TO_0_137_EQ__ETC___d2194 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2291 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2293 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_133_BITS_1_TO_0_137_EQ__ETC___d2194)) ?
|
|
m_tlb_m_validVec_28 &&
|
|
IF_m_tlb_m_entryVec_28_149_BITS_1_TO_0_153_EQ__ETC___d2204 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2292 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2294 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207 ?
|
|
m_tlb_m_validVec_29 &&
|
|
IF_m_tlb_m_entryVec_29_165_BITS_1_TO_0_169_EQ__ETC___d2214 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2293 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2295 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_165_BITS_1_TO_0_169_EQ__ETC___d2214)) ?
|
|
m_tlb_m_validVec_30 &&
|
|
IF_m_tlb_m_entryVec_30_181_BITS_1_TO_0_185_EQ__ETC___d2224 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2294 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2227 ?
|
|
m_tlb_m_validVec_31 &&
|
|
IF_m_tlb_m_entryVec_31_582_BITS_1_TO_0_586_EQ__ETC___d2234 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2295 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2372 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_17_BITS_1_TO_0_21_EQ_0_9_ETC___d1934)) ?
|
|
5'd2 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927 ?
|
|
5'd1 :
|
|
5'd0) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2374 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_49_BITS_1_TO_0_53_EQ_0_9_ETC___d1954)) ?
|
|
5'd4 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947 ?
|
|
5'd3 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2372) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2376 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_81_BITS_1_TO_0_85_EQ_0_9_ETC___d1974)) ?
|
|
5'd6 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967 ?
|
|
5'd5 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2374) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2378 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_13_BITS_1_TO_0_17_EQ_0_9_ETC___d1994)) ?
|
|
5'd8 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987 ?
|
|
5'd7 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2376) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2380 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_45_BITS_1_TO_0_49_EQ_0_0_ETC___d2014)) ?
|
|
5'd10 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007 ?
|
|
5'd9 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2378) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2382 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_77_BITS_1_TO_0_81_EQ_0__ETC___d2034)) ?
|
|
5'd12 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027 ?
|
|
5'd11 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2380) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2384 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_09_BITS_1_TO_0_13_EQ_0__ETC___d2054)) ?
|
|
5'd14 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047 ?
|
|
5'd13 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2382) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2386 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_41_BITS_1_TO_0_45_EQ_0__ETC___d2074)) ?
|
|
5'd16 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067 ?
|
|
5'd15 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2384) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2388 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_73_BITS_1_TO_0_77_EQ_0__ETC___d2094)) ?
|
|
5'd18 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087 ?
|
|
5'd17 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2386) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2390 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_005_BITS_1_TO_0_009_EQ__ETC___d2114)) ?
|
|
5'd20 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107 ?
|
|
5'd19 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2388) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2392 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_037_BITS_1_TO_0_041_EQ__ETC___d2134)) ?
|
|
5'd22 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127 ?
|
|
5'd21 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2390) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2394 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_069_BITS_1_TO_0_073_EQ__ETC___d2154)) ?
|
|
5'd24 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147 ?
|
|
5'd23 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2392) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2396 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_101_BITS_1_TO_0_105_EQ__ETC___d2174)) ?
|
|
5'd26 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167 ?
|
|
5'd25 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2394) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2398 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_133_BITS_1_TO_0_137_EQ__ETC___d2194)) ?
|
|
5'd28 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187 ?
|
|
5'd27 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2396) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2400 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_165_BITS_1_TO_0_169_EQ__ETC___d2214)) ?
|
|
5'd30 :
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207 ?
|
|
5'd29 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2398) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_ldTra_ETC___d1258 =
|
|
((!m_tlb_m_validVec_0 || !m_ldTransRsFromPQ_empty) &&
|
|
(!m_tlb_m_validVec_0 ||
|
|
NOT_m_tlb_m_entryVec_0_92_BITS_79_TO_53_93_EQ__ETC___d711)) ?
|
|
(!m_tlb_m_validVec_1 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_1_14_15_OR_NOT_m_tlb_m_ETC___d1256 :
|
|
!m_tlb_m_validVec_0 || !m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1629 =
|
|
v__h45375 == 5'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1631 =
|
|
v__h45375 == 5'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1633 =
|
|
v__h45375 == 5'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1635 =
|
|
v__h45375 == 5'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1637 =
|
|
v__h45375 == 5'd4 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1639 =
|
|
v__h45375 == 5'd5 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1641 =
|
|
v__h45375 == 5'd6 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1643 =
|
|
v__h45375 == 5'd7 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1645 =
|
|
v__h45375 == 5'd8 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1647 =
|
|
v__h45375 == 5'd9 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1649 =
|
|
v__h45375 == 5'd10 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1651 =
|
|
v__h45375 == 5'd11 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1653 =
|
|
v__h45375 == 5'd12 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1655 =
|
|
v__h45375 == 5'd13 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1657 =
|
|
v__h45375 == 5'd14 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1659 =
|
|
v__h45375 == 5'd15 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1661 =
|
|
v__h45375 == 5'd16 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1663 =
|
|
v__h45375 == 5'd17 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1665 =
|
|
v__h45375 == 5'd18 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1667 =
|
|
v__h45375 == 5'd19 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1669 =
|
|
v__h45375 == 5'd20 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1671 =
|
|
v__h45375 == 5'd21 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1673 =
|
|
v__h45375 == 5'd22 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1675 =
|
|
v__h45375 == 5'd23 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1677 =
|
|
v__h45375 == 5'd24 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1679 =
|
|
v__h45375 == 5'd25 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1681 =
|
|
v__h45375 == 5'd26 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1683 =
|
|
v__h45375 == 5'd27 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1685 =
|
|
v__h45375 == 5'd28 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1687 =
|
|
v__h45375 == 5'd29 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1689 =
|
|
v__h45375 == 5'd30 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_ETC___d1691 =
|
|
v__h45375 == 5'd31 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 ;
|
|
assign IF_NOT_m_tlb_m_validVec_10_58_59_OR_NOT_m_tlb__ETC___d1238 =
|
|
(!m_tlb_m_validVec_10 ||
|
|
NOT_m_tlb_m_entryVec_10_61_BITS_79_TO_53_62_EQ_ETC___d872) ?
|
|
(!m_tlb_m_validVec_11 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_11_74_75_OR_NOT_m_tlb__ETC___d1236 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_11_74_75_OR_NOT_m_tlb__ETC___d1236 =
|
|
(!m_tlb_m_validVec_11 ||
|
|
NOT_m_tlb_m_entryVec_11_77_BITS_79_TO_53_78_EQ_ETC___d888) ?
|
|
(!m_tlb_m_validVec_12 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_12_90_91_OR_NOT_m_tlb__ETC___d1234 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_12_90_91_OR_NOT_m_tlb__ETC___d1234 =
|
|
(!m_tlb_m_validVec_12 ||
|
|
NOT_m_tlb_m_entryVec_12_93_BITS_79_TO_53_94_EQ_ETC___d904) ?
|
|
(!m_tlb_m_validVec_13 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_13_06_07_OR_NOT_m_tlb__ETC___d1232 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_13_06_07_OR_NOT_m_tlb__ETC___d1232 =
|
|
(!m_tlb_m_validVec_13 ||
|
|
NOT_m_tlb_m_entryVec_13_09_BITS_79_TO_53_10_EQ_ETC___d920) ?
|
|
(!m_tlb_m_validVec_14 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_14_22_23_OR_NOT_m_tlb__ETC___d1230 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_14_22_23_OR_NOT_m_tlb__ETC___d1230 =
|
|
(!m_tlb_m_validVec_14 ||
|
|
NOT_m_tlb_m_entryVec_14_25_BITS_79_TO_53_26_EQ_ETC___d936) ?
|
|
(!m_tlb_m_validVec_15 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_15_38_39_OR_NOT_m_tlb__ETC___d1228 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_15_38_39_OR_NOT_m_tlb__ETC___d1228 =
|
|
(!m_tlb_m_validVec_15 ||
|
|
NOT_m_tlb_m_entryVec_15_41_BITS_79_TO_53_42_EQ_ETC___d952) ?
|
|
(!m_tlb_m_validVec_16 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_16_54_55_OR_NOT_m_tlb__ETC___d1226 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_16_54_55_OR_NOT_m_tlb__ETC___d1226 =
|
|
(!m_tlb_m_validVec_16 ||
|
|
NOT_m_tlb_m_entryVec_16_57_BITS_79_TO_53_58_EQ_ETC___d968) ?
|
|
(!m_tlb_m_validVec_17 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_17_70_71_OR_NOT_m_tlb__ETC___d1224 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_17_70_71_OR_NOT_m_tlb__ETC___d1224 =
|
|
(!m_tlb_m_validVec_17 ||
|
|
NOT_m_tlb_m_entryVec_17_73_BITS_79_TO_53_74_EQ_ETC___d984) ?
|
|
(!m_tlb_m_validVec_18 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_18_86_87_OR_NOT_m_tlb__ETC___d1222 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_18_86_87_OR_NOT_m_tlb__ETC___d1222 =
|
|
(!m_tlb_m_validVec_18 ||
|
|
NOT_m_tlb_m_entryVec_18_89_BITS_79_TO_53_90_EQ_ETC___d1000) ?
|
|
(!m_tlb_m_validVec_19 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_19_002_003_OR_NOT_m_tl_ETC___d1220 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_19_002_003_OR_NOT_m_tl_ETC___d1220 =
|
|
(!m_tlb_m_validVec_19 ||
|
|
NOT_m_tlb_m_entryVec_19_005_BITS_79_TO_53_006__ETC___d1016) ?
|
|
(!m_tlb_m_validVec_20 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_20_018_019_OR_NOT_m_tl_ETC___d1218 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_1_14_15_OR_NOT_m_tlb_m_ETC___d1256 =
|
|
(!m_tlb_m_validVec_1 ||
|
|
NOT_m_tlb_m_entryVec_1_17_BITS_79_TO_53_18_EQ__ETC___d728) ?
|
|
(!m_tlb_m_validVec_2 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_2_30_31_OR_NOT_m_tlb_m_ETC___d1254 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_20_018_019_OR_NOT_m_tl_ETC___d1218 =
|
|
(!m_tlb_m_validVec_20 ||
|
|
NOT_m_tlb_m_entryVec_20_021_BITS_79_TO_53_022__ETC___d1032) ?
|
|
(!m_tlb_m_validVec_21 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_21_034_035_OR_NOT_m_tl_ETC___d1216 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_21_034_035_OR_NOT_m_tl_ETC___d1216 =
|
|
(!m_tlb_m_validVec_21 ||
|
|
NOT_m_tlb_m_entryVec_21_037_BITS_79_TO_53_038__ETC___d1048) ?
|
|
(!m_tlb_m_validVec_22 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_22_050_051_OR_NOT_m_tl_ETC___d1214 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_22_050_051_OR_NOT_m_tl_ETC___d1214 =
|
|
(!m_tlb_m_validVec_22 ||
|
|
NOT_m_tlb_m_entryVec_22_053_BITS_79_TO_53_054__ETC___d1064) ?
|
|
(!m_tlb_m_validVec_23 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_23_066_067_OR_NOT_m_tl_ETC___d1212 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_23_066_067_OR_NOT_m_tl_ETC___d1212 =
|
|
(!m_tlb_m_validVec_23 ||
|
|
NOT_m_tlb_m_entryVec_23_069_BITS_79_TO_53_070__ETC___d1080) ?
|
|
(!m_tlb_m_validVec_24 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_24_082_083_OR_NOT_m_tl_ETC___d1210 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_24_082_083_OR_NOT_m_tl_ETC___d1210 =
|
|
(!m_tlb_m_validVec_24 ||
|
|
NOT_m_tlb_m_entryVec_24_085_BITS_79_TO_53_086__ETC___d1096) ?
|
|
(!m_tlb_m_validVec_25 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_25_098_099_OR_NOT_m_tl_ETC___d1208 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_25_098_099_OR_NOT_m_tl_ETC___d1208 =
|
|
(!m_tlb_m_validVec_25 ||
|
|
NOT_m_tlb_m_entryVec_25_101_BITS_79_TO_53_102__ETC___d1112) ?
|
|
(!m_tlb_m_validVec_26 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_26_114_115_OR_NOT_m_tl_ETC___d1206 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_26_114_115_OR_NOT_m_tl_ETC___d1206 =
|
|
(!m_tlb_m_validVec_26 ||
|
|
NOT_m_tlb_m_entryVec_26_117_BITS_79_TO_53_118__ETC___d1128) ?
|
|
(!m_tlb_m_validVec_27 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_27_130_131_OR_NOT_m_tl_ETC___d1204 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_27_130_131_OR_NOT_m_tl_ETC___d1204 =
|
|
(!m_tlb_m_validVec_27 ||
|
|
NOT_m_tlb_m_entryVec_27_133_BITS_79_TO_53_134__ETC___d1144) ?
|
|
(!m_tlb_m_validVec_28 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_28_146_147_OR_NOT_m_tl_ETC___d1202 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_28_146_147_OR_NOT_m_tl_ETC___d1202 =
|
|
(!m_tlb_m_validVec_28 ||
|
|
NOT_m_tlb_m_entryVec_28_149_BITS_79_TO_53_150__ETC___d1160) ?
|
|
(!m_tlb_m_validVec_29 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_29_162_163_OR_NOT_m_tl_ETC___d1200 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_29_162_163_OR_NOT_m_tl_ETC___d1200 =
|
|
(!m_tlb_m_validVec_29 ||
|
|
NOT_m_tlb_m_entryVec_29_165_BITS_79_TO_53_166__ETC___d1176) ?
|
|
(!m_tlb_m_validVec_30 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_30_178_179_OR_NOT_m_tl_ETC___d1198 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_2_30_31_OR_NOT_m_tlb_m_ETC___d1254 =
|
|
(!m_tlb_m_validVec_2 ||
|
|
NOT_m_tlb_m_entryVec_2_33_BITS_79_TO_53_34_EQ__ETC___d744) ?
|
|
(!m_tlb_m_validVec_3 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_3_46_47_OR_NOT_m_tlb_m_ETC___d1252 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_30_178_179_OR_NOT_m_tl_ETC___d1198 =
|
|
(!m_tlb_m_validVec_30 ||
|
|
NOT_m_tlb_m_entryVec_30_181_BITS_79_TO_53_182__ETC___d1192) ?
|
|
!m_tlb_m_validVec_31 || !m_ldTransRsFromPQ_empty :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_3_46_47_OR_NOT_m_tlb_m_ETC___d1252 =
|
|
(!m_tlb_m_validVec_3 ||
|
|
NOT_m_tlb_m_entryVec_3_49_BITS_79_TO_53_50_EQ__ETC___d760) ?
|
|
(!m_tlb_m_validVec_4 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_4_62_63_OR_NOT_m_tlb_m_ETC___d1250 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_4_62_63_OR_NOT_m_tlb_m_ETC___d1250 =
|
|
(!m_tlb_m_validVec_4 ||
|
|
NOT_m_tlb_m_entryVec_4_65_BITS_79_TO_53_66_EQ__ETC___d776) ?
|
|
(!m_tlb_m_validVec_5 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_5_78_79_OR_NOT_m_tlb_m_ETC___d1248 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_5_78_79_OR_NOT_m_tlb_m_ETC___d1248 =
|
|
(!m_tlb_m_validVec_5 ||
|
|
NOT_m_tlb_m_entryVec_5_81_BITS_79_TO_53_82_EQ__ETC___d792) ?
|
|
(!m_tlb_m_validVec_6 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_6_94_95_OR_NOT_m_tlb_m_ETC___d1246 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_6_94_95_OR_NOT_m_tlb_m_ETC___d1246 =
|
|
(!m_tlb_m_validVec_6 ||
|
|
NOT_m_tlb_m_entryVec_6_97_BITS_79_TO_53_98_EQ__ETC___d808) ?
|
|
(!m_tlb_m_validVec_7 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_7_10_11_OR_NOT_m_tlb_m_ETC___d1244 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_7_10_11_OR_NOT_m_tlb_m_ETC___d1244 =
|
|
(!m_tlb_m_validVec_7 ||
|
|
NOT_m_tlb_m_entryVec_7_13_BITS_79_TO_53_14_EQ__ETC___d824) ?
|
|
(!m_tlb_m_validVec_8 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_8_26_27_OR_NOT_m_tlb_m_ETC___d1242 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_8_26_27_OR_NOT_m_tlb_m_ETC___d1242 =
|
|
(!m_tlb_m_validVec_8 ||
|
|
NOT_m_tlb_m_entryVec_8_29_BITS_79_TO_53_30_EQ__ETC___d840) ?
|
|
(!m_tlb_m_validVec_9 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_9_42_43_OR_NOT_m_tlb_m_ETC___d1240 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_9_42_43_OR_NOT_m_tlb_m_ETC___d1240 =
|
|
(!m_tlb_m_validVec_9 ||
|
|
NOT_m_tlb_m_entryVec_9_45_BITS_79_TO_53_46_EQ__ETC___d856) ?
|
|
(!m_tlb_m_validVec_10 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_10_58_59_OR_NOT_m_tlb__ETC___d1238 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_procReq_req_BITS_490_TO_488_297_EQ_1_29_ETC___d2707 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_47_ETC___d2698 :
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 &&
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 &&
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2705 ;
|
|
assign IF_NOT_procReq_req_BITS_490_TO_488_297_EQ_1_29_ETC___d2756 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2748 :
|
|
!SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 ||
|
|
!SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 ||
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2754 ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3643 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3628 ?
|
|
5'd24 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3634 ?
|
|
5'd25 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3640 ?
|
|
5'd26 :
|
|
5'd27)) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3645 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3616 ?
|
|
5'd22 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3622 ?
|
|
5'd23 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3643) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3647 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3604 ?
|
|
5'd20 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3610 ?
|
|
5'd21 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3645) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3649 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3592 ?
|
|
5'd18 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3598 ?
|
|
5'd19 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3647) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3651 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3580 ?
|
|
5'd16 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3586 ?
|
|
5'd17 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3649) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3653 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3568 ?
|
|
5'd10 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3574 ?
|
|
5'd11 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3651) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3655 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3556 ?
|
|
5'd8 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3562 ?
|
|
5'd9 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3653) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3657 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3544 ?
|
|
5'd6 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3550 ?
|
|
5'd7 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3655) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3659 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3532 ?
|
|
5'd4 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3538 ?
|
|
5'd5 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3657) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3661 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3520 ?
|
|
5'd2 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3526 ?
|
|
5'd3 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3659) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3663 =
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3508 ?
|
|
5'd0 :
|
|
(SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3514 ?
|
|
5'd1 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3661) ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1750 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1747 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1747 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1758 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1755 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1755 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d672 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d667 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d667 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d682 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d679 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d679 ;
|
|
assign IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2946 =
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_12_ETC___d2931 ?
|
|
5'd12 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_13_ETC___d2937 ?
|
|
5'd13 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_15_ETC___d2943 ?
|
|
5'd15 :
|
|
5'd28)) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2948 =
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_9__ETC___d2919 ?
|
|
5'd9 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_11_ETC___d2925 ?
|
|
5'd11 :
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2946) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2950 =
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_7__ETC___d2907 ?
|
|
5'd7 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_8__ETC___d2913 ?
|
|
5'd8 :
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2948) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2952 =
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_5__ETC___d2895 ?
|
|
5'd5 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_6__ETC___d2901 ?
|
|
5'd6 :
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2950) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2954 =
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_3__ETC___d2883 ?
|
|
5'd3 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_4__ETC___d2889 ?
|
|
5'd4 :
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2952) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2956 =
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_1__ETC___d2871 ?
|
|
5'd1 :
|
|
(SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_2__ETC___d2877 ?
|
|
5'd2 :
|
|
IF_SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_ETC___d2954) ;
|
|
assign IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 =
|
|
EN_procReq || m_freeQ_deqReq_rl ;
|
|
assign IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 =
|
|
m_freeQ_enqReq_lat_0$whas ?
|
|
m_freeQ_enqReq_lat_0$wget[2] :
|
|
m_freeQ_enqReq_rl[2] ;
|
|
assign IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 =
|
|
m_ldTransRsFromPQ_deqReq_lat_0$whas ||
|
|
m_ldTransRsFromPQ_deqReq_rl ;
|
|
assign IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[83] :
|
|
m_ldTransRsFromPQ_enqReq_rl[83] ;
|
|
assign IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
!m_ldTransRsFromPQ_enqReq_lat_0$wget[83] :
|
|
!m_ldTransRsFromPQ_enqReq_rl[83] ;
|
|
assign IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1315 =
|
|
(m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1283 &&
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1292) ?
|
|
m_pendWait_2[3:2] == 2'd0 || m_pendWait_2[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
NOT_m_ldTransRsFromPQ_empty_68_90_AND_NOT_m_pe_ETC___d1313 ;
|
|
assign IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1332 =
|
|
(m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1283 &&
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1318) ?
|
|
m_pendWait_3[3:2] == 2'd0 || m_pendWait_3[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
NOT_m_ldTransRsFromPQ_empty_68_90_AND_NOT_m_pe_ETC___d1313 ;
|
|
assign IF_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_O_ETC___d1801 =
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1318 ?
|
|
2'd3 :
|
|
(m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1292 ?
|
|
2'd2 :
|
|
((m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_pendWait_0_264_BITS_1_TO_0_284_EQ_SEL_ARR_m__ETC___d1285 ||
|
|
idx__h37917 == 2'd0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 =
|
|
EN_perf_req ?
|
|
m_perfReqQ_enqReq_lat_0$wget[3] :
|
|
m_perfReqQ_enqReq_rl[3] ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1704 =
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1724 =
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1725 =
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 ;
|
|
assign IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1727 =
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 ;
|
|
assign IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 =
|
|
EN_toParent_rqToP_deq || m_rqToPQ_deqReq_rl ;
|
|
assign IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 =
|
|
m_rqToPQ_enqReq_lat_0$whas ?
|
|
m_rqToPQ_enqReq_lat_0$wget[29] :
|
|
m_rqToPQ_enqReq_rl[29] ;
|
|
assign IF_m_tlb_m_entryVec_10_61_BITS_1_TO_0_65_EQ_0__ETC___d2024 =
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 ==
|
|
m_tlb_m_entryVec_10[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_11_77_BITS_1_TO_0_81_EQ_0__ETC___d2034 =
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 ==
|
|
m_tlb_m_entryVec_11[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_12_93_BITS_1_TO_0_97_EQ_0__ETC___d2044 =
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 ==
|
|
m_tlb_m_entryVec_12[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_13_09_BITS_1_TO_0_13_EQ_0__ETC___d2054 =
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 ==
|
|
m_tlb_m_entryVec_13[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_14_25_BITS_1_TO_0_29_EQ_0__ETC___d2064 =
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 ==
|
|
m_tlb_m_entryVec_14[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_15_41_BITS_1_TO_0_45_EQ_0__ETC___d2074 =
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 ==
|
|
m_tlb_m_entryVec_15[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_16_57_BITS_1_TO_0_61_EQ_0__ETC___d2084 =
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 ==
|
|
m_tlb_m_entryVec_16[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_17_73_BITS_1_TO_0_77_EQ_0__ETC___d2094 =
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 ==
|
|
m_tlb_m_entryVec_17[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_18_89_BITS_1_TO_0_93_EQ_0__ETC___d2104 =
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 ==
|
|
m_tlb_m_entryVec_18[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_19_005_BITS_1_TO_0_009_EQ__ETC___d2114 =
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 ==
|
|
m_tlb_m_entryVec_19[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_1_17_BITS_1_TO_0_21_EQ_0_9_ETC___d1934 =
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 ==
|
|
m_tlb_m_entryVec_1[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_20_021_BITS_1_TO_0_025_EQ__ETC___d2124 =
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 ==
|
|
m_tlb_m_entryVec_20[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_21_037_BITS_1_TO_0_041_EQ__ETC___d2134 =
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 ==
|
|
m_tlb_m_entryVec_21[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_22_053_BITS_1_TO_0_057_EQ__ETC___d2144 =
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 ==
|
|
m_tlb_m_entryVec_22[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_23_069_BITS_1_TO_0_073_EQ__ETC___d2154 =
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 ==
|
|
m_tlb_m_entryVec_23[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_24_085_BITS_1_TO_0_089_EQ__ETC___d2164 =
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 ==
|
|
m_tlb_m_entryVec_24[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_25_101_BITS_1_TO_0_105_EQ__ETC___d2174 =
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 ==
|
|
m_tlb_m_entryVec_25[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_26_117_BITS_1_TO_0_121_EQ__ETC___d2184 =
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 ==
|
|
m_tlb_m_entryVec_26[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_27_133_BITS_1_TO_0_137_EQ__ETC___d2194 =
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 ==
|
|
m_tlb_m_entryVec_27[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_28_149_BITS_1_TO_0_153_EQ__ETC___d2204 =
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 ==
|
|
m_tlb_m_entryVec_28[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_29_165_BITS_1_TO_0_169_EQ__ETC___d2214 =
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 ==
|
|
m_tlb_m_entryVec_29[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_2_33_BITS_1_TO_0_37_EQ_0_9_ETC___d1944 =
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q2 ==
|
|
m_tlb_m_entryVec_2[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_30_181_BITS_1_TO_0_185_EQ__ETC___d2224 =
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 ==
|
|
m_tlb_m_entryVec_30[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_31_582_BITS_1_TO_0_586_EQ__ETC___d2234 =
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 ==
|
|
m_tlb_m_entryVec_31[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_3_49_BITS_1_TO_0_53_EQ_0_9_ETC___d1954 =
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 ==
|
|
m_tlb_m_entryVec_3[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_4_65_BITS_1_TO_0_69_EQ_0_9_ETC___d1964 =
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 ==
|
|
m_tlb_m_entryVec_4[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_5_81_BITS_1_TO_0_85_EQ_0_9_ETC___d1974 =
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 ==
|
|
m_tlb_m_entryVec_5[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_6_97_BITS_1_TO_0_01_EQ_0_9_ETC___d1984 =
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 ==
|
|
m_tlb_m_entryVec_6[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_7_13_BITS_1_TO_0_17_EQ_0_9_ETC___d1994 =
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 ==
|
|
m_tlb_m_entryVec_7[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_8_29_BITS_1_TO_0_33_EQ_0_9_ETC___d2004 =
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 ==
|
|
m_tlb_m_entryVec_8[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_9_45_BITS_1_TO_0_49_EQ_0_0_ETC___d2014 =
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 ==
|
|
m_tlb_m_entryVec_9[79:53] ;
|
|
assign IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17 =
|
|
m_tlb_m_updRepIdx_lat_1$whas ?
|
|
m_tlb_m_updRepIdx_lat_1$wget[5] :
|
|
!m_tlb_m_updRepIdx_lat_0$whas && m_tlb_m_updRepIdx_rl[5] ;
|
|
assign IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27 =
|
|
m_tlb_m_updRepIdx_lat_1$whas ?
|
|
m_tlb_m_updRepIdx_lat_1$wget[4:0] :
|
|
(m_tlb_m_updRepIdx_lat_0$whas ?
|
|
5'b01010 :
|
|
m_tlb_m_updRepIdx_rl[4:0]) ;
|
|
assign IF_m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec__ETC___d1420 =
|
|
(m_tlb_m_validVec_0 && m_tlb_m_validVec_1) ?
|
|
(m_tlb_m_validVec_2 ? 5'd3 : 5'd2) :
|
|
(m_tlb_m_validVec_0 ? 5'd1 : 5'd0) ;
|
|
assign IF_m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec__ETC___d1421 =
|
|
(m_tlb_m_validVec_0 && m_tlb_m_validVec_1 &&
|
|
m_tlb_m_validVec_2 &&
|
|
m_tlb_m_validVec_3) ?
|
|
IF_m_tlb_m_validVec_4_62_AND_m_tlb_m_validVec__ETC___d1417 :
|
|
IF_m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec__ETC___d1420 ;
|
|
assign IF_m_tlb_m_validVec_12_90_AND_m_tlb_m_validVec_ETC___d1410 =
|
|
(m_tlb_m_validVec_12 && m_tlb_m_validVec_13) ?
|
|
(m_tlb_m_validVec_14 ? 5'd15 : 5'd14) :
|
|
(m_tlb_m_validVec_12 ? 5'd13 : 5'd12) ;
|
|
assign IF_m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_ETC___d1405 =
|
|
(m_tlb_m_validVec_16 && m_tlb_m_validVec_17) ?
|
|
(m_tlb_m_validVec_18 ? 5'd19 : 5'd18) :
|
|
(m_tlb_m_validVec_16 ? 5'd17 : 5'd16) ;
|
|
assign IF_m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_ETC___d1406 =
|
|
(m_tlb_m_validVec_16 && m_tlb_m_validVec_17 &&
|
|
m_tlb_m_validVec_18 &&
|
|
m_tlb_m_validVec_19) ?
|
|
IF_m_tlb_m_validVec_20_018_AND_m_tlb_m_validVe_ETC___d1402 :
|
|
IF_m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_ETC___d1405 ;
|
|
assign IF_m_tlb_m_validVec_20_018_AND_m_tlb_m_validVe_ETC___d1402 =
|
|
(m_tlb_m_validVec_20 && m_tlb_m_validVec_21) ?
|
|
(m_tlb_m_validVec_22 ? 5'd23 : 5'd22) :
|
|
(m_tlb_m_validVec_20 ? 5'd21 : 5'd20) ;
|
|
assign IF_m_tlb_m_validVec_24_082_AND_m_tlb_m_validVe_ETC___d1398 =
|
|
(m_tlb_m_validVec_24 && m_tlb_m_validVec_25) ?
|
|
(m_tlb_m_validVec_26 ? 5'd27 : 5'd26) :
|
|
(m_tlb_m_validVec_24 ? 5'd25 : 5'd24) ;
|
|
assign IF_m_tlb_m_validVec_24_082_AND_m_tlb_m_validVe_ETC___d1399 =
|
|
(m_tlb_m_validVec_24 && m_tlb_m_validVec_25 &&
|
|
m_tlb_m_validVec_26 &&
|
|
m_tlb_m_validVec_27) ?
|
|
IF_m_tlb_m_validVec_28_146_AND_m_tlb_m_validVe_ETC___d1395 :
|
|
IF_m_tlb_m_validVec_24_082_AND_m_tlb_m_validVe_ETC___d1398 ;
|
|
assign IF_m_tlb_m_validVec_28_146_AND_m_tlb_m_validVe_ETC___d1395 =
|
|
(m_tlb_m_validVec_28 && m_tlb_m_validVec_29) ?
|
|
(m_tlb_m_validVec_30 ? 5'd31 : 5'd30) :
|
|
(m_tlb_m_validVec_28 ? 5'd29 : 5'd28) ;
|
|
assign IF_m_tlb_m_validVec_4_62_AND_m_tlb_m_validVec__ETC___d1417 =
|
|
(m_tlb_m_validVec_4 && m_tlb_m_validVec_5) ?
|
|
(m_tlb_m_validVec_6 ? 5'd7 : 5'd6) :
|
|
(m_tlb_m_validVec_4 ? 5'd5 : 5'd4) ;
|
|
assign IF_m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec__ETC___d1413 =
|
|
(m_tlb_m_validVec_8 && m_tlb_m_validVec_9) ?
|
|
(m_tlb_m_validVec_10 ? 5'd11 : 5'd10) :
|
|
(m_tlb_m_validVec_8 ? 5'd9 : 5'd8) ;
|
|
assign IF_m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec__ETC___d1414 =
|
|
(m_tlb_m_validVec_8 && m_tlb_m_validVec_9 &&
|
|
m_tlb_m_validVec_10 &&
|
|
m_tlb_m_validVec_11) ?
|
|
IF_m_tlb_m_validVec_12_90_AND_m_tlb_m_validVec_ETC___d1410 :
|
|
IF_m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec__ETC___d1413 ;
|
|
assign INV_n__read0928__q35 = ~n__read__h50928 ;
|
|
assign NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2744 =
|
|
level__h86706 != 2'd0 &&
|
|
((level__h86706 == 2'd1) ?
|
|
ppn__h91662[8:0] != 9'd0 :
|
|
level__h86706 != 2'd2 || ppn__h91662[17:0] != 18'd0) ||
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 &&
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 ;
|
|
assign NOT_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT__ETC___d2751 =
|
|
level__h86706 != 2'd0 &&
|
|
((level__h86706 == 2'd1) ?
|
|
ppn__h91662[8:0] != 9'd0 :
|
|
level__h86706 != 2'd2 || ppn__h91662[17:0] != 18'd0) ||
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 ;
|
|
assign NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BI_ETC___d673 =
|
|
(!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 &&
|
|
m_vm_info[45]) &&
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d672 ;
|
|
assign NOT_SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_98_ETC___d3719 =
|
|
{ !SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989,
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989 ?
|
|
SEL_ARR_m_pendInst_0_84_BITS_462_TO_458_991_m__ETC___d2996 :
|
|
{ 1'h0,
|
|
SEL_ARR_m_pendInst_0_84_BITS_461_TO_458_997_m__ETC___d3002 },
|
|
SEL_ARR_m_pendInst_0_84_BIT_457_005_m_pendInst_ETC___d3010,
|
|
SEL_ARR_m_pendInst_0_84_BIT_456_011_m_pendInst_ETC___d3016,
|
|
SEL_ARR_m_pendInst_0_84_BIT_455_018_m_pendInst_ETC___d3023,
|
|
SEL_ARR_m_pendInst_0_84_BIT_454_024_m_pendInst_ETC___d3029,
|
|
SEL_ARR_m_pendInst_0_84_BIT_453_031_m_pendInst_ETC___d3036,
|
|
SEL_ARR_m_pendInst_0_84_BIT_452_037_m_pendInst_ETC___d3042,
|
|
SEL_ARR_m_pendInst_0_84_BIT_451_044_m_pendInst_ETC___d3049,
|
|
SEL_ARR_m_pendInst_0_84_BIT_450_050_m_pendInst_ETC___d3055,
|
|
SEL_ARR_m_pendInst_0_84_BIT_449_057_m_pendInst_ETC___d3062,
|
|
SEL_ARR_m_pendInst_0_84_BIT_448_063_m_pendInst_ETC___d3068,
|
|
SEL_ARR_m_pendInst_0_84_BIT_447_070_m_pendInst_ETC___d3075,
|
|
SEL_ARR_m_pendInst_0_84_BIT_446_076_m_pendInst_ETC___d3081,
|
|
SEL_ARR_m_pendInst_0_84_BIT_445_083_m_pendInst_ETC___d3088,
|
|
SEL_ARR_m_pendInst_0_84_BIT_444_089_m_pendInst_ETC___d3094,
|
|
SEL_ARR_m_pendInst_0_84_BIT_443_096_m_pendInst_ETC___d3101,
|
|
SEL_ARR_m_pendInst_0_84_BIT_442_102_m_pendInst_ETC___d3107,
|
|
SEL_ARR_m_pendInst_0_84_BIT_441_109_m_pendInst_ETC___d3114,
|
|
SEL_ARR_m_pendInst_0_84_BITS_440_TO_375_705_m__ETC___d3115,
|
|
SEL_ARR_m_pendInst_0_84_BITS_374_TO_361_116_m__ETC___d3121,
|
|
SEL_ARR_m_pendInst_0_84_BITS_360_TO_357_122_m__ETC___d3127,
|
|
SEL_ARR_m_pendInst_0_84_BIT_356_128_m_pendInst_ETC___d3133,
|
|
SEL_ARR_m_pendInst_0_84_BIT_355_134_m_pendInst_ETC___d3139,
|
|
SEL_ARR_m_pendInst_0_84_BIT_354_140_m_pendInst_ETC___d3145,
|
|
SEL_ARR_m_pendInst_0_84_BIT_353_146_m_pendInst_ETC___d3151,
|
|
SEL_ARR_m_pendInst_0_84_BIT_352_152_m_pendInst_ETC___d3157,
|
|
SEL_ARR_m_pendInst_0_84_BIT_351_158_m_pendInst_ETC___d3163,
|
|
SEL_ARR_m_pendInst_0_84_BIT_350_164_m_pendInst_ETC___d3169,
|
|
SEL_ARR_m_pendInst_0_84_BIT_349_170_m_pendInst_ETC___d3175,
|
|
SEL_ARR_m_pendInst_0_84_BIT_348_176_m_pendInst_ETC___d3181,
|
|
SEL_ARR_m_pendInst_0_84_BIT_347_182_m_pendInst_ETC___d3187,
|
|
SEL_ARR_m_pendInst_0_84_BIT_346_188_m_pendInst_ETC___d3193,
|
|
SEL_ARR_m_pendInst_0_84_BIT_345_194_m_pendInst_ETC___d3199,
|
|
SEL_ARR_m_pendInst_0_84_BIT_344_206_m_pendInst_ETC___d3211,
|
|
SEL_ARR_m_pendInst_0_84_BITS_343_TO_342_212_m__ETC___d3217,
|
|
SEL_ARR_m_pendInst_0_84_BITS_341_TO_324_218_m__ETC___d3223,
|
|
SEL_ARR_m_pendInst_0_84_BIT_323_224_m_pendInst_ETC___d3229,
|
|
SEL_ARR_m_pendInst_0_84_BITS_322_TO_317_230_m__ETC___d3235,
|
|
x__h100777,
|
|
x__h100786,
|
|
SEL_ARR_m_pendInst_0_84_BITS_288_TO_286_253_m__ETC___d3258,
|
|
SEL_ARR_m_pendInst_0_84_BIT_285_259_m_pendInst_ETC___d3264,
|
|
SEL_ARR_m_pendInst_0_84_BIT_284_265_m_pendInst_ETC___d3270,
|
|
SEL_ARR_m_pendInst_0_84_BIT_283_271_m_pendInst_ETC___d3276,
|
|
SEL_ARR_m_pendInst_0_84_BITS_282_TO_281_277_m__ETC___d3282,
|
|
SEL_ARR_m_pendInst_0_84_BITS_280_TO_279_283_m__ETC___d3288,
|
|
SEL_ARR_m_pendInst_0_84_BIT_278_292_m_pendInst_ETC___d3297,
|
|
!SEL_ARR_NOT_m_pendInst_0_84_BIT_277_298_299_NO_ETC___d3307,
|
|
SEL_ARR_m_pendInst_0_84_BITS_276_TO_271_309_m__ETC___d3314,
|
|
IF_SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266__ETC___d3663,
|
|
!SEL_ARR_NOT_m_pendInst_0_84_BIT_265_666_667_NO_ETC___d3675,
|
|
x__h104272,
|
|
x__h104309,
|
|
SEL_ARR_m_pendInst_0_84_BITS_135_TO_130_689_m__ETC___d3694,
|
|
x__h104327,
|
|
x__h104336,
|
|
SEL_ARR_m_pendInst_0_84_BIT_0_707_m_pendInst_1_ETC___d3712 } ;
|
|
assign NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_47_ETC___d2698 =
|
|
(!SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 ||
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 &&
|
|
m_vm_info[45]) &&
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2697 ;
|
|
assign NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1747 =
|
|
level__h38292 != 2'd0 &&
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[8:0] !=
|
|
9'd0 :
|
|
level__h38292 != 2'd2 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662 &&
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 ||
|
|
!m_vm_info[46] ;
|
|
assign NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_ETC___d1755 =
|
|
level__h38292 != 2'd0 &&
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[8:0] !=
|
|
9'd0 :
|
|
level__h38292 != 2'd2 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 ||
|
|
!m_vm_info[46] ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d1626 =
|
|
NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 &&
|
|
(!m_tlb_m_validVec_0 ||
|
|
NOT_m_tlb_m_entryVec_0_92_BITS_79_TO_53_93_EQ__ETC___d711) &&
|
|
NOT_m_tlb_m_validVec_1_14_15_OR_NOT_m_tlb_m_en_ETC___d1624 ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_ETC___d686 =
|
|
(SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 !=
|
|
3'd4 ||
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d607) &&
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d615 &&
|
|
IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d684 ;
|
|
assign NOT_m_ldTransRsFromPQ_empty_68_90_AND_NOT_m_pe_ETC___d1313 =
|
|
!m_ldTransRsFromPQ_empty && m_pendWait_0[3:2] != 2'd0 &&
|
|
m_pendWait_0[3:2] != 2'd1 &&
|
|
m_pendWait_0_264_BITS_1_TO_0_284_EQ_SEL_ARR_m__ETC___d1285 &&
|
|
idx__h37917 != 2'd0 ||
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
m_pendWait_1_270_BITS_3_TO_2_271_EQ_0_272_OR_m_ETC___d1281 ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1820 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) &&
|
|
(!m_pendValid_1_rl || m_pendWait_1[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_1) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1824 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1820 &&
|
|
(!m_pendValid_2_rl || m_pendWait_2[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_2) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2838 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) &&
|
|
(!m_pendValid_1_rl || m_pendWait_1[3:2] != 2'd0 ||
|
|
m_pendPoisoned_1) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2840 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2838 &&
|
|
(!m_pendValid_2_rl || m_pendWait_2[3:2] != 2'd0 ||
|
|
m_pendPoisoned_2) ;
|
|
assign NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266__ETC___d1784 =
|
|
m_pendWait_0[3:2] != 2'd0 && m_pendWait_0[3:2] != 2'd1 &&
|
|
m_pendWait_0_264_BITS_1_TO_0_284_EQ_SEL_ARR_m__ETC___d1285 &&
|
|
idx__h37917 != 2'd0 ||
|
|
m_pendWait_1[3:2] != 2'd0 && m_pendWait_1[3:2] != 2'd1 &&
|
|
m_pendWait_1_270_BITS_1_TO_0_276_EQ_SEL_ARR_m__ETC___d1277 &&
|
|
idx__h37917 != 2'd1 ;
|
|
assign NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266__ETC___d1798 =
|
|
NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266__ETC___d1784 ||
|
|
m_pendWait_2[3:2] != 2'd0 && m_pendWait_2[3:2] != 2'd1 &&
|
|
m_pendWait_2_294_BITS_1_TO_0_300_EQ_SEL_ARR_m__ETC___d1301 &&
|
|
idx__h37917 != 2'd2 ||
|
|
m_pendWait_3[3:2] != 2'd0 && m_pendWait_3[3:2] != 2'd1 &&
|
|
m_pendWait_3_320_BITS_1_TO_0_326_EQ_SEL_ARR_m__ETC___d1327 &&
|
|
idx__h37917 != 2'd3 ;
|
|
assign NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267__ETC___d2795 =
|
|
(m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2771) &&
|
|
(m_pendWait_1[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2774) &&
|
|
(m_pendWait_2[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2778) ;
|
|
assign NOT_m_tlb_m_entryVec_0_92_BITS_79_TO_53_93_EQ__ETC___d711 =
|
|
m_tlb_m_entryVec_0[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_0[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_0[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_10_61_BITS_79_TO_53_62_EQ_ETC___d872 =
|
|
m_tlb_m_entryVec_10[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_10[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_10[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_11_77_BITS_79_TO_53_78_EQ_ETC___d888 =
|
|
m_tlb_m_entryVec_11[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_11[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_11[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_12_93_BITS_79_TO_53_94_EQ_ETC___d904 =
|
|
m_tlb_m_entryVec_12[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_12[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_12[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_13_09_BITS_79_TO_53_10_EQ_ETC___d920 =
|
|
m_tlb_m_entryVec_13[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_13[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_13[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_14_25_BITS_79_TO_53_26_EQ_ETC___d936 =
|
|
m_tlb_m_entryVec_14[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_14[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_14[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_15_41_BITS_79_TO_53_42_EQ_ETC___d952 =
|
|
m_tlb_m_entryVec_15[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_15[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_15[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_16_57_BITS_79_TO_53_58_EQ_ETC___d968 =
|
|
m_tlb_m_entryVec_16[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_16[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_16[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_17_73_BITS_79_TO_53_74_EQ_ETC___d984 =
|
|
m_tlb_m_entryVec_17[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_17[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_17[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_18_89_BITS_79_TO_53_90_EQ_ETC___d1000 =
|
|
m_tlb_m_entryVec_18[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_18[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_18[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_19_005_BITS_79_TO_53_006__ETC___d1016 =
|
|
m_tlb_m_entryVec_19[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_19[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_19[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_1_17_BITS_79_TO_53_18_EQ__ETC___d728 =
|
|
m_tlb_m_entryVec_1[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_1[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_1[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_20_021_BITS_79_TO_53_022__ETC___d1032 =
|
|
m_tlb_m_entryVec_20[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_20[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_20[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_21_037_BITS_79_TO_53_038__ETC___d1048 =
|
|
m_tlb_m_entryVec_21[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_21[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_21[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_22_053_BITS_79_TO_53_054__ETC___d1064 =
|
|
m_tlb_m_entryVec_22[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_22[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_22[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_23_069_BITS_79_TO_53_070__ETC___d1080 =
|
|
m_tlb_m_entryVec_23[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_23[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_23[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_24_085_BITS_79_TO_53_086__ETC___d1096 =
|
|
m_tlb_m_entryVec_24[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_24[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_24[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_25_101_BITS_79_TO_53_102__ETC___d1112 =
|
|
m_tlb_m_entryVec_25[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_25[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_25[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_26_117_BITS_79_TO_53_118__ETC___d1128 =
|
|
m_tlb_m_entryVec_26[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_26[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_26[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_27_133_BITS_79_TO_53_134__ETC___d1144 =
|
|
m_tlb_m_entryVec_27[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_27[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_27[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_28_149_BITS_79_TO_53_150__ETC___d1160 =
|
|
m_tlb_m_entryVec_28[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_28[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_28[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_29_165_BITS_79_TO_53_166__ETC___d1176 =
|
|
m_tlb_m_entryVec_29[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_29[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_29[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_2_33_BITS_79_TO_53_34_EQ__ETC___d744 =
|
|
m_tlb_m_entryVec_2[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_2[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_2[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_30_181_BITS_79_TO_53_182__ETC___d1192 =
|
|
m_tlb_m_entryVec_30[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_30[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_30[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_3_49_BITS_79_TO_53_50_EQ__ETC___d760 =
|
|
m_tlb_m_entryVec_3[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_3[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_3[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_4_65_BITS_79_TO_53_66_EQ__ETC___d776 =
|
|
m_tlb_m_entryVec_4[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_4[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_4[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_5_81_BITS_79_TO_53_82_EQ__ETC___d792 =
|
|
m_tlb_m_entryVec_5[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_5[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_5[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_6_97_BITS_79_TO_53_98_EQ__ETC___d808 =
|
|
m_tlb_m_entryVec_6[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_6[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_6[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_7_13_BITS_79_TO_53_14_EQ__ETC___d824 =
|
|
m_tlb_m_entryVec_7[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_7[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_7[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_8_29_BITS_79_TO_53_30_EQ__ETC___d840 =
|
|
m_tlb_m_entryVec_8[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_8[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_8[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_entryVec_9_45_BITS_79_TO_53_46_EQ__ETC___d856 =
|
|
m_tlb_m_entryVec_9[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_9[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_9[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 ;
|
|
assign NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d687 =
|
|
!CAN_FIRE_RL_m_doStartFlush &&
|
|
(m_tlb_m_updRepIdx_lat_0$whas || !m_tlb_m_updRepIdx_rl[5]) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927 =
|
|
!m_tlb_m_validVec_0 ||
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 !=
|
|
m_tlb_m_entryVec_0[79:53] ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1927 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_17_BITS_1_TO_0_21_EQ_0_9_ETC___d1934) &&
|
|
(!m_tlb_m_validVec_2 ||
|
|
!IF_m_tlb_m_entryVec_2_33_BITS_1_TO_0_37_EQ_0_9_ETC___d1944) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1947 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_49_BITS_1_TO_0_53_EQ_0_9_ETC___d1954) &&
|
|
(!m_tlb_m_validVec_4 ||
|
|
!IF_m_tlb_m_entryVec_4_65_BITS_1_TO_0_69_EQ_0_9_ETC___d1964) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1967 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_81_BITS_1_TO_0_85_EQ_0_9_ETC___d1974) &&
|
|
(!m_tlb_m_validVec_6 ||
|
|
!IF_m_tlb_m_entryVec_6_97_BITS_1_TO_0_01_EQ_0_9_ETC___d1984) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d1987 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_13_BITS_1_TO_0_17_EQ_0_9_ETC___d1994) &&
|
|
(!m_tlb_m_validVec_8 ||
|
|
!IF_m_tlb_m_entryVec_8_29_BITS_1_TO_0_33_EQ_0_9_ETC___d2004) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2007 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_45_BITS_1_TO_0_49_EQ_0_0_ETC___d2014) &&
|
|
(!m_tlb_m_validVec_10 ||
|
|
!IF_m_tlb_m_entryVec_10_61_BITS_1_TO_0_65_EQ_0__ETC___d2024) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2027 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_77_BITS_1_TO_0_81_EQ_0__ETC___d2034) &&
|
|
(!m_tlb_m_validVec_12 ||
|
|
!IF_m_tlb_m_entryVec_12_93_BITS_1_TO_0_97_EQ_0__ETC___d2044) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2047 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_09_BITS_1_TO_0_13_EQ_0__ETC___d2054) &&
|
|
(!m_tlb_m_validVec_14 ||
|
|
!IF_m_tlb_m_entryVec_14_25_BITS_1_TO_0_29_EQ_0__ETC___d2064) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2067 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_41_BITS_1_TO_0_45_EQ_0__ETC___d2074) &&
|
|
(!m_tlb_m_validVec_16 ||
|
|
!IF_m_tlb_m_entryVec_16_57_BITS_1_TO_0_61_EQ_0__ETC___d2084) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2087 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_73_BITS_1_TO_0_77_EQ_0__ETC___d2094) &&
|
|
(!m_tlb_m_validVec_18 ||
|
|
!IF_m_tlb_m_entryVec_18_89_BITS_1_TO_0_93_EQ_0__ETC___d2104) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2107 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_005_BITS_1_TO_0_009_EQ__ETC___d2114) &&
|
|
(!m_tlb_m_validVec_20 ||
|
|
!IF_m_tlb_m_entryVec_20_021_BITS_1_TO_0_025_EQ__ETC___d2124) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2127 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_037_BITS_1_TO_0_041_EQ__ETC___d2134) &&
|
|
(!m_tlb_m_validVec_22 ||
|
|
!IF_m_tlb_m_entryVec_22_053_BITS_1_TO_0_057_EQ__ETC___d2144) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2147 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_069_BITS_1_TO_0_073_EQ__ETC___d2154) &&
|
|
(!m_tlb_m_validVec_24 ||
|
|
!IF_m_tlb_m_entryVec_24_085_BITS_1_TO_0_089_EQ__ETC___d2164) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2167 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_101_BITS_1_TO_0_105_EQ__ETC___d2174) &&
|
|
(!m_tlb_m_validVec_26 ||
|
|
!IF_m_tlb_m_entryVec_26_117_BITS_1_TO_0_121_EQ__ETC___d2184) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2187 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_133_BITS_1_TO_0_137_EQ__ETC___d2194) &&
|
|
(!m_tlb_m_validVec_28 ||
|
|
!IF_m_tlb_m_entryVec_28_149_BITS_1_TO_0_153_EQ__ETC___d2204) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2227 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2207 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_165_BITS_1_TO_0_169_EQ__ETC___d2214) &&
|
|
(!m_tlb_m_validVec_30 ||
|
|
!IF_m_tlb_m_entryVec_30_181_BITS_1_TO_0_185_EQ__ETC___d2224) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2227 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_582_BITS_1_TO_0_586_EQ__ETC___d2234) &&
|
|
(m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267_AND__ETC___d2780 ||
|
|
m_pendWait_3[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2782) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2227 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_582_BITS_1_TO_0_586_EQ__ETC___d2234) &&
|
|
NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267__ETC___d2795 &&
|
|
(m_pendWait_3[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2782) ;
|
|
assign NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_va_ETC___d1342 =
|
|
!m_tlb_m_validVec_0 || !m_tlb_m_validVec_1 ||
|
|
!m_tlb_m_validVec_2 ||
|
|
!m_tlb_m_validVec_3 ||
|
|
!m_tlb_m_validVec_4 ||
|
|
!m_tlb_m_validVec_5 ||
|
|
!m_tlb_m_validVec_6 ||
|
|
!m_tlb_m_validVec_7 ;
|
|
assign NOT_m_tlb_m_validVec_11_74_75_OR_NOT_m_tlb_m_e_ETC___d1614 =
|
|
(!m_tlb_m_validVec_11 ||
|
|
NOT_m_tlb_m_entryVec_11_77_BITS_79_TO_53_78_EQ_ETC___d888) &&
|
|
(!m_tlb_m_validVec_12 ||
|
|
NOT_m_tlb_m_entryVec_12_93_BITS_79_TO_53_94_EQ_ETC___d904) &&
|
|
NOT_m_tlb_m_validVec_13_06_07_OR_NOT_m_tlb_m_e_ETC___d1612 ;
|
|
assign NOT_m_tlb_m_validVec_13_06_07_OR_NOT_m_tlb_m_e_ETC___d1612 =
|
|
(!m_tlb_m_validVec_13 ||
|
|
NOT_m_tlb_m_entryVec_13_09_BITS_79_TO_53_10_EQ_ETC___d920) &&
|
|
(!m_tlb_m_validVec_14 ||
|
|
NOT_m_tlb_m_entryVec_14_25_BITS_79_TO_53_26_EQ_ETC___d936) &&
|
|
NOT_m_tlb_m_validVec_15_38_39_OR_NOT_m_tlb_m_e_ETC___d1610 ;
|
|
assign NOT_m_tlb_m_validVec_15_38_39_OR_NOT_m_tlb_m_e_ETC___d1610 =
|
|
(!m_tlb_m_validVec_15 ||
|
|
NOT_m_tlb_m_entryVec_15_41_BITS_79_TO_53_42_EQ_ETC___d952) &&
|
|
(!m_tlb_m_validVec_16 ||
|
|
NOT_m_tlb_m_entryVec_16_57_BITS_79_TO_53_58_EQ_ETC___d968) &&
|
|
NOT_m_tlb_m_validVec_17_70_71_OR_NOT_m_tlb_m_e_ETC___d1608 ;
|
|
assign NOT_m_tlb_m_validVec_16_54_55_OR_NOT_m_tlb_m_v_ETC___d1357 =
|
|
!m_tlb_m_validVec_16 || !m_tlb_m_validVec_17 ||
|
|
!m_tlb_m_validVec_18 ||
|
|
!m_tlb_m_validVec_19 ||
|
|
!m_tlb_m_validVec_20 ||
|
|
!m_tlb_m_validVec_21 ||
|
|
!m_tlb_m_validVec_22 ||
|
|
!m_tlb_m_validVec_23 ;
|
|
assign NOT_m_tlb_m_validVec_17_70_71_OR_NOT_m_tlb_m_e_ETC___d1608 =
|
|
(!m_tlb_m_validVec_17 ||
|
|
NOT_m_tlb_m_entryVec_17_73_BITS_79_TO_53_74_EQ_ETC___d984) &&
|
|
(!m_tlb_m_validVec_18 ||
|
|
NOT_m_tlb_m_entryVec_18_89_BITS_79_TO_53_90_EQ_ETC___d1000) &&
|
|
NOT_m_tlb_m_validVec_19_002_003_OR_NOT_m_tlb_m_ETC___d1606 ;
|
|
assign NOT_m_tlb_m_validVec_19_002_003_OR_NOT_m_tlb_m_ETC___d1606 =
|
|
(!m_tlb_m_validVec_19 ||
|
|
NOT_m_tlb_m_entryVec_19_005_BITS_79_TO_53_006__ETC___d1016) &&
|
|
(!m_tlb_m_validVec_20 ||
|
|
NOT_m_tlb_m_entryVec_20_021_BITS_79_TO_53_022__ETC___d1032) &&
|
|
NOT_m_tlb_m_validVec_21_034_035_OR_NOT_m_tlb_m_ETC___d1604 ;
|
|
assign NOT_m_tlb_m_validVec_1_14_15_OR_NOT_m_tlb_m_en_ETC___d1624 =
|
|
(!m_tlb_m_validVec_1 ||
|
|
NOT_m_tlb_m_entryVec_1_17_BITS_79_TO_53_18_EQ__ETC___d728) &&
|
|
(!m_tlb_m_validVec_2 ||
|
|
NOT_m_tlb_m_entryVec_2_33_BITS_79_TO_53_34_EQ__ETC___d744) &&
|
|
NOT_m_tlb_m_validVec_3_46_47_OR_NOT_m_tlb_m_en_ETC___d1622 ;
|
|
assign NOT_m_tlb_m_validVec_21_034_035_OR_NOT_m_tlb_m_ETC___d1604 =
|
|
(!m_tlb_m_validVec_21 ||
|
|
NOT_m_tlb_m_entryVec_21_037_BITS_79_TO_53_038__ETC___d1048) &&
|
|
(!m_tlb_m_validVec_22 ||
|
|
NOT_m_tlb_m_entryVec_22_053_BITS_79_TO_53_054__ETC___d1064) &&
|
|
NOT_m_tlb_m_validVec_23_066_067_OR_NOT_m_tlb_m_ETC___d1602 ;
|
|
assign NOT_m_tlb_m_validVec_23_066_067_OR_NOT_m_tlb_m_ETC___d1602 =
|
|
(!m_tlb_m_validVec_23 ||
|
|
NOT_m_tlb_m_entryVec_23_069_BITS_79_TO_53_070__ETC___d1080) &&
|
|
(!m_tlb_m_validVec_24 ||
|
|
NOT_m_tlb_m_entryVec_24_085_BITS_79_TO_53_086__ETC___d1096) &&
|
|
NOT_m_tlb_m_validVec_25_098_099_OR_NOT_m_tlb_m_ETC___d1600 ;
|
|
assign NOT_m_tlb_m_validVec_24_082_083_OR_NOT_m_tlb_m_ETC___d1364 =
|
|
!m_tlb_m_validVec_24 || !m_tlb_m_validVec_25 ||
|
|
!m_tlb_m_validVec_26 ||
|
|
!m_tlb_m_validVec_27 ||
|
|
!m_tlb_m_validVec_28 ||
|
|
!m_tlb_m_validVec_29 ||
|
|
!m_tlb_m_validVec_30 ||
|
|
!m_tlb_m_validVec_31 ;
|
|
assign NOT_m_tlb_m_validVec_25_098_099_OR_NOT_m_tlb_m_ETC___d1600 =
|
|
(!m_tlb_m_validVec_25 ||
|
|
NOT_m_tlb_m_entryVec_25_101_BITS_79_TO_53_102__ETC___d1112) &&
|
|
(!m_tlb_m_validVec_26 ||
|
|
NOT_m_tlb_m_entryVec_26_117_BITS_79_TO_53_118__ETC___d1128) &&
|
|
NOT_m_tlb_m_validVec_27_130_131_OR_NOT_m_tlb_m_ETC___d1598 ;
|
|
assign NOT_m_tlb_m_validVec_27_130_131_OR_NOT_m_tlb_m_ETC___d1598 =
|
|
(!m_tlb_m_validVec_27 ||
|
|
NOT_m_tlb_m_entryVec_27_133_BITS_79_TO_53_134__ETC___d1144) &&
|
|
(!m_tlb_m_validVec_28 ||
|
|
NOT_m_tlb_m_entryVec_28_149_BITS_79_TO_53_150__ETC___d1160) &&
|
|
NOT_m_tlb_m_validVec_29_162_163_OR_NOT_m_tlb_m_ETC___d1596 ;
|
|
assign NOT_m_tlb_m_validVec_29_162_163_OR_NOT_m_tlb_m_ETC___d1596 =
|
|
(!m_tlb_m_validVec_29 ||
|
|
NOT_m_tlb_m_entryVec_29_165_BITS_79_TO_53_166__ETC___d1176) &&
|
|
(!m_tlb_m_validVec_30 ||
|
|
NOT_m_tlb_m_entryVec_30_181_BITS_79_TO_53_182__ETC___d1192) &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
m_tlb_m_entryVec_31[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 ||
|
|
m_tlb_m_entryVec_31[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_31[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708) ;
|
|
assign NOT_m_tlb_m_validVec_3_46_47_OR_NOT_m_tlb_m_en_ETC___d1622 =
|
|
(!m_tlb_m_validVec_3 ||
|
|
NOT_m_tlb_m_entryVec_3_49_BITS_79_TO_53_50_EQ__ETC___d760) &&
|
|
(!m_tlb_m_validVec_4 ||
|
|
NOT_m_tlb_m_entryVec_4_65_BITS_79_TO_53_66_EQ__ETC___d776) &&
|
|
NOT_m_tlb_m_validVec_5_78_79_OR_NOT_m_tlb_m_en_ETC___d1620 ;
|
|
assign NOT_m_tlb_m_validVec_5_78_79_OR_NOT_m_tlb_m_en_ETC___d1620 =
|
|
(!m_tlb_m_validVec_5 ||
|
|
NOT_m_tlb_m_entryVec_5_81_BITS_79_TO_53_82_EQ__ETC___d792) &&
|
|
(!m_tlb_m_validVec_6 ||
|
|
NOT_m_tlb_m_entryVec_6_97_BITS_79_TO_53_98_EQ__ETC___d808) &&
|
|
NOT_m_tlb_m_validVec_7_10_11_OR_NOT_m_tlb_m_en_ETC___d1618 ;
|
|
assign NOT_m_tlb_m_validVec_7_10_11_OR_NOT_m_tlb_m_en_ETC___d1618 =
|
|
(!m_tlb_m_validVec_7 ||
|
|
NOT_m_tlb_m_entryVec_7_13_BITS_79_TO_53_14_EQ__ETC___d824) &&
|
|
(!m_tlb_m_validVec_8 ||
|
|
NOT_m_tlb_m_entryVec_8_29_BITS_79_TO_53_30_EQ__ETC___d840) &&
|
|
NOT_m_tlb_m_validVec_9_42_43_OR_NOT_m_tlb_m_en_ETC___d1616 ;
|
|
assign NOT_m_tlb_m_validVec_8_26_27_OR_NOT_m_tlb_m_va_ETC___d1349 =
|
|
!m_tlb_m_validVec_8 || !m_tlb_m_validVec_9 ||
|
|
!m_tlb_m_validVec_10 ||
|
|
!m_tlb_m_validVec_11 ||
|
|
!m_tlb_m_validVec_12 ||
|
|
!m_tlb_m_validVec_13 ||
|
|
!m_tlb_m_validVec_14 ||
|
|
!m_tlb_m_validVec_15 ;
|
|
assign NOT_m_tlb_m_validVec_9_42_43_OR_NOT_m_tlb_m_en_ETC___d1616 =
|
|
(!m_tlb_m_validVec_9 ||
|
|
NOT_m_tlb_m_entryVec_9_45_BITS_79_TO_53_46_EQ__ETC___d856) &&
|
|
(!m_tlb_m_validVec_10 ||
|
|
NOT_m_tlb_m_entryVec_10_61_BITS_79_TO_53_62_EQ_ETC___d872) &&
|
|
NOT_m_tlb_m_validVec_11_74_75_OR_NOT_m_tlb_m_e_ETC___d1614 ;
|
|
assign NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4 ||
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402) &&
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 &&
|
|
IF_NOT_procReq_req_BITS_490_TO_488_297_EQ_1_29_ETC___d2707 ;
|
|
assign SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d1751 =
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 &&
|
|
(!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 ||
|
|
!m_vm_info[45]) ||
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_3_ETC___d1750 ;
|
|
assign SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2748 =
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 &&
|
|
(!SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 ||
|
|
!m_vm_info[45]) ||
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_I_ETC___d2747 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2713 =
|
|
idx__h73988 == 2'd0 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2714 =
|
|
idx__h73988 == 2'd1 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2715 =
|
|
idx__h73988 == 2'd2 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2716 =
|
|
idx__h73988 == 2'd3 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
NOT_procReq_req_BITS_490_TO_488_297_EQ_1_298_2_ETC___d2709 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2761 =
|
|
idx__h73988 == 2'd0 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
procReq_req_BITS_490_TO_488_297_EQ_1_298_OR_pr_ETC___d2758 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2762 =
|
|
idx__h73988 == 2'd1 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
procReq_req_BITS_490_TO_488_297_EQ_1_298_OR_pr_ETC___d2758 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2763 =
|
|
idx__h73988 == 2'd2 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
procReq_req_BITS_490_TO_488_297_EQ_1_298_OR_pr_ETC___d2758 ;
|
|
assign SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2764 =
|
|
idx__h73988 == 2'd3 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2296 &&
|
|
procReq_req_BITS_490_TO_488_297_EQ_1_298_OR_pr_ETC___d2758 ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d667 =
|
|
(level__h38292 == 2'd0 ||
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[8:0] ==
|
|
9'd0 :
|
|
level__h38292 == 2'd2 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[17:0] ==
|
|
18'd0)) &&
|
|
(!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662 ||
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622) &&
|
|
m_vm_info[46] ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_3_TO__ETC___d679 =
|
|
(level__h38292 == 2'd0 ||
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[8:0] ==
|
|
9'd0 :
|
|
level__h38292 == 2'd2 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[17:0] ==
|
|
18'd0)) &&
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 &&
|
|
m_vm_info[46] ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_10_02__ETC___d1699 =
|
|
{ CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_9_10_m_ETC___d1698,
|
|
level__h38292 } ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_9_10_m_ETC___d1698 =
|
|
{ CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_17_m_ETC___d675 } ;
|
|
assign SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d1762 =
|
|
(SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 ==
|
|
3'd1 ||
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 ==
|
|
3'd3 ||
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 ==
|
|
3'd4) &&
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d607 ||
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d615 ||
|
|
IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d1760 ;
|
|
assign SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d1263 =
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 ||
|
|
(SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ?
|
|
IF_NOT_SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_ETC___d1261 :
|
|
CASE_IF_m_respForOtherReq_69_BIT_2_70_THEN_m_r_ETC___d1260) ;
|
|
assign _2_CONCAT_IF_NOT_m_pendWait_0_264_BITS_3_TO_2_2_ETC___d2799 =
|
|
{ 2'd2,
|
|
NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267__ETC___d2795 ?
|
|
2'd3 :
|
|
IF_NOT_m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_2_ETC___d2797 } ;
|
|
assign _dfoo1 =
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d1762 ||
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo11 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1725 ||
|
|
_dfoo3 ;
|
|
assign _dfoo13 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1724 ||
|
|
_dfoo5 ;
|
|
assign _dfoo15 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1704 ||
|
|
_dfoo7 ;
|
|
assign _dfoo25 =
|
|
idx__h73988 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785 ||
|
|
idx__h73988 == 2'd3 &&
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo26 =
|
|
(idx__h73988 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_264_BITS_3_TO_2_2_ETC___d2799 :
|
|
((idx__h73988 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo27 =
|
|
idx__h73988 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785 ||
|
|
idx__h73988 == 2'd2 &&
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo28 =
|
|
(idx__h73988 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_264_BITS_3_TO_2_2_ETC___d2799 :
|
|
((idx__h73988 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo29 =
|
|
idx__h73988 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785 ||
|
|
idx__h73988 == 2'd1 &&
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo3 =
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d1762 ||
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo30 =
|
|
(idx__h73988 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_264_BITS_3_TO_2_2_ETC___d2799 :
|
|
((idx__h73988 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo31 =
|
|
idx__h73988 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785 ||
|
|
idx__h73988 == 2'd0 &&
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo32 =
|
|
(idx__h73988 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2785) ?
|
|
_2_CONCAT_IF_NOT_m_pendWait_0_264_BITS_3_TO_2_2_ETC___d2799 :
|
|
((idx__h73988 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2806) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo49 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2716 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2764 ||
|
|
idx__h73988 == 2'd3 && !m_vm_info[46] ;
|
|
assign _dfoo5 =
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d1762 ||
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo51 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2715 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2763 ||
|
|
idx__h73988 == 2'd2 && !m_vm_info[46] ;
|
|
assign _dfoo53 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2714 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2762 ||
|
|
idx__h73988 == 2'd1 && !m_vm_info[46] ;
|
|
assign _dfoo55 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2713 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2761 ||
|
|
idx__h73988 == 2'd0 && !m_vm_info[46] ;
|
|
assign _dfoo57 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2716 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2764 ||
|
|
_dfoo25 ;
|
|
assign _dfoo59 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2715 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2763 ||
|
|
_dfoo27 ;
|
|
assign _dfoo61 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2714 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2762 ||
|
|
_dfoo29 ;
|
|
assign _dfoo63 =
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2713 ||
|
|
SEL_ARR_m_freeQ_data_0_845_m_freeQ_data_1_846__ETC___d2761 ||
|
|
_dfoo31 ;
|
|
assign _dfoo7 =
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 &&
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d1762 ||
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 ;
|
|
assign _dfoo9 =
|
|
IF_m_respForOtherReq_69_BIT_2_70_THEN_m_respFo_ETC___d1727 ||
|
|
_dfoo1 ;
|
|
assign _theResult_____2__h13508 =
|
|
IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 ?
|
|
next_deqP___1__h13697 :
|
|
m_freeQ_deqP ;
|
|
assign _theResult_____2__h17468 =
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 ?
|
|
next_deqP___1__h17657 :
|
|
m_rqToPQ_deqP ;
|
|
assign _theResult_____2__h22136 =
|
|
IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 ?
|
|
next_deqP___1__h22325 :
|
|
m_ldTransRsFromPQ_deqP ;
|
|
assign addIdx__h55557 =
|
|
(!INV_n__read0928__q35[0] && !INV_n__read0928__q35[1] &&
|
|
!INV_n__read0928__q35[2] &&
|
|
!INV_n__read0928__q35[3] &&
|
|
!INV_n__read0928__q35[4] &&
|
|
!INV_n__read0928__q35[5] &&
|
|
!INV_n__read0928__q35[6] &&
|
|
!INV_n__read0928__q35[7] &&
|
|
!INV_n__read0928__q35[8] &&
|
|
!INV_n__read0928__q35[9] &&
|
|
!INV_n__read0928__q35[10] &&
|
|
!INV_n__read0928__q35[11] &&
|
|
!INV_n__read0928__q35[12] &&
|
|
!INV_n__read0928__q35[13] &&
|
|
!INV_n__read0928__q35[14] &&
|
|
!INV_n__read0928__q35[15]) ?
|
|
((!INV_n__read0928__q35[16] && !INV_n__read0928__q35[17] &&
|
|
!INV_n__read0928__q35[18] &&
|
|
!INV_n__read0928__q35[19] &&
|
|
!INV_n__read0928__q35[20] &&
|
|
!INV_n__read0928__q35[21] &&
|
|
!INV_n__read0928__q35[22] &&
|
|
!INV_n__read0928__q35[23]) ?
|
|
((!INV_n__read0928__q35[24] && !INV_n__read0928__q35[25] &&
|
|
!INV_n__read0928__q35[26] &&
|
|
!INV_n__read0928__q35[27]) ?
|
|
((!INV_n__read0928__q35[28] &&
|
|
!INV_n__read0928__q35[29]) ?
|
|
(INV_n__read0928__q35[30] ? 5'd30 : 5'd31) :
|
|
(INV_n__read0928__q35[28] ? 5'd28 : 5'd29)) :
|
|
((!INV_n__read0928__q35[24] &&
|
|
!INV_n__read0928__q35[25]) ?
|
|
(INV_n__read0928__q35[26] ? 5'd26 : 5'd27) :
|
|
(INV_n__read0928__q35[24] ? 5'd24 : 5'd25))) :
|
|
((!INV_n__read0928__q35[16] && !INV_n__read0928__q35[17] &&
|
|
!INV_n__read0928__q35[18] &&
|
|
!INV_n__read0928__q35[19]) ?
|
|
((!INV_n__read0928__q35[20] &&
|
|
!INV_n__read0928__q35[21]) ?
|
|
(INV_n__read0928__q35[22] ? 5'd22 : 5'd23) :
|
|
(INV_n__read0928__q35[20] ? 5'd20 : 5'd21)) :
|
|
((!INV_n__read0928__q35[16] &&
|
|
!INV_n__read0928__q35[17]) ?
|
|
(INV_n__read0928__q35[18] ? 5'd18 : 5'd19) :
|
|
(INV_n__read0928__q35[16] ? 5'd16 : 5'd17)))) :
|
|
((!INV_n__read0928__q35[0] && !INV_n__read0928__q35[1] &&
|
|
!INV_n__read0928__q35[2] &&
|
|
!INV_n__read0928__q35[3] &&
|
|
!INV_n__read0928__q35[4] &&
|
|
!INV_n__read0928__q35[5] &&
|
|
!INV_n__read0928__q35[6] &&
|
|
!INV_n__read0928__q35[7]) ?
|
|
((!INV_n__read0928__q35[8] && !INV_n__read0928__q35[9] &&
|
|
!INV_n__read0928__q35[10] &&
|
|
!INV_n__read0928__q35[11]) ?
|
|
((!INV_n__read0928__q35[12] &&
|
|
!INV_n__read0928__q35[13]) ?
|
|
(INV_n__read0928__q35[14] ? 5'd14 : 5'd15) :
|
|
(INV_n__read0928__q35[12] ? 5'd12 : 5'd13)) :
|
|
((!INV_n__read0928__q35[8] && !INV_n__read0928__q35[9]) ?
|
|
(INV_n__read0928__q35[10] ? 5'd10 : 5'd11) :
|
|
(INV_n__read0928__q35[8] ? 5'd8 : 5'd9))) :
|
|
((!INV_n__read0928__q35[0] && !INV_n__read0928__q35[1] &&
|
|
!INV_n__read0928__q35[2] &&
|
|
!INV_n__read0928__q35[3]) ?
|
|
((!INV_n__read0928__q35[4] && !INV_n__read0928__q35[5]) ?
|
|
(INV_n__read0928__q35[6] ? 5'd6 : 5'd7) :
|
|
(INV_n__read0928__q35[4] ? 5'd4 : 5'd5)) :
|
|
((!INV_n__read0928__q35[0] && !INV_n__read0928__q35[1]) ?
|
|
(INV_n__read0928__q35[2] ? 5'd2 : 5'd3) :
|
|
(INV_n__read0928__q35[0] ? 5'd0 : 5'd1)))) ;
|
|
assign addIdx__h60407 =
|
|
(m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec_1_1_ETC___d1373 &&
|
|
m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec_9_4_ETC___d1380) ?
|
|
(m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_17_ETC___d1388 ?
|
|
IF_m_tlb_m_validVec_24_082_AND_m_tlb_m_validVe_ETC___d1399 :
|
|
IF_m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_ETC___d1406) :
|
|
(m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec_1_1_ETC___d1373 ?
|
|
IF_m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec__ETC___d1414 :
|
|
IF_m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec__ETC___d1421) ;
|
|
assign idx__h37917 =
|
|
m_respForOtherReq[2] ?
|
|
m_respForOtherReq[1:0] :
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign idx__h73600 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1824 ?
|
|
2'd3 :
|
|
(NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1820 ?
|
|
2'd2 :
|
|
((!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign idx__h86667 =
|
|
NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tlb_m_ETC___d2227 ?
|
|
5'd31 :
|
|
IF_NOT_m_tlb_m_validVec_0_88_89_OR_NOT_IF_m_tl_ETC___d2400 ;
|
|
assign idx__h94435 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2840 ?
|
|
2'd3 :
|
|
(NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2838 ?
|
|
2'd2 :
|
|
((!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign m_pendWait_0_264_BITS_1_TO_0_284_EQ_SEL_ARR_m__ETC___d1285 =
|
|
m_pendWait_0[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1283 =
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
m_pendWait_1_270_BITS_3_TO_2_271_EQ_0_272_OR_m_ETC___d1281 ;
|
|
assign m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1292 =
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_pendWait_0_264_BITS_1_TO_0_284_EQ_SEL_ARR_m__ETC___d1285 ||
|
|
idx__h37917 == 2'd0) &&
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_pendWait_1_270_BITS_1_TO_0_276_EQ_SEL_ARR_m__ETC___d1277 ||
|
|
idx__h37917 == 2'd1) ;
|
|
assign m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1318 =
|
|
m_pendWait_0_264_BITS_3_TO_2_265_EQ_0_266_OR_m_ETC___d1292 &&
|
|
(m_pendWait_2[3:2] == 2'd0 || m_pendWait_2[3:2] == 2'd1 ||
|
|
!m_pendWait_2_294_BITS_1_TO_0_300_EQ_SEL_ARR_m__ETC___d1301 ||
|
|
idx__h37917 == 2'd2) ;
|
|
assign m_pendWait_0_264_BITS_3_TO_2_265_EQ_1_267_AND__ETC___d2780 =
|
|
m_pendWait_0[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2771 ||
|
|
m_pendWait_1[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2774 ||
|
|
m_pendWait_2[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2778 ;
|
|
assign m_pendWait_1_270_BITS_1_TO_0_276_EQ_SEL_ARR_m__ETC___d1277 =
|
|
m_pendWait_1[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_pendWait_1_270_BITS_3_TO_2_271_EQ_0_272_OR_m_ETC___d1281 =
|
|
m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_pendWait_1_270_BITS_1_TO_0_276_EQ_SEL_ARR_m__ETC___d1277 ||
|
|
m_respForOtherReq[2] ||
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign m_pendWait_2_294_BITS_1_TO_0_300_EQ_SEL_ARR_m__ETC___d1301 =
|
|
m_pendWait_2[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_pendWait_3_320_BITS_1_TO_0_326_EQ_SEL_ARR_m__ETC___d1327 =
|
|
m_pendWait_3[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 ;
|
|
assign m_tlb_m_validVec_0_88_AND_m_tlb_m_validVec_1_1_ETC___d1373 =
|
|
m_tlb_m_validVec_0 && m_tlb_m_validVec_1 && m_tlb_m_validVec_2 &&
|
|
m_tlb_m_validVec_3 &&
|
|
m_tlb_m_validVec_4 &&
|
|
m_tlb_m_validVec_5 &&
|
|
m_tlb_m_validVec_6 &&
|
|
m_tlb_m_validVec_7 ;
|
|
assign m_tlb_m_validVec_16_54_AND_m_tlb_m_validVec_17_ETC___d1388 =
|
|
m_tlb_m_validVec_16 && m_tlb_m_validVec_17 &&
|
|
m_tlb_m_validVec_18 &&
|
|
m_tlb_m_validVec_19 &&
|
|
m_tlb_m_validVec_20 &&
|
|
m_tlb_m_validVec_21 &&
|
|
m_tlb_m_validVec_22 &&
|
|
m_tlb_m_validVec_23 ;
|
|
assign m_tlb_m_validVec_8_26_AND_m_tlb_m_validVec_9_4_ETC___d1380 =
|
|
m_tlb_m_validVec_8 && m_tlb_m_validVec_9 &&
|
|
m_tlb_m_validVec_10 &&
|
|
m_tlb_m_validVec_11 &&
|
|
m_tlb_m_validVec_12 &&
|
|
m_tlb_m_validVec_13 &&
|
|
m_tlb_m_validVec_14 &&
|
|
m_tlb_m_validVec_15 ;
|
|
assign n__read__h106143 =
|
|
MUX_m_pendPoisoned_0$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_0_rl ;
|
|
assign n__read__h106274 =
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_1_rl ;
|
|
assign n__read__h106405 =
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_2_rl ;
|
|
assign n__read__h106536 =
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_3_rl ;
|
|
assign n__read__h50928 =
|
|
m_tlb_m_lruBit_lat_0$whas ? upd__h50955 : m_tlb_m_lruBit_rl ;
|
|
assign next_deqP___1__h13697 =
|
|
(m_freeQ_deqP == 2'd3) ? 2'd0 : m_freeQ_deqP + 2'd1 ;
|
|
assign next_deqP___1__h17657 =
|
|
(m_rqToPQ_deqP == 2'd3) ? 2'd0 : m_rqToPQ_deqP + 2'd1 ;
|
|
assign next_deqP___1__h22325 = m_ldTransRsFromPQ_deqP + 1'd1 ;
|
|
assign procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2771 =
|
|
procReq_req[425:399] == m_pendInst_0[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2774 =
|
|
procReq_req[425:399] == m_pendInst_1[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2778 =
|
|
procReq_req[425:399] == m_pendInst_2[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_915_EQ_m_pendInst__ETC___d2782 =
|
|
procReq_req[425:399] == m_pendInst_3[413:387] ;
|
|
assign procReq_req_BITS_490_TO_488_297_EQ_1_298_OR_pr_ETC___d2758 =
|
|
(procReq_req[490:488] == 3'd1 || procReq_req[490:488] == 3'd3 ||
|
|
procReq_req[490:488] == 3'd4) &&
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 ||
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 ||
|
|
IF_NOT_procReq_req_BITS_490_TO_488_297_EQ_1_29_ETC___d2756 ;
|
|
assign upd__h10027 = n__read__h106536 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h50955 =
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep ?
|
|
MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
32'd0 ;
|
|
assign upd__h8992 = n__read__h106143 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h9337 = n__read__h106274 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h9682 = n__read__h106405 & specUpdate_correctSpeculation_mask ;
|
|
assign v__h13028 =
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ?
|
|
v__h13179 :
|
|
m_freeQ_enqP ;
|
|
assign v__h13179 = (m_freeQ_enqP == 2'd3) ? 2'd0 : m_freeQ_enqP + 2'd1 ;
|
|
assign v__h16896 =
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ?
|
|
v__h17047 :
|
|
m_rqToPQ_enqP ;
|
|
assign v__h17047 = (m_rqToPQ_enqP == 2'd3) ? 2'd0 : m_rqToPQ_enqP + 2'd1 ;
|
|
assign v__h21066 =
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ?
|
|
v__h21217 :
|
|
m_ldTransRsFromPQ_enqP ;
|
|
assign v__h21217 = m_ldTransRsFromPQ_enqP + 1'd1 ;
|
|
assign v__h45375 =
|
|
(NOT_m_tlb_m_validVec_0_88_89_OR_NOT_m_tlb_m_va_ETC___d1342 ||
|
|
NOT_m_tlb_m_validVec_8_26_27_OR_NOT_m_tlb_m_va_ETC___d1349 ||
|
|
NOT_m_tlb_m_validVec_16_54_55_OR_NOT_m_tlb_m_v_ETC___d1357 ||
|
|
NOT_m_tlb_m_validVec_24_082_083_OR_NOT_m_tlb_m_ETC___d1364) ?
|
|
addIdx__h60407 :
|
|
v__h50192 ;
|
|
assign v__h50192 =
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 ?
|
|
m_tlb_m_randIdx :
|
|
v__h51720 ;
|
|
assign v__h51720 =
|
|
(INV_n__read0928__q35[0] || INV_n__read0928__q35[1] ||
|
|
INV_n__read0928__q35[2] ||
|
|
INV_n__read0928__q35[3] ||
|
|
INV_n__read0928__q35[4] ||
|
|
INV_n__read0928__q35[5] ||
|
|
INV_n__read0928__q35[6] ||
|
|
INV_n__read0928__q35[7] ||
|
|
INV_n__read0928__q35[8] ||
|
|
INV_n__read0928__q35[9] ||
|
|
INV_n__read0928__q35[10] ||
|
|
INV_n__read0928__q35[11] ||
|
|
INV_n__read0928__q35[12] ||
|
|
INV_n__read0928__q35[13] ||
|
|
INV_n__read0928__q35[14] ||
|
|
INV_n__read0928__q35[15] ||
|
|
INV_n__read0928__q35[16] ||
|
|
INV_n__read0928__q35[17] ||
|
|
INV_n__read0928__q35[18] ||
|
|
INV_n__read0928__q35[19] ||
|
|
INV_n__read0928__q35[20] ||
|
|
INV_n__read0928__q35[21] ||
|
|
INV_n__read0928__q35[22] ||
|
|
INV_n__read0928__q35[23] ||
|
|
INV_n__read0928__q35[24] ||
|
|
INV_n__read0928__q35[25] ||
|
|
INV_n__read0928__q35[26] ||
|
|
INV_n__read0928__q35[27] ||
|
|
INV_n__read0928__q35[28] ||
|
|
INV_n__read0928__q35[29] ||
|
|
INV_n__read0928__q35[30] ||
|
|
INV_n__read0928__q35[31]) ?
|
|
addIdx__h55557 :
|
|
5'd0 ;
|
|
assign val__h5329 = m_tlb_m_lruBit_rl | x__h5387 ;
|
|
assign x__h5387 = 32'd1 << m_tlb_m_updRepIdx_rl[4:0] ;
|
|
assign x__h70301 = { 8'd0, x__h70310 } ;
|
|
assign x__h91657 = { 8'd0, x__h91666 } ;
|
|
assign x_id__h21371 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[1:0] :
|
|
m_ldTransRsFromPQ_enqReq_rl[1:0] ;
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0: level__h38292 = m_ldTransRsFromPQ_data_0[3:2];
|
|
1'd1: level__h38292 = m_ldTransRsFromPQ_data_1[3:2];
|
|
endcase
|
|
end
|
|
always@(m_freeQ_deqP or
|
|
m_freeQ_data_0 or
|
|
m_freeQ_data_1 or m_freeQ_data_2 or m_freeQ_data_3)
|
|
begin
|
|
case (m_freeQ_deqP)
|
|
2'd0: idx__h73988 = m_freeQ_data_0;
|
|
2'd1: idx__h73988 = m_freeQ_data_1;
|
|
2'd2: idx__h73988 = m_freeQ_data_2;
|
|
2'd3: idx__h73988 = m_freeQ_data_3;
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 =
|
|
m_ldTransRsFromPQ_data_0[1:0];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_1_TO__ETC___d577 =
|
|
m_ldTransRsFromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0: x__h70397 = m_pendInst_0[440:375];
|
|
2'd1: x__h70397 = m_pendInst_1[440:375];
|
|
2'd2: x__h70397 = m_pendInst_2[440:375];
|
|
2'd3: x__h70397 = m_pendInst_3[440:375];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 =
|
|
m_pendInst_0[478:476];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 =
|
|
m_pendInst_1[478:476];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 =
|
|
m_pendInst_2[478:476];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d593 =
|
|
m_pendInst_3[478:476];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d607 =
|
|
!m_ldTransRsFromPQ_data_0[10];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_10_ETC___d607 =
|
|
!m_ldTransRsFromPQ_data_1[10];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d615 =
|
|
!m_ldTransRsFromPQ_data_0[9];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_9__ETC___d615 =
|
|
!m_ldTransRsFromPQ_data_1[9];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 =
|
|
!m_ldTransRsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_72_BIT_4__ETC___d622 =
|
|
!m_ldTransRsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 =
|
|
m_ldTransRsFromPQ_data_0[6];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_6_24_m_ETC___d627 =
|
|
m_ldTransRsFromPQ_data_1[6];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662 =
|
|
m_ldTransRsFromPQ_data_0[5];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_5_59_m_ETC___d662 =
|
|
m_ldTransRsFromPQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635 =
|
|
m_ldTransRsFromPQ_data_0[7];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_7_32_m_ETC___d635 =
|
|
m_ldTransRsFromPQ_data_1[7];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650 =
|
|
m_ldTransRsFromPQ_data_0[54:11];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650 =
|
|
m_ldTransRsFromPQ_data_1[54:11];
|
|
endcase
|
|
end
|
|
always@(level__h38292 or
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650 or
|
|
x__h70397)
|
|
begin
|
|
case (level__h38292)
|
|
2'd0:
|
|
x__h70310 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650,
|
|
x__h70397[11:0] };
|
|
2'd1:
|
|
x__h70310 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[43:9],
|
|
x__h70397[20:0] };
|
|
2'd2:
|
|
x__h70310 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_54_TO_ETC___d650[43:18],
|
|
x__h70397[29:0] };
|
|
2'd3: x__h70310 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_17_m_ETC___d675 =
|
|
m_ldTransRsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_4_17_m_ETC___d675 =
|
|
m_ldTransRsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 =
|
|
m_ldTransRsFromPQ_data_0[81:55];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BITS_81_TO_ETC___d697 =
|
|
m_ldTransRsFromPQ_data_1[81:55];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 =
|
|
m_ldTransRsFromPQ_data_0[8];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_8_05_m_ETC___d708 =
|
|
m_ldTransRsFromPQ_data_1[8];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 =
|
|
m_ldTransRsFromPQ_data_0[82];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_72_BIT_82_80__ETC___d583 =
|
|
m_ldTransRsFromPQ_data_1[82];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendPoisoned_0 or
|
|
m_pendPoisoned_1 or m_pendPoisoned_2 or m_pendPoisoned_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_0;
|
|
2'd1:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_1;
|
|
2'd2:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_2;
|
|
2'd3:
|
|
SEL_ARR_m_pendPoisoned_0_64_m_pendPoisoned_1_6_ETC___d579 =
|
|
m_pendPoisoned_3;
|
|
endcase
|
|
end
|
|
always@(idx__h37917)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0, 2'd1, 2'd2, 2'd3:
|
|
CASE_IF_m_respForOtherReq_69_BIT_2_70_THEN_m_r_ETC___d1260 = 1'd1;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_1 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q1 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_2 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q2 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q2 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q2 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q2 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_0 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q3 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_3 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_4 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_5 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q6 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_6 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q7 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_7 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_8 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_8[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q9 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_9 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_9[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_10 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_10[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q11 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_11 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_11[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_12 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_12[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q13 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_13 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_13[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_14 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_14[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_15 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_15[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_16 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_16[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_17 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_17[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q18 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_18 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_18[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q19 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_19 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_19[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q20 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_20 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_20[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q21 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_21 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_21[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q22 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_22 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_22[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q23 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_23 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_23[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q24 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_24 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_24[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q25 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_25 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_25[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q26 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_26 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_26[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q27 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_27 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_27[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q28 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_28 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_28[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q29 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_29 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_29[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q30 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_30 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_30[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q31 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0: ppn__h91662 = m_tlb_m_entryVec_0[52:9];
|
|
5'd1: ppn__h91662 = m_tlb_m_entryVec_1[52:9];
|
|
5'd2: ppn__h91662 = m_tlb_m_entryVec_2[52:9];
|
|
5'd3: ppn__h91662 = m_tlb_m_entryVec_3[52:9];
|
|
5'd4: ppn__h91662 = m_tlb_m_entryVec_4[52:9];
|
|
5'd5: ppn__h91662 = m_tlb_m_entryVec_5[52:9];
|
|
5'd6: ppn__h91662 = m_tlb_m_entryVec_6[52:9];
|
|
5'd7: ppn__h91662 = m_tlb_m_entryVec_7[52:9];
|
|
5'd8: ppn__h91662 = m_tlb_m_entryVec_8[52:9];
|
|
5'd9: ppn__h91662 = m_tlb_m_entryVec_9[52:9];
|
|
5'd10: ppn__h91662 = m_tlb_m_entryVec_10[52:9];
|
|
5'd11: ppn__h91662 = m_tlb_m_entryVec_11[52:9];
|
|
5'd12: ppn__h91662 = m_tlb_m_entryVec_12[52:9];
|
|
5'd13: ppn__h91662 = m_tlb_m_entryVec_13[52:9];
|
|
5'd14: ppn__h91662 = m_tlb_m_entryVec_14[52:9];
|
|
5'd15: ppn__h91662 = m_tlb_m_entryVec_15[52:9];
|
|
5'd16: ppn__h91662 = m_tlb_m_entryVec_16[52:9];
|
|
5'd17: ppn__h91662 = m_tlb_m_entryVec_17[52:9];
|
|
5'd18: ppn__h91662 = m_tlb_m_entryVec_18[52:9];
|
|
5'd19: ppn__h91662 = m_tlb_m_entryVec_19[52:9];
|
|
5'd20: ppn__h91662 = m_tlb_m_entryVec_20[52:9];
|
|
5'd21: ppn__h91662 = m_tlb_m_entryVec_21[52:9];
|
|
5'd22: ppn__h91662 = m_tlb_m_entryVec_22[52:9];
|
|
5'd23: ppn__h91662 = m_tlb_m_entryVec_23[52:9];
|
|
5'd24: ppn__h91662 = m_tlb_m_entryVec_24[52:9];
|
|
5'd25: ppn__h91662 = m_tlb_m_entryVec_25[52:9];
|
|
5'd26: ppn__h91662 = m_tlb_m_entryVec_26[52:9];
|
|
5'd27: ppn__h91662 = m_tlb_m_entryVec_27[52:9];
|
|
5'd28: ppn__h91662 = m_tlb_m_entryVec_28[52:9];
|
|
5'd29: ppn__h91662 = m_tlb_m_entryVec_29[52:9];
|
|
5'd30: ppn__h91662 = m_tlb_m_entryVec_30[52:9];
|
|
5'd31: ppn__h91662 = m_tlb_m_entryVec_31[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0: level__h86706 = m_tlb_m_entryVec_0[1:0];
|
|
5'd1: level__h86706 = m_tlb_m_entryVec_1[1:0];
|
|
5'd2: level__h86706 = m_tlb_m_entryVec_2[1:0];
|
|
5'd3: level__h86706 = m_tlb_m_entryVec_3[1:0];
|
|
5'd4: level__h86706 = m_tlb_m_entryVec_4[1:0];
|
|
5'd5: level__h86706 = m_tlb_m_entryVec_5[1:0];
|
|
5'd6: level__h86706 = m_tlb_m_entryVec_6[1:0];
|
|
5'd7: level__h86706 = m_tlb_m_entryVec_7[1:0];
|
|
5'd8: level__h86706 = m_tlb_m_entryVec_8[1:0];
|
|
5'd9: level__h86706 = m_tlb_m_entryVec_9[1:0];
|
|
5'd10: level__h86706 = m_tlb_m_entryVec_10[1:0];
|
|
5'd11: level__h86706 = m_tlb_m_entryVec_11[1:0];
|
|
5'd12: level__h86706 = m_tlb_m_entryVec_12[1:0];
|
|
5'd13: level__h86706 = m_tlb_m_entryVec_13[1:0];
|
|
5'd14: level__h86706 = m_tlb_m_entryVec_14[1:0];
|
|
5'd15: level__h86706 = m_tlb_m_entryVec_15[1:0];
|
|
5'd16: level__h86706 = m_tlb_m_entryVec_16[1:0];
|
|
5'd17: level__h86706 = m_tlb_m_entryVec_17[1:0];
|
|
5'd18: level__h86706 = m_tlb_m_entryVec_18[1:0];
|
|
5'd19: level__h86706 = m_tlb_m_entryVec_19[1:0];
|
|
5'd20: level__h86706 = m_tlb_m_entryVec_20[1:0];
|
|
5'd21: level__h86706 = m_tlb_m_entryVec_21[1:0];
|
|
5'd22: level__h86706 = m_tlb_m_entryVec_22[1:0];
|
|
5'd23: level__h86706 = m_tlb_m_entryVec_23[1:0];
|
|
5'd24: level__h86706 = m_tlb_m_entryVec_24[1:0];
|
|
5'd25: level__h86706 = m_tlb_m_entryVec_25[1:0];
|
|
5'd26: level__h86706 = m_tlb_m_entryVec_26[1:0];
|
|
5'd27: level__h86706 = m_tlb_m_entryVec_27[1:0];
|
|
5'd28: level__h86706 = m_tlb_m_entryVec_28[1:0];
|
|
5'd29: level__h86706 = m_tlb_m_entryVec_29[1:0];
|
|
5'd30: level__h86706 = m_tlb_m_entryVec_30[1:0];
|
|
5'd31: level__h86706 = m_tlb_m_entryVec_31[1:0];
|
|
endcase
|
|
end
|
|
always@(level__h86706 or ppn__h91662 or procReq_req)
|
|
begin
|
|
case (level__h86706)
|
|
2'd0: x__h91666 = { ppn__h91662, procReq_req[398:387] };
|
|
2'd1: x__h91666 = { ppn__h91662[43:9], procReq_req[407:387] };
|
|
2'd2: x__h91666 = { ppn__h91662[43:18], procReq_req[416:387] };
|
|
2'd3: x__h91666 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_0[8];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_1[8];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_2[8];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_3[8];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_4[8];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_5[8];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_6[8];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_7[8];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_8[8];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_9[8];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_10[8];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_11[8];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_12[8];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_13[8];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_14[8];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_15[8];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_16[8];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_17[8];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_18[8];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_19[8];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_20[8];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_21[8];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_22[8];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_23[8];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_24[8];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_25[8];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_26[8];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_27[8];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_28[8];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_29[8];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_30[8];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_8_306_30_ETC___d2402 =
|
|
!m_tlb_m_entryVec_31[8];
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_0[7];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_1[7];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_2[7];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_3[7];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_4[7];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_5[7];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_6[7];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_7[7];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_8[7];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_9[7];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_10[7];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_11[7];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_12[7];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_13[7];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_14[7];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_15[7];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_16[7];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_17[7];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_18[7];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_19[7];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_20[7];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_21[7];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_22[7];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_23[7];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_24[7];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_25[7];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_26[7];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_27[7];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_28[7];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_29[7];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_30[7];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_7_405_40_ETC___d2470 =
|
|
!m_tlb_m_entryVec_31[7];
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_92_BIT_2_472_47_ETC___d2537 =
|
|
!m_tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_0[4];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_1[4];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_2[4];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_3[4];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_4[4];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_5[4];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_6[4];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_7[4];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_8[4];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_9[4];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_10[4];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_11[4];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_12[4];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_13[4];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_14[4];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_15[4];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_16[4];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_17[4];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_18[4];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_19[4];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_20[4];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_21[4];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_22[4];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_23[4];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_24[4];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_25[4];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_26[4];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_27[4];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_28[4];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_29[4];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_30[4];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_4_539_m_tlb__ETC___d2572 =
|
|
m_tlb_m_entryVec_31[4];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_31 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_31[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q32 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_0[3];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_1[3];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_2[3];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_3[3];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_4[3];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_5[3];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_6[3];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_7[3];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_8[3];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_9[3];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_10[3];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_11[3];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_12[3];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_13[3];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_14[3];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_15[3];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_16[3];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_17[3];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_18[3];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_19[3];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_20[3];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_21[3];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_22[3];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_23[3];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_24[3];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_25[3];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_26[3];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_27[3];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_28[3];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_29[3];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_30[3];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_3_658_m_tlb__ETC___d2691 =
|
|
m_tlb_m_entryVec_31[3];
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_0[5];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_1[5];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_2[5];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_3[5];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_4[5];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_5[5];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_6[5];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_7[5];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_8[5];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_9[5];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_10[5];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_11[5];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_12[5];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_13[5];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_14[5];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_15[5];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_16[5];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_17[5];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_18[5];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_19[5];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_20[5];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_21[5];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_22[5];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_23[5];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_24[5];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_25[5];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_26[5];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_27[5];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_28[5];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_29[5];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_30[5];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_5_575_m_tlb__ETC___d2608 =
|
|
m_tlb_m_entryVec_31[5];
|
|
endcase
|
|
end
|
|
always@(idx__h86667 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h86667)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_92_BIT_2_472_m_tlb__ETC___d2700 =
|
|
m_tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h94088 = m_pendResp_0[69:6];
|
|
2'd1: x__h94088 = m_pendResp_1[69:6];
|
|
2'd2: x__h94088 = m_pendResp_2[69:6];
|
|
2'd3: x__h94088 = m_pendResp_3[69:6];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h100777 = m_pendInst_0[316:303];
|
|
2'd1: x__h100777 = m_pendInst_1[316:303];
|
|
2'd2: x__h100777 = m_pendInst_2[316:303];
|
|
2'd3: x__h100777 = m_pendInst_3[316:303];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h100786 = m_pendInst_0[302:289];
|
|
2'd1: x__h100786 = m_pendInst_1[302:289];
|
|
2'd2: x__h100786 = m_pendInst_2[302:289];
|
|
2'd3: x__h100786 = m_pendInst_3[302:289];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h104272 = m_pendInst_0[264:201];
|
|
2'd1: x__h104272 = m_pendInst_1[264:201];
|
|
2'd2: x__h104272 = m_pendInst_2[264:201];
|
|
2'd3: x__h104272 = m_pendInst_3[264:201];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h104327 = m_pendInst_0[129:66];
|
|
2'd1: x__h104327 = m_pendInst_1[129:66];
|
|
2'd2: x__h104327 = m_pendInst_2[129:66];
|
|
2'd3: x__h104327 = m_pendInst_3[129:66];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h104309 = m_pendInst_0[200:136];
|
|
2'd1: x__h104309 = m_pendInst_1[200:136];
|
|
2'd2: x__h104309 = m_pendInst_2[200:136];
|
|
2'd3: x__h104309 = m_pendInst_3[200:136];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0: x__h104336 = m_pendInst_0[65:1];
|
|
2'd1: x__h104336 = m_pendInst_1[65:1];
|
|
2'd2: x__h104336 = m_pendInst_2[65:1];
|
|
2'd3: x__h104336 = m_pendInst_3[65:1];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendResp_0_827_BIT_5_845_846_NOT_ETC___d2854 =
|
|
!m_pendResp_0[5];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendResp_0_827_BIT_5_845_846_NOT_ETC___d2854 =
|
|
!m_pendResp_1[5];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendResp_0_827_BIT_5_845_846_NOT_ETC___d2854 =
|
|
!m_pendResp_2[5];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendResp_0_827_BIT_5_845_846_NOT_ETC___d2854 =
|
|
!m_pendResp_3[5];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_15_ETC___d2943 =
|
|
m_pendResp_0[4:0] == 5'd15;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_15_ETC___d2943 =
|
|
m_pendResp_1[4:0] == 5'd15;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_15_ETC___d2943 =
|
|
m_pendResp_2[4:0] == 5'd15;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_15_ETC___d2943 =
|
|
m_pendResp_3[4:0] == 5'd15;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_13_ETC___d2937 =
|
|
m_pendResp_0[4:0] == 5'd13;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_13_ETC___d2937 =
|
|
m_pendResp_1[4:0] == 5'd13;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_13_ETC___d2937 =
|
|
m_pendResp_2[4:0] == 5'd13;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_13_ETC___d2937 =
|
|
m_pendResp_3[4:0] == 5'd13;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_12_ETC___d2931 =
|
|
m_pendResp_0[4:0] == 5'd12;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_12_ETC___d2931 =
|
|
m_pendResp_1[4:0] == 5'd12;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_12_ETC___d2931 =
|
|
m_pendResp_2[4:0] == 5'd12;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_12_ETC___d2931 =
|
|
m_pendResp_3[4:0] == 5'd12;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_11_ETC___d2925 =
|
|
m_pendResp_0[4:0] == 5'd11;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_11_ETC___d2925 =
|
|
m_pendResp_1[4:0] == 5'd11;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_11_ETC___d2925 =
|
|
m_pendResp_2[4:0] == 5'd11;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_11_ETC___d2925 =
|
|
m_pendResp_3[4:0] == 5'd11;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_9__ETC___d2919 =
|
|
m_pendResp_0[4:0] == 5'd9;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_9__ETC___d2919 =
|
|
m_pendResp_1[4:0] == 5'd9;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_9__ETC___d2919 =
|
|
m_pendResp_2[4:0] == 5'd9;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_9__ETC___d2919 =
|
|
m_pendResp_3[4:0] == 5'd9;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_7__ETC___d2907 =
|
|
m_pendResp_0[4:0] == 5'd7;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_7__ETC___d2907 =
|
|
m_pendResp_1[4:0] == 5'd7;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_7__ETC___d2907 =
|
|
m_pendResp_2[4:0] == 5'd7;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_7__ETC___d2907 =
|
|
m_pendResp_3[4:0] == 5'd7;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_8__ETC___d2913 =
|
|
m_pendResp_0[4:0] == 5'd8;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_8__ETC___d2913 =
|
|
m_pendResp_1[4:0] == 5'd8;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_8__ETC___d2913 =
|
|
m_pendResp_2[4:0] == 5'd8;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_8__ETC___d2913 =
|
|
m_pendResp_3[4:0] == 5'd8;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_6__ETC___d2901 =
|
|
m_pendResp_0[4:0] == 5'd6;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_6__ETC___d2901 =
|
|
m_pendResp_1[4:0] == 5'd6;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_6__ETC___d2901 =
|
|
m_pendResp_2[4:0] == 5'd6;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_6__ETC___d2901 =
|
|
m_pendResp_3[4:0] == 5'd6;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_5__ETC___d2895 =
|
|
m_pendResp_0[4:0] == 5'd5;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_5__ETC___d2895 =
|
|
m_pendResp_1[4:0] == 5'd5;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_5__ETC___d2895 =
|
|
m_pendResp_2[4:0] == 5'd5;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_5__ETC___d2895 =
|
|
m_pendResp_3[4:0] == 5'd5;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_4__ETC___d2889 =
|
|
m_pendResp_0[4:0] == 5'd4;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_4__ETC___d2889 =
|
|
m_pendResp_1[4:0] == 5'd4;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_4__ETC___d2889 =
|
|
m_pendResp_2[4:0] == 5'd4;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_4__ETC___d2889 =
|
|
m_pendResp_3[4:0] == 5'd4;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_3__ETC___d2883 =
|
|
m_pendResp_0[4:0] == 5'd3;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_3__ETC___d2883 =
|
|
m_pendResp_1[4:0] == 5'd3;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_3__ETC___d2883 =
|
|
m_pendResp_2[4:0] == 5'd3;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_3__ETC___d2883 =
|
|
m_pendResp_3[4:0] == 5'd3;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_1__ETC___d2871 =
|
|
m_pendResp_0[4:0] == 5'd1;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_1__ETC___d2871 =
|
|
m_pendResp_1[4:0] == 5'd1;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_1__ETC___d2871 =
|
|
m_pendResp_2[4:0] == 5'd1;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_1__ETC___d2871 =
|
|
m_pendResp_3[4:0] == 5'd1;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_2__ETC___d2877 =
|
|
m_pendResp_0[4:0] == 5'd2;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_2__ETC___d2877 =
|
|
m_pendResp_1[4:0] == 5'd2;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_2__ETC___d2877 =
|
|
m_pendResp_2[4:0] == 5'd2;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_2__ETC___d2877 =
|
|
m_pendResp_3[4:0] == 5'd2;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_0__ETC___d2865 =
|
|
m_pendResp_0[4:0] == 5'd0;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_0__ETC___d2865 =
|
|
m_pendResp_1[4:0] == 5'd0;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_0__ETC___d2865 =
|
|
m_pendResp_2[4:0] == 5'd0;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_827_BITS_4_TO_0_856_EQ_0__ETC___d2865 =
|
|
m_pendResp_3[4:0] == 5'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989 =
|
|
!m_pendInst_0[463];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989 =
|
|
!m_pendInst_1[463];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989 =
|
|
!m_pendInst_2[463];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_463_980_981_NO_ETC___d2989 =
|
|
!m_pendInst_3[463];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_475_961_m_pendInst_ETC___d2966 =
|
|
m_pendInst_0[475];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_475_961_m_pendInst_ETC___d2966 =
|
|
m_pendInst_1[475];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_475_961_m_pendInst_ETC___d2966 =
|
|
m_pendInst_2[475];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_475_961_m_pendInst_ETC___d2966 =
|
|
m_pendInst_3[475];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_457_005_m_pendInst_ETC___d3010 =
|
|
m_pendInst_0[457];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_457_005_m_pendInst_ETC___d3010 =
|
|
m_pendInst_1[457];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_457_005_m_pendInst_ETC___d3010 =
|
|
m_pendInst_2[457];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_457_005_m_pendInst_ETC___d3010 =
|
|
m_pendInst_3[457];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_353_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_0[353];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_353_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_1[353];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_353_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_2[353];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_353_146_m_pendInst_ETC___d3151 =
|
|
m_pendInst_3[353];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_347_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_0[347];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_347_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_1[347];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_347_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_2[347];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_347_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_3[347];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_282_TO_281_277_m__ETC___d3282 =
|
|
m_pendInst_0[282:281];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_282_TO_281_277_m__ETC___d3282 =
|
|
m_pendInst_1[282:281];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_282_TO_281_277_m__ETC___d3282 =
|
|
m_pendInst_2[282:281];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_282_TO_281_277_m__ETC___d3282 =
|
|
m_pendInst_3[282:281];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_456_011_m_pendInst_ETC___d3016 =
|
|
m_pendInst_0[456];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_456_011_m_pendInst_ETC___d3016 =
|
|
m_pendInst_1[456];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_456_011_m_pendInst_ETC___d3016 =
|
|
m_pendInst_2[456];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_456_011_m_pendInst_ETC___d3016 =
|
|
m_pendInst_3[456];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_284_265_m_pendInst_ETC___d3270 =
|
|
m_pendInst_0[284];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_284_265_m_pendInst_ETC___d3270 =
|
|
m_pendInst_1[284];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_284_265_m_pendInst_ETC___d3270 =
|
|
m_pendInst_2[284];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_284_265_m_pendInst_ETC___d3270 =
|
|
m_pendInst_3[284];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_277_298_299_NO_ETC___d3307 =
|
|
!m_pendInst_0[277];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_277_298_299_NO_ETC___d3307 =
|
|
!m_pendInst_1[277];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_277_298_299_NO_ETC___d3307 =
|
|
!m_pendInst_2[277];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_277_298_299_NO_ETC___d3307 =
|
|
!m_pendInst_3[277];
|
|
endcase
|
|
end
|
|
always@(m_pendInst_0)
|
|
begin
|
|
case (m_pendInst_0[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 =
|
|
m_pendInst_0[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 = 5'd22;
|
|
default: IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(m_pendInst_1)
|
|
begin
|
|
case (m_pendInst_1[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 =
|
|
m_pendInst_1[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 = 5'd22;
|
|
default: IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(m_pendInst_2)
|
|
begin
|
|
case (m_pendInst_2[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 =
|
|
m_pendInst_2[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 = 5'd22;
|
|
default: IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(m_pendInst_3)
|
|
begin
|
|
case (m_pendInst_3[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 =
|
|
m_pendInst_3[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 = 5'd22;
|
|
default: IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3640 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd22;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3640 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd22;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3640 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd22;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3640 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd22;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3634 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd21;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3634 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd21;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3634 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd21;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3634 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd21;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3628 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd20;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3628 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd20;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3628 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd20;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3628 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd20;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3622 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd19;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3622 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd19;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3622 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd19;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3622 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd19;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3616 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd18;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3616 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd18;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3616 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd18;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3616 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd18;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3610 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd17;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3610 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd17;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3610 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd17;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3610 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd17;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3604 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd16;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3604 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd16;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3604 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd16;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3604 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd16;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3598 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd15;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3598 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd15;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3598 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd15;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3598 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd15;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3592 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd14;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3592 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd14;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3592 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd14;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3592 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd14;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3580 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd12;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3580 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd12;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3580 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd12;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3580 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd12;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3586 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd13;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3586 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd13;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3586 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd13;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3586 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd13;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3574 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd11;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3574 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd11;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3574 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd11;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3574 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd11;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3562 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd9;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3562 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd9;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3562 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd9;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3562 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd9;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3568 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd10;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3568 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd10;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3568 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd10;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3568 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd10;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3556 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd8;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3556 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd8;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3556 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd8;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3556 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd8;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3550 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd7;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3550 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd7;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3550 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd7;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3550 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd7;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3544 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd6;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3544 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd6;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3544 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd6;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3544 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd6;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3538 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd5;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3538 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd5;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3538 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd5;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3538 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd5;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3532 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd4;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3532 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd4;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3532 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd4;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3532 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd4;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3526 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd3;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3526 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd3;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3526 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd3;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3526 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd3;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3514 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd1;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3514 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd1;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3514 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd1;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3514 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd1;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3520 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd2;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3520 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd2;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3520 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd2;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3520 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd2;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 or
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 or
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 or
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3508 =
|
|
IF_m_pendInst_0_84_BITS_270_TO_266_315_EQ_0_31_ETC___d3361 ==
|
|
5'd0;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3508 =
|
|
IF_m_pendInst_1_86_BITS_270_TO_266_363_EQ_0_36_ETC___d3409 ==
|
|
5'd0;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3508 =
|
|
IF_m_pendInst_2_88_BITS_270_TO_266_411_EQ_0_41_ETC___d3457 ==
|
|
5'd0;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_84_BITS_270_TO_266_315_ETC___d3508 =
|
|
IF_m_pendInst_3_90_BITS_270_TO_266_459_EQ_0_46_ETC___d3505 ==
|
|
5'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_265_666_667_NO_ETC___d3675 =
|
|
!m_pendInst_0[265];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_265_666_667_NO_ETC___d3675 =
|
|
!m_pendInst_1[265];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_265_666_667_NO_ETC___d3675 =
|
|
!m_pendInst_2[265];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_84_BIT_265_666_667_NO_ETC___d3675 =
|
|
!m_pendInst_3[265];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_276_TO_271_309_m__ETC___d3314 =
|
|
m_pendInst_0[276:271];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_276_TO_271_309_m__ETC___d3314 =
|
|
m_pendInst_1[276:271];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_276_TO_271_309_m__ETC___d3314 =
|
|
m_pendInst_2[276:271];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_276_TO_271_309_m__ETC___d3314 =
|
|
m_pendInst_3[276:271];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33 =
|
|
m_ldTransRsFromPQ_data_0[9];
|
|
1'd1:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q33 =
|
|
m_ldTransRsFromPQ_data_1[9];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34 =
|
|
m_ldTransRsFromPQ_data_0[10];
|
|
1'd1:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q34 =
|
|
m_ldTransRsFromPQ_data_1[10];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_346_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_0[346];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_346_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_1[346];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_346_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_2[346];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_346_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_3[346];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_345_194_m_pendInst_ETC___d3199 =
|
|
m_pendInst_0[345];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_345_194_m_pendInst_ETC___d3199 =
|
|
m_pendInst_1[345];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_345_194_m_pendInst_ETC___d3199 =
|
|
m_pendInst_2[345];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_345_194_m_pendInst_ETC___d3199 =
|
|
m_pendInst_3[345];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_280_TO_279_283_m__ETC___d3288 =
|
|
m_pendInst_0[280:279];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_280_TO_279_283_m__ETC___d3288 =
|
|
m_pendInst_1[280:279];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_280_TO_279_283_m__ETC___d3288 =
|
|
m_pendInst_2[280:279];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_280_TO_279_283_m__ETC___d3288 =
|
|
m_pendInst_3[280:279];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_454_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_0[454];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_454_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_1[454];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_454_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_2[454];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_454_024_m_pendInst_ETC___d3029 =
|
|
m_pendInst_3[454];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_455_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_0[455];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_455_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_1[455];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_455_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_2[455];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_455_018_m_pendInst_ETC___d3023 =
|
|
m_pendInst_3[455];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_349_170_m_pendInst_ETC___d3175 =
|
|
m_pendInst_0[349];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_349_170_m_pendInst_ETC___d3175 =
|
|
m_pendInst_1[349];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_349_170_m_pendInst_ETC___d3175 =
|
|
m_pendInst_2[349];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_349_170_m_pendInst_ETC___d3175 =
|
|
m_pendInst_3[349];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_348_176_m_pendInst_ETC___d3181 =
|
|
m_pendInst_0[348];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_348_176_m_pendInst_ETC___d3181 =
|
|
m_pendInst_1[348];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_348_176_m_pendInst_ETC___d3181 =
|
|
m_pendInst_2[348];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_348_176_m_pendInst_ETC___d3181 =
|
|
m_pendInst_3[348];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_461_TO_458_997_m__ETC___d3002 =
|
|
m_pendInst_0[461:458];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_461_TO_458_997_m__ETC___d3002 =
|
|
m_pendInst_1[461:458];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_461_TO_458_997_m__ETC___d3002 =
|
|
m_pendInst_2[461:458];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_461_TO_458_997_m__ETC___d3002 =
|
|
m_pendInst_3[461:458];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_283_271_m_pendInst_ETC___d3276 =
|
|
m_pendInst_0[283];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_283_271_m_pendInst_ETC___d3276 =
|
|
m_pendInst_1[283];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_283_271_m_pendInst_ETC___d3276 =
|
|
m_pendInst_2[283];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_283_271_m_pendInst_ETC___d3276 =
|
|
m_pendInst_3[283];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_453_031_m_pendInst_ETC___d3036 =
|
|
m_pendInst_0[453];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_453_031_m_pendInst_ETC___d3036 =
|
|
m_pendInst_1[453];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_453_031_m_pendInst_ETC___d3036 =
|
|
m_pendInst_2[453];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_453_031_m_pendInst_ETC___d3036 =
|
|
m_pendInst_3[453];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_452_037_m_pendInst_ETC___d3042 =
|
|
m_pendInst_0[452];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_452_037_m_pendInst_ETC___d3042 =
|
|
m_pendInst_1[452];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_452_037_m_pendInst_ETC___d3042 =
|
|
m_pendInst_2[452];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_452_037_m_pendInst_ETC___d3042 =
|
|
m_pendInst_3[452];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_351_158_m_pendInst_ETC___d3163 =
|
|
m_pendInst_0[351];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_351_158_m_pendInst_ETC___d3163 =
|
|
m_pendInst_1[351];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_351_158_m_pendInst_ETC___d3163 =
|
|
m_pendInst_2[351];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_351_158_m_pendInst_ETC___d3163 =
|
|
m_pendInst_3[351];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_350_164_m_pendInst_ETC___d3169 =
|
|
m_pendInst_0[350];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_350_164_m_pendInst_ETC___d3169 =
|
|
m_pendInst_1[350];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_350_164_m_pendInst_ETC___d3169 =
|
|
m_pendInst_2[350];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_350_164_m_pendInst_ETC___d3169 =
|
|
m_pendInst_3[350];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_451_044_m_pendInst_ETC___d3049 =
|
|
m_pendInst_0[451];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_451_044_m_pendInst_ETC___d3049 =
|
|
m_pendInst_1[451];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_451_044_m_pendInst_ETC___d3049 =
|
|
m_pendInst_2[451];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_451_044_m_pendInst_ETC___d3049 =
|
|
m_pendInst_3[451];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_450_050_m_pendInst_ETC___d3055 =
|
|
m_pendInst_0[450];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_450_050_m_pendInst_ETC___d3055 =
|
|
m_pendInst_1[450];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_450_050_m_pendInst_ETC___d3055 =
|
|
m_pendInst_2[450];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_450_050_m_pendInst_ETC___d3055 =
|
|
m_pendInst_3[450];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_352_152_m_pendInst_ETC___d3157 =
|
|
m_pendInst_0[352];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_352_152_m_pendInst_ETC___d3157 =
|
|
m_pendInst_1[352];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_352_152_m_pendInst_ETC___d3157 =
|
|
m_pendInst_2[352];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_352_152_m_pendInst_ETC___d3157 =
|
|
m_pendInst_3[352];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_288_TO_286_253_m__ETC___d3258 =
|
|
m_pendInst_0[288:286];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_288_TO_286_253_m__ETC___d3258 =
|
|
m_pendInst_1[288:286];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_288_TO_286_253_m__ETC___d3258 =
|
|
m_pendInst_2[288:286];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_288_TO_286_253_m__ETC___d3258 =
|
|
m_pendInst_3[288:286];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_285_259_m_pendInst_ETC___d3264 =
|
|
m_pendInst_0[285];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_285_259_m_pendInst_ETC___d3264 =
|
|
m_pendInst_1[285];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_285_259_m_pendInst_ETC___d3264 =
|
|
m_pendInst_2[285];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_285_259_m_pendInst_ETC___d3264 =
|
|
m_pendInst_3[285];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_448_063_m_pendInst_ETC___d3068 =
|
|
m_pendInst_0[448];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_448_063_m_pendInst_ETC___d3068 =
|
|
m_pendInst_1[448];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_448_063_m_pendInst_ETC___d3068 =
|
|
m_pendInst_2[448];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_448_063_m_pendInst_ETC___d3068 =
|
|
m_pendInst_3[448];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_449_057_m_pendInst_ETC___d3062 =
|
|
m_pendInst_0[449];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_449_057_m_pendInst_ETC___d3062 =
|
|
m_pendInst_1[449];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_449_057_m_pendInst_ETC___d3062 =
|
|
m_pendInst_2[449];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_449_057_m_pendInst_ETC___d3062 =
|
|
m_pendInst_3[449];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_355_134_m_pendInst_ETC___d3139 =
|
|
m_pendInst_0[355];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_355_134_m_pendInst_ETC___d3139 =
|
|
m_pendInst_1[355];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_355_134_m_pendInst_ETC___d3139 =
|
|
m_pendInst_2[355];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_355_134_m_pendInst_ETC___d3139 =
|
|
m_pendInst_3[355];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_354_140_m_pendInst_ETC___d3145 =
|
|
m_pendInst_0[354];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_354_140_m_pendInst_ETC___d3145 =
|
|
m_pendInst_1[354];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_354_140_m_pendInst_ETC___d3145 =
|
|
m_pendInst_2[354];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_354_140_m_pendInst_ETC___d3145 =
|
|
m_pendInst_3[354];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_474_TO_470_967_m__ETC___d2972 =
|
|
m_pendInst_0[474:470];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_474_TO_470_967_m__ETC___d2972 =
|
|
m_pendInst_1[474:470];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_474_TO_470_967_m__ETC___d2972 =
|
|
m_pendInst_2[474:470];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_474_TO_470_967_m__ETC___d2972 =
|
|
m_pendInst_3[474:470];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_447_070_m_pendInst_ETC___d3075 =
|
|
m_pendInst_0[447];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_447_070_m_pendInst_ETC___d3075 =
|
|
m_pendInst_1[447];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_447_070_m_pendInst_ETC___d3075 =
|
|
m_pendInst_2[447];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_447_070_m_pendInst_ETC___d3075 =
|
|
m_pendInst_3[447];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_469_TO_464_973_m__ETC___d2978 =
|
|
m_pendInst_0[469:464];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_469_TO_464_973_m__ETC___d2978 =
|
|
m_pendInst_1[469:464];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_469_TO_464_973_m__ETC___d2978 =
|
|
m_pendInst_2[469:464];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_469_TO_464_973_m__ETC___d2978 =
|
|
m_pendInst_3[469:464];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_446_076_m_pendInst_ETC___d3081 =
|
|
m_pendInst_0[446];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_446_076_m_pendInst_ETC___d3081 =
|
|
m_pendInst_1[446];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_446_076_m_pendInst_ETC___d3081 =
|
|
m_pendInst_2[446];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_446_076_m_pendInst_ETC___d3081 =
|
|
m_pendInst_3[446];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_444_089_m_pendInst_ETC___d3094 =
|
|
m_pendInst_0[444];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_444_089_m_pendInst_ETC___d3094 =
|
|
m_pendInst_1[444];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_444_089_m_pendInst_ETC___d3094 =
|
|
m_pendInst_2[444];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_444_089_m_pendInst_ETC___d3094 =
|
|
m_pendInst_3[444];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_445_083_m_pendInst_ETC___d3088 =
|
|
m_pendInst_0[445];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_445_083_m_pendInst_ETC___d3088 =
|
|
m_pendInst_1[445];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_445_083_m_pendInst_ETC___d3088 =
|
|
m_pendInst_2[445];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_445_083_m_pendInst_ETC___d3088 =
|
|
m_pendInst_3[445];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_360_TO_357_122_m__ETC___d3127 =
|
|
m_pendInst_0[360:357];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_360_TO_357_122_m__ETC___d3127 =
|
|
m_pendInst_1[360:357];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_360_TO_357_122_m__ETC___d3127 =
|
|
m_pendInst_2[360:357];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_360_TO_357_122_m__ETC___d3127 =
|
|
m_pendInst_3[360:357];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_356_128_m_pendInst_ETC___d3133 =
|
|
m_pendInst_0[356];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_356_128_m_pendInst_ETC___d3133 =
|
|
m_pendInst_1[356];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_356_128_m_pendInst_ETC___d3133 =
|
|
m_pendInst_2[356];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_356_128_m_pendInst_ETC___d3133 =
|
|
m_pendInst_3[356];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_443_096_m_pendInst_ETC___d3101 =
|
|
m_pendInst_0[443];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_443_096_m_pendInst_ETC___d3101 =
|
|
m_pendInst_1[443];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_443_096_m_pendInst_ETC___d3101 =
|
|
m_pendInst_2[443];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_443_096_m_pendInst_ETC___d3101 =
|
|
m_pendInst_3[443];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_442_102_m_pendInst_ETC___d3107 =
|
|
m_pendInst_0[442];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_442_102_m_pendInst_ETC___d3107 =
|
|
m_pendInst_1[442];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_442_102_m_pendInst_ETC___d3107 =
|
|
m_pendInst_2[442];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_442_102_m_pendInst_ETC___d3107 =
|
|
m_pendInst_3[442];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_322_TO_317_230_m__ETC___d3235 =
|
|
m_pendInst_0[322:317];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_322_TO_317_230_m__ETC___d3235 =
|
|
m_pendInst_1[322:317];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_322_TO_317_230_m__ETC___d3235 =
|
|
m_pendInst_2[322:317];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_322_TO_317_230_m__ETC___d3235 =
|
|
m_pendInst_3[322:317];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_341_TO_324_218_m__ETC___d3223 =
|
|
m_pendInst_0[341:324];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_341_TO_324_218_m__ETC___d3223 =
|
|
m_pendInst_1[341:324];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_341_TO_324_218_m__ETC___d3223 =
|
|
m_pendInst_2[341:324];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_341_TO_324_218_m__ETC___d3223 =
|
|
m_pendInst_3[341:324];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_323_224_m_pendInst_ETC___d3229 =
|
|
m_pendInst_0[323];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_323_224_m_pendInst_ETC___d3229 =
|
|
m_pendInst_1[323];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_323_224_m_pendInst_ETC___d3229 =
|
|
m_pendInst_2[323];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_323_224_m_pendInst_ETC___d3229 =
|
|
m_pendInst_3[323];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_344_206_m_pendInst_ETC___d3211 =
|
|
m_pendInst_0[344];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_344_206_m_pendInst_ETC___d3211 =
|
|
m_pendInst_1[344];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_344_206_m_pendInst_ETC___d3211 =
|
|
m_pendInst_2[344];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_344_206_m_pendInst_ETC___d3211 =
|
|
m_pendInst_3[344];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_343_TO_342_212_m__ETC___d3217 =
|
|
m_pendInst_0[343:342];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_343_TO_342_212_m__ETC___d3217 =
|
|
m_pendInst_1[343:342];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_343_TO_342_212_m__ETC___d3217 =
|
|
m_pendInst_2[343:342];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_343_TO_342_212_m__ETC___d3217 =
|
|
m_pendInst_3[343:342];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_374_TO_361_116_m__ETC___d3121 =
|
|
m_pendInst_0[374:361];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_374_TO_361_116_m__ETC___d3121 =
|
|
m_pendInst_1[374:361];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_374_TO_361_116_m__ETC___d3121 =
|
|
m_pendInst_2[374:361];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_374_TO_361_116_m__ETC___d3121 =
|
|
m_pendInst_3[374:361];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_0_707_m_pendInst_1_ETC___d3712 =
|
|
m_pendInst_0[0];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_0_707_m_pendInst_1_ETC___d3712 =
|
|
m_pendInst_1[0];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_0_707_m_pendInst_1_ETC___d3712 =
|
|
m_pendInst_2[0];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_0_707_m_pendInst_1_ETC___d3712 =
|
|
m_pendInst_3[0];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_135_TO_130_689_m__ETC___d3694 =
|
|
m_pendInst_0[135:130];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_135_TO_130_689_m__ETC___d3694 =
|
|
m_pendInst_1[135:130];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_135_TO_130_689_m__ETC___d3694 =
|
|
m_pendInst_2[135:130];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_135_TO_130_689_m__ETC___d3694 =
|
|
m_pendInst_3[135:130];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_441_109_m_pendInst_ETC___d3114 =
|
|
m_pendInst_0[441];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_441_109_m_pendInst_ETC___d3114 =
|
|
m_pendInst_1[441];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_441_109_m_pendInst_ETC___d3114 =
|
|
m_pendInst_2[441];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_441_109_m_pendInst_ETC___d3114 =
|
|
m_pendInst_3[441];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_440_TO_375_705_m__ETC___d3115 =
|
|
m_pendInst_0[440:375];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_440_TO_375_705_m__ETC___d3115 =
|
|
m_pendInst_1[440:375];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_440_TO_375_705_m__ETC___d3115 =
|
|
m_pendInst_2[440:375];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_440_TO_375_705_m__ETC___d3115 =
|
|
m_pendInst_3[440:375];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BIT_278_292_m_pendInst_ETC___d3297 =
|
|
m_pendInst_0[278];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BIT_278_292_m_pendInst_ETC___d3297 =
|
|
m_pendInst_1[278];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BIT_278_292_m_pendInst_ETC___d3297 =
|
|
m_pendInst_2[278];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BIT_278_292_m_pendInst_ETC___d3297 =
|
|
m_pendInst_3[278];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d2960 =
|
|
m_pendInst_0[478:476];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d2960 =
|
|
m_pendInst_1[478:476];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d2960 =
|
|
m_pendInst_2[478:476];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_478_TO_476_85_m_p_ETC___d2960 =
|
|
m_pendInst_3[478:476];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_84_BITS_462_TO_458_991_m__ETC___d2996 =
|
|
m_pendInst_0[462:458];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_84_BITS_462_TO_458_991_m__ETC___d2996 =
|
|
m_pendInst_1[462:458];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_84_BITS_462_TO_458_991_m__ETC___d2996 =
|
|
m_pendInst_2[462:458];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_84_BITS_462_TO_458_991_m__ETC___d2996 =
|
|
m_pendInst_3[462:458];
|
|
endcase
|
|
end
|
|
always@(idx__h94435 or
|
|
m_pendSpecBits_0_rl or
|
|
m_pendSpecBits_1_rl or m_pendSpecBits_2_rl or m_pendSpecBits_3_rl)
|
|
begin
|
|
case (idx__h94435)
|
|
2'd0:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3722 =
|
|
m_pendSpecBits_0_rl;
|
|
2'd1:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3722 =
|
|
m_pendSpecBits_1_rl;
|
|
2'd2:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3722 =
|
|
m_pendSpecBits_2_rl;
|
|
2'd3:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3722 =
|
|
m_pendSpecBits_3_rl;
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or
|
|
m_rqToPQ_data_0 or
|
|
m_rqToPQ_data_1 or m_rqToPQ_data_2 or m_rqToPQ_data_3)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_28_TO_2_738_m_ETC___d3746 =
|
|
m_rqToPQ_data_0[28:2];
|
|
2'd1:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_28_TO_2_738_m_ETC___d3746 =
|
|
m_rqToPQ_data_1[28:2];
|
|
2'd2:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_28_TO_2_738_m_ETC___d3746 =
|
|
m_rqToPQ_data_2[28:2];
|
|
2'd3:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_28_TO_2_738_m_ETC___d3746 =
|
|
m_rqToPQ_data_3[28:2];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or
|
|
m_rqToPQ_data_0 or
|
|
m_rqToPQ_data_1 or m_rqToPQ_data_2 or m_rqToPQ_data_3)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_1_TO_0_747_m__ETC___d3752 =
|
|
m_rqToPQ_data_0[1:0];
|
|
2'd1:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_1_TO_0_747_m__ETC___d3752 =
|
|
m_rqToPQ_data_1[1:0];
|
|
2'd2:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_1_TO_0_747_m__ETC___d3752 =
|
|
m_rqToPQ_data_2[1:0];
|
|
2'd3:
|
|
SEL_ARR_m_rqToPQ_data_0_737_BITS_1_TO_0_747_m__ETC___d3752 =
|
|
m_rqToPQ_data_3[1:0];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_randIdx or INV_n__read0928__q35)
|
|
begin
|
|
case (m_tlb_m_randIdx)
|
|
5'd0:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[0];
|
|
5'd1:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[1];
|
|
5'd2:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[2];
|
|
5'd3:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[3];
|
|
5'd4:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[4];
|
|
5'd5:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[5];
|
|
5'd6:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[6];
|
|
5'd7:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[7];
|
|
5'd8:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[8];
|
|
5'd9:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[9];
|
|
5'd10:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[10];
|
|
5'd11:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[11];
|
|
5'd12:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[12];
|
|
5'd13:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[13];
|
|
5'd14:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[14];
|
|
5'd15:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[15];
|
|
5'd16:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[16];
|
|
5'd17:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[17];
|
|
5'd18:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[18];
|
|
5'd19:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[19];
|
|
5'd20:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[20];
|
|
5'd21:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[21];
|
|
5'd22:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[22];
|
|
5'd23:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[23];
|
|
5'd24:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[24];
|
|
5'd25:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[25];
|
|
5'd26:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[26];
|
|
5'd27:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[27];
|
|
5'd28:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[28];
|
|
5'd29:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[29];
|
|
5'd30:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[30];
|
|
5'd31:
|
|
CASE_m_tlb_m_randIdx_0_INV_n__read09285_BIT_0__ETC__q36 =
|
|
INV_n__read0928__q35[31];
|
|
endcase
|
|
end
|
|
always@(procReq_req)
|
|
begin
|
|
case (procReq_req[282:278])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q37 =
|
|
procReq_req[282:278];
|
|
default: CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q37 =
|
|
5'd27;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQInitIdx <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQInited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_data_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_2 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_3 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_freeQ_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 3'd2;
|
|
m_freeQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
83'h2AAAAAAAAAAAAAAAAAAA8;
|
|
m_ldTransRsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
83'h2AAAAAAAAAAAAAAAAAAA8;
|
|
m_ldTransRsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_ldTransRsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
84'h2AAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_needFlush <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendSpecBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendSpecBits_1_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendSpecBits_2_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendSpecBits_3_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendWait_0 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_pendWait_1 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_pendWait_2 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_pendWait_3 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_respForOtherReq <= `BSV_ASSIGNMENT_DELAY 3'd2;
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_2 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_3 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 30'd178956970;
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
m_tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
m_tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY 6'd10;
|
|
m_tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_vm_info <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
m_waitFlushP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_flushRqToPQ_clearReq_rl$EN)
|
|
m_flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_clearReq_rl$D_IN;
|
|
if (m_flushRqToPQ_deqReq_rl$EN)
|
|
m_flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_deqReq_rl$D_IN;
|
|
if (m_flushRqToPQ_empty$EN)
|
|
m_flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_empty$D_IN;
|
|
if (m_flushRqToPQ_enqReq_rl$EN)
|
|
m_flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_enqReq_rl$D_IN;
|
|
if (m_flushRqToPQ_full$EN)
|
|
m_flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_flushRqToPQ_full$D_IN;
|
|
if (m_flushRsFromPQ_clearReq_rl$EN)
|
|
m_flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_clearReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_deqReq_rl$EN)
|
|
m_flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_deqReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_empty$EN)
|
|
m_flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_empty$D_IN;
|
|
if (m_flushRsFromPQ_enqReq_rl$EN)
|
|
m_flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_enqReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_full$EN)
|
|
m_flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_full$D_IN;
|
|
if (m_freeQInitIdx$EN)
|
|
m_freeQInitIdx <= `BSV_ASSIGNMENT_DELAY m_freeQInitIdx$D_IN;
|
|
if (m_freeQInited$EN)
|
|
m_freeQInited <= `BSV_ASSIGNMENT_DELAY m_freeQInited$D_IN;
|
|
if (m_freeQ_clearReq_rl$EN)
|
|
m_freeQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_freeQ_clearReq_rl$D_IN;
|
|
if (m_freeQ_data_0$EN)
|
|
m_freeQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_0$D_IN;
|
|
if (m_freeQ_data_1$EN)
|
|
m_freeQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_1$D_IN;
|
|
if (m_freeQ_data_2$EN)
|
|
m_freeQ_data_2 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_2$D_IN;
|
|
if (m_freeQ_data_3$EN)
|
|
m_freeQ_data_3 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_3$D_IN;
|
|
if (m_freeQ_deqP$EN)
|
|
m_freeQ_deqP <= `BSV_ASSIGNMENT_DELAY m_freeQ_deqP$D_IN;
|
|
if (m_freeQ_deqReq_rl$EN)
|
|
m_freeQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_freeQ_deqReq_rl$D_IN;
|
|
if (m_freeQ_empty$EN)
|
|
m_freeQ_empty <= `BSV_ASSIGNMENT_DELAY m_freeQ_empty$D_IN;
|
|
if (m_freeQ_enqP$EN)
|
|
m_freeQ_enqP <= `BSV_ASSIGNMENT_DELAY m_freeQ_enqP$D_IN;
|
|
if (m_freeQ_enqReq_rl$EN)
|
|
m_freeQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_freeQ_enqReq_rl$D_IN;
|
|
if (m_freeQ_full$EN)
|
|
m_freeQ_full <= `BSV_ASSIGNMENT_DELAY m_freeQ_full$D_IN;
|
|
if (m_ldTransRsFromPQ_clearReq_rl$EN)
|
|
m_ldTransRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_clearReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_data_0$EN)
|
|
m_ldTransRsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_data_0$D_IN;
|
|
if (m_ldTransRsFromPQ_data_1$EN)
|
|
m_ldTransRsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_data_1$D_IN;
|
|
if (m_ldTransRsFromPQ_deqP$EN)
|
|
m_ldTransRsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_deqP$D_IN;
|
|
if (m_ldTransRsFromPQ_deqReq_rl$EN)
|
|
m_ldTransRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_deqReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_empty$EN)
|
|
m_ldTransRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_empty$D_IN;
|
|
if (m_ldTransRsFromPQ_enqP$EN)
|
|
m_ldTransRsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_enqP$D_IN;
|
|
if (m_ldTransRsFromPQ_enqReq_rl$EN)
|
|
m_ldTransRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_enqReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_full$EN)
|
|
m_ldTransRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_full$D_IN;
|
|
if (m_needFlush$EN)
|
|
m_needFlush <= `BSV_ASSIGNMENT_DELAY m_needFlush$D_IN;
|
|
if (m_pendSpecBits_0_rl$EN)
|
|
m_pendSpecBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_0_rl$D_IN;
|
|
if (m_pendSpecBits_1_rl$EN)
|
|
m_pendSpecBits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_1_rl$D_IN;
|
|
if (m_pendSpecBits_2_rl$EN)
|
|
m_pendSpecBits_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_2_rl$D_IN;
|
|
if (m_pendSpecBits_3_rl$EN)
|
|
m_pendSpecBits_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_3_rl$D_IN;
|
|
if (m_pendValid_0_rl$EN)
|
|
m_pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_0_rl$D_IN;
|
|
if (m_pendValid_1_rl$EN)
|
|
m_pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_1_rl$D_IN;
|
|
if (m_pendValid_2_rl$EN)
|
|
m_pendValid_2_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_2_rl$D_IN;
|
|
if (m_pendValid_3_rl$EN)
|
|
m_pendValid_3_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_3_rl$D_IN;
|
|
if (m_pendWait_0$EN)
|
|
m_pendWait_0 <= `BSV_ASSIGNMENT_DELAY m_pendWait_0$D_IN;
|
|
if (m_pendWait_1$EN)
|
|
m_pendWait_1 <= `BSV_ASSIGNMENT_DELAY m_pendWait_1$D_IN;
|
|
if (m_pendWait_2$EN)
|
|
m_pendWait_2 <= `BSV_ASSIGNMENT_DELAY m_pendWait_2$D_IN;
|
|
if (m_pendWait_3$EN)
|
|
m_pendWait_3 <= `BSV_ASSIGNMENT_DELAY m_pendWait_3$D_IN;
|
|
if (m_perfReqQ_clearReq_rl$EN)
|
|
m_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_clearReq_rl$D_IN;
|
|
if (m_perfReqQ_data_0$EN)
|
|
m_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_data_0$D_IN;
|
|
if (m_perfReqQ_deqReq_rl$EN)
|
|
m_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_deqReq_rl$D_IN;
|
|
if (m_perfReqQ_empty$EN)
|
|
m_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_empty$D_IN;
|
|
if (m_perfReqQ_enqReq_rl$EN)
|
|
m_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_enqReq_rl$D_IN;
|
|
if (m_perfReqQ_full$EN)
|
|
m_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_full$D_IN;
|
|
if (m_respForOtherReq$EN)
|
|
m_respForOtherReq <= `BSV_ASSIGNMENT_DELAY m_respForOtherReq$D_IN;
|
|
if (m_rqToPQ_clearReq_rl$EN)
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rqToPQ_clearReq_rl$D_IN;
|
|
if (m_rqToPQ_data_0$EN)
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_0$D_IN;
|
|
if (m_rqToPQ_data_1$EN)
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_1$D_IN;
|
|
if (m_rqToPQ_data_2$EN)
|
|
m_rqToPQ_data_2 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_2$D_IN;
|
|
if (m_rqToPQ_data_3$EN)
|
|
m_rqToPQ_data_3 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_3$D_IN;
|
|
if (m_rqToPQ_deqP$EN)
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqP$D_IN;
|
|
if (m_rqToPQ_deqReq_rl$EN)
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqReq_rl$D_IN;
|
|
if (m_rqToPQ_empty$EN)
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_empty$D_IN;
|
|
if (m_rqToPQ_enqP$EN)
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqP$D_IN;
|
|
if (m_rqToPQ_enqReq_rl$EN)
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqReq_rl$D_IN;
|
|
if (m_rqToPQ_full$EN)
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_full$D_IN;
|
|
if (m_tlb_m_lruBit_rl$EN)
|
|
m_tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY m_tlb_m_lruBit_rl$D_IN;
|
|
if (m_tlb_m_randIdx$EN)
|
|
m_tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY m_tlb_m_randIdx$D_IN;
|
|
if (m_tlb_m_updRepIdx_rl$EN)
|
|
m_tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_updRepIdx_rl$D_IN;
|
|
if (m_tlb_m_validVec_0$EN)
|
|
m_tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_0$D_IN;
|
|
if (m_tlb_m_validVec_1$EN)
|
|
m_tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_1$D_IN;
|
|
if (m_tlb_m_validVec_10$EN)
|
|
m_tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_10$D_IN;
|
|
if (m_tlb_m_validVec_11$EN)
|
|
m_tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_11$D_IN;
|
|
if (m_tlb_m_validVec_12$EN)
|
|
m_tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_12$D_IN;
|
|
if (m_tlb_m_validVec_13$EN)
|
|
m_tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_13$D_IN;
|
|
if (m_tlb_m_validVec_14$EN)
|
|
m_tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_14$D_IN;
|
|
if (m_tlb_m_validVec_15$EN)
|
|
m_tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_15$D_IN;
|
|
if (m_tlb_m_validVec_16$EN)
|
|
m_tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_16$D_IN;
|
|
if (m_tlb_m_validVec_17$EN)
|
|
m_tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_17$D_IN;
|
|
if (m_tlb_m_validVec_18$EN)
|
|
m_tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_18$D_IN;
|
|
if (m_tlb_m_validVec_19$EN)
|
|
m_tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_19$D_IN;
|
|
if (m_tlb_m_validVec_2$EN)
|
|
m_tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_2$D_IN;
|
|
if (m_tlb_m_validVec_20$EN)
|
|
m_tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_20$D_IN;
|
|
if (m_tlb_m_validVec_21$EN)
|
|
m_tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_21$D_IN;
|
|
if (m_tlb_m_validVec_22$EN)
|
|
m_tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_22$D_IN;
|
|
if (m_tlb_m_validVec_23$EN)
|
|
m_tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_23$D_IN;
|
|
if (m_tlb_m_validVec_24$EN)
|
|
m_tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_24$D_IN;
|
|
if (m_tlb_m_validVec_25$EN)
|
|
m_tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_25$D_IN;
|
|
if (m_tlb_m_validVec_26$EN)
|
|
m_tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_26$D_IN;
|
|
if (m_tlb_m_validVec_27$EN)
|
|
m_tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_27$D_IN;
|
|
if (m_tlb_m_validVec_28$EN)
|
|
m_tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_28$D_IN;
|
|
if (m_tlb_m_validVec_29$EN)
|
|
m_tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_29$D_IN;
|
|
if (m_tlb_m_validVec_3$EN)
|
|
m_tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_3$D_IN;
|
|
if (m_tlb_m_validVec_30$EN)
|
|
m_tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_30$D_IN;
|
|
if (m_tlb_m_validVec_31$EN)
|
|
m_tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_31$D_IN;
|
|
if (m_tlb_m_validVec_4$EN)
|
|
m_tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_4$D_IN;
|
|
if (m_tlb_m_validVec_5$EN)
|
|
m_tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_5$D_IN;
|
|
if (m_tlb_m_validVec_6$EN)
|
|
m_tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_6$D_IN;
|
|
if (m_tlb_m_validVec_7$EN)
|
|
m_tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_7$D_IN;
|
|
if (m_tlb_m_validVec_8$EN)
|
|
m_tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_8$D_IN;
|
|
if (m_tlb_m_validVec_9$EN)
|
|
m_tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_9$D_IN;
|
|
if (m_vm_info$EN) m_vm_info <= `BSV_ASSIGNMENT_DELAY m_vm_info$D_IN;
|
|
if (m_waitFlushP$EN)
|
|
m_waitFlushP <= `BSV_ASSIGNMENT_DELAY m_waitFlushP$D_IN;
|
|
end
|
|
if (m_pendInst_0$EN)
|
|
m_pendInst_0 <= `BSV_ASSIGNMENT_DELAY m_pendInst_0$D_IN;
|
|
if (m_pendInst_1$EN)
|
|
m_pendInst_1 <= `BSV_ASSIGNMENT_DELAY m_pendInst_1$D_IN;
|
|
if (m_pendInst_2$EN)
|
|
m_pendInst_2 <= `BSV_ASSIGNMENT_DELAY m_pendInst_2$D_IN;
|
|
if (m_pendInst_3$EN)
|
|
m_pendInst_3 <= `BSV_ASSIGNMENT_DELAY m_pendInst_3$D_IN;
|
|
if (m_pendPoisoned_0$EN)
|
|
m_pendPoisoned_0 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_0$D_IN;
|
|
if (m_pendPoisoned_1$EN)
|
|
m_pendPoisoned_1 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_1$D_IN;
|
|
if (m_pendPoisoned_2$EN)
|
|
m_pendPoisoned_2 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_2$D_IN;
|
|
if (m_pendPoisoned_3$EN)
|
|
m_pendPoisoned_3 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_3$D_IN;
|
|
if (m_pendResp_0$EN)
|
|
m_pendResp_0 <= `BSV_ASSIGNMENT_DELAY m_pendResp_0$D_IN;
|
|
if (m_pendResp_1$EN)
|
|
m_pendResp_1 <= `BSV_ASSIGNMENT_DELAY m_pendResp_1$D_IN;
|
|
if (m_pendResp_2$EN)
|
|
m_pendResp_2 <= `BSV_ASSIGNMENT_DELAY m_pendResp_2$D_IN;
|
|
if (m_pendResp_3$EN)
|
|
m_pendResp_3 <= `BSV_ASSIGNMENT_DELAY m_pendResp_3$D_IN;
|
|
if (m_tlb_m_entryVec_0$EN)
|
|
m_tlb_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_0$D_IN;
|
|
if (m_tlb_m_entryVec_1$EN)
|
|
m_tlb_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_1$D_IN;
|
|
if (m_tlb_m_entryVec_10$EN)
|
|
m_tlb_m_entryVec_10 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_10$D_IN;
|
|
if (m_tlb_m_entryVec_11$EN)
|
|
m_tlb_m_entryVec_11 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_11$D_IN;
|
|
if (m_tlb_m_entryVec_12$EN)
|
|
m_tlb_m_entryVec_12 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_12$D_IN;
|
|
if (m_tlb_m_entryVec_13$EN)
|
|
m_tlb_m_entryVec_13 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_13$D_IN;
|
|
if (m_tlb_m_entryVec_14$EN)
|
|
m_tlb_m_entryVec_14 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_14$D_IN;
|
|
if (m_tlb_m_entryVec_15$EN)
|
|
m_tlb_m_entryVec_15 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_15$D_IN;
|
|
if (m_tlb_m_entryVec_16$EN)
|
|
m_tlb_m_entryVec_16 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_16$D_IN;
|
|
if (m_tlb_m_entryVec_17$EN)
|
|
m_tlb_m_entryVec_17 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_17$D_IN;
|
|
if (m_tlb_m_entryVec_18$EN)
|
|
m_tlb_m_entryVec_18 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_18$D_IN;
|
|
if (m_tlb_m_entryVec_19$EN)
|
|
m_tlb_m_entryVec_19 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_19$D_IN;
|
|
if (m_tlb_m_entryVec_2$EN)
|
|
m_tlb_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_2$D_IN;
|
|
if (m_tlb_m_entryVec_20$EN)
|
|
m_tlb_m_entryVec_20 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_20$D_IN;
|
|
if (m_tlb_m_entryVec_21$EN)
|
|
m_tlb_m_entryVec_21 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_21$D_IN;
|
|
if (m_tlb_m_entryVec_22$EN)
|
|
m_tlb_m_entryVec_22 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_22$D_IN;
|
|
if (m_tlb_m_entryVec_23$EN)
|
|
m_tlb_m_entryVec_23 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_23$D_IN;
|
|
if (m_tlb_m_entryVec_24$EN)
|
|
m_tlb_m_entryVec_24 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_24$D_IN;
|
|
if (m_tlb_m_entryVec_25$EN)
|
|
m_tlb_m_entryVec_25 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_25$D_IN;
|
|
if (m_tlb_m_entryVec_26$EN)
|
|
m_tlb_m_entryVec_26 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_26$D_IN;
|
|
if (m_tlb_m_entryVec_27$EN)
|
|
m_tlb_m_entryVec_27 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_27$D_IN;
|
|
if (m_tlb_m_entryVec_28$EN)
|
|
m_tlb_m_entryVec_28 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_28$D_IN;
|
|
if (m_tlb_m_entryVec_29$EN)
|
|
m_tlb_m_entryVec_29 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_29$D_IN;
|
|
if (m_tlb_m_entryVec_3$EN)
|
|
m_tlb_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_3$D_IN;
|
|
if (m_tlb_m_entryVec_30$EN)
|
|
m_tlb_m_entryVec_30 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_30$D_IN;
|
|
if (m_tlb_m_entryVec_31$EN)
|
|
m_tlb_m_entryVec_31 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_31$D_IN;
|
|
if (m_tlb_m_entryVec_4$EN)
|
|
m_tlb_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_4$D_IN;
|
|
if (m_tlb_m_entryVec_5$EN)
|
|
m_tlb_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_5$D_IN;
|
|
if (m_tlb_m_entryVec_6$EN)
|
|
m_tlb_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_6$D_IN;
|
|
if (m_tlb_m_entryVec_7$EN)
|
|
m_tlb_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_7$D_IN;
|
|
if (m_tlb_m_entryVec_8$EN)
|
|
m_tlb_m_entryVec_8 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_8$D_IN;
|
|
if (m_tlb_m_entryVec_9$EN)
|
|
m_tlb_m_entryVec_9 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_9$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_flushRqToPQ_clearReq_rl = 1'h0;
|
|
m_flushRqToPQ_deqReq_rl = 1'h0;
|
|
m_flushRqToPQ_empty = 1'h0;
|
|
m_flushRqToPQ_enqReq_rl = 1'h0;
|
|
m_flushRqToPQ_full = 1'h0;
|
|
m_flushRsFromPQ_clearReq_rl = 1'h0;
|
|
m_flushRsFromPQ_deqReq_rl = 1'h0;
|
|
m_flushRsFromPQ_empty = 1'h0;
|
|
m_flushRsFromPQ_enqReq_rl = 1'h0;
|
|
m_flushRsFromPQ_full = 1'h0;
|
|
m_freeQInitIdx = 2'h2;
|
|
m_freeQInited = 1'h0;
|
|
m_freeQ_clearReq_rl = 1'h0;
|
|
m_freeQ_data_0 = 2'h2;
|
|
m_freeQ_data_1 = 2'h2;
|
|
m_freeQ_data_2 = 2'h2;
|
|
m_freeQ_data_3 = 2'h2;
|
|
m_freeQ_deqP = 2'h2;
|
|
m_freeQ_deqReq_rl = 1'h0;
|
|
m_freeQ_empty = 1'h0;
|
|
m_freeQ_enqP = 2'h2;
|
|
m_freeQ_enqReq_rl = 3'h2;
|
|
m_freeQ_full = 1'h0;
|
|
m_ldTransRsFromPQ_clearReq_rl = 1'h0;
|
|
m_ldTransRsFromPQ_data_0 = 83'h2AAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_data_1 = 83'h2AAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_deqP = 1'h0;
|
|
m_ldTransRsFromPQ_deqReq_rl = 1'h0;
|
|
m_ldTransRsFromPQ_empty = 1'h0;
|
|
m_ldTransRsFromPQ_enqP = 1'h0;
|
|
m_ldTransRsFromPQ_enqReq_rl = 84'hAAAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_full = 1'h0;
|
|
m_needFlush = 1'h0;
|
|
m_pendInst_0 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendInst_1 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendInst_2 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendInst_3 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendPoisoned_0 = 1'h0;
|
|
m_pendPoisoned_1 = 1'h0;
|
|
m_pendPoisoned_2 = 1'h0;
|
|
m_pendPoisoned_3 = 1'h0;
|
|
m_pendResp_0 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_1 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_2 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_3 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendSpecBits_0_rl = 12'hAAA;
|
|
m_pendSpecBits_1_rl = 12'hAAA;
|
|
m_pendSpecBits_2_rl = 12'hAAA;
|
|
m_pendSpecBits_3_rl = 12'hAAA;
|
|
m_pendValid_0_rl = 1'h0;
|
|
m_pendValid_1_rl = 1'h0;
|
|
m_pendValid_2_rl = 1'h0;
|
|
m_pendValid_3_rl = 1'h0;
|
|
m_pendWait_0 = 4'hA;
|
|
m_pendWait_1 = 4'hA;
|
|
m_pendWait_2 = 4'hA;
|
|
m_pendWait_3 = 4'hA;
|
|
m_perfReqQ_clearReq_rl = 1'h0;
|
|
m_perfReqQ_data_0 = 3'h2;
|
|
m_perfReqQ_deqReq_rl = 1'h0;
|
|
m_perfReqQ_empty = 1'h0;
|
|
m_perfReqQ_enqReq_rl = 4'hA;
|
|
m_perfReqQ_full = 1'h0;
|
|
m_respForOtherReq = 3'h2;
|
|
m_rqToPQ_clearReq_rl = 1'h0;
|
|
m_rqToPQ_data_0 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_1 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_2 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_3 = 29'h0AAAAAAA;
|
|
m_rqToPQ_deqP = 2'h2;
|
|
m_rqToPQ_deqReq_rl = 1'h0;
|
|
m_rqToPQ_empty = 1'h0;
|
|
m_rqToPQ_enqP = 2'h2;
|
|
m_rqToPQ_enqReq_rl = 30'h2AAAAAAA;
|
|
m_rqToPQ_full = 1'h0;
|
|
m_tlb_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_10 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_11 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_12 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_13 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_14 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_15 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_16 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_17 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_18 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_19 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_20 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_21 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_22 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_23 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_24 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_25 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_26 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_27 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_28 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_29 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_30 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_31 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_8 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_9 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_lruBit_rl = 32'hAAAAAAAA;
|
|
m_tlb_m_randIdx = 5'h0A;
|
|
m_tlb_m_updRepIdx_rl = 6'h2A;
|
|
m_tlb_m_validVec_0 = 1'h0;
|
|
m_tlb_m_validVec_1 = 1'h0;
|
|
m_tlb_m_validVec_10 = 1'h0;
|
|
m_tlb_m_validVec_11 = 1'h0;
|
|
m_tlb_m_validVec_12 = 1'h0;
|
|
m_tlb_m_validVec_13 = 1'h0;
|
|
m_tlb_m_validVec_14 = 1'h0;
|
|
m_tlb_m_validVec_15 = 1'h0;
|
|
m_tlb_m_validVec_16 = 1'h0;
|
|
m_tlb_m_validVec_17 = 1'h0;
|
|
m_tlb_m_validVec_18 = 1'h0;
|
|
m_tlb_m_validVec_19 = 1'h0;
|
|
m_tlb_m_validVec_2 = 1'h0;
|
|
m_tlb_m_validVec_20 = 1'h0;
|
|
m_tlb_m_validVec_21 = 1'h0;
|
|
m_tlb_m_validVec_22 = 1'h0;
|
|
m_tlb_m_validVec_23 = 1'h0;
|
|
m_tlb_m_validVec_24 = 1'h0;
|
|
m_tlb_m_validVec_25 = 1'h0;
|
|
m_tlb_m_validVec_26 = 1'h0;
|
|
m_tlb_m_validVec_27 = 1'h0;
|
|
m_tlb_m_validVec_28 = 1'h0;
|
|
m_tlb_m_validVec_29 = 1'h0;
|
|
m_tlb_m_validVec_3 = 1'h0;
|
|
m_tlb_m_validVec_30 = 1'h0;
|
|
m_tlb_m_validVec_31 = 1'h0;
|
|
m_tlb_m_validVec_4 = 1'h0;
|
|
m_tlb_m_validVec_5 = 1'h0;
|
|
m_tlb_m_validVec_6 = 1'h0;
|
|
m_tlb_m_validVec_7 = 1'h0;
|
|
m_tlb_m_validVec_8 = 1'h0;
|
|
m_tlb_m_validVec_9 = 1'h0;
|
|
m_vm_info = 49'h0AAAAAAAAAAAA;
|
|
m_waitFlushP = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkDTlbSynth
|
|
|