840 lines
30 KiB
Verilog
840 lines
30 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Mon Jul 13 18:46:53 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// getEmptyEntryInit O 2 reg
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// RDY_getEmptyEntryInit O 1
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// sendRsToP_pRq_getRq O 66
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// RDY_sendRsToP_pRq_getRq O 1 const
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// RDY_sendRsToP_pRq_releaseEntry O 1
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// pipelineResp_getRq O 66
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// RDY_pipelineResp_getRq O 1 const
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// RDY_pipelineResp_releaseEntry O 1
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// RDY_pipelineResp_setDone O 1 const
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// stuck_get O 68 const
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// RDY_stuck_get O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// getEmptyEntryInit_r I 66
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// sendRsToP_pRq_getRq_n I 2
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// sendRsToP_pRq_releaseEntry_n I 2
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// pipelineResp_getRq_n I 2
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// pipelineResp_releaseEntry_n I 2
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// pipelineResp_setDone_n I 2
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// EN_sendRsToP_pRq_releaseEntry I 1
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// EN_pipelineResp_releaseEntry I 1
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// EN_pipelineResp_setDone I 1
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// EN_getEmptyEntryInit I 1
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// EN_stuck_get I 1 unused
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//
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// Combinational paths from inputs to outputs:
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// sendRsToP_pRq_getRq_n -> sendRsToP_pRq_getRq
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// pipelineResp_getRq_n -> pipelineResp_getRq
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkIPRqMshrWrapper(CLK,
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RST_N,
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getEmptyEntryInit_r,
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EN_getEmptyEntryInit,
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getEmptyEntryInit,
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RDY_getEmptyEntryInit,
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sendRsToP_pRq_getRq_n,
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sendRsToP_pRq_getRq,
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RDY_sendRsToP_pRq_getRq,
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sendRsToP_pRq_releaseEntry_n,
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EN_sendRsToP_pRq_releaseEntry,
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RDY_sendRsToP_pRq_releaseEntry,
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pipelineResp_getRq_n,
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pipelineResp_getRq,
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RDY_pipelineResp_getRq,
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pipelineResp_releaseEntry_n,
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EN_pipelineResp_releaseEntry,
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RDY_pipelineResp_releaseEntry,
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pipelineResp_setDone_n,
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EN_pipelineResp_setDone,
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RDY_pipelineResp_setDone,
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EN_stuck_get,
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stuck_get,
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RDY_stuck_get);
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input CLK;
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input RST_N;
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// actionvalue method getEmptyEntryInit
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input [65 : 0] getEmptyEntryInit_r;
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input EN_getEmptyEntryInit;
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output [1 : 0] getEmptyEntryInit;
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output RDY_getEmptyEntryInit;
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// value method sendRsToP_pRq_getRq
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input [1 : 0] sendRsToP_pRq_getRq_n;
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output [65 : 0] sendRsToP_pRq_getRq;
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output RDY_sendRsToP_pRq_getRq;
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// action method sendRsToP_pRq_releaseEntry
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input [1 : 0] sendRsToP_pRq_releaseEntry_n;
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input EN_sendRsToP_pRq_releaseEntry;
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output RDY_sendRsToP_pRq_releaseEntry;
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// value method pipelineResp_getRq
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input [1 : 0] pipelineResp_getRq_n;
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output [65 : 0] pipelineResp_getRq;
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output RDY_pipelineResp_getRq;
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// action method pipelineResp_releaseEntry
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input [1 : 0] pipelineResp_releaseEntry_n;
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input EN_pipelineResp_releaseEntry;
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output RDY_pipelineResp_releaseEntry;
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// action method pipelineResp_setDone
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input [1 : 0] pipelineResp_setDone_n;
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input EN_pipelineResp_setDone;
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output RDY_pipelineResp_setDone;
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// actionvalue method stuck_get
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input EN_stuck_get;
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output [67 : 0] stuck_get;
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output RDY_stuck_get;
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// signals for module outputs
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wire [67 : 0] stuck_get;
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wire [65 : 0] pipelineResp_getRq, sendRsToP_pRq_getRq;
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wire [1 : 0] getEmptyEntryInit;
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wire RDY_getEmptyEntryInit,
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RDY_pipelineResp_getRq,
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RDY_pipelineResp_releaseEntry,
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RDY_pipelineResp_setDone,
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RDY_sendRsToP_pRq_getRq,
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RDY_sendRsToP_pRq_releaseEntry,
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RDY_stuck_get;
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// inlined wires
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wire [1 : 0] m_m_stateVec_0_lat_0$wget,
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m_m_stateVec_1_lat_0$wget,
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m_m_stateVec_2_lat_0$wget,
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m_m_stateVec_3_lat_0$wget;
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wire m_m_stateVec_0_lat_0$whas,
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m_m_stateVec_0_lat_1$whas,
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m_m_stateVec_0_lat_2$whas,
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m_m_stateVec_1_lat_0$whas,
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m_m_stateVec_1_lat_1$whas,
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m_m_stateVec_1_lat_2$whas,
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m_m_stateVec_2_lat_0$whas,
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m_m_stateVec_2_lat_1$whas,
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m_m_stateVec_2_lat_2$whas,
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m_m_stateVec_3_lat_0$whas,
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m_m_stateVec_3_lat_1$whas,
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m_m_stateVec_3_lat_2$whas;
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// register m_m_initIdx
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reg [1 : 0] m_m_initIdx;
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wire [1 : 0] m_m_initIdx$D_IN;
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wire m_m_initIdx$EN;
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// register m_m_inited
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reg m_m_inited;
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wire m_m_inited$D_IN, m_m_inited$EN;
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// register m_m_releaseEntryQ_pipelineResp_data_0_rl
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reg [1 : 0] m_m_releaseEntryQ_pipelineResp_data_0_rl;
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wire [1 : 0] m_m_releaseEntryQ_pipelineResp_data_0_rl$D_IN;
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wire m_m_releaseEntryQ_pipelineResp_data_0_rl$EN;
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// register m_m_releaseEntryQ_pipelineResp_empty_rl
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reg m_m_releaseEntryQ_pipelineResp_empty_rl;
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wire m_m_releaseEntryQ_pipelineResp_empty_rl$D_IN,
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m_m_releaseEntryQ_pipelineResp_empty_rl$EN;
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// register m_m_releaseEntryQ_pipelineResp_full_rl
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reg m_m_releaseEntryQ_pipelineResp_full_rl;
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wire m_m_releaseEntryQ_pipelineResp_full_rl$D_IN,
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m_m_releaseEntryQ_pipelineResp_full_rl$EN;
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// register m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl
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reg [1 : 0] m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl;
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wire [1 : 0] m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$D_IN;
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wire m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$EN;
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// register m_m_releaseEntryQ_sendRsToP_pRq_empty_rl
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reg m_m_releaseEntryQ_sendRsToP_pRq_empty_rl;
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wire m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$D_IN,
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m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$EN;
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// register m_m_releaseEntryQ_sendRsToP_pRq_full_rl
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reg m_m_releaseEntryQ_sendRsToP_pRq_full_rl;
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wire m_m_releaseEntryQ_sendRsToP_pRq_full_rl$D_IN,
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m_m_releaseEntryQ_sendRsToP_pRq_full_rl$EN;
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// register m_m_reqVec_0_rl
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reg [65 : 0] m_m_reqVec_0_rl;
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wire [65 : 0] m_m_reqVec_0_rl$D_IN;
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wire m_m_reqVec_0_rl$EN;
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// register m_m_reqVec_1_rl
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reg [65 : 0] m_m_reqVec_1_rl;
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wire [65 : 0] m_m_reqVec_1_rl$D_IN;
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wire m_m_reqVec_1_rl$EN;
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// register m_m_reqVec_2_rl
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reg [65 : 0] m_m_reqVec_2_rl;
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wire [65 : 0] m_m_reqVec_2_rl$D_IN;
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wire m_m_reqVec_2_rl$EN;
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// register m_m_reqVec_3_rl
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reg [65 : 0] m_m_reqVec_3_rl;
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wire [65 : 0] m_m_reqVec_3_rl$D_IN;
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wire m_m_reqVec_3_rl$EN;
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// register m_m_stateVec_0_rl
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reg [1 : 0] m_m_stateVec_0_rl;
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wire [1 : 0] m_m_stateVec_0_rl$D_IN;
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wire m_m_stateVec_0_rl$EN;
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// register m_m_stateVec_1_rl
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reg [1 : 0] m_m_stateVec_1_rl;
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wire [1 : 0] m_m_stateVec_1_rl$D_IN;
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wire m_m_stateVec_1_rl$EN;
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// register m_m_stateVec_2_rl
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reg [1 : 0] m_m_stateVec_2_rl;
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wire [1 : 0] m_m_stateVec_2_rl$D_IN;
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wire m_m_stateVec_2_rl$EN;
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// register m_m_stateVec_3_rl
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reg [1 : 0] m_m_stateVec_3_rl;
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wire [1 : 0] m_m_stateVec_3_rl$D_IN;
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wire m_m_stateVec_3_rl$EN;
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// ports of submodule m_m_emptyEntryQ
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reg [1 : 0] m_m_emptyEntryQ$D_IN;
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wire [1 : 0] m_m_emptyEntryQ$D_OUT;
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wire m_m_emptyEntryQ$CLR,
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m_m_emptyEntryQ$DEQ,
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m_m_emptyEntryQ$EMPTY_N,
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m_m_emptyEntryQ$ENQ,
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m_m_emptyEntryQ$FULL_N;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_doReleaseEntry_pipelineResp,
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CAN_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq,
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CAN_FIRE_RL_m_m_initEmptyEntry,
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CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon,
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CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon,
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CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon,
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CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon,
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CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon,
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CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon,
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CAN_FIRE_RL_m_m_reqVec_0_canon,
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CAN_FIRE_RL_m_m_reqVec_1_canon,
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CAN_FIRE_RL_m_m_reqVec_2_canon,
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CAN_FIRE_RL_m_m_reqVec_3_canon,
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CAN_FIRE_RL_m_m_stateVec_0_canon,
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CAN_FIRE_RL_m_m_stateVec_1_canon,
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CAN_FIRE_RL_m_m_stateVec_2_canon,
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CAN_FIRE_RL_m_m_stateVec_3_canon,
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CAN_FIRE_getEmptyEntryInit,
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CAN_FIRE_pipelineResp_releaseEntry,
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CAN_FIRE_pipelineResp_setDone,
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CAN_FIRE_sendRsToP_pRq_releaseEntry,
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CAN_FIRE_stuck_get,
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WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp,
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WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq,
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WILL_FIRE_RL_m_m_initEmptyEntry,
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WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon,
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WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon,
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WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon,
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WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon,
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WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon,
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WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon,
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WILL_FIRE_RL_m_m_reqVec_0_canon,
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WILL_FIRE_RL_m_m_reqVec_1_canon,
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WILL_FIRE_RL_m_m_reqVec_2_canon,
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WILL_FIRE_RL_m_m_reqVec_3_canon,
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WILL_FIRE_RL_m_m_stateVec_0_canon,
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WILL_FIRE_RL_m_m_stateVec_1_canon,
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WILL_FIRE_RL_m_m_stateVec_2_canon,
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WILL_FIRE_RL_m_m_stateVec_3_canon,
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WILL_FIRE_getEmptyEntryInit,
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WILL_FIRE_pipelineResp_releaseEntry,
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WILL_FIRE_pipelineResp_setDone,
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WILL_FIRE_sendRsToP_pRq_releaseEntry,
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WILL_FIRE_stuck_get;
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// inputs to muxes for submodule ports
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wire [1 : 0] MUX_m_m_emptyEntryQ$enq_1__VAL_2,
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MUX_m_m_emptyEntryQ$enq_1__VAL_3;
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wire MUX_m_m_emptyEntryQ$enq_1__SEL_2,
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MUX_m_m_stateVec_0_lat_0$wset_1__SEL_1,
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MUX_m_m_stateVec_1_lat_0$wset_1__SEL_1,
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MUX_m_m_stateVec_2_lat_0$wset_1__SEL_1,
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MUX_m_m_stateVec_3_lat_0$wset_1__SEL_1;
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// remaining internal signals
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reg [63 : 0] SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d171,
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SEL_ARR_m_m_reqVec_0_rl_7_BITS_65_TO_2_59_m_m__ETC___d192;
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reg [1 : 0] SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d185,
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SEL_ARR_m_m_reqVec_0_rl_7_BITS_1_TO_0_73_m_m_r_ETC___d194;
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wire [1 : 0] IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9,
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IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19,
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IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29,
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IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39,
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v__h10232,
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v__h9493;
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// actionvalue method getEmptyEntryInit
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assign getEmptyEntryInit = m_m_emptyEntryQ$D_OUT ;
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assign RDY_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
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assign CAN_FIRE_getEmptyEntryInit = m_m_inited && m_m_emptyEntryQ$EMPTY_N ;
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assign WILL_FIRE_getEmptyEntryInit = EN_getEmptyEntryInit ;
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// value method sendRsToP_pRq_getRq
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assign sendRsToP_pRq_getRq =
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{ SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d171,
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SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d185 } ;
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assign RDY_sendRsToP_pRq_getRq = 1'd1 ;
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// action method sendRsToP_pRq_releaseEntry
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assign RDY_sendRsToP_pRq_releaseEntry =
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!m_m_releaseEntryQ_sendRsToP_pRq_full_rl && m_m_inited ;
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assign CAN_FIRE_sendRsToP_pRq_releaseEntry =
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!m_m_releaseEntryQ_sendRsToP_pRq_full_rl && m_m_inited ;
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assign WILL_FIRE_sendRsToP_pRq_releaseEntry =
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EN_sendRsToP_pRq_releaseEntry ;
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// value method pipelineResp_getRq
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assign pipelineResp_getRq =
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{ SEL_ARR_m_m_reqVec_0_rl_7_BITS_65_TO_2_59_m_m__ETC___d192,
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SEL_ARR_m_m_reqVec_0_rl_7_BITS_1_TO_0_73_m_m_r_ETC___d194 } ;
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assign RDY_pipelineResp_getRq = 1'd1 ;
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// action method pipelineResp_releaseEntry
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assign RDY_pipelineResp_releaseEntry =
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!m_m_releaseEntryQ_pipelineResp_full_rl && m_m_inited ;
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assign CAN_FIRE_pipelineResp_releaseEntry =
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!m_m_releaseEntryQ_pipelineResp_full_rl && m_m_inited ;
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assign WILL_FIRE_pipelineResp_releaseEntry = EN_pipelineResp_releaseEntry ;
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// action method pipelineResp_setDone
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assign RDY_pipelineResp_setDone = 1'd1 ;
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assign CAN_FIRE_pipelineResp_setDone = 1'd1 ;
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assign WILL_FIRE_pipelineResp_setDone = EN_pipelineResp_setDone ;
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// actionvalue method stuck_get
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assign stuck_get = 68'hAAAAAAAAAAAAAAAAA ;
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assign RDY_stuck_get = 1'd0 ;
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assign CAN_FIRE_stuck_get = 1'd0 ;
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assign WILL_FIRE_stuck_get = EN_stuck_get ;
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// submodule m_m_emptyEntryQ
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SizedFIFO #(.p1width(32'd2),
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.p2depth(32'd4),
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.p3cntr_width(32'd2),
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.guarded(32'd1)) m_m_emptyEntryQ(.RST(RST_N),
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.CLK(CLK),
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.D_IN(m_m_emptyEntryQ$D_IN),
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.ENQ(m_m_emptyEntryQ$ENQ),
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.DEQ(m_m_emptyEntryQ$DEQ),
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.CLR(m_m_emptyEntryQ$CLR),
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.D_OUT(m_m_emptyEntryQ$D_OUT),
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.FULL_N(m_m_emptyEntryQ$FULL_N),
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.EMPTY_N(m_m_emptyEntryQ$EMPTY_N));
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// rule RL_m_m_initEmptyEntry
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assign CAN_FIRE_RL_m_m_initEmptyEntry =
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m_m_emptyEntryQ$FULL_N && !m_m_inited ;
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assign WILL_FIRE_RL_m_m_initEmptyEntry = CAN_FIRE_RL_m_m_initEmptyEntry ;
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// rule RL_m_m_doReleaseEntry_sendRsToP_pRq
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assign CAN_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq =
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MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
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assign WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq =
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MUX_m_m_emptyEntryQ$enq_1__SEL_2 ;
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// rule RL_m_m_doReleaseEntry_pipelineResp
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assign CAN_FIRE_RL_m_m_doReleaseEntry_pipelineResp =
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(EN_pipelineResp_releaseEntry ||
|
|
!m_m_releaseEntryQ_pipelineResp_empty_rl) &&
|
|
m_m_emptyEntryQ$FULL_N &&
|
|
m_m_inited ;
|
|
assign WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp =
|
|
CAN_FIRE_RL_m_m_doReleaseEntry_pipelineResp &&
|
|
!WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq ;
|
|
|
|
// rule RL_m_m_stateVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_stateVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_stateVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_0_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_1_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_2_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_reqVec_3_canon
|
|
assign CAN_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_reqVec_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_sendRsToP_pRq_full_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_pipelineResp_data_0_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_data_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_pipelineResp_empty_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_empty_canon = 1'd1 ;
|
|
|
|
// rule RL_m_m_releaseEntryQ_pipelineResp_full_canon
|
|
assign CAN_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_m_releaseEntryQ_pipelineResp_full_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_m_emptyEntryQ$enq_1__SEL_2 =
|
|
(EN_sendRsToP_pRq_releaseEntry ||
|
|
!m_m_releaseEntryQ_sendRsToP_pRq_empty_rl) &&
|
|
m_m_emptyEntryQ$FULL_N &&
|
|
m_m_inited ;
|
|
assign MUX_m_m_stateVec_0_lat_0$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd0 ;
|
|
assign MUX_m_m_stateVec_1_lat_0$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd1 ;
|
|
assign MUX_m_m_stateVec_2_lat_0$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd2 ;
|
|
assign MUX_m_m_stateVec_3_lat_0$wset_1__SEL_1 =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd3 ;
|
|
assign MUX_m_m_emptyEntryQ$enq_1__VAL_2 =
|
|
EN_sendRsToP_pRq_releaseEntry ?
|
|
sendRsToP_pRq_releaseEntry_n :
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl ;
|
|
assign MUX_m_m_emptyEntryQ$enq_1__VAL_3 =
|
|
EN_pipelineResp_releaseEntry ?
|
|
pipelineResp_releaseEntry_n :
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl ;
|
|
|
|
// inlined wires
|
|
assign m_m_stateVec_0_lat_0$wget =
|
|
MUX_m_m_stateVec_0_lat_0$wset_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_0_lat_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd0 ||
|
|
EN_pipelineResp_setDone && pipelineResp_setDone_n == 2'd0 ;
|
|
assign m_m_stateVec_0_lat_1$whas =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd0 ;
|
|
assign m_m_stateVec_0_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd0 ;
|
|
assign m_m_stateVec_1_lat_0$wget =
|
|
MUX_m_m_stateVec_1_lat_0$wset_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_1_lat_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd1 ||
|
|
EN_pipelineResp_setDone && pipelineResp_setDone_n == 2'd1 ;
|
|
assign m_m_stateVec_1_lat_1$whas =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd1 ;
|
|
assign m_m_stateVec_1_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd1 ;
|
|
assign m_m_stateVec_2_lat_0$wget =
|
|
MUX_m_m_stateVec_2_lat_0$wset_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_2_lat_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd2 ||
|
|
EN_pipelineResp_setDone && pipelineResp_setDone_n == 2'd2 ;
|
|
assign m_m_stateVec_2_lat_1$whas =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd2 ;
|
|
assign m_m_stateVec_2_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd2 ;
|
|
assign m_m_stateVec_3_lat_0$wget =
|
|
MUX_m_m_stateVec_3_lat_0$wset_1__SEL_1 ? 2'd0 : 2'd2 ;
|
|
assign m_m_stateVec_3_lat_0$whas =
|
|
EN_pipelineResp_releaseEntry &&
|
|
pipelineResp_releaseEntry_n == 2'd3 ||
|
|
EN_pipelineResp_setDone && pipelineResp_setDone_n == 2'd3 ;
|
|
assign m_m_stateVec_3_lat_1$whas =
|
|
EN_sendRsToP_pRq_releaseEntry &&
|
|
sendRsToP_pRq_releaseEntry_n == 2'd3 ;
|
|
assign m_m_stateVec_3_lat_2$whas =
|
|
EN_getEmptyEntryInit && m_m_emptyEntryQ$D_OUT == 2'd3 ;
|
|
|
|
// register m_m_initIdx
|
|
assign m_m_initIdx$D_IN = m_m_initIdx + 2'd1 ;
|
|
assign m_m_initIdx$EN = CAN_FIRE_RL_m_m_initEmptyEntry ;
|
|
|
|
// register m_m_inited
|
|
assign m_m_inited$D_IN = 1'd1 ;
|
|
assign m_m_inited$EN =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry && m_m_initIdx == 2'd3 ;
|
|
|
|
// register m_m_releaseEntryQ_pipelineResp_data_0_rl
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_rl$D_IN = v__h10232 ;
|
|
assign m_m_releaseEntryQ_pipelineResp_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_pipelineResp_empty_rl
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_rl$D_IN =
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ||
|
|
!EN_pipelineResp_releaseEntry &&
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl ;
|
|
assign m_m_releaseEntryQ_pipelineResp_empty_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_pipelineResp_full_rl
|
|
assign m_m_releaseEntryQ_pipelineResp_full_rl$D_IN =
|
|
!WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp &&
|
|
(EN_pipelineResp_releaseEntry ||
|
|
m_m_releaseEntryQ_pipelineResp_full_rl) ;
|
|
assign m_m_releaseEntryQ_pipelineResp_full_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$D_IN = v__h9493 ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_sendRsToP_pRq_empty_rl
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$D_IN =
|
|
MUX_m_m_emptyEntryQ$enq_1__SEL_2 ||
|
|
!EN_sendRsToP_pRq_releaseEntry &&
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_releaseEntryQ_sendRsToP_pRq_full_rl
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_rl$D_IN =
|
|
!MUX_m_m_emptyEntryQ$enq_1__SEL_2 &&
|
|
(EN_sendRsToP_pRq_releaseEntry ||
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl) ;
|
|
assign m_m_releaseEntryQ_sendRsToP_pRq_full_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_0_rl
|
|
assign m_m_reqVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_0_rl ;
|
|
assign m_m_reqVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_1_rl
|
|
assign m_m_reqVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_1_rl ;
|
|
assign m_m_reqVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_2_rl
|
|
assign m_m_reqVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_2_rl ;
|
|
assign m_m_reqVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_reqVec_3_rl
|
|
assign m_m_reqVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
getEmptyEntryInit_r :
|
|
m_m_reqVec_3_rl ;
|
|
assign m_m_reqVec_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_0_rl
|
|
assign m_m_stateVec_0_rl$D_IN =
|
|
m_m_stateVec_0_lat_2$whas ?
|
|
2'd1 :
|
|
IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 ;
|
|
assign m_m_stateVec_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_1_rl
|
|
assign m_m_stateVec_1_rl$D_IN =
|
|
m_m_stateVec_1_lat_2$whas ?
|
|
2'd1 :
|
|
IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 ;
|
|
assign m_m_stateVec_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_2_rl
|
|
assign m_m_stateVec_2_rl$D_IN =
|
|
m_m_stateVec_2_lat_2$whas ?
|
|
2'd1 :
|
|
IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 ;
|
|
assign m_m_stateVec_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_m_stateVec_3_rl
|
|
assign m_m_stateVec_3_rl$D_IN =
|
|
m_m_stateVec_3_lat_2$whas ?
|
|
2'd1 :
|
|
IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 ;
|
|
assign m_m_stateVec_3_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_m_emptyEntryQ
|
|
always@(WILL_FIRE_RL_m_m_initEmptyEntry or
|
|
m_m_initIdx or
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq or
|
|
MUX_m_m_emptyEntryQ$enq_1__VAL_2 or
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp or
|
|
MUX_m_m_emptyEntryQ$enq_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_m_m_initEmptyEntry: m_m_emptyEntryQ$D_IN = m_m_initIdx;
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq:
|
|
m_m_emptyEntryQ$D_IN = MUX_m_m_emptyEntryQ$enq_1__VAL_2;
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp:
|
|
m_m_emptyEntryQ$D_IN = MUX_m_m_emptyEntryQ$enq_1__VAL_3;
|
|
default: m_m_emptyEntryQ$D_IN = 2'b10 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign m_m_emptyEntryQ$ENQ =
|
|
WILL_FIRE_RL_m_m_initEmptyEntry ||
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_sendRsToP_pRq ||
|
|
WILL_FIRE_RL_m_m_doReleaseEntry_pipelineResp ;
|
|
assign m_m_emptyEntryQ$DEQ = EN_getEmptyEntryInit ;
|
|
assign m_m_emptyEntryQ$CLR = 1'b0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_m_m_stateVec_0_lat_1_whas_THEN_m_m_stateVec_ETC___d9 =
|
|
m_m_stateVec_0_lat_1$whas ?
|
|
2'd0 :
|
|
(m_m_stateVec_0_lat_0$whas ?
|
|
m_m_stateVec_0_lat_0$wget :
|
|
m_m_stateVec_0_rl) ;
|
|
assign IF_m_m_stateVec_1_lat_1_whas__3_THEN_m_m_state_ETC___d19 =
|
|
m_m_stateVec_1_lat_1$whas ?
|
|
2'd0 :
|
|
(m_m_stateVec_1_lat_0$whas ?
|
|
m_m_stateVec_1_lat_0$wget :
|
|
m_m_stateVec_1_rl) ;
|
|
assign IF_m_m_stateVec_2_lat_1_whas__3_THEN_m_m_state_ETC___d29 =
|
|
m_m_stateVec_2_lat_1$whas ?
|
|
2'd0 :
|
|
(m_m_stateVec_2_lat_0$whas ?
|
|
m_m_stateVec_2_lat_0$wget :
|
|
m_m_stateVec_2_rl) ;
|
|
assign IF_m_m_stateVec_3_lat_1_whas__3_THEN_m_m_state_ETC___d39 =
|
|
m_m_stateVec_3_lat_1$whas ?
|
|
2'd0 :
|
|
(m_m_stateVec_3_lat_0$whas ?
|
|
m_m_stateVec_3_lat_0$wget :
|
|
m_m_stateVec_3_rl) ;
|
|
assign v__h10232 = MUX_m_m_emptyEntryQ$enq_1__VAL_3 ;
|
|
assign v__h9493 = MUX_m_m_emptyEntryQ$enq_1__VAL_2 ;
|
|
always@(sendRsToP_pRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or m_m_reqVec_2_rl or m_m_reqVec_3_rl)
|
|
begin
|
|
case (sendRsToP_pRq_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d171 =
|
|
m_m_reqVec_0_rl[65:2];
|
|
2'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d171 =
|
|
m_m_reqVec_1_rl[65:2];
|
|
2'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d171 =
|
|
m_m_reqVec_2_rl[65:2];
|
|
2'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d171 =
|
|
m_m_reqVec_3_rl[65:2];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or m_m_reqVec_2_rl or m_m_reqVec_3_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_1_TO_0_73_m_m_r_ETC___d194 =
|
|
m_m_reqVec_0_rl[1:0];
|
|
2'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_1_TO_0_73_m_m_r_ETC___d194 =
|
|
m_m_reqVec_1_rl[1:0];
|
|
2'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_1_TO_0_73_m_m_r_ETC___d194 =
|
|
m_m_reqVec_2_rl[1:0];
|
|
2'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_1_TO_0_73_m_m_r_ETC___d194 =
|
|
m_m_reqVec_3_rl[1:0];
|
|
endcase
|
|
end
|
|
always@(sendRsToP_pRq_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or m_m_reqVec_2_rl or m_m_reqVec_3_rl)
|
|
begin
|
|
case (sendRsToP_pRq_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d185 =
|
|
m_m_reqVec_0_rl[1:0];
|
|
2'd1:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d185 =
|
|
m_m_reqVec_1_rl[1:0];
|
|
2'd2:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d185 =
|
|
m_m_reqVec_2_rl[1:0];
|
|
2'd3:
|
|
SEL_ARR_IF_m_m_reqVec_0_lat_0_whas__5_THEN_m_m_ETC___d185 =
|
|
m_m_reqVec_3_rl[1:0];
|
|
endcase
|
|
end
|
|
always@(pipelineResp_getRq_n or
|
|
m_m_reqVec_0_rl or
|
|
m_m_reqVec_1_rl or m_m_reqVec_2_rl or m_m_reqVec_3_rl)
|
|
begin
|
|
case (pipelineResp_getRq_n)
|
|
2'd0:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_65_TO_2_59_m_m__ETC___d192 =
|
|
m_m_reqVec_0_rl[65:2];
|
|
2'd1:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_65_TO_2_59_m_m__ETC___d192 =
|
|
m_m_reqVec_1_rl[65:2];
|
|
2'd2:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_65_TO_2_59_m_m__ETC___d192 =
|
|
m_m_reqVec_2_rl[65:2];
|
|
2'd3:
|
|
SEL_ARR_m_m_reqVec_0_rl_7_BITS_65_TO_2_59_m_m__ETC___d192 =
|
|
m_m_reqVec_3_rl[65:2];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
2'h2;
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_m_releaseEntryQ_pipelineResp_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
2'h2;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_initIdx$EN)
|
|
m_m_initIdx <= `BSV_ASSIGNMENT_DELAY m_m_initIdx$D_IN;
|
|
if (m_m_inited$EN)
|
|
m_m_inited <= `BSV_ASSIGNMENT_DELAY m_m_inited$D_IN;
|
|
if (m_m_releaseEntryQ_pipelineResp_data_0_rl$EN)
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl$D_IN;
|
|
if (m_m_releaseEntryQ_pipelineResp_empty_rl$EN)
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl$D_IN;
|
|
if (m_m_releaseEntryQ_pipelineResp_full_rl$EN)
|
|
m_m_releaseEntryQ_pipelineResp_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_pipelineResp_full_rl$D_IN;
|
|
if (m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$EN)
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl$D_IN;
|
|
if (m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$EN)
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl$D_IN;
|
|
if (m_m_releaseEntryQ_sendRsToP_pRq_full_rl$EN)
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl$D_IN;
|
|
if (m_m_reqVec_0_rl$EN)
|
|
m_m_reqVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_0_rl$D_IN;
|
|
if (m_m_reqVec_1_rl$EN)
|
|
m_m_reqVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_1_rl$D_IN;
|
|
if (m_m_reqVec_2_rl$EN)
|
|
m_m_reqVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_2_rl$D_IN;
|
|
if (m_m_reqVec_3_rl$EN)
|
|
m_m_reqVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_reqVec_3_rl$D_IN;
|
|
if (m_m_stateVec_0_rl$EN)
|
|
m_m_stateVec_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_0_rl$D_IN;
|
|
if (m_m_stateVec_1_rl$EN)
|
|
m_m_stateVec_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_1_rl$D_IN;
|
|
if (m_m_stateVec_2_rl$EN)
|
|
m_m_stateVec_2_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_2_rl$D_IN;
|
|
if (m_m_stateVec_3_rl$EN)
|
|
m_m_stateVec_3_rl <= `BSV_ASSIGNMENT_DELAY m_m_stateVec_3_rl$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_initIdx = 2'h2;
|
|
m_m_inited = 1'h0;
|
|
m_m_releaseEntryQ_pipelineResp_data_0_rl = 2'h2;
|
|
m_m_releaseEntryQ_pipelineResp_empty_rl = 1'h0;
|
|
m_m_releaseEntryQ_pipelineResp_full_rl = 1'h0;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_data_0_rl = 2'h2;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_empty_rl = 1'h0;
|
|
m_m_releaseEntryQ_sendRsToP_pRq_full_rl = 1'h0;
|
|
m_m_reqVec_0_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_1_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_2_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_reqVec_3_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
m_m_stateVec_0_rl = 2'h2;
|
|
m_m_stateVec_1_rl = 2'h2;
|
|
m_m_stateVec_2_rl = 2'h2;
|
|
m_m_stateVec_3_rl = 2'h2;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkIPRqMshrWrapper
|
|
|