5665 lines
223 KiB
Verilog
5665 lines
223 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
|
|
//
|
|
// On Mon Jul 13 18:40:44 BST 2020
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// flush_done O 1
|
|
// RDY_flush_done O 1 const
|
|
// RDY_flush O 1
|
|
// RDY_updateVMInfo O 1 const
|
|
// noPendingReq O 1
|
|
// RDY_noPendingReq O 1 const
|
|
// RDY_to_proc_request_put O 1
|
|
// to_proc_response_get O 70
|
|
// RDY_to_proc_response_get O 1
|
|
// toParent_rqToP_notEmpty O 1
|
|
// RDY_toParent_rqToP_notEmpty O 1 const
|
|
// RDY_toParent_rqToP_deq O 1
|
|
// toParent_rqToP_first O 27
|
|
// RDY_toParent_rqToP_first O 1
|
|
// toParent_rsFromP_notFull O 1
|
|
// RDY_toParent_rsFromP_notFull O 1 const
|
|
// RDY_toParent_rsFromP_enq O 1
|
|
// RDY_toParent_flush_request_get O 1
|
|
// RDY_toParent_flush_response_put O 1
|
|
// RDY_perf_setStatus O 1 const
|
|
// RDY_perf_req O 1
|
|
// perf_resp O 67
|
|
// RDY_perf_resp O 1
|
|
// perf_respValid O 1
|
|
// RDY_perf_respValid O 1 const
|
|
// CLK I 1 clock
|
|
// RST_N I 1 reset
|
|
// updateVMInfo_vm I 49 reg
|
|
// to_proc_request_put I 64
|
|
// toParent_rsFromP_enq_x I 81
|
|
// perf_setStatus_doStats I 1 unused
|
|
// perf_req_r I 3
|
|
// EN_flush I 1
|
|
// EN_updateVMInfo I 1
|
|
// EN_to_proc_request_put I 1
|
|
// EN_toParent_rqToP_deq I 1
|
|
// EN_toParent_rsFromP_enq I 1
|
|
// EN_toParent_flush_request_get I 1
|
|
// EN_toParent_flush_response_put I 1
|
|
// EN_perf_setStatus I 1 unused
|
|
// EN_perf_req I 1
|
|
// EN_to_proc_response_get I 1
|
|
// EN_perf_resp I 1
|
|
//
|
|
// No combinational paths from inputs to outputs
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module mkITlb(CLK,
|
|
RST_N,
|
|
|
|
flush_done,
|
|
RDY_flush_done,
|
|
|
|
EN_flush,
|
|
RDY_flush,
|
|
|
|
updateVMInfo_vm,
|
|
EN_updateVMInfo,
|
|
RDY_updateVMInfo,
|
|
|
|
noPendingReq,
|
|
RDY_noPendingReq,
|
|
|
|
to_proc_request_put,
|
|
EN_to_proc_request_put,
|
|
RDY_to_proc_request_put,
|
|
|
|
EN_to_proc_response_get,
|
|
to_proc_response_get,
|
|
RDY_to_proc_response_get,
|
|
|
|
toParent_rqToP_notEmpty,
|
|
RDY_toParent_rqToP_notEmpty,
|
|
|
|
EN_toParent_rqToP_deq,
|
|
RDY_toParent_rqToP_deq,
|
|
|
|
toParent_rqToP_first,
|
|
RDY_toParent_rqToP_first,
|
|
|
|
toParent_rsFromP_notFull,
|
|
RDY_toParent_rsFromP_notFull,
|
|
|
|
toParent_rsFromP_enq_x,
|
|
EN_toParent_rsFromP_enq,
|
|
RDY_toParent_rsFromP_enq,
|
|
|
|
EN_toParent_flush_request_get,
|
|
RDY_toParent_flush_request_get,
|
|
|
|
EN_toParent_flush_response_put,
|
|
RDY_toParent_flush_response_put,
|
|
|
|
perf_setStatus_doStats,
|
|
EN_perf_setStatus,
|
|
RDY_perf_setStatus,
|
|
|
|
perf_req_r,
|
|
EN_perf_req,
|
|
RDY_perf_req,
|
|
|
|
EN_perf_resp,
|
|
perf_resp,
|
|
RDY_perf_resp,
|
|
|
|
perf_respValid,
|
|
RDY_perf_respValid);
|
|
input CLK;
|
|
input RST_N;
|
|
|
|
// value method flush_done
|
|
output flush_done;
|
|
output RDY_flush_done;
|
|
|
|
// action method flush
|
|
input EN_flush;
|
|
output RDY_flush;
|
|
|
|
// action method updateVMInfo
|
|
input [48 : 0] updateVMInfo_vm;
|
|
input EN_updateVMInfo;
|
|
output RDY_updateVMInfo;
|
|
|
|
// value method noPendingReq
|
|
output noPendingReq;
|
|
output RDY_noPendingReq;
|
|
|
|
// action method to_proc_request_put
|
|
input [63 : 0] to_proc_request_put;
|
|
input EN_to_proc_request_put;
|
|
output RDY_to_proc_request_put;
|
|
|
|
// actionvalue method to_proc_response_get
|
|
input EN_to_proc_response_get;
|
|
output [69 : 0] to_proc_response_get;
|
|
output RDY_to_proc_response_get;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
output toParent_rqToP_notEmpty;
|
|
output RDY_toParent_rqToP_notEmpty;
|
|
|
|
// action method toParent_rqToP_deq
|
|
input EN_toParent_rqToP_deq;
|
|
output RDY_toParent_rqToP_deq;
|
|
|
|
// value method toParent_rqToP_first
|
|
output [26 : 0] toParent_rqToP_first;
|
|
output RDY_toParent_rqToP_first;
|
|
|
|
// value method toParent_rsFromP_notFull
|
|
output toParent_rsFromP_notFull;
|
|
output RDY_toParent_rsFromP_notFull;
|
|
|
|
// action method toParent_rsFromP_enq
|
|
input [80 : 0] toParent_rsFromP_enq_x;
|
|
input EN_toParent_rsFromP_enq;
|
|
output RDY_toParent_rsFromP_enq;
|
|
|
|
// action method toParent_flush_request_get
|
|
input EN_toParent_flush_request_get;
|
|
output RDY_toParent_flush_request_get;
|
|
|
|
// action method toParent_flush_response_put
|
|
input EN_toParent_flush_response_put;
|
|
output RDY_toParent_flush_response_put;
|
|
|
|
// action method perf_setStatus
|
|
input perf_setStatus_doStats;
|
|
input EN_perf_setStatus;
|
|
output RDY_perf_setStatus;
|
|
|
|
// action method perf_req
|
|
input [2 : 0] perf_req_r;
|
|
input EN_perf_req;
|
|
output RDY_perf_req;
|
|
|
|
// actionvalue method perf_resp
|
|
input EN_perf_resp;
|
|
output [66 : 0] perf_resp;
|
|
output RDY_perf_resp;
|
|
|
|
// value method perf_respValid
|
|
output perf_respValid;
|
|
output RDY_perf_respValid;
|
|
|
|
// signals for module outputs
|
|
reg [26 : 0] toParent_rqToP_first;
|
|
wire [69 : 0] to_proc_response_get;
|
|
wire [66 : 0] perf_resp;
|
|
wire RDY_flush,
|
|
RDY_flush_done,
|
|
RDY_noPendingReq,
|
|
RDY_perf_req,
|
|
RDY_perf_resp,
|
|
RDY_perf_respValid,
|
|
RDY_perf_setStatus,
|
|
RDY_toParent_flush_request_get,
|
|
RDY_toParent_flush_response_put,
|
|
RDY_toParent_rqToP_deq,
|
|
RDY_toParent_rqToP_first,
|
|
RDY_toParent_rqToP_notEmpty,
|
|
RDY_toParent_rsFromP_enq,
|
|
RDY_toParent_rsFromP_notFull,
|
|
RDY_to_proc_request_put,
|
|
RDY_to_proc_response_get,
|
|
RDY_updateVMInfo,
|
|
flush_done,
|
|
noPendingReq,
|
|
perf_respValid,
|
|
toParent_rqToP_notEmpty,
|
|
toParent_rsFromP_notFull;
|
|
|
|
// inlined wires
|
|
wire [81 : 0] rsFromPQ_enqReq_lat_0$wget;
|
|
wire [70 : 0] hitQ_enqReq_lat_0$wget;
|
|
wire [27 : 0] rqToPQ_enqReq_lat_0$wget;
|
|
wire [5 : 0] tlb_m_updRepIdx_lat_1$wget;
|
|
wire [3 : 0] perfReqQ_enqReq_lat_0$wget;
|
|
wire hitQ_enqReq_lat_0$whas,
|
|
tlb_m_lruBit_lat_0$whas,
|
|
tlb_m_updRepIdx_lat_0$whas,
|
|
tlb_m_updRepIdx_lat_1$whas;
|
|
|
|
// register flushRqToPQ_clearReq_rl
|
|
reg flushRqToPQ_clearReq_rl;
|
|
wire flushRqToPQ_clearReq_rl$D_IN, flushRqToPQ_clearReq_rl$EN;
|
|
|
|
// register flushRqToPQ_deqReq_rl
|
|
reg flushRqToPQ_deqReq_rl;
|
|
wire flushRqToPQ_deqReq_rl$D_IN, flushRqToPQ_deqReq_rl$EN;
|
|
|
|
// register flushRqToPQ_empty
|
|
reg flushRqToPQ_empty;
|
|
wire flushRqToPQ_empty$D_IN, flushRqToPQ_empty$EN;
|
|
|
|
// register flushRqToPQ_enqReq_rl
|
|
reg flushRqToPQ_enqReq_rl;
|
|
wire flushRqToPQ_enqReq_rl$D_IN, flushRqToPQ_enqReq_rl$EN;
|
|
|
|
// register flushRqToPQ_full
|
|
reg flushRqToPQ_full;
|
|
wire flushRqToPQ_full$D_IN, flushRqToPQ_full$EN;
|
|
|
|
// register flushRsFromPQ_clearReq_rl
|
|
reg flushRsFromPQ_clearReq_rl;
|
|
wire flushRsFromPQ_clearReq_rl$D_IN, flushRsFromPQ_clearReq_rl$EN;
|
|
|
|
// register flushRsFromPQ_deqReq_rl
|
|
reg flushRsFromPQ_deqReq_rl;
|
|
wire flushRsFromPQ_deqReq_rl$D_IN, flushRsFromPQ_deqReq_rl$EN;
|
|
|
|
// register flushRsFromPQ_empty
|
|
reg flushRsFromPQ_empty;
|
|
wire flushRsFromPQ_empty$D_IN, flushRsFromPQ_empty$EN;
|
|
|
|
// register flushRsFromPQ_enqReq_rl
|
|
reg flushRsFromPQ_enqReq_rl;
|
|
wire flushRsFromPQ_enqReq_rl$D_IN, flushRsFromPQ_enqReq_rl$EN;
|
|
|
|
// register flushRsFromPQ_full
|
|
reg flushRsFromPQ_full;
|
|
wire flushRsFromPQ_full$D_IN, flushRsFromPQ_full$EN;
|
|
|
|
// register hitQ_clearReq_rl
|
|
reg hitQ_clearReq_rl;
|
|
wire hitQ_clearReq_rl$D_IN, hitQ_clearReq_rl$EN;
|
|
|
|
// register hitQ_data_0
|
|
reg [69 : 0] hitQ_data_0;
|
|
wire [69 : 0] hitQ_data_0$D_IN;
|
|
wire hitQ_data_0$EN;
|
|
|
|
// register hitQ_data_1
|
|
reg [69 : 0] hitQ_data_1;
|
|
wire [69 : 0] hitQ_data_1$D_IN;
|
|
wire hitQ_data_1$EN;
|
|
|
|
// register hitQ_deqP
|
|
reg hitQ_deqP;
|
|
wire hitQ_deqP$D_IN, hitQ_deqP$EN;
|
|
|
|
// register hitQ_deqReq_rl
|
|
reg hitQ_deqReq_rl;
|
|
wire hitQ_deqReq_rl$D_IN, hitQ_deqReq_rl$EN;
|
|
|
|
// register hitQ_empty
|
|
reg hitQ_empty;
|
|
wire hitQ_empty$D_IN, hitQ_empty$EN;
|
|
|
|
// register hitQ_enqP
|
|
reg hitQ_enqP;
|
|
wire hitQ_enqP$D_IN, hitQ_enqP$EN;
|
|
|
|
// register hitQ_enqReq_rl
|
|
reg [70 : 0] hitQ_enqReq_rl;
|
|
wire [70 : 0] hitQ_enqReq_rl$D_IN;
|
|
wire hitQ_enqReq_rl$EN;
|
|
|
|
// register hitQ_full
|
|
reg hitQ_full;
|
|
wire hitQ_full$D_IN, hitQ_full$EN;
|
|
|
|
// register miss
|
|
reg [64 : 0] miss;
|
|
wire [64 : 0] miss$D_IN;
|
|
wire miss$EN;
|
|
|
|
// register needFlush
|
|
reg needFlush;
|
|
wire needFlush$D_IN, needFlush$EN;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
reg perfReqQ_clearReq_rl;
|
|
wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
|
|
|
|
// register perfReqQ_data_0
|
|
reg [2 : 0] perfReqQ_data_0;
|
|
wire [2 : 0] perfReqQ_data_0$D_IN;
|
|
wire perfReqQ_data_0$EN;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
reg perfReqQ_deqReq_rl;
|
|
wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
|
|
|
|
// register perfReqQ_empty
|
|
reg perfReqQ_empty;
|
|
wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
reg [3 : 0] perfReqQ_enqReq_rl;
|
|
wire [3 : 0] perfReqQ_enqReq_rl$D_IN;
|
|
wire perfReqQ_enqReq_rl$EN;
|
|
|
|
// register perfReqQ_full
|
|
reg perfReqQ_full;
|
|
wire perfReqQ_full$D_IN, perfReqQ_full$EN;
|
|
|
|
// register rqToPQ_clearReq_rl
|
|
reg rqToPQ_clearReq_rl;
|
|
wire rqToPQ_clearReq_rl$D_IN, rqToPQ_clearReq_rl$EN;
|
|
|
|
// register rqToPQ_data_0
|
|
reg [26 : 0] rqToPQ_data_0;
|
|
wire [26 : 0] rqToPQ_data_0$D_IN;
|
|
wire rqToPQ_data_0$EN;
|
|
|
|
// register rqToPQ_data_1
|
|
reg [26 : 0] rqToPQ_data_1;
|
|
wire [26 : 0] rqToPQ_data_1$D_IN;
|
|
wire rqToPQ_data_1$EN;
|
|
|
|
// register rqToPQ_deqP
|
|
reg rqToPQ_deqP;
|
|
wire rqToPQ_deqP$D_IN, rqToPQ_deqP$EN;
|
|
|
|
// register rqToPQ_deqReq_rl
|
|
reg rqToPQ_deqReq_rl;
|
|
wire rqToPQ_deqReq_rl$D_IN, rqToPQ_deqReq_rl$EN;
|
|
|
|
// register rqToPQ_empty
|
|
reg rqToPQ_empty;
|
|
wire rqToPQ_empty$D_IN, rqToPQ_empty$EN;
|
|
|
|
// register rqToPQ_enqP
|
|
reg rqToPQ_enqP;
|
|
wire rqToPQ_enqP$D_IN, rqToPQ_enqP$EN;
|
|
|
|
// register rqToPQ_enqReq_rl
|
|
reg [27 : 0] rqToPQ_enqReq_rl;
|
|
wire [27 : 0] rqToPQ_enqReq_rl$D_IN;
|
|
wire rqToPQ_enqReq_rl$EN;
|
|
|
|
// register rqToPQ_full
|
|
reg rqToPQ_full;
|
|
wire rqToPQ_full$D_IN, rqToPQ_full$EN;
|
|
|
|
// register rsFromPQ_clearReq_rl
|
|
reg rsFromPQ_clearReq_rl;
|
|
wire rsFromPQ_clearReq_rl$D_IN, rsFromPQ_clearReq_rl$EN;
|
|
|
|
// register rsFromPQ_data_0
|
|
reg [80 : 0] rsFromPQ_data_0;
|
|
wire [80 : 0] rsFromPQ_data_0$D_IN;
|
|
wire rsFromPQ_data_0$EN;
|
|
|
|
// register rsFromPQ_data_1
|
|
reg [80 : 0] rsFromPQ_data_1;
|
|
wire [80 : 0] rsFromPQ_data_1$D_IN;
|
|
wire rsFromPQ_data_1$EN;
|
|
|
|
// register rsFromPQ_deqP
|
|
reg rsFromPQ_deqP;
|
|
wire rsFromPQ_deqP$D_IN, rsFromPQ_deqP$EN;
|
|
|
|
// register rsFromPQ_deqReq_rl
|
|
reg rsFromPQ_deqReq_rl;
|
|
wire rsFromPQ_deqReq_rl$D_IN, rsFromPQ_deqReq_rl$EN;
|
|
|
|
// register rsFromPQ_empty
|
|
reg rsFromPQ_empty;
|
|
wire rsFromPQ_empty$D_IN, rsFromPQ_empty$EN;
|
|
|
|
// register rsFromPQ_enqP
|
|
reg rsFromPQ_enqP;
|
|
wire rsFromPQ_enqP$D_IN, rsFromPQ_enqP$EN;
|
|
|
|
// register rsFromPQ_enqReq_rl
|
|
reg [81 : 0] rsFromPQ_enqReq_rl;
|
|
wire [81 : 0] rsFromPQ_enqReq_rl$D_IN;
|
|
wire rsFromPQ_enqReq_rl$EN;
|
|
|
|
// register rsFromPQ_full
|
|
reg rsFromPQ_full;
|
|
wire rsFromPQ_full$D_IN, rsFromPQ_full$EN;
|
|
|
|
// register tlb_m_entryVec_0
|
|
reg [79 : 0] tlb_m_entryVec_0;
|
|
wire [79 : 0] tlb_m_entryVec_0$D_IN;
|
|
wire tlb_m_entryVec_0$EN;
|
|
|
|
// register tlb_m_entryVec_1
|
|
reg [79 : 0] tlb_m_entryVec_1;
|
|
wire [79 : 0] tlb_m_entryVec_1$D_IN;
|
|
wire tlb_m_entryVec_1$EN;
|
|
|
|
// register tlb_m_entryVec_10
|
|
reg [79 : 0] tlb_m_entryVec_10;
|
|
wire [79 : 0] tlb_m_entryVec_10$D_IN;
|
|
wire tlb_m_entryVec_10$EN;
|
|
|
|
// register tlb_m_entryVec_11
|
|
reg [79 : 0] tlb_m_entryVec_11;
|
|
wire [79 : 0] tlb_m_entryVec_11$D_IN;
|
|
wire tlb_m_entryVec_11$EN;
|
|
|
|
// register tlb_m_entryVec_12
|
|
reg [79 : 0] tlb_m_entryVec_12;
|
|
wire [79 : 0] tlb_m_entryVec_12$D_IN;
|
|
wire tlb_m_entryVec_12$EN;
|
|
|
|
// register tlb_m_entryVec_13
|
|
reg [79 : 0] tlb_m_entryVec_13;
|
|
wire [79 : 0] tlb_m_entryVec_13$D_IN;
|
|
wire tlb_m_entryVec_13$EN;
|
|
|
|
// register tlb_m_entryVec_14
|
|
reg [79 : 0] tlb_m_entryVec_14;
|
|
wire [79 : 0] tlb_m_entryVec_14$D_IN;
|
|
wire tlb_m_entryVec_14$EN;
|
|
|
|
// register tlb_m_entryVec_15
|
|
reg [79 : 0] tlb_m_entryVec_15;
|
|
wire [79 : 0] tlb_m_entryVec_15$D_IN;
|
|
wire tlb_m_entryVec_15$EN;
|
|
|
|
// register tlb_m_entryVec_16
|
|
reg [79 : 0] tlb_m_entryVec_16;
|
|
wire [79 : 0] tlb_m_entryVec_16$D_IN;
|
|
wire tlb_m_entryVec_16$EN;
|
|
|
|
// register tlb_m_entryVec_17
|
|
reg [79 : 0] tlb_m_entryVec_17;
|
|
wire [79 : 0] tlb_m_entryVec_17$D_IN;
|
|
wire tlb_m_entryVec_17$EN;
|
|
|
|
// register tlb_m_entryVec_18
|
|
reg [79 : 0] tlb_m_entryVec_18;
|
|
wire [79 : 0] tlb_m_entryVec_18$D_IN;
|
|
wire tlb_m_entryVec_18$EN;
|
|
|
|
// register tlb_m_entryVec_19
|
|
reg [79 : 0] tlb_m_entryVec_19;
|
|
wire [79 : 0] tlb_m_entryVec_19$D_IN;
|
|
wire tlb_m_entryVec_19$EN;
|
|
|
|
// register tlb_m_entryVec_2
|
|
reg [79 : 0] tlb_m_entryVec_2;
|
|
wire [79 : 0] tlb_m_entryVec_2$D_IN;
|
|
wire tlb_m_entryVec_2$EN;
|
|
|
|
// register tlb_m_entryVec_20
|
|
reg [79 : 0] tlb_m_entryVec_20;
|
|
wire [79 : 0] tlb_m_entryVec_20$D_IN;
|
|
wire tlb_m_entryVec_20$EN;
|
|
|
|
// register tlb_m_entryVec_21
|
|
reg [79 : 0] tlb_m_entryVec_21;
|
|
wire [79 : 0] tlb_m_entryVec_21$D_IN;
|
|
wire tlb_m_entryVec_21$EN;
|
|
|
|
// register tlb_m_entryVec_22
|
|
reg [79 : 0] tlb_m_entryVec_22;
|
|
wire [79 : 0] tlb_m_entryVec_22$D_IN;
|
|
wire tlb_m_entryVec_22$EN;
|
|
|
|
// register tlb_m_entryVec_23
|
|
reg [79 : 0] tlb_m_entryVec_23;
|
|
wire [79 : 0] tlb_m_entryVec_23$D_IN;
|
|
wire tlb_m_entryVec_23$EN;
|
|
|
|
// register tlb_m_entryVec_24
|
|
reg [79 : 0] tlb_m_entryVec_24;
|
|
wire [79 : 0] tlb_m_entryVec_24$D_IN;
|
|
wire tlb_m_entryVec_24$EN;
|
|
|
|
// register tlb_m_entryVec_25
|
|
reg [79 : 0] tlb_m_entryVec_25;
|
|
wire [79 : 0] tlb_m_entryVec_25$D_IN;
|
|
wire tlb_m_entryVec_25$EN;
|
|
|
|
// register tlb_m_entryVec_26
|
|
reg [79 : 0] tlb_m_entryVec_26;
|
|
wire [79 : 0] tlb_m_entryVec_26$D_IN;
|
|
wire tlb_m_entryVec_26$EN;
|
|
|
|
// register tlb_m_entryVec_27
|
|
reg [79 : 0] tlb_m_entryVec_27;
|
|
wire [79 : 0] tlb_m_entryVec_27$D_IN;
|
|
wire tlb_m_entryVec_27$EN;
|
|
|
|
// register tlb_m_entryVec_28
|
|
reg [79 : 0] tlb_m_entryVec_28;
|
|
wire [79 : 0] tlb_m_entryVec_28$D_IN;
|
|
wire tlb_m_entryVec_28$EN;
|
|
|
|
// register tlb_m_entryVec_29
|
|
reg [79 : 0] tlb_m_entryVec_29;
|
|
wire [79 : 0] tlb_m_entryVec_29$D_IN;
|
|
wire tlb_m_entryVec_29$EN;
|
|
|
|
// register tlb_m_entryVec_3
|
|
reg [79 : 0] tlb_m_entryVec_3;
|
|
wire [79 : 0] tlb_m_entryVec_3$D_IN;
|
|
wire tlb_m_entryVec_3$EN;
|
|
|
|
// register tlb_m_entryVec_30
|
|
reg [79 : 0] tlb_m_entryVec_30;
|
|
wire [79 : 0] tlb_m_entryVec_30$D_IN;
|
|
wire tlb_m_entryVec_30$EN;
|
|
|
|
// register tlb_m_entryVec_31
|
|
reg [79 : 0] tlb_m_entryVec_31;
|
|
wire [79 : 0] tlb_m_entryVec_31$D_IN;
|
|
wire tlb_m_entryVec_31$EN;
|
|
|
|
// register tlb_m_entryVec_4
|
|
reg [79 : 0] tlb_m_entryVec_4;
|
|
wire [79 : 0] tlb_m_entryVec_4$D_IN;
|
|
wire tlb_m_entryVec_4$EN;
|
|
|
|
// register tlb_m_entryVec_5
|
|
reg [79 : 0] tlb_m_entryVec_5;
|
|
wire [79 : 0] tlb_m_entryVec_5$D_IN;
|
|
wire tlb_m_entryVec_5$EN;
|
|
|
|
// register tlb_m_entryVec_6
|
|
reg [79 : 0] tlb_m_entryVec_6;
|
|
wire [79 : 0] tlb_m_entryVec_6$D_IN;
|
|
wire tlb_m_entryVec_6$EN;
|
|
|
|
// register tlb_m_entryVec_7
|
|
reg [79 : 0] tlb_m_entryVec_7;
|
|
wire [79 : 0] tlb_m_entryVec_7$D_IN;
|
|
wire tlb_m_entryVec_7$EN;
|
|
|
|
// register tlb_m_entryVec_8
|
|
reg [79 : 0] tlb_m_entryVec_8;
|
|
wire [79 : 0] tlb_m_entryVec_8$D_IN;
|
|
wire tlb_m_entryVec_8$EN;
|
|
|
|
// register tlb_m_entryVec_9
|
|
reg [79 : 0] tlb_m_entryVec_9;
|
|
wire [79 : 0] tlb_m_entryVec_9$D_IN;
|
|
wire tlb_m_entryVec_9$EN;
|
|
|
|
// register tlb_m_lruBit_rl
|
|
reg [31 : 0] tlb_m_lruBit_rl;
|
|
wire [31 : 0] tlb_m_lruBit_rl$D_IN;
|
|
wire tlb_m_lruBit_rl$EN;
|
|
|
|
// register tlb_m_randIdx
|
|
reg [4 : 0] tlb_m_randIdx;
|
|
wire [4 : 0] tlb_m_randIdx$D_IN;
|
|
wire tlb_m_randIdx$EN;
|
|
|
|
// register tlb_m_updRepIdx_rl
|
|
reg [5 : 0] tlb_m_updRepIdx_rl;
|
|
wire [5 : 0] tlb_m_updRepIdx_rl$D_IN;
|
|
wire tlb_m_updRepIdx_rl$EN;
|
|
|
|
// register tlb_m_validVec_0
|
|
reg tlb_m_validVec_0;
|
|
wire tlb_m_validVec_0$D_IN, tlb_m_validVec_0$EN;
|
|
|
|
// register tlb_m_validVec_1
|
|
reg tlb_m_validVec_1;
|
|
wire tlb_m_validVec_1$D_IN, tlb_m_validVec_1$EN;
|
|
|
|
// register tlb_m_validVec_10
|
|
reg tlb_m_validVec_10;
|
|
wire tlb_m_validVec_10$D_IN, tlb_m_validVec_10$EN;
|
|
|
|
// register tlb_m_validVec_11
|
|
reg tlb_m_validVec_11;
|
|
wire tlb_m_validVec_11$D_IN, tlb_m_validVec_11$EN;
|
|
|
|
// register tlb_m_validVec_12
|
|
reg tlb_m_validVec_12;
|
|
wire tlb_m_validVec_12$D_IN, tlb_m_validVec_12$EN;
|
|
|
|
// register tlb_m_validVec_13
|
|
reg tlb_m_validVec_13;
|
|
wire tlb_m_validVec_13$D_IN, tlb_m_validVec_13$EN;
|
|
|
|
// register tlb_m_validVec_14
|
|
reg tlb_m_validVec_14;
|
|
wire tlb_m_validVec_14$D_IN, tlb_m_validVec_14$EN;
|
|
|
|
// register tlb_m_validVec_15
|
|
reg tlb_m_validVec_15;
|
|
wire tlb_m_validVec_15$D_IN, tlb_m_validVec_15$EN;
|
|
|
|
// register tlb_m_validVec_16
|
|
reg tlb_m_validVec_16;
|
|
wire tlb_m_validVec_16$D_IN, tlb_m_validVec_16$EN;
|
|
|
|
// register tlb_m_validVec_17
|
|
reg tlb_m_validVec_17;
|
|
wire tlb_m_validVec_17$D_IN, tlb_m_validVec_17$EN;
|
|
|
|
// register tlb_m_validVec_18
|
|
reg tlb_m_validVec_18;
|
|
wire tlb_m_validVec_18$D_IN, tlb_m_validVec_18$EN;
|
|
|
|
// register tlb_m_validVec_19
|
|
reg tlb_m_validVec_19;
|
|
wire tlb_m_validVec_19$D_IN, tlb_m_validVec_19$EN;
|
|
|
|
// register tlb_m_validVec_2
|
|
reg tlb_m_validVec_2;
|
|
wire tlb_m_validVec_2$D_IN, tlb_m_validVec_2$EN;
|
|
|
|
// register tlb_m_validVec_20
|
|
reg tlb_m_validVec_20;
|
|
wire tlb_m_validVec_20$D_IN, tlb_m_validVec_20$EN;
|
|
|
|
// register tlb_m_validVec_21
|
|
reg tlb_m_validVec_21;
|
|
wire tlb_m_validVec_21$D_IN, tlb_m_validVec_21$EN;
|
|
|
|
// register tlb_m_validVec_22
|
|
reg tlb_m_validVec_22;
|
|
wire tlb_m_validVec_22$D_IN, tlb_m_validVec_22$EN;
|
|
|
|
// register tlb_m_validVec_23
|
|
reg tlb_m_validVec_23;
|
|
wire tlb_m_validVec_23$D_IN, tlb_m_validVec_23$EN;
|
|
|
|
// register tlb_m_validVec_24
|
|
reg tlb_m_validVec_24;
|
|
wire tlb_m_validVec_24$D_IN, tlb_m_validVec_24$EN;
|
|
|
|
// register tlb_m_validVec_25
|
|
reg tlb_m_validVec_25;
|
|
wire tlb_m_validVec_25$D_IN, tlb_m_validVec_25$EN;
|
|
|
|
// register tlb_m_validVec_26
|
|
reg tlb_m_validVec_26;
|
|
wire tlb_m_validVec_26$D_IN, tlb_m_validVec_26$EN;
|
|
|
|
// register tlb_m_validVec_27
|
|
reg tlb_m_validVec_27;
|
|
wire tlb_m_validVec_27$D_IN, tlb_m_validVec_27$EN;
|
|
|
|
// register tlb_m_validVec_28
|
|
reg tlb_m_validVec_28;
|
|
wire tlb_m_validVec_28$D_IN, tlb_m_validVec_28$EN;
|
|
|
|
// register tlb_m_validVec_29
|
|
reg tlb_m_validVec_29;
|
|
wire tlb_m_validVec_29$D_IN, tlb_m_validVec_29$EN;
|
|
|
|
// register tlb_m_validVec_3
|
|
reg tlb_m_validVec_3;
|
|
wire tlb_m_validVec_3$D_IN, tlb_m_validVec_3$EN;
|
|
|
|
// register tlb_m_validVec_30
|
|
reg tlb_m_validVec_30;
|
|
wire tlb_m_validVec_30$D_IN, tlb_m_validVec_30$EN;
|
|
|
|
// register tlb_m_validVec_31
|
|
reg tlb_m_validVec_31;
|
|
wire tlb_m_validVec_31$D_IN, tlb_m_validVec_31$EN;
|
|
|
|
// register tlb_m_validVec_4
|
|
reg tlb_m_validVec_4;
|
|
wire tlb_m_validVec_4$D_IN, tlb_m_validVec_4$EN;
|
|
|
|
// register tlb_m_validVec_5
|
|
reg tlb_m_validVec_5;
|
|
wire tlb_m_validVec_5$D_IN, tlb_m_validVec_5$EN;
|
|
|
|
// register tlb_m_validVec_6
|
|
reg tlb_m_validVec_6;
|
|
wire tlb_m_validVec_6$D_IN, tlb_m_validVec_6$EN;
|
|
|
|
// register tlb_m_validVec_7
|
|
reg tlb_m_validVec_7;
|
|
wire tlb_m_validVec_7$D_IN, tlb_m_validVec_7$EN;
|
|
|
|
// register tlb_m_validVec_8
|
|
reg tlb_m_validVec_8;
|
|
wire tlb_m_validVec_8$D_IN, tlb_m_validVec_8$EN;
|
|
|
|
// register tlb_m_validVec_9
|
|
reg tlb_m_validVec_9;
|
|
wire tlb_m_validVec_9$D_IN, tlb_m_validVec_9$EN;
|
|
|
|
// register vm_info
|
|
reg [48 : 0] vm_info;
|
|
wire [48 : 0] vm_info$D_IN;
|
|
wire vm_info$EN;
|
|
|
|
// register waitFlushP
|
|
reg waitFlushP;
|
|
wire waitFlushP$D_IN, waitFlushP$EN;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_doFinishFlush,
|
|
CAN_FIRE_RL_doRsFromP,
|
|
CAN_FIRE_RL_doStartFlush,
|
|
CAN_FIRE_RL_flushRqToPQ_canonicalize,
|
|
CAN_FIRE_RL_flushRqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushRqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushRqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_flushRsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_flushRsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_hitQ_canonicalize,
|
|
CAN_FIRE_RL_hitQ_clearReq_canon,
|
|
CAN_FIRE_RL_hitQ_deqReq_canon,
|
|
CAN_FIRE_RL_hitQ_enqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_canonicalize,
|
|
CAN_FIRE_RL_rsFromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_rsFromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_set_no_pending,
|
|
CAN_FIRE_RL_tlb_m_doUpdateRep,
|
|
CAN_FIRE_RL_tlb_m_incRandIdx,
|
|
CAN_FIRE_RL_tlb_m_lruBit_canon,
|
|
CAN_FIRE_RL_tlb_m_updRepIdx_canon,
|
|
CAN_FIRE_flush,
|
|
CAN_FIRE_perf_req,
|
|
CAN_FIRE_perf_resp,
|
|
CAN_FIRE_perf_setStatus,
|
|
CAN_FIRE_toParent_flush_request_get,
|
|
CAN_FIRE_toParent_flush_response_put,
|
|
CAN_FIRE_toParent_rqToP_deq,
|
|
CAN_FIRE_toParent_rsFromP_enq,
|
|
CAN_FIRE_to_proc_request_put,
|
|
CAN_FIRE_to_proc_response_get,
|
|
CAN_FIRE_updateVMInfo,
|
|
WILL_FIRE_RL_doFinishFlush,
|
|
WILL_FIRE_RL_doRsFromP,
|
|
WILL_FIRE_RL_doStartFlush,
|
|
WILL_FIRE_RL_flushRqToPQ_canonicalize,
|
|
WILL_FIRE_RL_flushRqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushRqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushRqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_flushRsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_flushRsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_hitQ_canonicalize,
|
|
WILL_FIRE_RL_hitQ_clearReq_canon,
|
|
WILL_FIRE_RL_hitQ_deqReq_canon,
|
|
WILL_FIRE_RL_hitQ_enqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_canonicalize,
|
|
WILL_FIRE_RL_rsFromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_rsFromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_set_no_pending,
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep,
|
|
WILL_FIRE_RL_tlb_m_incRandIdx,
|
|
WILL_FIRE_RL_tlb_m_lruBit_canon,
|
|
WILL_FIRE_RL_tlb_m_updRepIdx_canon,
|
|
WILL_FIRE_flush,
|
|
WILL_FIRE_perf_req,
|
|
WILL_FIRE_perf_resp,
|
|
WILL_FIRE_perf_setStatus,
|
|
WILL_FIRE_toParent_flush_request_get,
|
|
WILL_FIRE_toParent_flush_response_put,
|
|
WILL_FIRE_toParent_rqToP_deq,
|
|
WILL_FIRE_toParent_rsFromP_enq,
|
|
WILL_FIRE_to_proc_request_put,
|
|
WILL_FIRE_to_proc_response_get,
|
|
WILL_FIRE_updateVMInfo;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [70 : 0] MUX_hitQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [64 : 0] MUX_miss$write_1__VAL_1;
|
|
wire [31 : 0] MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1;
|
|
wire [5 : 0] MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1,
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2;
|
|
wire MUX_hitQ_enqReq_lat_0$wset_1__SEL_1,
|
|
MUX_miss$write_1__SEL_1,
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1,
|
|
MUX_tlb_m_validVec_0$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_1$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_10$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_11$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_12$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_13$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_14$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_15$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_16$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_17$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_18$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_19$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_2$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_20$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_21$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_22$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_23$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_24$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_25$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_26$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_27$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_28$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_29$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_3$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_30$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_31$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_4$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_5$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_6$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_7$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_8$write_1__SEL_1,
|
|
MUX_tlb_m_validVec_9$write_1__SEL_1,
|
|
MUX_waitFlushP$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] x__h74975;
|
|
reg [55 : 0] x__h65238, x__h74750;
|
|
reg [43 : 0] SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737,
|
|
ppn__h74746;
|
|
reg [26 : 0] CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q2,
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q11,
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q12,
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q13,
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q14,
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q15,
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q16,
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q17,
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q18,
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q19,
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q20,
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q1,
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q21,
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q22,
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q23,
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q24,
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q25,
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q26,
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q27,
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q28,
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q29,
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q30,
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q3,
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q31,
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q32,
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q4,
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q5,
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q6,
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q7,
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q8,
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q9,
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q10,
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123;
|
|
reg [4 : 0] CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55;
|
|
reg [3 : 0] CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53,
|
|
CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54;
|
|
reg [1 : 0] level__h33681, level__h70028;
|
|
reg CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q50,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_0__ETC__q49,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_11_ETC__q39,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_12_ETC__q38,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_13_ETC__q36,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_15_ETC__q37,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_1__ETC__q48,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_2__ETC__q47,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_3__ETC__q46,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_4__ETC__q45,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_5__ETC__q44,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_6__ETC__q43,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_7__ETC__q42,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_8__ETC__q41,
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_9__ETC__q40,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q34,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q33,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q35,
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_2_53_54_NOT_ETC___d758,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d719,
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352,
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_3_49_rsFromPQ_d_ETC___d752,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d723,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d712,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707,
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285,
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203,
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102;
|
|
wire [69 : 0] IF_vm_info_24_BIT_46_60_THEN_IF_SEL_ARR_tlb_m__ETC___d2376;
|
|
wire [63 : 0] x__h65230, x__h74742, x__h9109;
|
|
wire [31 : 0] INV_n__read6006__q51,
|
|
n__read__h46006,
|
|
upd__h46033,
|
|
val__h5317,
|
|
x__h5375;
|
|
wire [8 : 0] SEL_ARR_rsFromPQ_data_0_02_BIT_8_638_rsFromPQ__ETC___d1649;
|
|
wire [4 : 0] IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2072,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2074,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2076,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2078,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2080,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2082,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2084,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2086,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2088,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2090,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2092,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2094,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2096,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2098,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2100,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2464,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2465,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2466,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2467,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2468,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2469,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2470,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2471,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2472,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2473,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2474,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2475,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2476,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27,
|
|
IF_tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_ETC___d957,
|
|
IF_tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_ETC___d958,
|
|
IF_tlb_m_validVec_12_43_AND_tlb_m_validVec_13__ETC___d947,
|
|
IF_tlb_m_validVec_16_56_AND_tlb_m_validVec_17__ETC___d942,
|
|
IF_tlb_m_validVec_16_56_AND_tlb_m_validVec_17__ETC___d943,
|
|
IF_tlb_m_validVec_20_67_AND_tlb_m_validVec_21__ETC___d939,
|
|
IF_tlb_m_validVec_24_79_AND_tlb_m_validVec_25__ETC___d935,
|
|
IF_tlb_m_validVec_24_79_AND_tlb_m_validVec_25__ETC___d936,
|
|
IF_tlb_m_validVec_28_90_AND_tlb_m_validVec_29__ETC___d932,
|
|
IF_tlb_m_validVec_4_20_AND_tlb_m_validVec_5_22_ETC___d954,
|
|
IF_tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_ETC___d950,
|
|
IF_tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_ETC___d951,
|
|
addIdx__h50635,
|
|
addIdx__h55485,
|
|
idx__h70014,
|
|
v__h40453,
|
|
v__h45270,
|
|
v__h46798;
|
|
wire [3 : 0] SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d1647;
|
|
wire IF_IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_ETC___d2355,
|
|
IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d234,
|
|
IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d243,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d396,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d405,
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d410,
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d497,
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d506,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2006,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2007,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2008,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2009,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2010,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2011,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2012,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2013,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2014,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2015,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2016,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2017,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2018,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2019,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2020,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2021,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2022,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2023,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2024,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2025,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2026,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2027,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2028,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2029,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2030,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2031,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2032,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2033,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2034,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2035,
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2036,
|
|
IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deqReq_ETC___d210,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52,
|
|
IF_perfReqQ_enqReq_lat_1_whas__23_THEN_perfReq_ETC___d632,
|
|
IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_de_ETC___d372,
|
|
IF_rqToPQ_enqReq_lat_1_whas__37_THEN_rqToPQ_en_ETC___d346,
|
|
IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFromP_ETC___d473,
|
|
IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_NOT_rsF_ETC___d438,
|
|
IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_rsFromP_ETC___d431,
|
|
IF_tlb_m_entryVec_10_256_BITS_1_TO_0_260_EQ_0__ETC___d1764,
|
|
IF_tlb_m_entryVec_11_269_BITS_1_TO_0_273_EQ_0__ETC___d1774,
|
|
IF_tlb_m_entryVec_12_282_BITS_1_TO_0_286_EQ_0__ETC___d1784,
|
|
IF_tlb_m_entryVec_13_295_BITS_1_TO_0_299_EQ_0__ETC___d1794,
|
|
IF_tlb_m_entryVec_14_308_BITS_1_TO_0_312_EQ_0__ETC___d1804,
|
|
IF_tlb_m_entryVec_15_321_BITS_1_TO_0_325_EQ_0__ETC___d1814,
|
|
IF_tlb_m_entryVec_16_334_BITS_1_TO_0_338_EQ_0__ETC___d1824,
|
|
IF_tlb_m_entryVec_17_347_BITS_1_TO_0_351_EQ_0__ETC___d1834,
|
|
IF_tlb_m_entryVec_18_360_BITS_1_TO_0_364_EQ_0__ETC___d1844,
|
|
IF_tlb_m_entryVec_19_373_BITS_1_TO_0_377_EQ_0__ETC___d1854,
|
|
IF_tlb_m_entryVec_1_139_BITS_1_TO_0_143_EQ_0_6_ETC___d1674,
|
|
IF_tlb_m_entryVec_20_386_BITS_1_TO_0_390_EQ_0__ETC___d1864,
|
|
IF_tlb_m_entryVec_21_399_BITS_1_TO_0_403_EQ_0__ETC___d1874,
|
|
IF_tlb_m_entryVec_22_412_BITS_1_TO_0_416_EQ_0__ETC___d1884,
|
|
IF_tlb_m_entryVec_23_425_BITS_1_TO_0_429_EQ_0__ETC___d1894,
|
|
IF_tlb_m_entryVec_24_438_BITS_1_TO_0_442_EQ_0__ETC___d1904,
|
|
IF_tlb_m_entryVec_25_451_BITS_1_TO_0_455_EQ_0__ETC___d1914,
|
|
IF_tlb_m_entryVec_26_464_BITS_1_TO_0_468_EQ_0__ETC___d1924,
|
|
IF_tlb_m_entryVec_27_477_BITS_1_TO_0_481_EQ_0__ETC___d1934,
|
|
IF_tlb_m_entryVec_28_490_BITS_1_TO_0_494_EQ_0__ETC___d1944,
|
|
IF_tlb_m_entryVec_29_503_BITS_1_TO_0_507_EQ_0__ETC___d1954,
|
|
IF_tlb_m_entryVec_2_152_BITS_1_TO_0_156_EQ_0_6_ETC___d1684,
|
|
IF_tlb_m_entryVec_30_516_BITS_1_TO_0_520_EQ_0__ETC___d1964,
|
|
IF_tlb_m_entryVec_31_529_BITS_1_TO_0_533_EQ_0__ETC___d1974,
|
|
IF_tlb_m_entryVec_3_165_BITS_1_TO_0_169_EQ_0_6_ETC___d1694,
|
|
IF_tlb_m_entryVec_4_178_BITS_1_TO_0_182_EQ_0_6_ETC___d1704,
|
|
IF_tlb_m_entryVec_5_191_BITS_1_TO_0_195_EQ_0_7_ETC___d1714,
|
|
IF_tlb_m_entryVec_6_204_BITS_1_TO_0_208_EQ_0_7_ETC___d1724,
|
|
IF_tlb_m_entryVec_7_217_BITS_1_TO_0_221_EQ_0_7_ETC___d1734,
|
|
IF_tlb_m_entryVec_8_230_BITS_1_TO_0_234_EQ_0_7_ETC___d1744,
|
|
IF_tlb_m_entryVec_9_243_BITS_1_TO_0_247_EQ_0_7_ETC___d1754,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17,
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_ETC___d790,
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_ETC___d2359,
|
|
NOT_SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27__ETC___d763,
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d770,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1967,
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_tlb_m_validV_ETC___d831,
|
|
NOT_tlb_m_validVec_11_39_40_OR_NOT_tlb_m_entry_ETC___d1561,
|
|
NOT_tlb_m_validVec_13_45_46_OR_NOT_tlb_m_entry_ETC___d1559,
|
|
NOT_tlb_m_validVec_15_50_51_OR_NOT_tlb_m_entry_ETC___d1557,
|
|
NOT_tlb_m_validVec_16_56_57_OR_NOT_tlb_m_valid_ETC___d878,
|
|
NOT_tlb_m_validVec_17_58_59_OR_NOT_tlb_m_entry_ETC___d1555,
|
|
NOT_tlb_m_validVec_19_63_64_OR_NOT_tlb_m_entry_ETC___d1553,
|
|
NOT_tlb_m_validVec_1_11_12_OR_NOT_tlb_m_entryV_ETC___d1571,
|
|
NOT_tlb_m_validVec_21_69_70_OR_NOT_tlb_m_entry_ETC___d1551,
|
|
NOT_tlb_m_validVec_23_74_75_OR_NOT_tlb_m_entry_ETC___d1549,
|
|
NOT_tlb_m_validVec_24_79_80_OR_NOT_tlb_m_valid_ETC___d901,
|
|
NOT_tlb_m_validVec_25_81_82_OR_NOT_tlb_m_entry_ETC___d1547,
|
|
NOT_tlb_m_validVec_27_86_87_OR_NOT_tlb_m_entry_ETC___d1545,
|
|
NOT_tlb_m_validVec_29_92_93_OR_NOT_tlb_m_entry_ETC___d1543,
|
|
NOT_tlb_m_validVec_3_16_17_OR_NOT_tlb_m_entryV_ETC___d1569,
|
|
NOT_tlb_m_validVec_5_22_23_OR_NOT_tlb_m_entryV_ETC___d1567,
|
|
NOT_tlb_m_validVec_7_27_28_OR_NOT_tlb_m_entryV_ETC___d1565,
|
|
NOT_tlb_m_validVec_8_32_33_OR_NOT_tlb_m_validV_ETC___d854,
|
|
NOT_tlb_m_validVec_9_34_35_OR_NOT_tlb_m_entryV_ETC___d1563,
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d768,
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27_rsFr_ETC___d785,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573,
|
|
_theResult_____2__h10173,
|
|
_theResult_____2__h13809,
|
|
_theResult_____2__h18424,
|
|
next_deqP___1__h10362,
|
|
next_deqP___1__h13998,
|
|
next_deqP___1__h18613,
|
|
tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_04_ETC___d910,
|
|
tlb_m_validVec_16_56_AND_tlb_m_validVec_17_58__ETC___d925,
|
|
tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_11_ETC___d917,
|
|
v__h13437,
|
|
v__h13588,
|
|
v__h17382,
|
|
v__h17533,
|
|
v__h8839,
|
|
v__h8990,
|
|
vm_info_24_BIT_46_60_AND_IF_NOT_tlb_m_validVec_ETC___d2379,
|
|
vm_info_24_BIT_46_60_AND_NOT_tlb_m_validVec_0__ETC___d2384;
|
|
|
|
// value method flush_done
|
|
assign flush_done = !needFlush ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = !needFlush ;
|
|
assign CAN_FIRE_flush = !needFlush ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// value method noPendingReq
|
|
assign noPendingReq = !miss[64] ;
|
|
assign RDY_noPendingReq = 1'd1 ;
|
|
|
|
// action method to_proc_request_put
|
|
assign RDY_to_proc_request_put =
|
|
!needFlush && !miss[64] && !hitQ_full && !rqToPQ_full &&
|
|
(!vm_info[46] ||
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d770) ;
|
|
assign CAN_FIRE_to_proc_request_put = RDY_to_proc_request_put ;
|
|
assign WILL_FIRE_to_proc_request_put = EN_to_proc_request_put ;
|
|
|
|
// actionvalue method to_proc_response_get
|
|
assign to_proc_response_get =
|
|
{ x__h74975,
|
|
!CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q50,
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2476 } ;
|
|
assign RDY_to_proc_response_get = !hitQ_empty ;
|
|
assign CAN_FIRE_to_proc_response_get = !hitQ_empty ;
|
|
assign WILL_FIRE_to_proc_response_get = EN_to_proc_response_get ;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
assign toParent_rqToP_notEmpty = !rqToPQ_empty ;
|
|
assign RDY_toParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method toParent_rqToP_deq
|
|
assign RDY_toParent_rqToP_deq = !rqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_rqToP_deq = !rqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_rqToP_deq = EN_toParent_rqToP_deq ;
|
|
|
|
// value method toParent_rqToP_first
|
|
always@(rqToPQ_deqP or rqToPQ_data_0 or rqToPQ_data_1)
|
|
begin
|
|
case (rqToPQ_deqP)
|
|
1'd0: toParent_rqToP_first = rqToPQ_data_0;
|
|
1'd1: toParent_rqToP_first = rqToPQ_data_1;
|
|
endcase
|
|
end
|
|
assign RDY_toParent_rqToP_first = !rqToPQ_empty ;
|
|
|
|
// value method toParent_rsFromP_notFull
|
|
assign toParent_rsFromP_notFull = !rsFromPQ_full ;
|
|
assign RDY_toParent_rsFromP_notFull = 1'd1 ;
|
|
|
|
// action method toParent_rsFromP_enq
|
|
assign RDY_toParent_rsFromP_enq = !rsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_rsFromP_enq = !rsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_rsFromP_enq = EN_toParent_rsFromP_enq ;
|
|
|
|
// action method toParent_flush_request_get
|
|
assign RDY_toParent_flush_request_get = !flushRqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_flush_request_get = !flushRqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_flush_request_get =
|
|
EN_toParent_flush_request_get ;
|
|
|
|
// action method toParent_flush_response_put
|
|
assign RDY_toParent_flush_response_put = !flushRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_flush_response_put = !flushRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_flush_response_put =
|
|
EN_toParent_flush_response_put ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// rule RL_doStartFlush
|
|
assign CAN_FIRE_RL_doStartFlush =
|
|
!flushRqToPQ_full && needFlush && !waitFlushP && !miss[64] ;
|
|
assign WILL_FIRE_RL_doStartFlush = CAN_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doFinishFlush
|
|
assign CAN_FIRE_RL_doFinishFlush =
|
|
!flushRsFromPQ_empty && needFlush && waitFlushP && !miss[64] ;
|
|
assign WILL_FIRE_RL_doFinishFlush = CAN_FIRE_RL_doFinishFlush ;
|
|
|
|
// rule RL_set_no_pending
|
|
assign CAN_FIRE_RL_set_no_pending = 1'd1 ;
|
|
assign WILL_FIRE_RL_set_no_pending = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_doUpdateRep
|
|
assign CAN_FIRE_RL_tlb_m_doUpdateRep =
|
|
!CAN_FIRE_RL_doStartFlush && tlb_m_updRepIdx_rl[5] ;
|
|
assign WILL_FIRE_RL_tlb_m_doUpdateRep =
|
|
CAN_FIRE_RL_tlb_m_doUpdateRep && !WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// rule RL_doRsFromP
|
|
assign CAN_FIRE_RL_doRsFromP =
|
|
!hitQ_full && !rsFromPQ_empty &&
|
|
(!SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 ||
|
|
!SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d712 ||
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d768 ||
|
|
NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d770) &&
|
|
miss[64] ;
|
|
assign WILL_FIRE_RL_doRsFromP = CAN_FIRE_RL_doRsFromP ;
|
|
|
|
// rule RL_tlb_m_incRandIdx
|
|
assign CAN_FIRE_RL_tlb_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_lruBit_canon
|
|
assign CAN_FIRE_RL_tlb_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_tlb_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_canonicalize
|
|
assign CAN_FIRE_RL_hitQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_hitQ_enqReq_canon
|
|
assign CAN_FIRE_RL_hitQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_deqReq_canon
|
|
assign CAN_FIRE_RL_hitQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_hitQ_clearReq_canon
|
|
assign CAN_FIRE_RL_hitQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_hitQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_rsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_rsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_rsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_rsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_flushRqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_flushRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__SEL_1 =
|
|
EN_to_proc_request_put &&
|
|
(IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2036 ||
|
|
!vm_info[46]) ;
|
|
assign MUX_miss$write_1__SEL_1 =
|
|
EN_to_proc_request_put &&
|
|
vm_info_24_BIT_46_60_AND_NOT_tlb_m_validVec_0__ETC___d2384 ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_10$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd10 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_11$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd11 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_12$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd12 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_13$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd13 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_14$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd14 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_15$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd15 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_16$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd16 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_17$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd17 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_18$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd18 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_19$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd19 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_20$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd20 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_21$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd21 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_22$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd22 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_23$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd23 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_24$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd24 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_25$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd25 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_26$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd26 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_27$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd27 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_28$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd28 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_29$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd29 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd3 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_30$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd30 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_31$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd31 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd4 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd5 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd6 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd7 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_8$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd8 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_tlb_m_validVec_9$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd9 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ;
|
|
assign MUX_waitFlushP$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doFinishFlush || EN_flush ;
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
IF_vm_info_24_BIT_46_60_THEN_IF_SEL_ARR_tlb_m__ETC___d2376 } ;
|
|
assign MUX_hitQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 ?
|
|
((SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d712 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_ETC___d790) ?
|
|
{ x__h65230, 6'd10 } :
|
|
70'h2AAAAAAAAAAAAAAAAC) :
|
|
70'h2AAAAAAAAAAAAAAAAC } ;
|
|
assign MUX_miss$write_1__VAL_1 = { 1'd1, to_proc_request_put } ;
|
|
assign MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h5317 == 32'hFFFFFFFF) ? x__h5375 : val__h5317 ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, v__h40453 } ;
|
|
assign MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, idx__h70014 } ;
|
|
|
|
// inlined wires
|
|
assign tlb_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep || WILL_FIRE_RL_doStartFlush ;
|
|
assign tlb_m_updRepIdx_lat_0$whas =
|
|
WILL_FIRE_RL_doStartFlush || WILL_FIRE_RL_tlb_m_doUpdateRep ;
|
|
assign tlb_m_updRepIdx_lat_1$wget =
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign tlb_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_doRsFromP &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
EN_to_proc_request_put &&
|
|
vm_info_24_BIT_46_60_AND_IF_NOT_tlb_m_validVec_ETC___d2379 ;
|
|
assign hitQ_enqReq_lat_0$wget =
|
|
MUX_hitQ_enqReq_lat_0$wset_1__SEL_1 ?
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_hitQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign hitQ_enqReq_lat_0$whas =
|
|
EN_to_proc_request_put &&
|
|
(IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2036 ||
|
|
!vm_info[46]) ||
|
|
WILL_FIRE_RL_doRsFromP ;
|
|
assign rqToPQ_enqReq_lat_0$wget = { 1'd1, to_proc_request_put[38:12] } ;
|
|
assign rsFromPQ_enqReq_lat_0$wget = { 1'd1, toParent_rsFromP_enq_x } ;
|
|
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
|
|
// register flushRqToPQ_clearReq_rl
|
|
assign flushRqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_deqReq_rl
|
|
assign flushRqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_empty
|
|
assign flushRqToPQ_empty$D_IN =
|
|
flushRqToPQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_doStartFlush && !flushRqToPQ_enqReq_rl &&
|
|
(EN_toParent_flush_request_get || flushRqToPQ_deqReq_rl ||
|
|
flushRqToPQ_empty) ;
|
|
assign flushRqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_enqReq_rl
|
|
assign flushRqToPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRqToPQ_full
|
|
assign flushRqToPQ_full$D_IN =
|
|
!flushRqToPQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_doStartFlush || flushRqToPQ_enqReq_rl ||
|
|
!EN_toParent_flush_request_get && !flushRqToPQ_deqReq_rl &&
|
|
flushRqToPQ_full) ;
|
|
assign flushRqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_clearReq_rl
|
|
assign flushRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_deqReq_rl
|
|
assign flushRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_empty
|
|
assign flushRsFromPQ_empty$D_IN =
|
|
flushRsFromPQ_clearReq_rl ||
|
|
!EN_toParent_flush_response_put && !flushRsFromPQ_enqReq_rl &&
|
|
(CAN_FIRE_RL_doFinishFlush || flushRsFromPQ_deqReq_rl ||
|
|
flushRsFromPQ_empty) ;
|
|
assign flushRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_enqReq_rl
|
|
assign flushRsFromPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign flushRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register flushRsFromPQ_full
|
|
assign flushRsFromPQ_full$D_IN =
|
|
!flushRsFromPQ_clearReq_rl &&
|
|
(EN_toParent_flush_response_put || flushRsFromPQ_enqReq_rl ||
|
|
!CAN_FIRE_RL_doFinishFlush && !flushRsFromPQ_deqReq_rl &&
|
|
flushRsFromPQ_full) ;
|
|
assign flushRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register hitQ_clearReq_rl
|
|
assign hitQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign hitQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_data_0
|
|
assign hitQ_data_0$D_IN =
|
|
{ x__h9109,
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 ||
|
|
(hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[5] :
|
|
hitQ_enqReq_rl[5]),
|
|
CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 } ;
|
|
assign hitQ_data_0$EN =
|
|
hitQ_enqP == 1'd0 && !hitQ_clearReq_rl &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ;
|
|
|
|
// register hitQ_data_1
|
|
assign hitQ_data_1$D_IN = hitQ_data_0$D_IN ;
|
|
assign hitQ_data_1$EN =
|
|
hitQ_enqP == 1'd1 && !hitQ_clearReq_rl &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ;
|
|
|
|
// register hitQ_deqP
|
|
assign hitQ_deqP$D_IN = !hitQ_clearReq_rl && _theResult_____2__h10173 ;
|
|
assign hitQ_deqP$EN = 1'd1 ;
|
|
|
|
// register hitQ_deqReq_rl
|
|
assign hitQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign hitQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_empty
|
|
assign hitQ_empty$D_IN =
|
|
hitQ_clearReq_rl ||
|
|
IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d234 &&
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 &&
|
|
(IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deqReq_ETC___d210 ||
|
|
hitQ_empty) ;
|
|
assign hitQ_empty$EN = 1'd1 ;
|
|
|
|
// register hitQ_enqP
|
|
assign hitQ_enqP$D_IN = !hitQ_clearReq_rl && v__h8839 ;
|
|
assign hitQ_enqP$EN = 1'd1 ;
|
|
|
|
// register hitQ_enqReq_rl
|
|
assign hitQ_enqReq_rl$D_IN = 71'h2AAAAAAAAAAAAAAABC ;
|
|
assign hitQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register hitQ_full
|
|
assign hitQ_full$D_IN =
|
|
!hitQ_clearReq_rl &&
|
|
IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d243 ;
|
|
assign hitQ_full$EN = 1'd1 ;
|
|
|
|
// register miss
|
|
assign miss$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
MUX_miss$write_1__VAL_1 :
|
|
65'h0AAAAAAAAAAAAAAAA ;
|
|
assign miss$EN =
|
|
EN_to_proc_request_put &&
|
|
vm_info_24_BIT_46_60_AND_NOT_tlb_m_validVec_0__ETC___d2384 ||
|
|
WILL_FIRE_RL_doRsFromP ;
|
|
|
|
// register needFlush
|
|
assign needFlush$D_IN = !WILL_FIRE_RL_doFinishFlush ;
|
|
assign needFlush$EN = MUX_waitFlushP$write_1__SEL_1 ;
|
|
|
|
// register perfReqQ_clearReq_rl
|
|
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_data_0
|
|
assign perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[2:0] :
|
|
perfReqQ_enqReq_rl[2:0] ;
|
|
assign perfReqQ_data_0$EN =
|
|
!perfReqQ_clearReq_rl &&
|
|
IF_perfReqQ_enqReq_lat_1_whas__23_THEN_perfReq_ETC___d632 ;
|
|
|
|
// register perfReqQ_deqReq_rl
|
|
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_empty
|
|
assign perfReqQ_empty$D_IN =
|
|
perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!perfReqQ_enqReq_lat_0$wget[3] :
|
|
!perfReqQ_enqReq_rl[3]) &&
|
|
(EN_perf_resp || perfReqQ_deqReq_rl || perfReqQ_empty) ;
|
|
assign perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_enqReq_rl
|
|
assign perfReqQ_enqReq_rl$D_IN = 4'b0010 ;
|
|
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register perfReqQ_full
|
|
assign perfReqQ_full$D_IN =
|
|
!perfReqQ_clearReq_rl &&
|
|
(IF_perfReqQ_enqReq_lat_1_whas__23_THEN_perfReq_ETC___d632 ||
|
|
!EN_perf_resp && !perfReqQ_deqReq_rl && perfReqQ_full) ;
|
|
assign perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_clearReq_rl
|
|
assign rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_data_0
|
|
assign rqToPQ_data_0$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[26:0] :
|
|
rqToPQ_enqReq_rl[26:0] ;
|
|
assign rqToPQ_data_0$EN =
|
|
rqToPQ_enqP == 1'd0 && !rqToPQ_clearReq_rl &&
|
|
IF_rqToPQ_enqReq_lat_1_whas__37_THEN_rqToPQ_en_ETC___d346 ;
|
|
|
|
// register rqToPQ_data_1
|
|
assign rqToPQ_data_1$D_IN =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[26:0] :
|
|
rqToPQ_enqReq_rl[26:0] ;
|
|
assign rqToPQ_data_1$EN =
|
|
rqToPQ_enqP == 1'd1 && !rqToPQ_clearReq_rl &&
|
|
IF_rqToPQ_enqReq_lat_1_whas__37_THEN_rqToPQ_en_ETC___d346 ;
|
|
|
|
// register rqToPQ_deqP
|
|
assign rqToPQ_deqP$D_IN = !rqToPQ_clearReq_rl && _theResult_____2__h13809 ;
|
|
assign rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_deqReq_rl
|
|
assign rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_empty
|
|
assign rqToPQ_empty$D_IN =
|
|
rqToPQ_clearReq_rl ||
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d410 ;
|
|
assign rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_enqP
|
|
assign rqToPQ_enqP$D_IN = !rqToPQ_clearReq_rl && v__h13437 ;
|
|
assign rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_enqReq_rl
|
|
assign rqToPQ_enqReq_rl$D_IN = 28'b0010101010101010101010101010 ;
|
|
assign rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rqToPQ_full
|
|
assign rqToPQ_full$D_IN =
|
|
!rqToPQ_clearReq_rl &&
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d405 ;
|
|
assign rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_clearReq_rl
|
|
assign rsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign rsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_data_0
|
|
assign rsFromPQ_data_0$D_IN =
|
|
{ IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_NOT_rsF_ETC___d438 ||
|
|
(EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[80] :
|
|
rsFromPQ_enqReq_rl[80]),
|
|
EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[79:0] :
|
|
rsFromPQ_enqReq_rl[79:0] } ;
|
|
assign rsFromPQ_data_0$EN =
|
|
rsFromPQ_enqP == 1'd0 && !rsFromPQ_clearReq_rl &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_rsFromP_ETC___d431 ;
|
|
|
|
// register rsFromPQ_data_1
|
|
assign rsFromPQ_data_1$D_IN = rsFromPQ_data_0$D_IN ;
|
|
assign rsFromPQ_data_1$EN =
|
|
rsFromPQ_enqP == 1'd1 && !rsFromPQ_clearReq_rl &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_rsFromP_ETC___d431 ;
|
|
|
|
// register rsFromPQ_deqP
|
|
assign rsFromPQ_deqP$D_IN =
|
|
!rsFromPQ_clearReq_rl && _theResult_____2__h18424 ;
|
|
assign rsFromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_deqReq_rl
|
|
assign rsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign rsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_empty
|
|
assign rsFromPQ_empty$D_IN =
|
|
rsFromPQ_clearReq_rl ||
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d497 &&
|
|
IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_NOT_rsF_ETC___d438 &&
|
|
(IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFromP_ETC___d473 ||
|
|
rsFromPQ_empty) ;
|
|
assign rsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_enqP
|
|
assign rsFromPQ_enqP$D_IN = !rsFromPQ_clearReq_rl && v__h17382 ;
|
|
assign rsFromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_enqReq_rl
|
|
assign rsFromPQ_enqReq_rl$D_IN = 82'h0AAAAAAAAAAAAAAAAAAAA ;
|
|
assign rsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register rsFromPQ_full
|
|
assign rsFromPQ_full$D_IN =
|
|
!rsFromPQ_clearReq_rl &&
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d506 ;
|
|
assign rsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register tlb_m_entryVec_0
|
|
assign tlb_m_entryVec_0$D_IN =
|
|
{ SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123,
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_8_638_rsFromPQ__ETC___d1649 } ;
|
|
assign tlb_m_entryVec_0$EN = MUX_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_1
|
|
assign tlb_m_entryVec_1$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_1$EN = MUX_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_10
|
|
assign tlb_m_entryVec_10$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_10$EN = MUX_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_11
|
|
assign tlb_m_entryVec_11$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_11$EN = MUX_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_12
|
|
assign tlb_m_entryVec_12$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_12$EN = MUX_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_13
|
|
assign tlb_m_entryVec_13$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_13$EN = MUX_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_14
|
|
assign tlb_m_entryVec_14$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_14$EN = MUX_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_15
|
|
assign tlb_m_entryVec_15$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_15$EN = MUX_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_16
|
|
assign tlb_m_entryVec_16$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_16$EN = MUX_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_17
|
|
assign tlb_m_entryVec_17$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_17$EN = MUX_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_18
|
|
assign tlb_m_entryVec_18$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_18$EN = MUX_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_19
|
|
assign tlb_m_entryVec_19$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_19$EN = MUX_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_2
|
|
assign tlb_m_entryVec_2$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_2$EN = MUX_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_20
|
|
assign tlb_m_entryVec_20$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_20$EN = MUX_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_21
|
|
assign tlb_m_entryVec_21$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_21$EN = MUX_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_22
|
|
assign tlb_m_entryVec_22$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_22$EN = MUX_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_23
|
|
assign tlb_m_entryVec_23$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_23$EN = MUX_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_24
|
|
assign tlb_m_entryVec_24$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_24$EN = MUX_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_25
|
|
assign tlb_m_entryVec_25$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_25$EN = MUX_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_26
|
|
assign tlb_m_entryVec_26$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_26$EN = MUX_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_27
|
|
assign tlb_m_entryVec_27$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_27$EN = MUX_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_28
|
|
assign tlb_m_entryVec_28$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_28$EN = MUX_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_29
|
|
assign tlb_m_entryVec_29$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_29$EN = MUX_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_3
|
|
assign tlb_m_entryVec_3$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_3$EN = MUX_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_30
|
|
assign tlb_m_entryVec_30$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_30$EN = MUX_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_31
|
|
assign tlb_m_entryVec_31$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_31$EN = MUX_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_4
|
|
assign tlb_m_entryVec_4$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_4$EN = MUX_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_5
|
|
assign tlb_m_entryVec_5$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_5$EN = MUX_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_6
|
|
assign tlb_m_entryVec_6$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_6$EN = MUX_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_7
|
|
assign tlb_m_entryVec_7$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_7$EN = MUX_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_8
|
|
assign tlb_m_entryVec_8$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_8$EN = MUX_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_entryVec_9
|
|
assign tlb_m_entryVec_9$D_IN = tlb_m_entryVec_0$D_IN ;
|
|
assign tlb_m_entryVec_9$EN = MUX_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
|
|
// register tlb_m_lruBit_rl
|
|
assign tlb_m_lruBit_rl$D_IN = n__read__h46006 ;
|
|
assign tlb_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register tlb_m_randIdx
|
|
assign tlb_m_randIdx$D_IN = tlb_m_randIdx + 5'd1 ;
|
|
assign tlb_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register tlb_m_updRepIdx_rl
|
|
assign tlb_m_updRepIdx_rl$D_IN =
|
|
{ IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17,
|
|
IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27 } ;
|
|
assign tlb_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register tlb_m_validVec_0
|
|
assign tlb_m_validVec_0$D_IN = MUX_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_0$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_1
|
|
assign tlb_m_validVec_1$D_IN = MUX_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_1$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_10
|
|
assign tlb_m_validVec_10$D_IN = MUX_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_10$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd10 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_11
|
|
assign tlb_m_validVec_11$D_IN = MUX_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_11$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd11 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_12
|
|
assign tlb_m_validVec_12$D_IN = MUX_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_12$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd12 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_13
|
|
assign tlb_m_validVec_13$D_IN = MUX_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_13$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd13 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_14
|
|
assign tlb_m_validVec_14$D_IN = MUX_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_14$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd14 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_15
|
|
assign tlb_m_validVec_15$D_IN = MUX_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_15$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd15 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_16
|
|
assign tlb_m_validVec_16$D_IN = MUX_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_16$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd16 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_17
|
|
assign tlb_m_validVec_17$D_IN = MUX_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_17$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd17 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_18
|
|
assign tlb_m_validVec_18$D_IN = MUX_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_18$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd18 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_19
|
|
assign tlb_m_validVec_19$D_IN = MUX_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_19$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd19 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_2
|
|
assign tlb_m_validVec_2$D_IN = MUX_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_2$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_20
|
|
assign tlb_m_validVec_20$D_IN = MUX_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_20$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd20 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_21
|
|
assign tlb_m_validVec_21$D_IN = MUX_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_21$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd21 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_22
|
|
assign tlb_m_validVec_22$D_IN = MUX_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_22$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd22 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_23
|
|
assign tlb_m_validVec_23$D_IN = MUX_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_23$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd23 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_24
|
|
assign tlb_m_validVec_24$D_IN = MUX_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_24$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd24 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_25
|
|
assign tlb_m_validVec_25$D_IN = MUX_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_25$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd25 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_26
|
|
assign tlb_m_validVec_26$D_IN = MUX_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_26$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd26 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_27
|
|
assign tlb_m_validVec_27$D_IN = MUX_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_27$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd27 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_28
|
|
assign tlb_m_validVec_28$D_IN = MUX_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_28$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd28 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_29
|
|
assign tlb_m_validVec_29$D_IN = MUX_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_29$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd29 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_3
|
|
assign tlb_m_validVec_3$D_IN = MUX_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_3$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd3 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_30
|
|
assign tlb_m_validVec_30$D_IN = MUX_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_30$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd30 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_31
|
|
assign tlb_m_validVec_31$D_IN = MUX_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_31$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd31 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_4
|
|
assign tlb_m_validVec_4$D_IN = MUX_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_4$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd4 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_5
|
|
assign tlb_m_validVec_5$D_IN = MUX_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_5$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd5 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_6
|
|
assign tlb_m_validVec_6$D_IN = MUX_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_6$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd6 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_7
|
|
assign tlb_m_validVec_7$D_IN = MUX_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_7$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd7 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_8
|
|
assign tlb_m_validVec_8$D_IN = MUX_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_8$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd8 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register tlb_m_validVec_9
|
|
assign tlb_m_validVec_9$D_IN = MUX_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
assign tlb_m_validVec_9$EN =
|
|
WILL_FIRE_RL_doRsFromP && v__h40453 == 5'd9 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// register vm_info
|
|
assign vm_info$D_IN = updateVMInfo_vm ;
|
|
assign vm_info$EN = EN_updateVMInfo ;
|
|
|
|
// register waitFlushP
|
|
assign waitFlushP$D_IN = !MUX_waitFlushP$write_1__SEL_1 ;
|
|
assign waitFlushP$EN =
|
|
WILL_FIRE_RL_doFinishFlush || EN_flush ||
|
|
WILL_FIRE_RL_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_ETC___d2355 =
|
|
(level__h70028 == 2'd0 ||
|
|
((level__h70028 == 2'd1) ?
|
|
ppn__h74746[8:0] == 9'd0 :
|
|
level__h70028 == 2'd2 && ppn__h74746[17:0] == 18'd0)) &&
|
|
(!SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 ||
|
|
!SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352) ;
|
|
assign IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d234 =
|
|
_theResult_____2__h10173 == v__h8839 ;
|
|
assign IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d243 =
|
|
IF_IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deq_ETC___d234 &&
|
|
(IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ||
|
|
!EN_to_proc_response_get && !hitQ_deqReq_rl && hitQ_full) ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d396 =
|
|
_theResult_____2__h13809 == v__h13437 ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d405 =
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d396 &&
|
|
(IF_rqToPQ_enqReq_lat_1_whas__37_THEN_rqToPQ_en_ETC___d346 ||
|
|
!EN_toParent_rqToP_deq && !rqToPQ_deqReq_rl && rqToPQ_full) ;
|
|
assign IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d410 =
|
|
IF_IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_ETC___d396 &&
|
|
(MUX_miss$write_1__SEL_1 ?
|
|
!rqToPQ_enqReq_lat_0$wget[27] :
|
|
!rqToPQ_enqReq_rl[27]) &&
|
|
(IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_de_ETC___d372 ||
|
|
rqToPQ_empty) ;
|
|
assign IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d497 =
|
|
_theResult_____2__h18424 == v__h17382 ;
|
|
assign IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d506 =
|
|
IF_IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFr_ETC___d497 &&
|
|
(IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_rsFromP_ETC___d431 ||
|
|
!CAN_FIRE_RL_doRsFromP && !rsFromPQ_deqReq_rl &&
|
|
rsFromPQ_full) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2006 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667 ?
|
|
tlb_m_validVec_1 &&
|
|
IF_tlb_m_entryVec_1_139_BITS_1_TO_0_143_EQ_0_6_ETC___d1674 :
|
|
tlb_m_validVec_0 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2007 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_139_BITS_1_TO_0_143_EQ_0_6_ETC___d1674)) ?
|
|
tlb_m_validVec_2 &&
|
|
IF_tlb_m_entryVec_2_152_BITS_1_TO_0_156_EQ_0_6_ETC___d1684 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2006 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2008 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687 ?
|
|
tlb_m_validVec_3 &&
|
|
IF_tlb_m_entryVec_3_165_BITS_1_TO_0_169_EQ_0_6_ETC___d1694 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2007 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2009 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_165_BITS_1_TO_0_169_EQ_0_6_ETC___d1694)) ?
|
|
tlb_m_validVec_4 &&
|
|
IF_tlb_m_entryVec_4_178_BITS_1_TO_0_182_EQ_0_6_ETC___d1704 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2008 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2010 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707 ?
|
|
tlb_m_validVec_5 &&
|
|
IF_tlb_m_entryVec_5_191_BITS_1_TO_0_195_EQ_0_7_ETC___d1714 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2009 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2011 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_191_BITS_1_TO_0_195_EQ_0_7_ETC___d1714)) ?
|
|
tlb_m_validVec_6 &&
|
|
IF_tlb_m_entryVec_6_204_BITS_1_TO_0_208_EQ_0_7_ETC___d1724 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2010 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2012 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727 ?
|
|
tlb_m_validVec_7 &&
|
|
IF_tlb_m_entryVec_7_217_BITS_1_TO_0_221_EQ_0_7_ETC___d1734 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2011 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2013 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_217_BITS_1_TO_0_221_EQ_0_7_ETC___d1734)) ?
|
|
tlb_m_validVec_8 &&
|
|
IF_tlb_m_entryVec_8_230_BITS_1_TO_0_234_EQ_0_7_ETC___d1744 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2012 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2014 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747 ?
|
|
tlb_m_validVec_9 &&
|
|
IF_tlb_m_entryVec_9_243_BITS_1_TO_0_247_EQ_0_7_ETC___d1754 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2013 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2015 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_243_BITS_1_TO_0_247_EQ_0_7_ETC___d1754)) ?
|
|
tlb_m_validVec_10 &&
|
|
IF_tlb_m_entryVec_10_256_BITS_1_TO_0_260_EQ_0__ETC___d1764 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2014 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2016 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767 ?
|
|
tlb_m_validVec_11 &&
|
|
IF_tlb_m_entryVec_11_269_BITS_1_TO_0_273_EQ_0__ETC___d1774 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2015 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2017 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_269_BITS_1_TO_0_273_EQ_0__ETC___d1774)) ?
|
|
tlb_m_validVec_12 &&
|
|
IF_tlb_m_entryVec_12_282_BITS_1_TO_0_286_EQ_0__ETC___d1784 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2016 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2018 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787 ?
|
|
tlb_m_validVec_13 &&
|
|
IF_tlb_m_entryVec_13_295_BITS_1_TO_0_299_EQ_0__ETC___d1794 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2017 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2019 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_295_BITS_1_TO_0_299_EQ_0__ETC___d1794)) ?
|
|
tlb_m_validVec_14 &&
|
|
IF_tlb_m_entryVec_14_308_BITS_1_TO_0_312_EQ_0__ETC___d1804 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2018 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2020 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807 ?
|
|
tlb_m_validVec_15 &&
|
|
IF_tlb_m_entryVec_15_321_BITS_1_TO_0_325_EQ_0__ETC___d1814 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2019 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2021 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_321_BITS_1_TO_0_325_EQ_0__ETC___d1814)) ?
|
|
tlb_m_validVec_16 &&
|
|
IF_tlb_m_entryVec_16_334_BITS_1_TO_0_338_EQ_0__ETC___d1824 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2020 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2022 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827 ?
|
|
tlb_m_validVec_17 &&
|
|
IF_tlb_m_entryVec_17_347_BITS_1_TO_0_351_EQ_0__ETC___d1834 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2021 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2023 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_347_BITS_1_TO_0_351_EQ_0__ETC___d1834)) ?
|
|
tlb_m_validVec_18 &&
|
|
IF_tlb_m_entryVec_18_360_BITS_1_TO_0_364_EQ_0__ETC___d1844 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2022 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2024 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847 ?
|
|
tlb_m_validVec_19 &&
|
|
IF_tlb_m_entryVec_19_373_BITS_1_TO_0_377_EQ_0__ETC___d1854 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2023 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2025 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_373_BITS_1_TO_0_377_EQ_0__ETC___d1854)) ?
|
|
tlb_m_validVec_20 &&
|
|
IF_tlb_m_entryVec_20_386_BITS_1_TO_0_390_EQ_0__ETC___d1864 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2024 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2026 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867 ?
|
|
tlb_m_validVec_21 &&
|
|
IF_tlb_m_entryVec_21_399_BITS_1_TO_0_403_EQ_0__ETC___d1874 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2025 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2027 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_399_BITS_1_TO_0_403_EQ_0__ETC___d1874)) ?
|
|
tlb_m_validVec_22 &&
|
|
IF_tlb_m_entryVec_22_412_BITS_1_TO_0_416_EQ_0__ETC___d1884 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2026 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2028 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887 ?
|
|
tlb_m_validVec_23 &&
|
|
IF_tlb_m_entryVec_23_425_BITS_1_TO_0_429_EQ_0__ETC___d1894 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2027 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2029 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_425_BITS_1_TO_0_429_EQ_0__ETC___d1894)) ?
|
|
tlb_m_validVec_24 &&
|
|
IF_tlb_m_entryVec_24_438_BITS_1_TO_0_442_EQ_0__ETC___d1904 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2028 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2030 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907 ?
|
|
tlb_m_validVec_25 &&
|
|
IF_tlb_m_entryVec_25_451_BITS_1_TO_0_455_EQ_0__ETC___d1914 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2029 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2031 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_451_BITS_1_TO_0_455_EQ_0__ETC___d1914)) ?
|
|
tlb_m_validVec_26 &&
|
|
IF_tlb_m_entryVec_26_464_BITS_1_TO_0_468_EQ_0__ETC___d1924 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2030 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2032 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927 ?
|
|
tlb_m_validVec_27 &&
|
|
IF_tlb_m_entryVec_27_477_BITS_1_TO_0_481_EQ_0__ETC___d1934 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2031 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2033 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_477_BITS_1_TO_0_481_EQ_0__ETC___d1934)) ?
|
|
tlb_m_validVec_28 &&
|
|
IF_tlb_m_entryVec_28_490_BITS_1_TO_0_494_EQ_0__ETC___d1944 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2032 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2034 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947 ?
|
|
tlb_m_validVec_29 &&
|
|
IF_tlb_m_entryVec_29_503_BITS_1_TO_0_507_EQ_0__ETC___d1954 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2033 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2035 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_503_BITS_1_TO_0_507_EQ_0__ETC___d1954)) ?
|
|
tlb_m_validVec_30 &&
|
|
IF_tlb_m_entryVec_30_516_BITS_1_TO_0_520_EQ_0__ETC___d1964 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2034 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2036 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1967 ?
|
|
tlb_m_validVec_31 &&
|
|
IF_tlb_m_entryVec_31_529_BITS_1_TO_0_533_EQ_0__ETC___d1974 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2035 ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2072 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_139_BITS_1_TO_0_143_EQ_0_6_ETC___d1674)) ?
|
|
5'd2 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667 ?
|
|
5'd1 :
|
|
5'd0) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2074 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_165_BITS_1_TO_0_169_EQ_0_6_ETC___d1694)) ?
|
|
5'd4 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687 ?
|
|
5'd3 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2072) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2076 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_191_BITS_1_TO_0_195_EQ_0_7_ETC___d1714)) ?
|
|
5'd6 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707 ?
|
|
5'd5 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2074) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2078 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_217_BITS_1_TO_0_221_EQ_0_7_ETC___d1734)) ?
|
|
5'd8 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727 ?
|
|
5'd7 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2076) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2080 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_243_BITS_1_TO_0_247_EQ_0_7_ETC___d1754)) ?
|
|
5'd10 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747 ?
|
|
5'd9 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2078) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2082 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_269_BITS_1_TO_0_273_EQ_0__ETC___d1774)) ?
|
|
5'd12 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767 ?
|
|
5'd11 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2080) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2084 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_295_BITS_1_TO_0_299_EQ_0__ETC___d1794)) ?
|
|
5'd14 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787 ?
|
|
5'd13 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2082) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2086 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_321_BITS_1_TO_0_325_EQ_0__ETC___d1814)) ?
|
|
5'd16 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807 ?
|
|
5'd15 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2084) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2088 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_347_BITS_1_TO_0_351_EQ_0__ETC___d1834)) ?
|
|
5'd18 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827 ?
|
|
5'd17 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2086) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2090 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_373_BITS_1_TO_0_377_EQ_0__ETC___d1854)) ?
|
|
5'd20 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847 ?
|
|
5'd19 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2088) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2092 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_399_BITS_1_TO_0_403_EQ_0__ETC___d1874)) ?
|
|
5'd22 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867 ?
|
|
5'd21 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2090) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2094 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_425_BITS_1_TO_0_429_EQ_0__ETC___d1894)) ?
|
|
5'd24 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887 ?
|
|
5'd23 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2092) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2096 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_451_BITS_1_TO_0_455_EQ_0__ETC___d1914)) ?
|
|
5'd26 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907 ?
|
|
5'd25 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2094) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2098 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_477_BITS_1_TO_0_481_EQ_0__ETC___d1934)) ?
|
|
5'd28 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927 ?
|
|
5'd27 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2096) ;
|
|
assign IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2100 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_503_BITS_1_TO_0_507_EQ_0__ETC___d1954)) ?
|
|
5'd30 :
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947 ?
|
|
5'd29 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2098) ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2464 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_13_ETC__q36 ?
|
|
5'd13 :
|
|
(CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_15_ETC__q37 ?
|
|
5'd15 :
|
|
5'd28) ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2465 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_12_ETC__q38 ?
|
|
5'd12 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2464 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2466 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_11_ETC__q39 ?
|
|
5'd11 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2465 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2467 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_9__ETC__q40 ?
|
|
5'd9 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2466 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2468 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_8__ETC__q41 ?
|
|
5'd8 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2467 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2469 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_7__ETC__q42 ?
|
|
5'd7 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2468 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2470 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_6__ETC__q43 ?
|
|
5'd6 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2469 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2471 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_5__ETC__q44 ?
|
|
5'd5 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2470 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2472 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_4__ETC__q45 ?
|
|
5'd4 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2471 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2473 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_3__ETC__q46 ?
|
|
5'd3 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2472 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2474 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_2__ETC__q47 ?
|
|
5'd2 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2473 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2475 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_1__ETC__q48 ?
|
|
5'd1 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2474 ;
|
|
assign IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2476 =
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_0__ETC__q49 ?
|
|
5'd0 :
|
|
IF_SEL_ARR_hitQ_data_0_392_BITS_4_TO_0_405_EQ__ETC___d2475 ;
|
|
assign IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deqReq_ETC___d210 =
|
|
EN_to_proc_response_get || hitQ_deqReq_rl ;
|
|
assign IF_hitQ_enqReq_lat_1_whas__3_THEN_NOT_hitQ_enq_ETC___d59 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
!hitQ_enqReq_lat_0$wget[70] :
|
|
!hitQ_enqReq_rl[70] ;
|
|
assign IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[70] :
|
|
hitQ_enqReq_rl[70] ;
|
|
assign IF_perfReqQ_enqReq_lat_1_whas__23_THEN_perfReq_ETC___d632 =
|
|
EN_perf_req ?
|
|
perfReqQ_enqReq_lat_0$wget[3] :
|
|
perfReqQ_enqReq_rl[3] ;
|
|
assign IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_de_ETC___d372 =
|
|
EN_toParent_rqToP_deq || rqToPQ_deqReq_rl ;
|
|
assign IF_rqToPQ_enqReq_lat_1_whas__37_THEN_rqToPQ_en_ETC___d346 =
|
|
MUX_miss$write_1__SEL_1 ?
|
|
rqToPQ_enqReq_lat_0$wget[27] :
|
|
rqToPQ_enqReq_rl[27] ;
|
|
assign IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFromP_ETC___d473 =
|
|
CAN_FIRE_RL_doRsFromP || rsFromPQ_deqReq_rl ;
|
|
assign IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_NOT_rsF_ETC___d438 =
|
|
EN_toParent_rsFromP_enq ?
|
|
!rsFromPQ_enqReq_lat_0$wget[81] :
|
|
!rsFromPQ_enqReq_rl[81] ;
|
|
assign IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_rsFromP_ETC___d431 =
|
|
EN_toParent_rsFromP_enq ?
|
|
rsFromPQ_enqReq_lat_0$wget[81] :
|
|
rsFromPQ_enqReq_rl[81] ;
|
|
assign IF_tlb_m_entryVec_10_256_BITS_1_TO_0_260_EQ_0__ETC___d1764 =
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q11 ==
|
|
tlb_m_entryVec_10[79:53] ;
|
|
assign IF_tlb_m_entryVec_11_269_BITS_1_TO_0_273_EQ_0__ETC___d1774 =
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q12 ==
|
|
tlb_m_entryVec_11[79:53] ;
|
|
assign IF_tlb_m_entryVec_12_282_BITS_1_TO_0_286_EQ_0__ETC___d1784 =
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q13 ==
|
|
tlb_m_entryVec_12[79:53] ;
|
|
assign IF_tlb_m_entryVec_13_295_BITS_1_TO_0_299_EQ_0__ETC___d1794 =
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q14 ==
|
|
tlb_m_entryVec_13[79:53] ;
|
|
assign IF_tlb_m_entryVec_14_308_BITS_1_TO_0_312_EQ_0__ETC___d1804 =
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q15 ==
|
|
tlb_m_entryVec_14[79:53] ;
|
|
assign IF_tlb_m_entryVec_15_321_BITS_1_TO_0_325_EQ_0__ETC___d1814 =
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q16 ==
|
|
tlb_m_entryVec_15[79:53] ;
|
|
assign IF_tlb_m_entryVec_16_334_BITS_1_TO_0_338_EQ_0__ETC___d1824 =
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q17 ==
|
|
tlb_m_entryVec_16[79:53] ;
|
|
assign IF_tlb_m_entryVec_17_347_BITS_1_TO_0_351_EQ_0__ETC___d1834 =
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q18 ==
|
|
tlb_m_entryVec_17[79:53] ;
|
|
assign IF_tlb_m_entryVec_18_360_BITS_1_TO_0_364_EQ_0__ETC___d1844 =
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q19 ==
|
|
tlb_m_entryVec_18[79:53] ;
|
|
assign IF_tlb_m_entryVec_19_373_BITS_1_TO_0_377_EQ_0__ETC___d1854 =
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q20 ==
|
|
tlb_m_entryVec_19[79:53] ;
|
|
assign IF_tlb_m_entryVec_1_139_BITS_1_TO_0_143_EQ_0_6_ETC___d1674 =
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q1 ==
|
|
tlb_m_entryVec_1[79:53] ;
|
|
assign IF_tlb_m_entryVec_20_386_BITS_1_TO_0_390_EQ_0__ETC___d1864 =
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q21 ==
|
|
tlb_m_entryVec_20[79:53] ;
|
|
assign IF_tlb_m_entryVec_21_399_BITS_1_TO_0_403_EQ_0__ETC___d1874 =
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q22 ==
|
|
tlb_m_entryVec_21[79:53] ;
|
|
assign IF_tlb_m_entryVec_22_412_BITS_1_TO_0_416_EQ_0__ETC___d1884 =
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q23 ==
|
|
tlb_m_entryVec_22[79:53] ;
|
|
assign IF_tlb_m_entryVec_23_425_BITS_1_TO_0_429_EQ_0__ETC___d1894 =
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q24 ==
|
|
tlb_m_entryVec_23[79:53] ;
|
|
assign IF_tlb_m_entryVec_24_438_BITS_1_TO_0_442_EQ_0__ETC___d1904 =
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q25 ==
|
|
tlb_m_entryVec_24[79:53] ;
|
|
assign IF_tlb_m_entryVec_25_451_BITS_1_TO_0_455_EQ_0__ETC___d1914 =
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q26 ==
|
|
tlb_m_entryVec_25[79:53] ;
|
|
assign IF_tlb_m_entryVec_26_464_BITS_1_TO_0_468_EQ_0__ETC___d1924 =
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q27 ==
|
|
tlb_m_entryVec_26[79:53] ;
|
|
assign IF_tlb_m_entryVec_27_477_BITS_1_TO_0_481_EQ_0__ETC___d1934 =
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q28 ==
|
|
tlb_m_entryVec_27[79:53] ;
|
|
assign IF_tlb_m_entryVec_28_490_BITS_1_TO_0_494_EQ_0__ETC___d1944 =
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q29 ==
|
|
tlb_m_entryVec_28[79:53] ;
|
|
assign IF_tlb_m_entryVec_29_503_BITS_1_TO_0_507_EQ_0__ETC___d1954 =
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q30 ==
|
|
tlb_m_entryVec_29[79:53] ;
|
|
assign IF_tlb_m_entryVec_2_152_BITS_1_TO_0_156_EQ_0_6_ETC___d1684 =
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q3 ==
|
|
tlb_m_entryVec_2[79:53] ;
|
|
assign IF_tlb_m_entryVec_30_516_BITS_1_TO_0_520_EQ_0__ETC___d1964 =
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q31 ==
|
|
tlb_m_entryVec_30[79:53] ;
|
|
assign IF_tlb_m_entryVec_31_529_BITS_1_TO_0_533_EQ_0__ETC___d1974 =
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q32 ==
|
|
tlb_m_entryVec_31[79:53] ;
|
|
assign IF_tlb_m_entryVec_3_165_BITS_1_TO_0_169_EQ_0_6_ETC___d1694 =
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q4 ==
|
|
tlb_m_entryVec_3[79:53] ;
|
|
assign IF_tlb_m_entryVec_4_178_BITS_1_TO_0_182_EQ_0_6_ETC___d1704 =
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q5 ==
|
|
tlb_m_entryVec_4[79:53] ;
|
|
assign IF_tlb_m_entryVec_5_191_BITS_1_TO_0_195_EQ_0_7_ETC___d1714 =
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q6 ==
|
|
tlb_m_entryVec_5[79:53] ;
|
|
assign IF_tlb_m_entryVec_6_204_BITS_1_TO_0_208_EQ_0_7_ETC___d1724 =
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q7 ==
|
|
tlb_m_entryVec_6[79:53] ;
|
|
assign IF_tlb_m_entryVec_7_217_BITS_1_TO_0_221_EQ_0_7_ETC___d1734 =
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q8 ==
|
|
tlb_m_entryVec_7[79:53] ;
|
|
assign IF_tlb_m_entryVec_8_230_BITS_1_TO_0_234_EQ_0_7_ETC___d1744 =
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q9 ==
|
|
tlb_m_entryVec_8[79:53] ;
|
|
assign IF_tlb_m_entryVec_9_243_BITS_1_TO_0_247_EQ_0_7_ETC___d1754 =
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q10 ==
|
|
tlb_m_entryVec_9[79:53] ;
|
|
assign IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d17 =
|
|
tlb_m_updRepIdx_lat_1$whas ?
|
|
tlb_m_updRepIdx_lat_1$wget[5] :
|
|
!tlb_m_updRepIdx_lat_0$whas && tlb_m_updRepIdx_rl[5] ;
|
|
assign IF_tlb_m_updRepIdx_lat_1_whas_THEN_tlb_m_updRe_ETC___d27 =
|
|
tlb_m_updRepIdx_lat_1$whas ?
|
|
tlb_m_updRepIdx_lat_1$wget[4:0] :
|
|
(tlb_m_updRepIdx_lat_0$whas ?
|
|
5'b01010 :
|
|
tlb_m_updRepIdx_rl[4:0]) ;
|
|
assign IF_tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_ETC___d957 =
|
|
(tlb_m_validVec_0 && tlb_m_validVec_1) ?
|
|
(tlb_m_validVec_2 ? 5'd3 : 5'd2) :
|
|
(tlb_m_validVec_0 ? 5'd1 : 5'd0) ;
|
|
assign IF_tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_ETC___d958 =
|
|
(tlb_m_validVec_0 && tlb_m_validVec_1 && tlb_m_validVec_2 &&
|
|
tlb_m_validVec_3) ?
|
|
IF_tlb_m_validVec_4_20_AND_tlb_m_validVec_5_22_ETC___d954 :
|
|
IF_tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_ETC___d957 ;
|
|
assign IF_tlb_m_validVec_12_43_AND_tlb_m_validVec_13__ETC___d947 =
|
|
(tlb_m_validVec_12 && tlb_m_validVec_13) ?
|
|
(tlb_m_validVec_14 ? 5'd15 : 5'd14) :
|
|
(tlb_m_validVec_12 ? 5'd13 : 5'd12) ;
|
|
assign IF_tlb_m_validVec_16_56_AND_tlb_m_validVec_17__ETC___d942 =
|
|
(tlb_m_validVec_16 && tlb_m_validVec_17) ?
|
|
(tlb_m_validVec_18 ? 5'd19 : 5'd18) :
|
|
(tlb_m_validVec_16 ? 5'd17 : 5'd16) ;
|
|
assign IF_tlb_m_validVec_16_56_AND_tlb_m_validVec_17__ETC___d943 =
|
|
(tlb_m_validVec_16 && tlb_m_validVec_17 && tlb_m_validVec_18 &&
|
|
tlb_m_validVec_19) ?
|
|
IF_tlb_m_validVec_20_67_AND_tlb_m_validVec_21__ETC___d939 :
|
|
IF_tlb_m_validVec_16_56_AND_tlb_m_validVec_17__ETC___d942 ;
|
|
assign IF_tlb_m_validVec_20_67_AND_tlb_m_validVec_21__ETC___d939 =
|
|
(tlb_m_validVec_20 && tlb_m_validVec_21) ?
|
|
(tlb_m_validVec_22 ? 5'd23 : 5'd22) :
|
|
(tlb_m_validVec_20 ? 5'd21 : 5'd20) ;
|
|
assign IF_tlb_m_validVec_24_79_AND_tlb_m_validVec_25__ETC___d935 =
|
|
(tlb_m_validVec_24 && tlb_m_validVec_25) ?
|
|
(tlb_m_validVec_26 ? 5'd27 : 5'd26) :
|
|
(tlb_m_validVec_24 ? 5'd25 : 5'd24) ;
|
|
assign IF_tlb_m_validVec_24_79_AND_tlb_m_validVec_25__ETC___d936 =
|
|
(tlb_m_validVec_24 && tlb_m_validVec_25 && tlb_m_validVec_26 &&
|
|
tlb_m_validVec_27) ?
|
|
IF_tlb_m_validVec_28_90_AND_tlb_m_validVec_29__ETC___d932 :
|
|
IF_tlb_m_validVec_24_79_AND_tlb_m_validVec_25__ETC___d935 ;
|
|
assign IF_tlb_m_validVec_28_90_AND_tlb_m_validVec_29__ETC___d932 =
|
|
(tlb_m_validVec_28 && tlb_m_validVec_29) ?
|
|
(tlb_m_validVec_30 ? 5'd31 : 5'd30) :
|
|
(tlb_m_validVec_28 ? 5'd29 : 5'd28) ;
|
|
assign IF_tlb_m_validVec_4_20_AND_tlb_m_validVec_5_22_ETC___d954 =
|
|
(tlb_m_validVec_4 && tlb_m_validVec_5) ?
|
|
(tlb_m_validVec_6 ? 5'd7 : 5'd6) :
|
|
(tlb_m_validVec_4 ? 5'd5 : 5'd4) ;
|
|
assign IF_tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_ETC___d950 =
|
|
(tlb_m_validVec_8 && tlb_m_validVec_9) ?
|
|
(tlb_m_validVec_10 ? 5'd11 : 5'd10) :
|
|
(tlb_m_validVec_8 ? 5'd9 : 5'd8) ;
|
|
assign IF_tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_ETC___d951 =
|
|
(tlb_m_validVec_8 && tlb_m_validVec_9 && tlb_m_validVec_10 &&
|
|
tlb_m_validVec_11) ?
|
|
IF_tlb_m_validVec_12_43_AND_tlb_m_validVec_13__ETC___d947 :
|
|
IF_tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_ETC___d950 ;
|
|
assign IF_vm_info_24_BIT_46_60_THEN_IF_SEL_ARR_tlb_m__ETC___d2376 =
|
|
vm_info[46] ?
|
|
((SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 &&
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_ETC___d2359) ?
|
|
{ x__h74742, 6'd10 } :
|
|
70'h2AAAAAAAAAAAAAAAAC) :
|
|
{ to_proc_request_put, 6'd10 } ;
|
|
assign INV_n__read6006__q51 = ~n__read__h46006 ;
|
|
assign NOT_SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_ETC___d790 =
|
|
!SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d719 &&
|
|
(SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d723 ?
|
|
vm_info[48:47] != 2'd1 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27_rsFr_ETC___d785 :
|
|
vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27_rsFr_ETC___d785) ;
|
|
assign NOT_SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_ETC___d2359 =
|
|
!SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 &&
|
|
(SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 ?
|
|
vm_info[48:47] != 2'd1 &&
|
|
IF_IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_ETC___d2355 :
|
|
vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_ETC___d2355) ;
|
|
assign NOT_SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27__ETC___d763 =
|
|
level__h33681 != 2'd0 &&
|
|
((level__h33681 == 2'd1) ?
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737[8:0] !=
|
|
9'd0 :
|
|
level__h33681 != 2'd2 ||
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_3_49_rsFromPQ_d_ETC___d752 &&
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_2_53_54_NOT_ETC___d758 ||
|
|
!vm_info[46] ;
|
|
assign NOT_tlb_m_flushEn_whas__2_3_AND_IF_tlb_m_updRe_ETC___d770 =
|
|
!CAN_FIRE_RL_doStartFlush &&
|
|
(tlb_m_updRepIdx_lat_0$whas || !tlb_m_updRepIdx_rl[5]) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667 =
|
|
!tlb_m_validVec_0 ||
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q2 !=
|
|
tlb_m_entryVec_0[79:53] ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1667 &&
|
|
(!tlb_m_validVec_1 ||
|
|
!IF_tlb_m_entryVec_1_139_BITS_1_TO_0_143_EQ_0_6_ETC___d1674) &&
|
|
(!tlb_m_validVec_2 ||
|
|
!IF_tlb_m_entryVec_2_152_BITS_1_TO_0_156_EQ_0_6_ETC___d1684) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1687 &&
|
|
(!tlb_m_validVec_3 ||
|
|
!IF_tlb_m_entryVec_3_165_BITS_1_TO_0_169_EQ_0_6_ETC___d1694) &&
|
|
(!tlb_m_validVec_4 ||
|
|
!IF_tlb_m_entryVec_4_178_BITS_1_TO_0_182_EQ_0_6_ETC___d1704) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1707 &&
|
|
(!tlb_m_validVec_5 ||
|
|
!IF_tlb_m_entryVec_5_191_BITS_1_TO_0_195_EQ_0_7_ETC___d1714) &&
|
|
(!tlb_m_validVec_6 ||
|
|
!IF_tlb_m_entryVec_6_204_BITS_1_TO_0_208_EQ_0_7_ETC___d1724) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1727 &&
|
|
(!tlb_m_validVec_7 ||
|
|
!IF_tlb_m_entryVec_7_217_BITS_1_TO_0_221_EQ_0_7_ETC___d1734) &&
|
|
(!tlb_m_validVec_8 ||
|
|
!IF_tlb_m_entryVec_8_230_BITS_1_TO_0_234_EQ_0_7_ETC___d1744) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1747 &&
|
|
(!tlb_m_validVec_9 ||
|
|
!IF_tlb_m_entryVec_9_243_BITS_1_TO_0_247_EQ_0_7_ETC___d1754) &&
|
|
(!tlb_m_validVec_10 ||
|
|
!IF_tlb_m_entryVec_10_256_BITS_1_TO_0_260_EQ_0__ETC___d1764) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1767 &&
|
|
(!tlb_m_validVec_11 ||
|
|
!IF_tlb_m_entryVec_11_269_BITS_1_TO_0_273_EQ_0__ETC___d1774) &&
|
|
(!tlb_m_validVec_12 ||
|
|
!IF_tlb_m_entryVec_12_282_BITS_1_TO_0_286_EQ_0__ETC___d1784) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1787 &&
|
|
(!tlb_m_validVec_13 ||
|
|
!IF_tlb_m_entryVec_13_295_BITS_1_TO_0_299_EQ_0__ETC___d1794) &&
|
|
(!tlb_m_validVec_14 ||
|
|
!IF_tlb_m_entryVec_14_308_BITS_1_TO_0_312_EQ_0__ETC___d1804) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1807 &&
|
|
(!tlb_m_validVec_15 ||
|
|
!IF_tlb_m_entryVec_15_321_BITS_1_TO_0_325_EQ_0__ETC___d1814) &&
|
|
(!tlb_m_validVec_16 ||
|
|
!IF_tlb_m_entryVec_16_334_BITS_1_TO_0_338_EQ_0__ETC___d1824) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1827 &&
|
|
(!tlb_m_validVec_17 ||
|
|
!IF_tlb_m_entryVec_17_347_BITS_1_TO_0_351_EQ_0__ETC___d1834) &&
|
|
(!tlb_m_validVec_18 ||
|
|
!IF_tlb_m_entryVec_18_360_BITS_1_TO_0_364_EQ_0__ETC___d1844) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1847 &&
|
|
(!tlb_m_validVec_19 ||
|
|
!IF_tlb_m_entryVec_19_373_BITS_1_TO_0_377_EQ_0__ETC___d1854) &&
|
|
(!tlb_m_validVec_20 ||
|
|
!IF_tlb_m_entryVec_20_386_BITS_1_TO_0_390_EQ_0__ETC___d1864) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1867 &&
|
|
(!tlb_m_validVec_21 ||
|
|
!IF_tlb_m_entryVec_21_399_BITS_1_TO_0_403_EQ_0__ETC___d1874) &&
|
|
(!tlb_m_validVec_22 ||
|
|
!IF_tlb_m_entryVec_22_412_BITS_1_TO_0_416_EQ_0__ETC___d1884) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1887 &&
|
|
(!tlb_m_validVec_23 ||
|
|
!IF_tlb_m_entryVec_23_425_BITS_1_TO_0_429_EQ_0__ETC___d1894) &&
|
|
(!tlb_m_validVec_24 ||
|
|
!IF_tlb_m_entryVec_24_438_BITS_1_TO_0_442_EQ_0__ETC___d1904) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1907 &&
|
|
(!tlb_m_validVec_25 ||
|
|
!IF_tlb_m_entryVec_25_451_BITS_1_TO_0_455_EQ_0__ETC___d1914) &&
|
|
(!tlb_m_validVec_26 ||
|
|
!IF_tlb_m_entryVec_26_464_BITS_1_TO_0_468_EQ_0__ETC___d1924) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1927 &&
|
|
(!tlb_m_validVec_27 ||
|
|
!IF_tlb_m_entryVec_27_477_BITS_1_TO_0_481_EQ_0__ETC___d1934) &&
|
|
(!tlb_m_validVec_28 ||
|
|
!IF_tlb_m_entryVec_28_490_BITS_1_TO_0_494_EQ_0__ETC___d1944) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1967 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1947 &&
|
|
(!tlb_m_validVec_29 ||
|
|
!IF_tlb_m_entryVec_29_503_BITS_1_TO_0_507_EQ_0__ETC___d1954) &&
|
|
(!tlb_m_validVec_30 ||
|
|
!IF_tlb_m_entryVec_30_516_BITS_1_TO_0_520_EQ_0__ETC___d1964) ;
|
|
assign NOT_tlb_m_validVec_0_09_10_OR_NOT_tlb_m_validV_ETC___d831 =
|
|
!tlb_m_validVec_0 || !tlb_m_validVec_1 || !tlb_m_validVec_2 ||
|
|
!tlb_m_validVec_3 ||
|
|
!tlb_m_validVec_4 ||
|
|
!tlb_m_validVec_5 ||
|
|
!tlb_m_validVec_6 ||
|
|
!tlb_m_validVec_7 ;
|
|
assign NOT_tlb_m_validVec_11_39_40_OR_NOT_tlb_m_entry_ETC___d1561 =
|
|
(!tlb_m_validVec_11 ||
|
|
tlb_m_entryVec_11[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_11[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_11[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_12 ||
|
|
tlb_m_entryVec_12[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_12[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_12[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_13_45_46_OR_NOT_tlb_m_entry_ETC___d1559 ;
|
|
assign NOT_tlb_m_validVec_13_45_46_OR_NOT_tlb_m_entry_ETC___d1559 =
|
|
(!tlb_m_validVec_13 ||
|
|
tlb_m_entryVec_13[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_13[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_13[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_14 ||
|
|
tlb_m_entryVec_14[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_14[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_14[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_15_50_51_OR_NOT_tlb_m_entry_ETC___d1557 ;
|
|
assign NOT_tlb_m_validVec_15_50_51_OR_NOT_tlb_m_entry_ETC___d1557 =
|
|
(!tlb_m_validVec_15 ||
|
|
tlb_m_entryVec_15[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_15[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_15[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_16 ||
|
|
tlb_m_entryVec_16[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_16[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_16[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_17_58_59_OR_NOT_tlb_m_entry_ETC___d1555 ;
|
|
assign NOT_tlb_m_validVec_16_56_57_OR_NOT_tlb_m_valid_ETC___d878 =
|
|
!tlb_m_validVec_16 || !tlb_m_validVec_17 || !tlb_m_validVec_18 ||
|
|
!tlb_m_validVec_19 ||
|
|
!tlb_m_validVec_20 ||
|
|
!tlb_m_validVec_21 ||
|
|
!tlb_m_validVec_22 ||
|
|
!tlb_m_validVec_23 ;
|
|
assign NOT_tlb_m_validVec_17_58_59_OR_NOT_tlb_m_entry_ETC___d1555 =
|
|
(!tlb_m_validVec_17 ||
|
|
tlb_m_entryVec_17[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_17[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_17[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_18 ||
|
|
tlb_m_entryVec_18[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_18[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_18[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_19_63_64_OR_NOT_tlb_m_entry_ETC___d1553 ;
|
|
assign NOT_tlb_m_validVec_19_63_64_OR_NOT_tlb_m_entry_ETC___d1553 =
|
|
(!tlb_m_validVec_19 ||
|
|
tlb_m_entryVec_19[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_19[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_19[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_20 ||
|
|
tlb_m_entryVec_20[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_20[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_20[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_21_69_70_OR_NOT_tlb_m_entry_ETC___d1551 ;
|
|
assign NOT_tlb_m_validVec_1_11_12_OR_NOT_tlb_m_entryV_ETC___d1571 =
|
|
(!tlb_m_validVec_1 ||
|
|
tlb_m_entryVec_1[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_1[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_1[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_2 ||
|
|
tlb_m_entryVec_2[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_2[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_2[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_3_16_17_OR_NOT_tlb_m_entryV_ETC___d1569 ;
|
|
assign NOT_tlb_m_validVec_21_69_70_OR_NOT_tlb_m_entry_ETC___d1551 =
|
|
(!tlb_m_validVec_21 ||
|
|
tlb_m_entryVec_21[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_21[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_21[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_22 ||
|
|
tlb_m_entryVec_22[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_22[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_22[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_23_74_75_OR_NOT_tlb_m_entry_ETC___d1549 ;
|
|
assign NOT_tlb_m_validVec_23_74_75_OR_NOT_tlb_m_entry_ETC___d1549 =
|
|
(!tlb_m_validVec_23 ||
|
|
tlb_m_entryVec_23[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_23[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_23[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_24 ||
|
|
tlb_m_entryVec_24[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_24[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_24[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_25_81_82_OR_NOT_tlb_m_entry_ETC___d1547 ;
|
|
assign NOT_tlb_m_validVec_24_79_80_OR_NOT_tlb_m_valid_ETC___d901 =
|
|
!tlb_m_validVec_24 || !tlb_m_validVec_25 || !tlb_m_validVec_26 ||
|
|
!tlb_m_validVec_27 ||
|
|
!tlb_m_validVec_28 ||
|
|
!tlb_m_validVec_29 ||
|
|
!tlb_m_validVec_30 ||
|
|
!tlb_m_validVec_31 ;
|
|
assign NOT_tlb_m_validVec_25_81_82_OR_NOT_tlb_m_entry_ETC___d1547 =
|
|
(!tlb_m_validVec_25 ||
|
|
tlb_m_entryVec_25[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_25[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_25[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_26 ||
|
|
tlb_m_entryVec_26[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_26[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_26[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_27_86_87_OR_NOT_tlb_m_entry_ETC___d1545 ;
|
|
assign NOT_tlb_m_validVec_27_86_87_OR_NOT_tlb_m_entry_ETC___d1545 =
|
|
(!tlb_m_validVec_27 ||
|
|
tlb_m_entryVec_27[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_27[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_27[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_28 ||
|
|
tlb_m_entryVec_28[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_28[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_28[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_29_92_93_OR_NOT_tlb_m_entry_ETC___d1543 ;
|
|
assign NOT_tlb_m_validVec_29_92_93_OR_NOT_tlb_m_entry_ETC___d1543 =
|
|
(!tlb_m_validVec_29 ||
|
|
tlb_m_entryVec_29[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_29[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_29[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_30 ||
|
|
tlb_m_entryVec_30[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_30[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_30[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_31 ||
|
|
tlb_m_entryVec_31[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_31[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_31[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) ;
|
|
assign NOT_tlb_m_validVec_3_16_17_OR_NOT_tlb_m_entryV_ETC___d1569 =
|
|
(!tlb_m_validVec_3 ||
|
|
tlb_m_entryVec_3[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_3[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_3[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_4 ||
|
|
tlb_m_entryVec_4[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_4[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_4[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_5_22_23_OR_NOT_tlb_m_entryV_ETC___d1567 ;
|
|
assign NOT_tlb_m_validVec_5_22_23_OR_NOT_tlb_m_entryV_ETC___d1567 =
|
|
(!tlb_m_validVec_5 ||
|
|
tlb_m_entryVec_5[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_5[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_5[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_6 ||
|
|
tlb_m_entryVec_6[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_6[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_6[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_7_27_28_OR_NOT_tlb_m_entryV_ETC___d1565 ;
|
|
assign NOT_tlb_m_validVec_7_27_28_OR_NOT_tlb_m_entryV_ETC___d1565 =
|
|
(!tlb_m_validVec_7 ||
|
|
tlb_m_entryVec_7[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_7[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_7[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_8 ||
|
|
tlb_m_entryVec_8[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_8[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_8[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_9_34_35_OR_NOT_tlb_m_entryV_ETC___d1563 ;
|
|
assign NOT_tlb_m_validVec_8_32_33_OR_NOT_tlb_m_validV_ETC___d854 =
|
|
!tlb_m_validVec_8 || !tlb_m_validVec_9 || !tlb_m_validVec_10 ||
|
|
!tlb_m_validVec_11 ||
|
|
!tlb_m_validVec_12 ||
|
|
!tlb_m_validVec_13 ||
|
|
!tlb_m_validVec_14 ||
|
|
!tlb_m_validVec_15 ;
|
|
assign NOT_tlb_m_validVec_9_34_35_OR_NOT_tlb_m_entryV_ETC___d1563 =
|
|
(!tlb_m_validVec_9 ||
|
|
tlb_m_entryVec_9[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_9[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_9[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
(!tlb_m_validVec_10 ||
|
|
tlb_m_entryVec_10[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_10[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_10[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_11_39_40_OR_NOT_tlb_m_entry_ETC___d1561 ;
|
|
assign SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d768 =
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d719 ||
|
|
(SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d723 ?
|
|
vm_info[48:47] == 2'd1 ||
|
|
NOT_SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27__ETC___d763 :
|
|
vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27__ETC___d763) ;
|
|
assign SEL_ARR_rsFromPQ_data_0_02_BITS_1_TO_0_27_rsFr_ETC___d785 =
|
|
(level__h33681 == 2'd0 ||
|
|
((level__h33681 == 2'd1) ?
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737[8:0] ==
|
|
9'd0 :
|
|
level__h33681 == 2'd2 &&
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737[17:0] ==
|
|
18'd0)) &&
|
|
(!SEL_ARR_rsFromPQ_data_0_02_BIT_3_49_rsFromPQ_d_ETC___d752 ||
|
|
!SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_2_53_54_NOT_ETC___d758) &&
|
|
vm_info[46] ;
|
|
assign SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d1647 =
|
|
{ SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d723,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q33,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_3_49_rsFromPQ_d_ETC___d752,
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q34 } ;
|
|
assign SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d1573 =
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d712 &&
|
|
NOT_SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_ETC___d790 &&
|
|
(!tlb_m_validVec_0 ||
|
|
tlb_m_entryVec_0[79:53] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 ||
|
|
tlb_m_entryVec_0[1:0] != level__h33681 ||
|
|
tlb_m_entryVec_0[6] !=
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134) &&
|
|
NOT_tlb_m_validVec_1_11_12_OR_NOT_tlb_m_entryV_ETC___d1571 ;
|
|
assign SEL_ARR_rsFromPQ_data_0_02_BIT_8_638_rsFromPQ__ETC___d1649 =
|
|
{ CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q35,
|
|
1'd1,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134,
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d1647,
|
|
level__h33681 } ;
|
|
assign _theResult_____2__h10173 =
|
|
IF_hitQ_deqReq_lat_1_whas__04_THEN_hitQ_deqReq_ETC___d210 ?
|
|
next_deqP___1__h10362 :
|
|
hitQ_deqP ;
|
|
assign _theResult_____2__h13809 =
|
|
IF_rqToPQ_deqReq_lat_1_whas__66_THEN_rqToPQ_de_ETC___d372 ?
|
|
next_deqP___1__h13998 :
|
|
rqToPQ_deqP ;
|
|
assign _theResult_____2__h18424 =
|
|
IF_rsFromPQ_deqReq_lat_1_whas__67_THEN_rsFromP_ETC___d473 ?
|
|
next_deqP___1__h18613 :
|
|
rsFromPQ_deqP ;
|
|
assign addIdx__h50635 =
|
|
(!INV_n__read6006__q51[0] && !INV_n__read6006__q51[1] &&
|
|
!INV_n__read6006__q51[2] &&
|
|
!INV_n__read6006__q51[3] &&
|
|
!INV_n__read6006__q51[4] &&
|
|
!INV_n__read6006__q51[5] &&
|
|
!INV_n__read6006__q51[6] &&
|
|
!INV_n__read6006__q51[7] &&
|
|
!INV_n__read6006__q51[8] &&
|
|
!INV_n__read6006__q51[9] &&
|
|
!INV_n__read6006__q51[10] &&
|
|
!INV_n__read6006__q51[11] &&
|
|
!INV_n__read6006__q51[12] &&
|
|
!INV_n__read6006__q51[13] &&
|
|
!INV_n__read6006__q51[14] &&
|
|
!INV_n__read6006__q51[15]) ?
|
|
((!INV_n__read6006__q51[16] && !INV_n__read6006__q51[17] &&
|
|
!INV_n__read6006__q51[18] &&
|
|
!INV_n__read6006__q51[19] &&
|
|
!INV_n__read6006__q51[20] &&
|
|
!INV_n__read6006__q51[21] &&
|
|
!INV_n__read6006__q51[22] &&
|
|
!INV_n__read6006__q51[23]) ?
|
|
((!INV_n__read6006__q51[24] && !INV_n__read6006__q51[25] &&
|
|
!INV_n__read6006__q51[26] &&
|
|
!INV_n__read6006__q51[27]) ?
|
|
((!INV_n__read6006__q51[28] &&
|
|
!INV_n__read6006__q51[29]) ?
|
|
(INV_n__read6006__q51[30] ? 5'd30 : 5'd31) :
|
|
(INV_n__read6006__q51[28] ? 5'd28 : 5'd29)) :
|
|
((!INV_n__read6006__q51[24] &&
|
|
!INV_n__read6006__q51[25]) ?
|
|
(INV_n__read6006__q51[26] ? 5'd26 : 5'd27) :
|
|
(INV_n__read6006__q51[24] ? 5'd24 : 5'd25))) :
|
|
((!INV_n__read6006__q51[16] && !INV_n__read6006__q51[17] &&
|
|
!INV_n__read6006__q51[18] &&
|
|
!INV_n__read6006__q51[19]) ?
|
|
((!INV_n__read6006__q51[20] &&
|
|
!INV_n__read6006__q51[21]) ?
|
|
(INV_n__read6006__q51[22] ? 5'd22 : 5'd23) :
|
|
(INV_n__read6006__q51[20] ? 5'd20 : 5'd21)) :
|
|
((!INV_n__read6006__q51[16] &&
|
|
!INV_n__read6006__q51[17]) ?
|
|
(INV_n__read6006__q51[18] ? 5'd18 : 5'd19) :
|
|
(INV_n__read6006__q51[16] ? 5'd16 : 5'd17)))) :
|
|
((!INV_n__read6006__q51[0] && !INV_n__read6006__q51[1] &&
|
|
!INV_n__read6006__q51[2] &&
|
|
!INV_n__read6006__q51[3] &&
|
|
!INV_n__read6006__q51[4] &&
|
|
!INV_n__read6006__q51[5] &&
|
|
!INV_n__read6006__q51[6] &&
|
|
!INV_n__read6006__q51[7]) ?
|
|
((!INV_n__read6006__q51[8] && !INV_n__read6006__q51[9] &&
|
|
!INV_n__read6006__q51[10] &&
|
|
!INV_n__read6006__q51[11]) ?
|
|
((!INV_n__read6006__q51[12] &&
|
|
!INV_n__read6006__q51[13]) ?
|
|
(INV_n__read6006__q51[14] ? 5'd14 : 5'd15) :
|
|
(INV_n__read6006__q51[12] ? 5'd12 : 5'd13)) :
|
|
((!INV_n__read6006__q51[8] && !INV_n__read6006__q51[9]) ?
|
|
(INV_n__read6006__q51[10] ? 5'd10 : 5'd11) :
|
|
(INV_n__read6006__q51[8] ? 5'd8 : 5'd9))) :
|
|
((!INV_n__read6006__q51[0] && !INV_n__read6006__q51[1] &&
|
|
!INV_n__read6006__q51[2] &&
|
|
!INV_n__read6006__q51[3]) ?
|
|
((!INV_n__read6006__q51[4] && !INV_n__read6006__q51[5]) ?
|
|
(INV_n__read6006__q51[6] ? 5'd6 : 5'd7) :
|
|
(INV_n__read6006__q51[4] ? 5'd4 : 5'd5)) :
|
|
((!INV_n__read6006__q51[0] && !INV_n__read6006__q51[1]) ?
|
|
(INV_n__read6006__q51[2] ? 5'd2 : 5'd3) :
|
|
(INV_n__read6006__q51[0] ? 5'd0 : 5'd1)))) ;
|
|
assign addIdx__h55485 =
|
|
(tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_04_ETC___d910 &&
|
|
tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_11_ETC___d917) ?
|
|
(tlb_m_validVec_16_56_AND_tlb_m_validVec_17_58__ETC___d925 ?
|
|
IF_tlb_m_validVec_24_79_AND_tlb_m_validVec_25__ETC___d936 :
|
|
IF_tlb_m_validVec_16_56_AND_tlb_m_validVec_17__ETC___d943) :
|
|
(tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_04_ETC___d910 ?
|
|
IF_tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_ETC___d951 :
|
|
IF_tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_ETC___d958) ;
|
|
assign idx__h70014 =
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1967 ?
|
|
5'd31 :
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2100 ;
|
|
assign n__read__h46006 =
|
|
tlb_m_lruBit_lat_0$whas ? upd__h46033 : tlb_m_lruBit_rl ;
|
|
assign next_deqP___1__h10362 = hitQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h13998 = rqToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h18613 = rsFromPQ_deqP + 1'd1 ;
|
|
assign tlb_m_validVec_0_09_AND_tlb_m_validVec_1_11_04_ETC___d910 =
|
|
tlb_m_validVec_0 && tlb_m_validVec_1 && tlb_m_validVec_2 &&
|
|
tlb_m_validVec_3 &&
|
|
tlb_m_validVec_4 &&
|
|
tlb_m_validVec_5 &&
|
|
tlb_m_validVec_6 &&
|
|
tlb_m_validVec_7 ;
|
|
assign tlb_m_validVec_16_56_AND_tlb_m_validVec_17_58__ETC___d925 =
|
|
tlb_m_validVec_16 && tlb_m_validVec_17 && tlb_m_validVec_18 &&
|
|
tlb_m_validVec_19 &&
|
|
tlb_m_validVec_20 &&
|
|
tlb_m_validVec_21 &&
|
|
tlb_m_validVec_22 &&
|
|
tlb_m_validVec_23 ;
|
|
assign tlb_m_validVec_8_32_AND_tlb_m_validVec_9_34_11_ETC___d917 =
|
|
tlb_m_validVec_8 && tlb_m_validVec_9 && tlb_m_validVec_10 &&
|
|
tlb_m_validVec_11 &&
|
|
tlb_m_validVec_12 &&
|
|
tlb_m_validVec_13 &&
|
|
tlb_m_validVec_14 &&
|
|
tlb_m_validVec_15 ;
|
|
assign upd__h46033 =
|
|
WILL_FIRE_RL_tlb_m_doUpdateRep ?
|
|
MUX_tlb_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
32'd0 ;
|
|
assign v__h13437 =
|
|
IF_rqToPQ_enqReq_lat_1_whas__37_THEN_rqToPQ_en_ETC___d346 ?
|
|
v__h13588 :
|
|
rqToPQ_enqP ;
|
|
assign v__h13588 = rqToPQ_enqP + 1'd1 ;
|
|
assign v__h17382 =
|
|
IF_rsFromPQ_enqReq_lat_1_whas__22_THEN_rsFromP_ETC___d431 ?
|
|
v__h17533 :
|
|
rsFromPQ_enqP ;
|
|
assign v__h17533 = rsFromPQ_enqP + 1'd1 ;
|
|
assign v__h40453 =
|
|
(NOT_tlb_m_validVec_0_09_10_OR_NOT_tlb_m_validV_ETC___d831 ||
|
|
NOT_tlb_m_validVec_8_32_33_OR_NOT_tlb_m_validV_ETC___d854 ||
|
|
NOT_tlb_m_validVec_16_56_57_OR_NOT_tlb_m_valid_ETC___d878 ||
|
|
NOT_tlb_m_validVec_24_79_80_OR_NOT_tlb_m_valid_ETC___d901) ?
|
|
addIdx__h55485 :
|
|
v__h45270 ;
|
|
assign v__h45270 =
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 ?
|
|
tlb_m_randIdx :
|
|
v__h46798 ;
|
|
assign v__h46798 =
|
|
(INV_n__read6006__q51[0] || INV_n__read6006__q51[1] ||
|
|
INV_n__read6006__q51[2] ||
|
|
INV_n__read6006__q51[3] ||
|
|
INV_n__read6006__q51[4] ||
|
|
INV_n__read6006__q51[5] ||
|
|
INV_n__read6006__q51[6] ||
|
|
INV_n__read6006__q51[7] ||
|
|
INV_n__read6006__q51[8] ||
|
|
INV_n__read6006__q51[9] ||
|
|
INV_n__read6006__q51[10] ||
|
|
INV_n__read6006__q51[11] ||
|
|
INV_n__read6006__q51[12] ||
|
|
INV_n__read6006__q51[13] ||
|
|
INV_n__read6006__q51[14] ||
|
|
INV_n__read6006__q51[15] ||
|
|
INV_n__read6006__q51[16] ||
|
|
INV_n__read6006__q51[17] ||
|
|
INV_n__read6006__q51[18] ||
|
|
INV_n__read6006__q51[19] ||
|
|
INV_n__read6006__q51[20] ||
|
|
INV_n__read6006__q51[21] ||
|
|
INV_n__read6006__q51[22] ||
|
|
INV_n__read6006__q51[23] ||
|
|
INV_n__read6006__q51[24] ||
|
|
INV_n__read6006__q51[25] ||
|
|
INV_n__read6006__q51[26] ||
|
|
INV_n__read6006__q51[27] ||
|
|
INV_n__read6006__q51[28] ||
|
|
INV_n__read6006__q51[29] ||
|
|
INV_n__read6006__q51[30] ||
|
|
INV_n__read6006__q51[31]) ?
|
|
addIdx__h50635 :
|
|
5'd0 ;
|
|
assign v__h8839 =
|
|
IF_hitQ_enqReq_lat_1_whas__3_THEN_hitQ_enqReq__ETC___d52 ?
|
|
v__h8990 :
|
|
hitQ_enqP ;
|
|
assign v__h8990 = hitQ_enqP + 1'd1 ;
|
|
assign val__h5317 = tlb_m_lruBit_rl | x__h5375 ;
|
|
assign vm_info_24_BIT_46_60_AND_IF_NOT_tlb_m_validVec_ETC___d2379 =
|
|
vm_info[46] &&
|
|
IF_NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m__ETC___d2036 &&
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 &&
|
|
NOT_SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_ETC___d2359 ;
|
|
assign vm_info_24_BIT_46_60_AND_NOT_tlb_m_validVec_0__ETC___d2384 =
|
|
vm_info[46] &&
|
|
NOT_tlb_m_validVec_0_09_10_OR_NOT_IF_tlb_m_ent_ETC___d1967 &&
|
|
(!tlb_m_validVec_31 ||
|
|
!IF_tlb_m_entryVec_31_529_BITS_1_TO_0_533_EQ_0__ETC___d1974) ;
|
|
assign x__h5375 = 32'd1 << tlb_m_updRepIdx_rl[4:0] ;
|
|
assign x__h65230 = { 8'd0, x__h65238 } ;
|
|
assign x__h74742 = { 8'd0, x__h74750 } ;
|
|
assign x__h9109 =
|
|
hitQ_enqReq_lat_0$whas ?
|
|
hitQ_enqReq_lat_0$wget[69:6] :
|
|
hitQ_enqReq_rl[69:6] ;
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0: level__h33681 = rsFromPQ_data_0[1:0];
|
|
1'd1: level__h33681 = rsFromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0: x__h74975 = hitQ_data_0[69:6];
|
|
1'd1: x__h74975 = hitQ_data_1[69:6];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 =
|
|
rsFromPQ_data_0[80];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_80_03_rsFromPQ__ETC___d707 =
|
|
rsFromPQ_data_1[80];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d712 =
|
|
rsFromPQ_data_0[7];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_7_09_rsFromPQ_d_ETC___d712 =
|
|
rsFromPQ_data_1[7];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737 =
|
|
rsFromPQ_data_0[52:9];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737 =
|
|
rsFromPQ_data_1[52:9];
|
|
endcase
|
|
end
|
|
always@(level__h33681 or
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737 or miss)
|
|
begin
|
|
case (level__h33681)
|
|
2'd0:
|
|
x__h65238 =
|
|
{ SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737,
|
|
miss[11:0] };
|
|
2'd1:
|
|
x__h65238 =
|
|
{ SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737[43:9],
|
|
miss[20:0] };
|
|
2'd2:
|
|
x__h65238 =
|
|
{ SEL_ARR_rsFromPQ_data_0_02_BITS_52_TO_9_34_rsF_ETC___d737[43:18],
|
|
miss[29:0] };
|
|
2'd3: x__h65238 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_3_49_rsFromPQ_d_ETC___d752 =
|
|
rsFromPQ_data_0[3];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_3_49_rsFromPQ_d_ETC___d752 =
|
|
rsFromPQ_data_1[3];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_2_53_54_NOT_ETC___d758 =
|
|
!rsFromPQ_data_0[2];
|
|
1'd1:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_2_53_54_NOT_ETC___d758 =
|
|
!rsFromPQ_data_1[2];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d723 =
|
|
rsFromPQ_data_0[5];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_5_20_rsFromPQ_d_ETC___d723 =
|
|
rsFromPQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d719 =
|
|
!rsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_NOT_rsFromPQ_data_0_02_BIT_4_14_15_NOT_ETC___d719 =
|
|
!rsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 =
|
|
rsFromPQ_data_0[79:53];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BITS_79_TO_53_120_r_ETC___d1123 =
|
|
rsFromPQ_data_1[79:53];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134 =
|
|
rsFromPQ_data_0[6];
|
|
1'd1:
|
|
SEL_ARR_rsFromPQ_data_0_02_BIT_6_131_rsFromPQ__ETC___d1134 =
|
|
rsFromPQ_data_1[6];
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_1 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q1 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q1 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q1 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_1_BITS_1_TO_0_0_to_proc_re_ETC__q1 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_0 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q2 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q2 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q2 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_0_BITS_1_TO_0_0_to_proc_re_ETC__q2 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_2 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q3 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q3 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q3 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_2_BITS_1_TO_0_0_to_proc_re_ETC__q3 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_3 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q4 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q4 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q4 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_3_BITS_1_TO_0_0_to_proc_re_ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_4 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q5 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_4_BITS_1_TO_0_0_to_proc_re_ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_5 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q6 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_5_BITS_1_TO_0_0_to_proc_re_ETC__q6 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_6 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q7 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_6_BITS_1_TO_0_0_to_proc_re_ETC__q7 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_7 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q8 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_7_BITS_1_TO_0_0_to_proc_re_ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_8 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_8[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q9 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_8_BITS_1_TO_0_0_to_proc_re_ETC__q9 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_9 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_9[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q10 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_9_BITS_1_TO_0_0_to_proc_re_ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_10 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_10[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q11 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q11 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q11 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_10_BITS_1_TO_0_0_to_proc_r_ETC__q11 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_11 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_11[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q12 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q12 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q12 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_11_BITS_1_TO_0_0_to_proc_r_ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_12 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_12[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q13 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q13 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q13 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_12_BITS_1_TO_0_0_to_proc_r_ETC__q13 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_13 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_13[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q14 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q14 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q14 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_13_BITS_1_TO_0_0_to_proc_r_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_14 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_14[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q15 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_14_BITS_1_TO_0_0_to_proc_r_ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_15 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_15[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q16 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_15_BITS_1_TO_0_0_to_proc_r_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_16 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_16[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q17 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_16_BITS_1_TO_0_0_to_proc_r_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_17 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_17[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q18 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_17_BITS_1_TO_0_0_to_proc_r_ETC__q18 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_18 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_18[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q19 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_18_BITS_1_TO_0_0_to_proc_r_ETC__q19 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_19 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_19[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q20 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_19_BITS_1_TO_0_0_to_proc_r_ETC__q20 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_20 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_20[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q21 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_20_BITS_1_TO_0_0_to_proc_r_ETC__q21 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_21 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_21[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q22 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_21_BITS_1_TO_0_0_to_proc_r_ETC__q22 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_22 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_22[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q23 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_22_BITS_1_TO_0_0_to_proc_r_ETC__q23 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_23 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_23[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q24 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_23_BITS_1_TO_0_0_to_proc_r_ETC__q24 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_24 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_24[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q25 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_24_BITS_1_TO_0_0_to_proc_r_ETC__q25 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_25 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_25[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q26 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_25_BITS_1_TO_0_0_to_proc_r_ETC__q26 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_26 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_26[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q27 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_26_BITS_1_TO_0_0_to_proc_r_ETC__q27 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_27 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_27[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q28 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_27_BITS_1_TO_0_0_to_proc_r_ETC__q28 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_28 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_28[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q29 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_28_BITS_1_TO_0_0_to_proc_r_ETC__q29 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_29 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_29[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q30 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_29_BITS_1_TO_0_0_to_proc_r_ETC__q30 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_30 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_30[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q31 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_30_BITS_1_TO_0_0_to_proc_r_ETC__q31 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(tlb_m_entryVec_31 or to_proc_request_put)
|
|
begin
|
|
case (tlb_m_entryVec_31[1:0])
|
|
2'd0:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
to_proc_request_put[38:12];
|
|
2'd1:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
{ to_proc_request_put[38:21], 9'd0 };
|
|
2'd2:
|
|
CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q32 =
|
|
{ to_proc_request_put[38:30], 18'd0 };
|
|
2'd3: CASE_tlb_m_entryVec_31_BITS_1_TO_0_0_to_proc_r_ETC__q32 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0: ppn__h74746 = tlb_m_entryVec_0[52:9];
|
|
5'd1: ppn__h74746 = tlb_m_entryVec_1[52:9];
|
|
5'd2: ppn__h74746 = tlb_m_entryVec_2[52:9];
|
|
5'd3: ppn__h74746 = tlb_m_entryVec_3[52:9];
|
|
5'd4: ppn__h74746 = tlb_m_entryVec_4[52:9];
|
|
5'd5: ppn__h74746 = tlb_m_entryVec_5[52:9];
|
|
5'd6: ppn__h74746 = tlb_m_entryVec_6[52:9];
|
|
5'd7: ppn__h74746 = tlb_m_entryVec_7[52:9];
|
|
5'd8: ppn__h74746 = tlb_m_entryVec_8[52:9];
|
|
5'd9: ppn__h74746 = tlb_m_entryVec_9[52:9];
|
|
5'd10: ppn__h74746 = tlb_m_entryVec_10[52:9];
|
|
5'd11: ppn__h74746 = tlb_m_entryVec_11[52:9];
|
|
5'd12: ppn__h74746 = tlb_m_entryVec_12[52:9];
|
|
5'd13: ppn__h74746 = tlb_m_entryVec_13[52:9];
|
|
5'd14: ppn__h74746 = tlb_m_entryVec_14[52:9];
|
|
5'd15: ppn__h74746 = tlb_m_entryVec_15[52:9];
|
|
5'd16: ppn__h74746 = tlb_m_entryVec_16[52:9];
|
|
5'd17: ppn__h74746 = tlb_m_entryVec_17[52:9];
|
|
5'd18: ppn__h74746 = tlb_m_entryVec_18[52:9];
|
|
5'd19: ppn__h74746 = tlb_m_entryVec_19[52:9];
|
|
5'd20: ppn__h74746 = tlb_m_entryVec_20[52:9];
|
|
5'd21: ppn__h74746 = tlb_m_entryVec_21[52:9];
|
|
5'd22: ppn__h74746 = tlb_m_entryVec_22[52:9];
|
|
5'd23: ppn__h74746 = tlb_m_entryVec_23[52:9];
|
|
5'd24: ppn__h74746 = tlb_m_entryVec_24[52:9];
|
|
5'd25: ppn__h74746 = tlb_m_entryVec_25[52:9];
|
|
5'd26: ppn__h74746 = tlb_m_entryVec_26[52:9];
|
|
5'd27: ppn__h74746 = tlb_m_entryVec_27[52:9];
|
|
5'd28: ppn__h74746 = tlb_m_entryVec_28[52:9];
|
|
5'd29: ppn__h74746 = tlb_m_entryVec_29[52:9];
|
|
5'd30: ppn__h74746 = tlb_m_entryVec_30[52:9];
|
|
5'd31: ppn__h74746 = tlb_m_entryVec_31[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0: level__h70028 = tlb_m_entryVec_0[1:0];
|
|
5'd1: level__h70028 = tlb_m_entryVec_1[1:0];
|
|
5'd2: level__h70028 = tlb_m_entryVec_2[1:0];
|
|
5'd3: level__h70028 = tlb_m_entryVec_3[1:0];
|
|
5'd4: level__h70028 = tlb_m_entryVec_4[1:0];
|
|
5'd5: level__h70028 = tlb_m_entryVec_5[1:0];
|
|
5'd6: level__h70028 = tlb_m_entryVec_6[1:0];
|
|
5'd7: level__h70028 = tlb_m_entryVec_7[1:0];
|
|
5'd8: level__h70028 = tlb_m_entryVec_8[1:0];
|
|
5'd9: level__h70028 = tlb_m_entryVec_9[1:0];
|
|
5'd10: level__h70028 = tlb_m_entryVec_10[1:0];
|
|
5'd11: level__h70028 = tlb_m_entryVec_11[1:0];
|
|
5'd12: level__h70028 = tlb_m_entryVec_12[1:0];
|
|
5'd13: level__h70028 = tlb_m_entryVec_13[1:0];
|
|
5'd14: level__h70028 = tlb_m_entryVec_14[1:0];
|
|
5'd15: level__h70028 = tlb_m_entryVec_15[1:0];
|
|
5'd16: level__h70028 = tlb_m_entryVec_16[1:0];
|
|
5'd17: level__h70028 = tlb_m_entryVec_17[1:0];
|
|
5'd18: level__h70028 = tlb_m_entryVec_18[1:0];
|
|
5'd19: level__h70028 = tlb_m_entryVec_19[1:0];
|
|
5'd20: level__h70028 = tlb_m_entryVec_20[1:0];
|
|
5'd21: level__h70028 = tlb_m_entryVec_21[1:0];
|
|
5'd22: level__h70028 = tlb_m_entryVec_22[1:0];
|
|
5'd23: level__h70028 = tlb_m_entryVec_23[1:0];
|
|
5'd24: level__h70028 = tlb_m_entryVec_24[1:0];
|
|
5'd25: level__h70028 = tlb_m_entryVec_25[1:0];
|
|
5'd26: level__h70028 = tlb_m_entryVec_26[1:0];
|
|
5'd27: level__h70028 = tlb_m_entryVec_27[1:0];
|
|
5'd28: level__h70028 = tlb_m_entryVec_28[1:0];
|
|
5'd29: level__h70028 = tlb_m_entryVec_29[1:0];
|
|
5'd30: level__h70028 = tlb_m_entryVec_30[1:0];
|
|
5'd31: level__h70028 = tlb_m_entryVec_31[1:0];
|
|
endcase
|
|
end
|
|
always@(level__h70028 or ppn__h74746 or to_proc_request_put)
|
|
begin
|
|
case (level__h70028)
|
|
2'd0: x__h74750 = { ppn__h74746, to_proc_request_put[11:0] };
|
|
2'd1: x__h74750 = { ppn__h74746[43:9], to_proc_request_put[20:0] };
|
|
2'd2: x__h74750 = { ppn__h74746[43:18], to_proc_request_put[29:0] };
|
|
2'd3: x__h74750 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_0[4];
|
|
5'd1:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_1[4];
|
|
5'd2:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_2[4];
|
|
5'd3:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_3[4];
|
|
5'd4:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_4[4];
|
|
5'd5:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_5[4];
|
|
5'd6:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_6[4];
|
|
5'd7:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_7[4];
|
|
5'd8:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_8[4];
|
|
5'd9:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_9[4];
|
|
5'd10:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_10[4];
|
|
5'd11:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_11[4];
|
|
5'd12:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_12[4];
|
|
5'd13:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_13[4];
|
|
5'd14:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_14[4];
|
|
5'd15:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_15[4];
|
|
5'd16:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_16[4];
|
|
5'd17:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_17[4];
|
|
5'd18:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_18[4];
|
|
5'd19:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_19[4];
|
|
5'd20:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_20[4];
|
|
5'd21:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_21[4];
|
|
5'd22:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_22[4];
|
|
5'd23:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_23[4];
|
|
5'd24:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_24[4];
|
|
5'd25:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_25[4];
|
|
5'd26:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_26[4];
|
|
5'd27:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_27[4];
|
|
5'd28:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_28[4];
|
|
5'd29:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_29[4];
|
|
5'd30:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_30[4];
|
|
5'd31:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_4_103_104_ETC___d2168 =
|
|
!tlb_m_entryVec_31[4];
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_0[3];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_1[3];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_2[3];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_3[3];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_4[3];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_5[3];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_6[3];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_7[3];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_8[3];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_9[3];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_10[3];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_11[3];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_12[3];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_13[3];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_14[3];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_15[3];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_16[3];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_17[3];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_18[3];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_19[3];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_20[3];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_21[3];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_22[3];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_23[3];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_24[3];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_25[3];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_26[3];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_27[3];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_28[3];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_29[3];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_30[3];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_3_252_tlb_m_e_ETC___d2285 =
|
|
tlb_m_entryVec_31[3];
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_NOT_tlb_m_entryVec_0_118_BIT_2_287_288_ETC___d2352 =
|
|
!tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_0[5];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_1[5];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_2[5];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_3[5];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_4[5];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_5[5];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_6[5];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_7[5];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_8[5];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_9[5];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_10[5];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_11[5];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_12[5];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_13[5];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_14[5];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_15[5];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_16[5];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_17[5];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_18[5];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_19[5];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_20[5];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_21[5];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_22[5];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_23[5];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_24[5];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_25[5];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_26[5];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_27[5];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_28[5];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_29[5];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_30[5];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_5_170_tlb_m_e_ETC___d2203 =
|
|
tlb_m_entryVec_31[5];
|
|
endcase
|
|
end
|
|
always@(idx__h70014 or
|
|
tlb_m_entryVec_0 or
|
|
tlb_m_entryVec_1 or
|
|
tlb_m_entryVec_2 or
|
|
tlb_m_entryVec_3 or
|
|
tlb_m_entryVec_4 or
|
|
tlb_m_entryVec_5 or
|
|
tlb_m_entryVec_6 or
|
|
tlb_m_entryVec_7 or
|
|
tlb_m_entryVec_8 or
|
|
tlb_m_entryVec_9 or
|
|
tlb_m_entryVec_10 or
|
|
tlb_m_entryVec_11 or
|
|
tlb_m_entryVec_12 or
|
|
tlb_m_entryVec_13 or
|
|
tlb_m_entryVec_14 or
|
|
tlb_m_entryVec_15 or
|
|
tlb_m_entryVec_16 or
|
|
tlb_m_entryVec_17 or
|
|
tlb_m_entryVec_18 or
|
|
tlb_m_entryVec_19 or
|
|
tlb_m_entryVec_20 or
|
|
tlb_m_entryVec_21 or
|
|
tlb_m_entryVec_22 or
|
|
tlb_m_entryVec_23 or
|
|
tlb_m_entryVec_24 or
|
|
tlb_m_entryVec_25 or
|
|
tlb_m_entryVec_26 or
|
|
tlb_m_entryVec_27 or
|
|
tlb_m_entryVec_28 or
|
|
tlb_m_entryVec_29 or tlb_m_entryVec_30 or tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h70014)
|
|
5'd0:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_0[7];
|
|
5'd1:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_1[7];
|
|
5'd2:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_2[7];
|
|
5'd3:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_3[7];
|
|
5'd4:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_4[7];
|
|
5'd5:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_5[7];
|
|
5'd6:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_6[7];
|
|
5'd7:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_7[7];
|
|
5'd8:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_8[7];
|
|
5'd9:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_9[7];
|
|
5'd10:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_10[7];
|
|
5'd11:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_11[7];
|
|
5'd12:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_12[7];
|
|
5'd13:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_13[7];
|
|
5'd14:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_14[7];
|
|
5'd15:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_15[7];
|
|
5'd16:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_16[7];
|
|
5'd17:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_17[7];
|
|
5'd18:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_18[7];
|
|
5'd19:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_19[7];
|
|
5'd20:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_20[7];
|
|
5'd21:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_21[7];
|
|
5'd22:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_22[7];
|
|
5'd23:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_23[7];
|
|
5'd24:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_24[7];
|
|
5'd25:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_25[7];
|
|
5'd26:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_26[7];
|
|
5'd27:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_27[7];
|
|
5'd28:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_28[7];
|
|
5'd29:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_29[7];
|
|
5'd30:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_30[7];
|
|
5'd31:
|
|
SEL_ARR_tlb_m_entryVec_0_118_BIT_7_038_tlb_m_e_ETC___d2102 =
|
|
tlb_m_entryVec_31[7];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q33 =
|
|
rsFromPQ_data_0[4];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_4_1_r_ETC__q33 =
|
|
rsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q34 =
|
|
rsFromPQ_data_0[2];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_2_1_r_ETC__q34 =
|
|
rsFromPQ_data_1[2];
|
|
endcase
|
|
end
|
|
always@(rsFromPQ_deqP or rsFromPQ_data_0 or rsFromPQ_data_1)
|
|
begin
|
|
case (rsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q35 =
|
|
rsFromPQ_data_0[8];
|
|
1'd1:
|
|
CASE_rsFromPQ_deqP_0_rsFromPQ_data_0_BIT_8_1_r_ETC__q35 =
|
|
rsFromPQ_data_1[8];
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_13_ETC__q36 =
|
|
hitQ_data_0[4:0] == 5'd13;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_13_ETC__q36 =
|
|
hitQ_data_1[4:0] == 5'd13;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_15_ETC__q37 =
|
|
hitQ_data_0[4:0] == 5'd15;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_15_ETC__q37 =
|
|
hitQ_data_1[4:0] == 5'd15;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_12_ETC__q38 =
|
|
hitQ_data_0[4:0] == 5'd12;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_12_ETC__q38 =
|
|
hitQ_data_1[4:0] == 5'd12;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_11_ETC__q39 =
|
|
hitQ_data_0[4:0] == 5'd11;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_11_ETC__q39 =
|
|
hitQ_data_1[4:0] == 5'd11;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_9__ETC__q40 =
|
|
hitQ_data_0[4:0] == 5'd9;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_9__ETC__q40 =
|
|
hitQ_data_1[4:0] == 5'd9;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_8__ETC__q41 =
|
|
hitQ_data_0[4:0] == 5'd8;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_8__ETC__q41 =
|
|
hitQ_data_1[4:0] == 5'd8;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_7__ETC__q42 =
|
|
hitQ_data_0[4:0] == 5'd7;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_7__ETC__q42 =
|
|
hitQ_data_1[4:0] == 5'd7;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_6__ETC__q43 =
|
|
hitQ_data_0[4:0] == 5'd6;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_6__ETC__q43 =
|
|
hitQ_data_1[4:0] == 5'd6;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_5__ETC__q44 =
|
|
hitQ_data_0[4:0] == 5'd5;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_5__ETC__q44 =
|
|
hitQ_data_1[4:0] == 5'd5;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_4__ETC__q45 =
|
|
hitQ_data_0[4:0] == 5'd4;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_4__ETC__q45 =
|
|
hitQ_data_1[4:0] == 5'd4;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_3__ETC__q46 =
|
|
hitQ_data_0[4:0] == 5'd3;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_3__ETC__q46 =
|
|
hitQ_data_1[4:0] == 5'd3;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_2__ETC__q47 =
|
|
hitQ_data_0[4:0] == 5'd2;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_2__ETC__q47 =
|
|
hitQ_data_1[4:0] == 5'd2;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_1__ETC__q48 =
|
|
hitQ_data_0[4:0] == 5'd1;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_1__ETC__q48 =
|
|
hitQ_data_1[4:0] == 5'd1;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_0__ETC__q49 =
|
|
hitQ_data_0[4:0] == 5'd0;
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_hitQ_data_0_BITS_4_TO_0_EQ_0__ETC__q49 =
|
|
hitQ_data_1[4:0] == 5'd0;
|
|
endcase
|
|
end
|
|
always@(hitQ_deqP or hitQ_data_0 or hitQ_data_1)
|
|
begin
|
|
case (hitQ_deqP)
|
|
1'd0:
|
|
CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q50 =
|
|
!hitQ_data_0[5];
|
|
1'd1:
|
|
CASE_hitQ_deqP_0_NOT_hitQ_data_0_BIT_5_1_NOT_h_ETC__q50 =
|
|
!hitQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(tlb_m_randIdx or INV_n__read6006__q51)
|
|
begin
|
|
case (tlb_m_randIdx)
|
|
5'd0:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[0];
|
|
5'd1:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[1];
|
|
5'd2:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[2];
|
|
5'd3:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[3];
|
|
5'd4:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[4];
|
|
5'd5:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[5];
|
|
5'd6:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[6];
|
|
5'd7:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[7];
|
|
5'd8:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[8];
|
|
5'd9:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[9];
|
|
5'd10:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[10];
|
|
5'd11:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[11];
|
|
5'd12:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[12];
|
|
5'd13:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[13];
|
|
5'd14:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[14];
|
|
5'd15:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[15];
|
|
5'd16:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[16];
|
|
5'd17:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[17];
|
|
5'd18:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[18];
|
|
5'd19:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[19];
|
|
5'd20:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[20];
|
|
5'd21:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[21];
|
|
5'd22:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[22];
|
|
5'd23:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[23];
|
|
5'd24:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[24];
|
|
5'd25:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[25];
|
|
5'd26:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[26];
|
|
5'd27:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[27];
|
|
5'd28:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[28];
|
|
5'd29:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[29];
|
|
5'd30:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[30];
|
|
5'd31:
|
|
CASE_tlb_m_randIdx_0_INV_n__read60061_BIT_0_1__ETC__q52 =
|
|
INV_n__read6006__q51[31];
|
|
endcase
|
|
end
|
|
always@(hitQ_enqReq_lat_0$wget)
|
|
begin
|
|
case (hitQ_enqReq_lat_0$wget[4:0])
|
|
5'd0: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd0;
|
|
5'd1: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd1;
|
|
5'd2: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd2;
|
|
5'd3: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd3;
|
|
5'd4: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd4;
|
|
5'd5: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd5;
|
|
5'd6: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd6;
|
|
5'd7: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd7;
|
|
5'd8: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd8;
|
|
5'd9: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd9;
|
|
5'd11: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd10;
|
|
5'd12: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd11;
|
|
5'd13: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd12;
|
|
5'd15: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd13;
|
|
default: CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 = 4'd14;
|
|
endcase
|
|
end
|
|
always@(hitQ_enqReq_rl)
|
|
begin
|
|
case (hitQ_enqReq_rl[4:0])
|
|
5'd0: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd0;
|
|
5'd1: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd1;
|
|
5'd2: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd2;
|
|
5'd3: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd3;
|
|
5'd4: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd4;
|
|
5'd5: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd5;
|
|
5'd6: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd6;
|
|
5'd7: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd7;
|
|
5'd8: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd8;
|
|
5'd9: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd9;
|
|
5'd11: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd10;
|
|
5'd12: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd11;
|
|
5'd13: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd12;
|
|
5'd15: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 = 4'd13;
|
|
default: CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54 =
|
|
4'd14;
|
|
endcase
|
|
end
|
|
always@(hitQ_enqReq_lat_0$whas or
|
|
CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 or
|
|
CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54)
|
|
begin
|
|
case (hitQ_enqReq_lat_0$whas ?
|
|
CASE_hitQ_enqReq_lat_0wget_BITS_4_TO_0_0_0_1__ETC__q53 :
|
|
CASE_hitQ_enqReq_rl_BITS_4_TO_0_0_0_1_1_2_2_3__ETC__q54)
|
|
4'd0: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd0;
|
|
4'd1: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd1;
|
|
4'd2: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd2;
|
|
4'd3: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd3;
|
|
4'd4: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd4;
|
|
4'd5: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd5;
|
|
4'd6: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd6;
|
|
4'd7: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd7;
|
|
4'd8: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd8;
|
|
4'd9: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd9;
|
|
4'd10: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd11;
|
|
4'd11: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd12;
|
|
4'd12: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd13;
|
|
4'd13: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd15;
|
|
default: CASE_IF_hitQ_enqReq_lat_0whas_THEN_CASE_hitQ__ETC__q55 = 5'd28;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_data_0 <= `BSV_ASSIGNMENT_DELAY 70'd10;
|
|
hitQ_data_1 <= `BSV_ASSIGNMENT_DELAY 70'd10;
|
|
hitQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
hitQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
hitQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 71'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
miss <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA;
|
|
needFlush <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 27'd0;
|
|
rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 27'd0;
|
|
rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 28'd44739242;
|
|
rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
rsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 82'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY 6'd10;
|
|
tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
vm_info <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
waitFlushP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (flushRqToPQ_clearReq_rl$EN)
|
|
flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_clearReq_rl$D_IN;
|
|
if (flushRqToPQ_deqReq_rl$EN)
|
|
flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_deqReq_rl$D_IN;
|
|
if (flushRqToPQ_empty$EN)
|
|
flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY flushRqToPQ_empty$D_IN;
|
|
if (flushRqToPQ_enqReq_rl$EN)
|
|
flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRqToPQ_enqReq_rl$D_IN;
|
|
if (flushRqToPQ_full$EN)
|
|
flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY flushRqToPQ_full$D_IN;
|
|
if (flushRsFromPQ_clearReq_rl$EN)
|
|
flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_clearReq_rl$D_IN;
|
|
if (flushRsFromPQ_deqReq_rl$EN)
|
|
flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_deqReq_rl$D_IN;
|
|
if (flushRsFromPQ_empty$EN)
|
|
flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_empty$D_IN;
|
|
if (flushRsFromPQ_enqReq_rl$EN)
|
|
flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
flushRsFromPQ_enqReq_rl$D_IN;
|
|
if (flushRsFromPQ_full$EN)
|
|
flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY flushRsFromPQ_full$D_IN;
|
|
if (hitQ_clearReq_rl$EN)
|
|
hitQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_clearReq_rl$D_IN;
|
|
if (hitQ_data_0$EN)
|
|
hitQ_data_0 <= `BSV_ASSIGNMENT_DELAY hitQ_data_0$D_IN;
|
|
if (hitQ_data_1$EN)
|
|
hitQ_data_1 <= `BSV_ASSIGNMENT_DELAY hitQ_data_1$D_IN;
|
|
if (hitQ_deqP$EN) hitQ_deqP <= `BSV_ASSIGNMENT_DELAY hitQ_deqP$D_IN;
|
|
if (hitQ_deqReq_rl$EN)
|
|
hitQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_deqReq_rl$D_IN;
|
|
if (hitQ_empty$EN)
|
|
hitQ_empty <= `BSV_ASSIGNMENT_DELAY hitQ_empty$D_IN;
|
|
if (hitQ_enqP$EN) hitQ_enqP <= `BSV_ASSIGNMENT_DELAY hitQ_enqP$D_IN;
|
|
if (hitQ_enqReq_rl$EN)
|
|
hitQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY hitQ_enqReq_rl$D_IN;
|
|
if (hitQ_full$EN) hitQ_full <= `BSV_ASSIGNMENT_DELAY hitQ_full$D_IN;
|
|
if (miss$EN) miss <= `BSV_ASSIGNMENT_DELAY miss$D_IN;
|
|
if (needFlush$EN) needFlush <= `BSV_ASSIGNMENT_DELAY needFlush$D_IN;
|
|
if (perfReqQ_clearReq_rl$EN)
|
|
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
perfReqQ_clearReq_rl$D_IN;
|
|
if (perfReqQ_data_0$EN)
|
|
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
|
|
if (perfReqQ_deqReq_rl$EN)
|
|
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
|
|
if (perfReqQ_empty$EN)
|
|
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
|
|
if (perfReqQ_enqReq_rl$EN)
|
|
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
|
|
if (perfReqQ_full$EN)
|
|
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
|
|
if (rqToPQ_clearReq_rl$EN)
|
|
rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_clearReq_rl$D_IN;
|
|
if (rqToPQ_data_0$EN)
|
|
rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY rqToPQ_data_0$D_IN;
|
|
if (rqToPQ_data_1$EN)
|
|
rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY rqToPQ_data_1$D_IN;
|
|
if (rqToPQ_deqP$EN)
|
|
rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY rqToPQ_deqP$D_IN;
|
|
if (rqToPQ_deqReq_rl$EN)
|
|
rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_deqReq_rl$D_IN;
|
|
if (rqToPQ_empty$EN)
|
|
rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY rqToPQ_empty$D_IN;
|
|
if (rqToPQ_enqP$EN)
|
|
rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY rqToPQ_enqP$D_IN;
|
|
if (rqToPQ_enqReq_rl$EN)
|
|
rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY rqToPQ_enqReq_rl$D_IN;
|
|
if (rqToPQ_full$EN)
|
|
rqToPQ_full <= `BSV_ASSIGNMENT_DELAY rqToPQ_full$D_IN;
|
|
if (rsFromPQ_clearReq_rl$EN)
|
|
rsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
rsFromPQ_clearReq_rl$D_IN;
|
|
if (rsFromPQ_data_0$EN)
|
|
rsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY rsFromPQ_data_0$D_IN;
|
|
if (rsFromPQ_data_1$EN)
|
|
rsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY rsFromPQ_data_1$D_IN;
|
|
if (rsFromPQ_deqP$EN)
|
|
rsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY rsFromPQ_deqP$D_IN;
|
|
if (rsFromPQ_deqReq_rl$EN)
|
|
rsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY rsFromPQ_deqReq_rl$D_IN;
|
|
if (rsFromPQ_empty$EN)
|
|
rsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY rsFromPQ_empty$D_IN;
|
|
if (rsFromPQ_enqP$EN)
|
|
rsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY rsFromPQ_enqP$D_IN;
|
|
if (rsFromPQ_enqReq_rl$EN)
|
|
rsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY rsFromPQ_enqReq_rl$D_IN;
|
|
if (rsFromPQ_full$EN)
|
|
rsFromPQ_full <= `BSV_ASSIGNMENT_DELAY rsFromPQ_full$D_IN;
|
|
if (tlb_m_lruBit_rl$EN)
|
|
tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY tlb_m_lruBit_rl$D_IN;
|
|
if (tlb_m_randIdx$EN)
|
|
tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY tlb_m_randIdx$D_IN;
|
|
if (tlb_m_updRepIdx_rl$EN)
|
|
tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY tlb_m_updRepIdx_rl$D_IN;
|
|
if (tlb_m_validVec_0$EN)
|
|
tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_0$D_IN;
|
|
if (tlb_m_validVec_1$EN)
|
|
tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_1$D_IN;
|
|
if (tlb_m_validVec_10$EN)
|
|
tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_10$D_IN;
|
|
if (tlb_m_validVec_11$EN)
|
|
tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_11$D_IN;
|
|
if (tlb_m_validVec_12$EN)
|
|
tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_12$D_IN;
|
|
if (tlb_m_validVec_13$EN)
|
|
tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_13$D_IN;
|
|
if (tlb_m_validVec_14$EN)
|
|
tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_14$D_IN;
|
|
if (tlb_m_validVec_15$EN)
|
|
tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_15$D_IN;
|
|
if (tlb_m_validVec_16$EN)
|
|
tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_16$D_IN;
|
|
if (tlb_m_validVec_17$EN)
|
|
tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_17$D_IN;
|
|
if (tlb_m_validVec_18$EN)
|
|
tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_18$D_IN;
|
|
if (tlb_m_validVec_19$EN)
|
|
tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_19$D_IN;
|
|
if (tlb_m_validVec_2$EN)
|
|
tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_2$D_IN;
|
|
if (tlb_m_validVec_20$EN)
|
|
tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_20$D_IN;
|
|
if (tlb_m_validVec_21$EN)
|
|
tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_21$D_IN;
|
|
if (tlb_m_validVec_22$EN)
|
|
tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_22$D_IN;
|
|
if (tlb_m_validVec_23$EN)
|
|
tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_23$D_IN;
|
|
if (tlb_m_validVec_24$EN)
|
|
tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_24$D_IN;
|
|
if (tlb_m_validVec_25$EN)
|
|
tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_25$D_IN;
|
|
if (tlb_m_validVec_26$EN)
|
|
tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_26$D_IN;
|
|
if (tlb_m_validVec_27$EN)
|
|
tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_27$D_IN;
|
|
if (tlb_m_validVec_28$EN)
|
|
tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_28$D_IN;
|
|
if (tlb_m_validVec_29$EN)
|
|
tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_29$D_IN;
|
|
if (tlb_m_validVec_3$EN)
|
|
tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_3$D_IN;
|
|
if (tlb_m_validVec_30$EN)
|
|
tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_30$D_IN;
|
|
if (tlb_m_validVec_31$EN)
|
|
tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_31$D_IN;
|
|
if (tlb_m_validVec_4$EN)
|
|
tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_4$D_IN;
|
|
if (tlb_m_validVec_5$EN)
|
|
tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_5$D_IN;
|
|
if (tlb_m_validVec_6$EN)
|
|
tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_6$D_IN;
|
|
if (tlb_m_validVec_7$EN)
|
|
tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_7$D_IN;
|
|
if (tlb_m_validVec_8$EN)
|
|
tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_8$D_IN;
|
|
if (tlb_m_validVec_9$EN)
|
|
tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY tlb_m_validVec_9$D_IN;
|
|
if (vm_info$EN) vm_info <= `BSV_ASSIGNMENT_DELAY vm_info$D_IN;
|
|
if (waitFlushP$EN)
|
|
waitFlushP <= `BSV_ASSIGNMENT_DELAY waitFlushP$D_IN;
|
|
end
|
|
if (tlb_m_entryVec_0$EN)
|
|
tlb_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_0$D_IN;
|
|
if (tlb_m_entryVec_1$EN)
|
|
tlb_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_1$D_IN;
|
|
if (tlb_m_entryVec_10$EN)
|
|
tlb_m_entryVec_10 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_10$D_IN;
|
|
if (tlb_m_entryVec_11$EN)
|
|
tlb_m_entryVec_11 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_11$D_IN;
|
|
if (tlb_m_entryVec_12$EN)
|
|
tlb_m_entryVec_12 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_12$D_IN;
|
|
if (tlb_m_entryVec_13$EN)
|
|
tlb_m_entryVec_13 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_13$D_IN;
|
|
if (tlb_m_entryVec_14$EN)
|
|
tlb_m_entryVec_14 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_14$D_IN;
|
|
if (tlb_m_entryVec_15$EN)
|
|
tlb_m_entryVec_15 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_15$D_IN;
|
|
if (tlb_m_entryVec_16$EN)
|
|
tlb_m_entryVec_16 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_16$D_IN;
|
|
if (tlb_m_entryVec_17$EN)
|
|
tlb_m_entryVec_17 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_17$D_IN;
|
|
if (tlb_m_entryVec_18$EN)
|
|
tlb_m_entryVec_18 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_18$D_IN;
|
|
if (tlb_m_entryVec_19$EN)
|
|
tlb_m_entryVec_19 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_19$D_IN;
|
|
if (tlb_m_entryVec_2$EN)
|
|
tlb_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_2$D_IN;
|
|
if (tlb_m_entryVec_20$EN)
|
|
tlb_m_entryVec_20 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_20$D_IN;
|
|
if (tlb_m_entryVec_21$EN)
|
|
tlb_m_entryVec_21 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_21$D_IN;
|
|
if (tlb_m_entryVec_22$EN)
|
|
tlb_m_entryVec_22 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_22$D_IN;
|
|
if (tlb_m_entryVec_23$EN)
|
|
tlb_m_entryVec_23 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_23$D_IN;
|
|
if (tlb_m_entryVec_24$EN)
|
|
tlb_m_entryVec_24 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_24$D_IN;
|
|
if (tlb_m_entryVec_25$EN)
|
|
tlb_m_entryVec_25 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_25$D_IN;
|
|
if (tlb_m_entryVec_26$EN)
|
|
tlb_m_entryVec_26 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_26$D_IN;
|
|
if (tlb_m_entryVec_27$EN)
|
|
tlb_m_entryVec_27 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_27$D_IN;
|
|
if (tlb_m_entryVec_28$EN)
|
|
tlb_m_entryVec_28 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_28$D_IN;
|
|
if (tlb_m_entryVec_29$EN)
|
|
tlb_m_entryVec_29 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_29$D_IN;
|
|
if (tlb_m_entryVec_3$EN)
|
|
tlb_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_3$D_IN;
|
|
if (tlb_m_entryVec_30$EN)
|
|
tlb_m_entryVec_30 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_30$D_IN;
|
|
if (tlb_m_entryVec_31$EN)
|
|
tlb_m_entryVec_31 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_31$D_IN;
|
|
if (tlb_m_entryVec_4$EN)
|
|
tlb_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_4$D_IN;
|
|
if (tlb_m_entryVec_5$EN)
|
|
tlb_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_5$D_IN;
|
|
if (tlb_m_entryVec_6$EN)
|
|
tlb_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_6$D_IN;
|
|
if (tlb_m_entryVec_7$EN)
|
|
tlb_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_7$D_IN;
|
|
if (tlb_m_entryVec_8$EN)
|
|
tlb_m_entryVec_8 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_8$D_IN;
|
|
if (tlb_m_entryVec_9$EN)
|
|
tlb_m_entryVec_9 <= `BSV_ASSIGNMENT_DELAY tlb_m_entryVec_9$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
flushRqToPQ_clearReq_rl = 1'h0;
|
|
flushRqToPQ_deqReq_rl = 1'h0;
|
|
flushRqToPQ_empty = 1'h0;
|
|
flushRqToPQ_enqReq_rl = 1'h0;
|
|
flushRqToPQ_full = 1'h0;
|
|
flushRsFromPQ_clearReq_rl = 1'h0;
|
|
flushRsFromPQ_deqReq_rl = 1'h0;
|
|
flushRsFromPQ_empty = 1'h0;
|
|
flushRsFromPQ_enqReq_rl = 1'h0;
|
|
flushRsFromPQ_full = 1'h0;
|
|
hitQ_clearReq_rl = 1'h0;
|
|
hitQ_data_0 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_data_1 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_deqP = 1'h0;
|
|
hitQ_deqReq_rl = 1'h0;
|
|
hitQ_empty = 1'h0;
|
|
hitQ_enqP = 1'h0;
|
|
hitQ_enqReq_rl = 71'h2AAAAAAAAAAAAAAAAA;
|
|
hitQ_full = 1'h0;
|
|
miss = 65'h0AAAAAAAAAAAAAAAA;
|
|
needFlush = 1'h0;
|
|
perfReqQ_clearReq_rl = 1'h0;
|
|
perfReqQ_data_0 = 3'h2;
|
|
perfReqQ_deqReq_rl = 1'h0;
|
|
perfReqQ_empty = 1'h0;
|
|
perfReqQ_enqReq_rl = 4'hA;
|
|
perfReqQ_full = 1'h0;
|
|
rqToPQ_clearReq_rl = 1'h0;
|
|
rqToPQ_data_0 = 27'h2AAAAAA;
|
|
rqToPQ_data_1 = 27'h2AAAAAA;
|
|
rqToPQ_deqP = 1'h0;
|
|
rqToPQ_deqReq_rl = 1'h0;
|
|
rqToPQ_empty = 1'h0;
|
|
rqToPQ_enqP = 1'h0;
|
|
rqToPQ_enqReq_rl = 28'hAAAAAAA;
|
|
rqToPQ_full = 1'h0;
|
|
rsFromPQ_clearReq_rl = 1'h0;
|
|
rsFromPQ_data_0 = 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_data_1 = 81'h0AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_deqP = 1'h0;
|
|
rsFromPQ_deqReq_rl = 1'h0;
|
|
rsFromPQ_empty = 1'h0;
|
|
rsFromPQ_enqP = 1'h0;
|
|
rsFromPQ_enqReq_rl = 82'h2AAAAAAAAAAAAAAAAAAAA;
|
|
rsFromPQ_full = 1'h0;
|
|
tlb_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_10 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_11 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_12 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_13 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_14 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_15 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_16 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_17 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_18 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_19 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_20 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_21 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_22 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_23 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_24 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_25 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_26 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_27 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_28 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_29 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_30 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_31 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_8 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_entryVec_9 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
tlb_m_lruBit_rl = 32'hAAAAAAAA;
|
|
tlb_m_randIdx = 5'h0A;
|
|
tlb_m_updRepIdx_rl = 6'h2A;
|
|
tlb_m_validVec_0 = 1'h0;
|
|
tlb_m_validVec_1 = 1'h0;
|
|
tlb_m_validVec_10 = 1'h0;
|
|
tlb_m_validVec_11 = 1'h0;
|
|
tlb_m_validVec_12 = 1'h0;
|
|
tlb_m_validVec_13 = 1'h0;
|
|
tlb_m_validVec_14 = 1'h0;
|
|
tlb_m_validVec_15 = 1'h0;
|
|
tlb_m_validVec_16 = 1'h0;
|
|
tlb_m_validVec_17 = 1'h0;
|
|
tlb_m_validVec_18 = 1'h0;
|
|
tlb_m_validVec_19 = 1'h0;
|
|
tlb_m_validVec_2 = 1'h0;
|
|
tlb_m_validVec_20 = 1'h0;
|
|
tlb_m_validVec_21 = 1'h0;
|
|
tlb_m_validVec_22 = 1'h0;
|
|
tlb_m_validVec_23 = 1'h0;
|
|
tlb_m_validVec_24 = 1'h0;
|
|
tlb_m_validVec_25 = 1'h0;
|
|
tlb_m_validVec_26 = 1'h0;
|
|
tlb_m_validVec_27 = 1'h0;
|
|
tlb_m_validVec_28 = 1'h0;
|
|
tlb_m_validVec_29 = 1'h0;
|
|
tlb_m_validVec_3 = 1'h0;
|
|
tlb_m_validVec_30 = 1'h0;
|
|
tlb_m_validVec_31 = 1'h0;
|
|
tlb_m_validVec_4 = 1'h0;
|
|
tlb_m_validVec_5 = 1'h0;
|
|
tlb_m_validVec_6 = 1'h0;
|
|
tlb_m_validVec_7 = 1'h0;
|
|
tlb_m_validVec_8 = 1'h0;
|
|
tlb_m_validVec_9 = 1'h0;
|
|
vm_info = 49'h0AAAAAAAAAAAA;
|
|
waitFlushP = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkITlb
|
|
|