10517 lines
418 KiB
Verilog
10517 lines
418 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Mon Jul 13 18:32:59 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// flush_done O 1
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// RDY_flush_done O 1 const
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// RDY_flush O 1
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// RDY_updateVMInfo O 1 const
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// noPendingReq O 1
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// RDY_noPendingReq O 1 const
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// RDY_procReq O 1
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// procResp O 561
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// RDY_procResp O 1
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// RDY_deqProcResp O 1
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// toParent_rqToP_notEmpty O 1
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// RDY_toParent_rqToP_notEmpty O 1 const
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// RDY_toParent_rqToP_deq O 1
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// toParent_rqToP_first O 29
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// RDY_toParent_rqToP_first O 1
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// toParent_ldTransRsFromP_notFull O 1
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// RDY_toParent_ldTransRsFromP_notFull O 1 const
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// RDY_toParent_ldTransRsFromP_enq O 1
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// RDY_toParent_flush_request_get O 1
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// RDY_toParent_flush_response_put O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// RDY_perf_setStatus O 1 const
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// RDY_perf_req O 1
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// perf_resp O 67
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// RDY_perf_resp O 1
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// perf_respValid O 1
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// RDY_perf_respValid O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// updateVMInfo_vm I 49 reg
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// procReq_req I 491
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// toParent_ldTransRsFromP_enq_x I 83
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// perf_setStatus_doStats I 1 unused
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// perf_req_r I 3
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// EN_flush I 1
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// EN_updateVMInfo I 1
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// EN_procReq I 1
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// EN_deqProcResp I 1
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// EN_toParent_rqToP_deq I 1
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// EN_toParent_ldTransRsFromP_enq I 1
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// EN_toParent_flush_request_get I 1
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// EN_toParent_flush_response_put I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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// EN_perf_setStatus I 1 unused
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// EN_perf_req I 1
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// EN_perf_resp I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDTlbSynth(CLK,
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RST_N,
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flush_done,
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RDY_flush_done,
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EN_flush,
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RDY_flush,
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updateVMInfo_vm,
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EN_updateVMInfo,
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RDY_updateVMInfo,
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noPendingReq,
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RDY_noPendingReq,
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procReq_req,
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EN_procReq,
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RDY_procReq,
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procResp,
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RDY_procResp,
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EN_deqProcResp,
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RDY_deqProcResp,
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toParent_rqToP_notEmpty,
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RDY_toParent_rqToP_notEmpty,
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EN_toParent_rqToP_deq,
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RDY_toParent_rqToP_deq,
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toParent_rqToP_first,
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RDY_toParent_rqToP_first,
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toParent_ldTransRsFromP_notFull,
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RDY_toParent_ldTransRsFromP_notFull,
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toParent_ldTransRsFromP_enq_x,
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EN_toParent_ldTransRsFromP_enq,
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RDY_toParent_ldTransRsFromP_enq,
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EN_toParent_flush_request_get,
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RDY_toParent_flush_request_get,
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EN_toParent_flush_response_put,
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RDY_toParent_flush_response_put,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation,
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perf_setStatus_doStats,
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EN_perf_setStatus,
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RDY_perf_setStatus,
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perf_req_r,
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EN_perf_req,
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RDY_perf_req,
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EN_perf_resp,
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perf_resp,
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RDY_perf_resp,
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perf_respValid,
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RDY_perf_respValid);
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input CLK;
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input RST_N;
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// value method flush_done
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output flush_done;
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output RDY_flush_done;
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// action method flush
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input EN_flush;
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output RDY_flush;
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// action method updateVMInfo
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input [48 : 0] updateVMInfo_vm;
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input EN_updateVMInfo;
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output RDY_updateVMInfo;
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// value method noPendingReq
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output noPendingReq;
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output RDY_noPendingReq;
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// action method procReq
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input [490 : 0] procReq_req;
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input EN_procReq;
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output RDY_procReq;
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// value method procResp
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output [560 : 0] procResp;
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output RDY_procResp;
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// action method deqProcResp
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input EN_deqProcResp;
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output RDY_deqProcResp;
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// value method toParent_rqToP_notEmpty
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output toParent_rqToP_notEmpty;
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output RDY_toParent_rqToP_notEmpty;
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// action method toParent_rqToP_deq
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input EN_toParent_rqToP_deq;
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output RDY_toParent_rqToP_deq;
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// value method toParent_rqToP_first
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output [28 : 0] toParent_rqToP_first;
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output RDY_toParent_rqToP_first;
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// value method toParent_ldTransRsFromP_notFull
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output toParent_ldTransRsFromP_notFull;
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output RDY_toParent_ldTransRsFromP_notFull;
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// action method toParent_ldTransRsFromP_enq
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input [82 : 0] toParent_ldTransRsFromP_enq_x;
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input EN_toParent_ldTransRsFromP_enq;
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output RDY_toParent_ldTransRsFromP_enq;
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// action method toParent_flush_request_get
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input EN_toParent_flush_request_get;
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output RDY_toParent_flush_request_get;
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// action method toParent_flush_response_put
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input EN_toParent_flush_response_put;
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output RDY_toParent_flush_response_put;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// action method perf_setStatus
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input perf_setStatus_doStats;
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input EN_perf_setStatus;
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output RDY_perf_setStatus;
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// action method perf_req
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input [2 : 0] perf_req_r;
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input EN_perf_req;
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output RDY_perf_req;
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// actionvalue method perf_resp
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input EN_perf_resp;
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output [66 : 0] perf_resp;
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output RDY_perf_resp;
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// value method perf_respValid
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output perf_respValid;
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output RDY_perf_respValid;
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// signals for module outputs
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wire [560 : 0] procResp;
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wire [66 : 0] perf_resp;
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wire [28 : 0] toParent_rqToP_first;
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wire RDY_deqProcResp,
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RDY_flush,
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RDY_flush_done,
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RDY_noPendingReq,
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RDY_perf_req,
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RDY_perf_resp,
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RDY_perf_respValid,
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RDY_perf_setStatus,
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RDY_procReq,
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RDY_procResp,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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RDY_toParent_flush_request_get,
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RDY_toParent_flush_response_put,
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RDY_toParent_ldTransRsFromP_enq,
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RDY_toParent_ldTransRsFromP_notFull,
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RDY_toParent_rqToP_deq,
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RDY_toParent_rqToP_first,
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RDY_toParent_rqToP_notEmpty,
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RDY_updateVMInfo,
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flush_done,
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noPendingReq,
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perf_respValid,
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toParent_ldTransRsFromP_notFull,
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toParent_rqToP_notEmpty;
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// inlined wires
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reg [2 : 0] m_freeQ_enqReq_lat_0$wget;
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wire [83 : 0] m_ldTransRsFromPQ_enqReq_lat_0$wget;
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wire [29 : 0] m_rqToPQ_enqReq_lat_0$wget;
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wire [5 : 0] m_tlb_m_updRepIdx_lat_1$wget;
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wire [3 : 0] m_perfReqQ_enqReq_lat_0$wget;
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wire m_freeQ_enqReq_lat_0$whas,
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m_ldTransRsFromPQ_deqReq_lat_0$whas,
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m_pendValid_0_lat_0$whas,
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m_pendValid_1_lat_0$whas,
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m_pendValid_2_lat_0$whas,
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m_pendValid_3_lat_0$whas,
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m_rqToPQ_enqReq_lat_0$whas,
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m_tlb_m_lruBit_lat_0$whas,
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m_tlb_m_updRepIdx_lat_0$whas,
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m_tlb_m_updRepIdx_lat_1$whas;
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// register m_flushRqToPQ_clearReq_rl
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reg m_flushRqToPQ_clearReq_rl;
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wire m_flushRqToPQ_clearReq_rl$D_IN, m_flushRqToPQ_clearReq_rl$EN;
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// register m_flushRqToPQ_deqReq_rl
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reg m_flushRqToPQ_deqReq_rl;
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wire m_flushRqToPQ_deqReq_rl$D_IN, m_flushRqToPQ_deqReq_rl$EN;
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// register m_flushRqToPQ_empty
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reg m_flushRqToPQ_empty;
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wire m_flushRqToPQ_empty$D_IN, m_flushRqToPQ_empty$EN;
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// register m_flushRqToPQ_enqReq_rl
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reg m_flushRqToPQ_enqReq_rl;
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wire m_flushRqToPQ_enqReq_rl$D_IN, m_flushRqToPQ_enqReq_rl$EN;
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// register m_flushRqToPQ_full
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reg m_flushRqToPQ_full;
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wire m_flushRqToPQ_full$D_IN, m_flushRqToPQ_full$EN;
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// register m_flushRsFromPQ_clearReq_rl
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reg m_flushRsFromPQ_clearReq_rl;
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wire m_flushRsFromPQ_clearReq_rl$D_IN, m_flushRsFromPQ_clearReq_rl$EN;
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// register m_flushRsFromPQ_deqReq_rl
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reg m_flushRsFromPQ_deqReq_rl;
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wire m_flushRsFromPQ_deqReq_rl$D_IN, m_flushRsFromPQ_deqReq_rl$EN;
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// register m_flushRsFromPQ_empty
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reg m_flushRsFromPQ_empty;
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wire m_flushRsFromPQ_empty$D_IN, m_flushRsFromPQ_empty$EN;
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// register m_flushRsFromPQ_enqReq_rl
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reg m_flushRsFromPQ_enqReq_rl;
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wire m_flushRsFromPQ_enqReq_rl$D_IN, m_flushRsFromPQ_enqReq_rl$EN;
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// register m_flushRsFromPQ_full
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reg m_flushRsFromPQ_full;
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wire m_flushRsFromPQ_full$D_IN, m_flushRsFromPQ_full$EN;
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// register m_freeQInitIdx
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reg [1 : 0] m_freeQInitIdx;
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wire [1 : 0] m_freeQInitIdx$D_IN;
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wire m_freeQInitIdx$EN;
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// register m_freeQInited
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reg m_freeQInited;
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wire m_freeQInited$D_IN, m_freeQInited$EN;
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// register m_freeQ_clearReq_rl
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reg m_freeQ_clearReq_rl;
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wire m_freeQ_clearReq_rl$D_IN, m_freeQ_clearReq_rl$EN;
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// register m_freeQ_data_0
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reg [1 : 0] m_freeQ_data_0;
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wire [1 : 0] m_freeQ_data_0$D_IN;
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wire m_freeQ_data_0$EN;
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// register m_freeQ_data_1
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reg [1 : 0] m_freeQ_data_1;
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wire [1 : 0] m_freeQ_data_1$D_IN;
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wire m_freeQ_data_1$EN;
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// register m_freeQ_data_2
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reg [1 : 0] m_freeQ_data_2;
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wire [1 : 0] m_freeQ_data_2$D_IN;
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wire m_freeQ_data_2$EN;
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// register m_freeQ_data_3
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reg [1 : 0] m_freeQ_data_3;
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wire [1 : 0] m_freeQ_data_3$D_IN;
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wire m_freeQ_data_3$EN;
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// register m_freeQ_deqP
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reg [1 : 0] m_freeQ_deqP;
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wire [1 : 0] m_freeQ_deqP$D_IN;
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wire m_freeQ_deqP$EN;
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// register m_freeQ_deqReq_rl
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reg m_freeQ_deqReq_rl;
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wire m_freeQ_deqReq_rl$D_IN, m_freeQ_deqReq_rl$EN;
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// register m_freeQ_empty
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reg m_freeQ_empty;
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wire m_freeQ_empty$D_IN, m_freeQ_empty$EN;
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// register m_freeQ_enqP
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reg [1 : 0] m_freeQ_enqP;
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wire [1 : 0] m_freeQ_enqP$D_IN;
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wire m_freeQ_enqP$EN;
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// register m_freeQ_enqReq_rl
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reg [2 : 0] m_freeQ_enqReq_rl;
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wire [2 : 0] m_freeQ_enqReq_rl$D_IN;
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wire m_freeQ_enqReq_rl$EN;
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// register m_freeQ_full
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reg m_freeQ_full;
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wire m_freeQ_full$D_IN, m_freeQ_full$EN;
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// register m_ldTransRsFromPQ_clearReq_rl
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reg m_ldTransRsFromPQ_clearReq_rl;
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wire m_ldTransRsFromPQ_clearReq_rl$D_IN, m_ldTransRsFromPQ_clearReq_rl$EN;
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// register m_ldTransRsFromPQ_data_0
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reg [82 : 0] m_ldTransRsFromPQ_data_0;
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wire [82 : 0] m_ldTransRsFromPQ_data_0$D_IN;
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wire m_ldTransRsFromPQ_data_0$EN;
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// register m_ldTransRsFromPQ_data_1
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reg [82 : 0] m_ldTransRsFromPQ_data_1;
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wire [82 : 0] m_ldTransRsFromPQ_data_1$D_IN;
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wire m_ldTransRsFromPQ_data_1$EN;
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// register m_ldTransRsFromPQ_deqP
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reg m_ldTransRsFromPQ_deqP;
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wire m_ldTransRsFromPQ_deqP$D_IN, m_ldTransRsFromPQ_deqP$EN;
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// register m_ldTransRsFromPQ_deqReq_rl
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reg m_ldTransRsFromPQ_deqReq_rl;
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wire m_ldTransRsFromPQ_deqReq_rl$D_IN, m_ldTransRsFromPQ_deqReq_rl$EN;
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// register m_ldTransRsFromPQ_empty
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reg m_ldTransRsFromPQ_empty;
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wire m_ldTransRsFromPQ_empty$D_IN, m_ldTransRsFromPQ_empty$EN;
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// register m_ldTransRsFromPQ_enqP
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reg m_ldTransRsFromPQ_enqP;
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wire m_ldTransRsFromPQ_enqP$D_IN, m_ldTransRsFromPQ_enqP$EN;
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// register m_ldTransRsFromPQ_enqReq_rl
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reg [83 : 0] m_ldTransRsFromPQ_enqReq_rl;
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wire [83 : 0] m_ldTransRsFromPQ_enqReq_rl$D_IN;
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wire m_ldTransRsFromPQ_enqReq_rl$EN;
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// register m_ldTransRsFromPQ_full
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reg m_ldTransRsFromPQ_full;
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wire m_ldTransRsFromPQ_full$D_IN, m_ldTransRsFromPQ_full$EN;
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// register m_needFlush
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reg m_needFlush;
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wire m_needFlush$D_IN, m_needFlush$EN;
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// register m_pendInst_0
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reg [478 : 0] m_pendInst_0;
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wire [478 : 0] m_pendInst_0$D_IN;
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wire m_pendInst_0$EN;
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// register m_pendInst_1
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reg [478 : 0] m_pendInst_1;
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wire [478 : 0] m_pendInst_1$D_IN;
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wire m_pendInst_1$EN;
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// register m_pendInst_2
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reg [478 : 0] m_pendInst_2;
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wire [478 : 0] m_pendInst_2$D_IN;
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wire m_pendInst_2$EN;
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// register m_pendInst_3
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reg [478 : 0] m_pendInst_3;
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wire [478 : 0] m_pendInst_3$D_IN;
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wire m_pendInst_3$EN;
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// register m_pendPoisoned_0
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reg m_pendPoisoned_0;
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wire m_pendPoisoned_0$D_IN, m_pendPoisoned_0$EN;
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// register m_pendPoisoned_1
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reg m_pendPoisoned_1;
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wire m_pendPoisoned_1$D_IN, m_pendPoisoned_1$EN;
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// register m_pendPoisoned_2
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reg m_pendPoisoned_2;
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wire m_pendPoisoned_2$D_IN, m_pendPoisoned_2$EN;
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// register m_pendPoisoned_3
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reg m_pendPoisoned_3;
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wire m_pendPoisoned_3$D_IN, m_pendPoisoned_3$EN;
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// register m_pendResp_0
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reg [69 : 0] m_pendResp_0;
|
|
wire [69 : 0] m_pendResp_0$D_IN;
|
|
wire m_pendResp_0$EN;
|
|
|
|
// register m_pendResp_1
|
|
reg [69 : 0] m_pendResp_1;
|
|
wire [69 : 0] m_pendResp_1$D_IN;
|
|
wire m_pendResp_1$EN;
|
|
|
|
// register m_pendResp_2
|
|
reg [69 : 0] m_pendResp_2;
|
|
wire [69 : 0] m_pendResp_2$D_IN;
|
|
wire m_pendResp_2$EN;
|
|
|
|
// register m_pendResp_3
|
|
reg [69 : 0] m_pendResp_3;
|
|
wire [69 : 0] m_pendResp_3$D_IN;
|
|
wire m_pendResp_3$EN;
|
|
|
|
// register m_pendSpecBits_0_rl
|
|
reg [11 : 0] m_pendSpecBits_0_rl;
|
|
wire [11 : 0] m_pendSpecBits_0_rl$D_IN;
|
|
wire m_pendSpecBits_0_rl$EN;
|
|
|
|
// register m_pendSpecBits_1_rl
|
|
reg [11 : 0] m_pendSpecBits_1_rl;
|
|
wire [11 : 0] m_pendSpecBits_1_rl$D_IN;
|
|
wire m_pendSpecBits_1_rl$EN;
|
|
|
|
// register m_pendSpecBits_2_rl
|
|
reg [11 : 0] m_pendSpecBits_2_rl;
|
|
wire [11 : 0] m_pendSpecBits_2_rl$D_IN;
|
|
wire m_pendSpecBits_2_rl$EN;
|
|
|
|
// register m_pendSpecBits_3_rl
|
|
reg [11 : 0] m_pendSpecBits_3_rl;
|
|
wire [11 : 0] m_pendSpecBits_3_rl$D_IN;
|
|
wire m_pendSpecBits_3_rl$EN;
|
|
|
|
// register m_pendValid_0_rl
|
|
reg m_pendValid_0_rl;
|
|
wire m_pendValid_0_rl$D_IN, m_pendValid_0_rl$EN;
|
|
|
|
// register m_pendValid_1_rl
|
|
reg m_pendValid_1_rl;
|
|
wire m_pendValid_1_rl$D_IN, m_pendValid_1_rl$EN;
|
|
|
|
// register m_pendValid_2_rl
|
|
reg m_pendValid_2_rl;
|
|
wire m_pendValid_2_rl$D_IN, m_pendValid_2_rl$EN;
|
|
|
|
// register m_pendValid_3_rl
|
|
reg m_pendValid_3_rl;
|
|
wire m_pendValid_3_rl$D_IN, m_pendValid_3_rl$EN;
|
|
|
|
// register m_pendWait_0
|
|
reg [3 : 0] m_pendWait_0;
|
|
wire [3 : 0] m_pendWait_0$D_IN;
|
|
wire m_pendWait_0$EN;
|
|
|
|
// register m_pendWait_1
|
|
reg [3 : 0] m_pendWait_1;
|
|
wire [3 : 0] m_pendWait_1$D_IN;
|
|
wire m_pendWait_1$EN;
|
|
|
|
// register m_pendWait_2
|
|
reg [3 : 0] m_pendWait_2;
|
|
wire [3 : 0] m_pendWait_2$D_IN;
|
|
wire m_pendWait_2$EN;
|
|
|
|
// register m_pendWait_3
|
|
reg [3 : 0] m_pendWait_3;
|
|
wire [3 : 0] m_pendWait_3$D_IN;
|
|
wire m_pendWait_3$EN;
|
|
|
|
// register m_perfReqQ_clearReq_rl
|
|
reg m_perfReqQ_clearReq_rl;
|
|
wire m_perfReqQ_clearReq_rl$D_IN, m_perfReqQ_clearReq_rl$EN;
|
|
|
|
// register m_perfReqQ_data_0
|
|
reg [2 : 0] m_perfReqQ_data_0;
|
|
wire [2 : 0] m_perfReqQ_data_0$D_IN;
|
|
wire m_perfReqQ_data_0$EN;
|
|
|
|
// register m_perfReqQ_deqReq_rl
|
|
reg m_perfReqQ_deqReq_rl;
|
|
wire m_perfReqQ_deqReq_rl$D_IN, m_perfReqQ_deqReq_rl$EN;
|
|
|
|
// register m_perfReqQ_empty
|
|
reg m_perfReqQ_empty;
|
|
wire m_perfReqQ_empty$D_IN, m_perfReqQ_empty$EN;
|
|
|
|
// register m_perfReqQ_enqReq_rl
|
|
reg [3 : 0] m_perfReqQ_enqReq_rl;
|
|
wire [3 : 0] m_perfReqQ_enqReq_rl$D_IN;
|
|
wire m_perfReqQ_enqReq_rl$EN;
|
|
|
|
// register m_perfReqQ_full
|
|
reg m_perfReqQ_full;
|
|
wire m_perfReqQ_full$D_IN, m_perfReqQ_full$EN;
|
|
|
|
// register m_respForOtherReq
|
|
reg [2 : 0] m_respForOtherReq;
|
|
wire [2 : 0] m_respForOtherReq$D_IN;
|
|
wire m_respForOtherReq$EN;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
reg m_rqToPQ_clearReq_rl;
|
|
wire m_rqToPQ_clearReq_rl$D_IN, m_rqToPQ_clearReq_rl$EN;
|
|
|
|
// register m_rqToPQ_data_0
|
|
reg [28 : 0] m_rqToPQ_data_0;
|
|
wire [28 : 0] m_rqToPQ_data_0$D_IN;
|
|
wire m_rqToPQ_data_0$EN;
|
|
|
|
// register m_rqToPQ_data_1
|
|
reg [28 : 0] m_rqToPQ_data_1;
|
|
wire [28 : 0] m_rqToPQ_data_1$D_IN;
|
|
wire m_rqToPQ_data_1$EN;
|
|
|
|
// register m_rqToPQ_data_2
|
|
reg [28 : 0] m_rqToPQ_data_2;
|
|
wire [28 : 0] m_rqToPQ_data_2$D_IN;
|
|
wire m_rqToPQ_data_2$EN;
|
|
|
|
// register m_rqToPQ_data_3
|
|
reg [28 : 0] m_rqToPQ_data_3;
|
|
wire [28 : 0] m_rqToPQ_data_3$D_IN;
|
|
wire m_rqToPQ_data_3$EN;
|
|
|
|
// register m_rqToPQ_deqP
|
|
reg [1 : 0] m_rqToPQ_deqP;
|
|
wire [1 : 0] m_rqToPQ_deqP$D_IN;
|
|
wire m_rqToPQ_deqP$EN;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
reg m_rqToPQ_deqReq_rl;
|
|
wire m_rqToPQ_deqReq_rl$D_IN, m_rqToPQ_deqReq_rl$EN;
|
|
|
|
// register m_rqToPQ_empty
|
|
reg m_rqToPQ_empty;
|
|
wire m_rqToPQ_empty$D_IN, m_rqToPQ_empty$EN;
|
|
|
|
// register m_rqToPQ_enqP
|
|
reg [1 : 0] m_rqToPQ_enqP;
|
|
wire [1 : 0] m_rqToPQ_enqP$D_IN;
|
|
wire m_rqToPQ_enqP$EN;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
reg [29 : 0] m_rqToPQ_enqReq_rl;
|
|
wire [29 : 0] m_rqToPQ_enqReq_rl$D_IN;
|
|
wire m_rqToPQ_enqReq_rl$EN;
|
|
|
|
// register m_rqToPQ_full
|
|
reg m_rqToPQ_full;
|
|
wire m_rqToPQ_full$D_IN, m_rqToPQ_full$EN;
|
|
|
|
// register m_tlb_m_entryVec_0
|
|
reg [79 : 0] m_tlb_m_entryVec_0;
|
|
wire [79 : 0] m_tlb_m_entryVec_0$D_IN;
|
|
wire m_tlb_m_entryVec_0$EN;
|
|
|
|
// register m_tlb_m_entryVec_1
|
|
reg [79 : 0] m_tlb_m_entryVec_1;
|
|
wire [79 : 0] m_tlb_m_entryVec_1$D_IN;
|
|
wire m_tlb_m_entryVec_1$EN;
|
|
|
|
// register m_tlb_m_entryVec_10
|
|
reg [79 : 0] m_tlb_m_entryVec_10;
|
|
wire [79 : 0] m_tlb_m_entryVec_10$D_IN;
|
|
wire m_tlb_m_entryVec_10$EN;
|
|
|
|
// register m_tlb_m_entryVec_11
|
|
reg [79 : 0] m_tlb_m_entryVec_11;
|
|
wire [79 : 0] m_tlb_m_entryVec_11$D_IN;
|
|
wire m_tlb_m_entryVec_11$EN;
|
|
|
|
// register m_tlb_m_entryVec_12
|
|
reg [79 : 0] m_tlb_m_entryVec_12;
|
|
wire [79 : 0] m_tlb_m_entryVec_12$D_IN;
|
|
wire m_tlb_m_entryVec_12$EN;
|
|
|
|
// register m_tlb_m_entryVec_13
|
|
reg [79 : 0] m_tlb_m_entryVec_13;
|
|
wire [79 : 0] m_tlb_m_entryVec_13$D_IN;
|
|
wire m_tlb_m_entryVec_13$EN;
|
|
|
|
// register m_tlb_m_entryVec_14
|
|
reg [79 : 0] m_tlb_m_entryVec_14;
|
|
wire [79 : 0] m_tlb_m_entryVec_14$D_IN;
|
|
wire m_tlb_m_entryVec_14$EN;
|
|
|
|
// register m_tlb_m_entryVec_15
|
|
reg [79 : 0] m_tlb_m_entryVec_15;
|
|
wire [79 : 0] m_tlb_m_entryVec_15$D_IN;
|
|
wire m_tlb_m_entryVec_15$EN;
|
|
|
|
// register m_tlb_m_entryVec_16
|
|
reg [79 : 0] m_tlb_m_entryVec_16;
|
|
wire [79 : 0] m_tlb_m_entryVec_16$D_IN;
|
|
wire m_tlb_m_entryVec_16$EN;
|
|
|
|
// register m_tlb_m_entryVec_17
|
|
reg [79 : 0] m_tlb_m_entryVec_17;
|
|
wire [79 : 0] m_tlb_m_entryVec_17$D_IN;
|
|
wire m_tlb_m_entryVec_17$EN;
|
|
|
|
// register m_tlb_m_entryVec_18
|
|
reg [79 : 0] m_tlb_m_entryVec_18;
|
|
wire [79 : 0] m_tlb_m_entryVec_18$D_IN;
|
|
wire m_tlb_m_entryVec_18$EN;
|
|
|
|
// register m_tlb_m_entryVec_19
|
|
reg [79 : 0] m_tlb_m_entryVec_19;
|
|
wire [79 : 0] m_tlb_m_entryVec_19$D_IN;
|
|
wire m_tlb_m_entryVec_19$EN;
|
|
|
|
// register m_tlb_m_entryVec_2
|
|
reg [79 : 0] m_tlb_m_entryVec_2;
|
|
wire [79 : 0] m_tlb_m_entryVec_2$D_IN;
|
|
wire m_tlb_m_entryVec_2$EN;
|
|
|
|
// register m_tlb_m_entryVec_20
|
|
reg [79 : 0] m_tlb_m_entryVec_20;
|
|
wire [79 : 0] m_tlb_m_entryVec_20$D_IN;
|
|
wire m_tlb_m_entryVec_20$EN;
|
|
|
|
// register m_tlb_m_entryVec_21
|
|
reg [79 : 0] m_tlb_m_entryVec_21;
|
|
wire [79 : 0] m_tlb_m_entryVec_21$D_IN;
|
|
wire m_tlb_m_entryVec_21$EN;
|
|
|
|
// register m_tlb_m_entryVec_22
|
|
reg [79 : 0] m_tlb_m_entryVec_22;
|
|
wire [79 : 0] m_tlb_m_entryVec_22$D_IN;
|
|
wire m_tlb_m_entryVec_22$EN;
|
|
|
|
// register m_tlb_m_entryVec_23
|
|
reg [79 : 0] m_tlb_m_entryVec_23;
|
|
wire [79 : 0] m_tlb_m_entryVec_23$D_IN;
|
|
wire m_tlb_m_entryVec_23$EN;
|
|
|
|
// register m_tlb_m_entryVec_24
|
|
reg [79 : 0] m_tlb_m_entryVec_24;
|
|
wire [79 : 0] m_tlb_m_entryVec_24$D_IN;
|
|
wire m_tlb_m_entryVec_24$EN;
|
|
|
|
// register m_tlb_m_entryVec_25
|
|
reg [79 : 0] m_tlb_m_entryVec_25;
|
|
wire [79 : 0] m_tlb_m_entryVec_25$D_IN;
|
|
wire m_tlb_m_entryVec_25$EN;
|
|
|
|
// register m_tlb_m_entryVec_26
|
|
reg [79 : 0] m_tlb_m_entryVec_26;
|
|
wire [79 : 0] m_tlb_m_entryVec_26$D_IN;
|
|
wire m_tlb_m_entryVec_26$EN;
|
|
|
|
// register m_tlb_m_entryVec_27
|
|
reg [79 : 0] m_tlb_m_entryVec_27;
|
|
wire [79 : 0] m_tlb_m_entryVec_27$D_IN;
|
|
wire m_tlb_m_entryVec_27$EN;
|
|
|
|
// register m_tlb_m_entryVec_28
|
|
reg [79 : 0] m_tlb_m_entryVec_28;
|
|
wire [79 : 0] m_tlb_m_entryVec_28$D_IN;
|
|
wire m_tlb_m_entryVec_28$EN;
|
|
|
|
// register m_tlb_m_entryVec_29
|
|
reg [79 : 0] m_tlb_m_entryVec_29;
|
|
wire [79 : 0] m_tlb_m_entryVec_29$D_IN;
|
|
wire m_tlb_m_entryVec_29$EN;
|
|
|
|
// register m_tlb_m_entryVec_3
|
|
reg [79 : 0] m_tlb_m_entryVec_3;
|
|
wire [79 : 0] m_tlb_m_entryVec_3$D_IN;
|
|
wire m_tlb_m_entryVec_3$EN;
|
|
|
|
// register m_tlb_m_entryVec_30
|
|
reg [79 : 0] m_tlb_m_entryVec_30;
|
|
wire [79 : 0] m_tlb_m_entryVec_30$D_IN;
|
|
wire m_tlb_m_entryVec_30$EN;
|
|
|
|
// register m_tlb_m_entryVec_31
|
|
reg [79 : 0] m_tlb_m_entryVec_31;
|
|
wire [79 : 0] m_tlb_m_entryVec_31$D_IN;
|
|
wire m_tlb_m_entryVec_31$EN;
|
|
|
|
// register m_tlb_m_entryVec_4
|
|
reg [79 : 0] m_tlb_m_entryVec_4;
|
|
wire [79 : 0] m_tlb_m_entryVec_4$D_IN;
|
|
wire m_tlb_m_entryVec_4$EN;
|
|
|
|
// register m_tlb_m_entryVec_5
|
|
reg [79 : 0] m_tlb_m_entryVec_5;
|
|
wire [79 : 0] m_tlb_m_entryVec_5$D_IN;
|
|
wire m_tlb_m_entryVec_5$EN;
|
|
|
|
// register m_tlb_m_entryVec_6
|
|
reg [79 : 0] m_tlb_m_entryVec_6;
|
|
wire [79 : 0] m_tlb_m_entryVec_6$D_IN;
|
|
wire m_tlb_m_entryVec_6$EN;
|
|
|
|
// register m_tlb_m_entryVec_7
|
|
reg [79 : 0] m_tlb_m_entryVec_7;
|
|
wire [79 : 0] m_tlb_m_entryVec_7$D_IN;
|
|
wire m_tlb_m_entryVec_7$EN;
|
|
|
|
// register m_tlb_m_entryVec_8
|
|
reg [79 : 0] m_tlb_m_entryVec_8;
|
|
wire [79 : 0] m_tlb_m_entryVec_8$D_IN;
|
|
wire m_tlb_m_entryVec_8$EN;
|
|
|
|
// register m_tlb_m_entryVec_9
|
|
reg [79 : 0] m_tlb_m_entryVec_9;
|
|
wire [79 : 0] m_tlb_m_entryVec_9$D_IN;
|
|
wire m_tlb_m_entryVec_9$EN;
|
|
|
|
// register m_tlb_m_lruBit_rl
|
|
reg [31 : 0] m_tlb_m_lruBit_rl;
|
|
wire [31 : 0] m_tlb_m_lruBit_rl$D_IN;
|
|
wire m_tlb_m_lruBit_rl$EN;
|
|
|
|
// register m_tlb_m_randIdx
|
|
reg [4 : 0] m_tlb_m_randIdx;
|
|
wire [4 : 0] m_tlb_m_randIdx$D_IN;
|
|
wire m_tlb_m_randIdx$EN;
|
|
|
|
// register m_tlb_m_updRepIdx_rl
|
|
reg [5 : 0] m_tlb_m_updRepIdx_rl;
|
|
wire [5 : 0] m_tlb_m_updRepIdx_rl$D_IN;
|
|
wire m_tlb_m_updRepIdx_rl$EN;
|
|
|
|
// register m_tlb_m_validVec_0
|
|
reg m_tlb_m_validVec_0;
|
|
wire m_tlb_m_validVec_0$D_IN, m_tlb_m_validVec_0$EN;
|
|
|
|
// register m_tlb_m_validVec_1
|
|
reg m_tlb_m_validVec_1;
|
|
wire m_tlb_m_validVec_1$D_IN, m_tlb_m_validVec_1$EN;
|
|
|
|
// register m_tlb_m_validVec_10
|
|
reg m_tlb_m_validVec_10;
|
|
wire m_tlb_m_validVec_10$D_IN, m_tlb_m_validVec_10$EN;
|
|
|
|
// register m_tlb_m_validVec_11
|
|
reg m_tlb_m_validVec_11;
|
|
wire m_tlb_m_validVec_11$D_IN, m_tlb_m_validVec_11$EN;
|
|
|
|
// register m_tlb_m_validVec_12
|
|
reg m_tlb_m_validVec_12;
|
|
wire m_tlb_m_validVec_12$D_IN, m_tlb_m_validVec_12$EN;
|
|
|
|
// register m_tlb_m_validVec_13
|
|
reg m_tlb_m_validVec_13;
|
|
wire m_tlb_m_validVec_13$D_IN, m_tlb_m_validVec_13$EN;
|
|
|
|
// register m_tlb_m_validVec_14
|
|
reg m_tlb_m_validVec_14;
|
|
wire m_tlb_m_validVec_14$D_IN, m_tlb_m_validVec_14$EN;
|
|
|
|
// register m_tlb_m_validVec_15
|
|
reg m_tlb_m_validVec_15;
|
|
wire m_tlb_m_validVec_15$D_IN, m_tlb_m_validVec_15$EN;
|
|
|
|
// register m_tlb_m_validVec_16
|
|
reg m_tlb_m_validVec_16;
|
|
wire m_tlb_m_validVec_16$D_IN, m_tlb_m_validVec_16$EN;
|
|
|
|
// register m_tlb_m_validVec_17
|
|
reg m_tlb_m_validVec_17;
|
|
wire m_tlb_m_validVec_17$D_IN, m_tlb_m_validVec_17$EN;
|
|
|
|
// register m_tlb_m_validVec_18
|
|
reg m_tlb_m_validVec_18;
|
|
wire m_tlb_m_validVec_18$D_IN, m_tlb_m_validVec_18$EN;
|
|
|
|
// register m_tlb_m_validVec_19
|
|
reg m_tlb_m_validVec_19;
|
|
wire m_tlb_m_validVec_19$D_IN, m_tlb_m_validVec_19$EN;
|
|
|
|
// register m_tlb_m_validVec_2
|
|
reg m_tlb_m_validVec_2;
|
|
wire m_tlb_m_validVec_2$D_IN, m_tlb_m_validVec_2$EN;
|
|
|
|
// register m_tlb_m_validVec_20
|
|
reg m_tlb_m_validVec_20;
|
|
wire m_tlb_m_validVec_20$D_IN, m_tlb_m_validVec_20$EN;
|
|
|
|
// register m_tlb_m_validVec_21
|
|
reg m_tlb_m_validVec_21;
|
|
wire m_tlb_m_validVec_21$D_IN, m_tlb_m_validVec_21$EN;
|
|
|
|
// register m_tlb_m_validVec_22
|
|
reg m_tlb_m_validVec_22;
|
|
wire m_tlb_m_validVec_22$D_IN, m_tlb_m_validVec_22$EN;
|
|
|
|
// register m_tlb_m_validVec_23
|
|
reg m_tlb_m_validVec_23;
|
|
wire m_tlb_m_validVec_23$D_IN, m_tlb_m_validVec_23$EN;
|
|
|
|
// register m_tlb_m_validVec_24
|
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reg m_tlb_m_validVec_24;
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wire m_tlb_m_validVec_24$D_IN, m_tlb_m_validVec_24$EN;
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// register m_tlb_m_validVec_25
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reg m_tlb_m_validVec_25;
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wire m_tlb_m_validVec_25$D_IN, m_tlb_m_validVec_25$EN;
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// register m_tlb_m_validVec_26
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reg m_tlb_m_validVec_26;
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wire m_tlb_m_validVec_26$D_IN, m_tlb_m_validVec_26$EN;
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// register m_tlb_m_validVec_27
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reg m_tlb_m_validVec_27;
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wire m_tlb_m_validVec_27$D_IN, m_tlb_m_validVec_27$EN;
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// register m_tlb_m_validVec_28
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reg m_tlb_m_validVec_28;
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wire m_tlb_m_validVec_28$D_IN, m_tlb_m_validVec_28$EN;
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// register m_tlb_m_validVec_29
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reg m_tlb_m_validVec_29;
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wire m_tlb_m_validVec_29$D_IN, m_tlb_m_validVec_29$EN;
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// register m_tlb_m_validVec_3
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reg m_tlb_m_validVec_3;
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wire m_tlb_m_validVec_3$D_IN, m_tlb_m_validVec_3$EN;
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// register m_tlb_m_validVec_30
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reg m_tlb_m_validVec_30;
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wire m_tlb_m_validVec_30$D_IN, m_tlb_m_validVec_30$EN;
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// register m_tlb_m_validVec_31
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reg m_tlb_m_validVec_31;
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wire m_tlb_m_validVec_31$D_IN, m_tlb_m_validVec_31$EN;
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// register m_tlb_m_validVec_4
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reg m_tlb_m_validVec_4;
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wire m_tlb_m_validVec_4$D_IN, m_tlb_m_validVec_4$EN;
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// register m_tlb_m_validVec_5
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reg m_tlb_m_validVec_5;
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wire m_tlb_m_validVec_5$D_IN, m_tlb_m_validVec_5$EN;
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// register m_tlb_m_validVec_6
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reg m_tlb_m_validVec_6;
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wire m_tlb_m_validVec_6$D_IN, m_tlb_m_validVec_6$EN;
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// register m_tlb_m_validVec_7
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reg m_tlb_m_validVec_7;
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wire m_tlb_m_validVec_7$D_IN, m_tlb_m_validVec_7$EN;
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// register m_tlb_m_validVec_8
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reg m_tlb_m_validVec_8;
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wire m_tlb_m_validVec_8$D_IN, m_tlb_m_validVec_8$EN;
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// register m_tlb_m_validVec_9
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reg m_tlb_m_validVec_9;
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wire m_tlb_m_validVec_9$D_IN, m_tlb_m_validVec_9$EN;
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// register m_vm_info
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reg [48 : 0] m_vm_info;
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wire [48 : 0] m_vm_info$D_IN;
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wire m_vm_info$EN;
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// register m_waitFlushP
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reg m_waitFlushP;
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wire m_waitFlushP$D_IN, m_waitFlushP$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_doFinishFlush,
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CAN_FIRE_RL_m_doInitFreeQ,
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CAN_FIRE_RL_m_doPRs,
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CAN_FIRE_RL_m_doPoisonedProcResp,
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CAN_FIRE_RL_m_doStartFlush,
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CAN_FIRE_RL_m_flushRqToPQ_canonicalize,
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CAN_FIRE_RL_m_flushRqToPQ_clearReq_canon,
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CAN_FIRE_RL_m_flushRqToPQ_deqReq_canon,
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CAN_FIRE_RL_m_flushRqToPQ_enqReq_canon,
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CAN_FIRE_RL_m_flushRsFromPQ_canonicalize,
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CAN_FIRE_RL_m_flushRsFromPQ_clearReq_canon,
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CAN_FIRE_RL_m_flushRsFromPQ_deqReq_canon,
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CAN_FIRE_RL_m_flushRsFromPQ_enqReq_canon,
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CAN_FIRE_RL_m_freeQ_canonicalize,
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CAN_FIRE_RL_m_freeQ_clearReq_canon,
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CAN_FIRE_RL_m_freeQ_deqReq_canon,
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CAN_FIRE_RL_m_freeQ_enqReq_canon,
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CAN_FIRE_RL_m_ldTransRsFromPQ_canonicalize,
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CAN_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon,
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CAN_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon,
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CAN_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon,
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CAN_FIRE_RL_m_pendSpecBits_0_canon,
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CAN_FIRE_RL_m_pendSpecBits_1_canon,
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CAN_FIRE_RL_m_pendSpecBits_2_canon,
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CAN_FIRE_RL_m_pendSpecBits_3_canon,
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CAN_FIRE_RL_m_pendValid_0_canon,
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CAN_FIRE_RL_m_pendValid_1_canon,
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CAN_FIRE_RL_m_pendValid_2_canon,
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CAN_FIRE_RL_m_pendValid_3_canon,
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CAN_FIRE_RL_m_perfReqQ_canonicalize,
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CAN_FIRE_RL_m_perfReqQ_clearReq_canon,
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CAN_FIRE_RL_m_perfReqQ_deqReq_canon,
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CAN_FIRE_RL_m_perfReqQ_enqReq_canon,
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CAN_FIRE_RL_m_rqToPQ_canonicalize,
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CAN_FIRE_RL_m_rqToPQ_clearReq_canon,
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CAN_FIRE_RL_m_rqToPQ_deqReq_canon,
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CAN_FIRE_RL_m_rqToPQ_enqReq_canon,
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CAN_FIRE_RL_m_tlb_m_doUpdateRep,
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CAN_FIRE_RL_m_tlb_m_incRandIdx,
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CAN_FIRE_RL_m_tlb_m_lruBit_canon,
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CAN_FIRE_RL_m_tlb_m_updRepIdx_canon,
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CAN_FIRE_deqProcResp,
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CAN_FIRE_flush,
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CAN_FIRE_perf_req,
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CAN_FIRE_perf_resp,
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CAN_FIRE_perf_setStatus,
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CAN_FIRE_procReq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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CAN_FIRE_toParent_flush_request_get,
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CAN_FIRE_toParent_flush_response_put,
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CAN_FIRE_toParent_ldTransRsFromP_enq,
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CAN_FIRE_toParent_rqToP_deq,
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CAN_FIRE_updateVMInfo,
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WILL_FIRE_RL_m_doFinishFlush,
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WILL_FIRE_RL_m_doInitFreeQ,
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WILL_FIRE_RL_m_doPRs,
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WILL_FIRE_RL_m_doPoisonedProcResp,
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WILL_FIRE_RL_m_doStartFlush,
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WILL_FIRE_RL_m_flushRqToPQ_canonicalize,
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WILL_FIRE_RL_m_flushRqToPQ_clearReq_canon,
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WILL_FIRE_RL_m_flushRqToPQ_deqReq_canon,
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WILL_FIRE_RL_m_flushRqToPQ_enqReq_canon,
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WILL_FIRE_RL_m_flushRsFromPQ_canonicalize,
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WILL_FIRE_RL_m_flushRsFromPQ_clearReq_canon,
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WILL_FIRE_RL_m_flushRsFromPQ_deqReq_canon,
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WILL_FIRE_RL_m_flushRsFromPQ_enqReq_canon,
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WILL_FIRE_RL_m_freeQ_canonicalize,
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WILL_FIRE_RL_m_freeQ_clearReq_canon,
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WILL_FIRE_RL_m_freeQ_deqReq_canon,
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WILL_FIRE_RL_m_freeQ_enqReq_canon,
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WILL_FIRE_RL_m_ldTransRsFromPQ_canonicalize,
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WILL_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon,
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WILL_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon,
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WILL_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon,
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WILL_FIRE_RL_m_pendSpecBits_0_canon,
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WILL_FIRE_RL_m_pendSpecBits_1_canon,
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WILL_FIRE_RL_m_pendSpecBits_2_canon,
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WILL_FIRE_RL_m_pendSpecBits_3_canon,
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WILL_FIRE_RL_m_pendValid_0_canon,
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WILL_FIRE_RL_m_pendValid_1_canon,
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WILL_FIRE_RL_m_pendValid_2_canon,
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WILL_FIRE_RL_m_pendValid_3_canon,
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WILL_FIRE_RL_m_perfReqQ_canonicalize,
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WILL_FIRE_RL_m_perfReqQ_clearReq_canon,
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WILL_FIRE_RL_m_perfReqQ_deqReq_canon,
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WILL_FIRE_RL_m_perfReqQ_enqReq_canon,
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WILL_FIRE_RL_m_rqToPQ_canonicalize,
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WILL_FIRE_RL_m_rqToPQ_clearReq_canon,
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WILL_FIRE_RL_m_rqToPQ_deqReq_canon,
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WILL_FIRE_RL_m_rqToPQ_enqReq_canon,
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WILL_FIRE_RL_m_tlb_m_doUpdateRep,
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WILL_FIRE_RL_m_tlb_m_incRandIdx,
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WILL_FIRE_RL_m_tlb_m_lruBit_canon,
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WILL_FIRE_RL_m_tlb_m_updRepIdx_canon,
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WILL_FIRE_deqProcResp,
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WILL_FIRE_flush,
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WILL_FIRE_perf_req,
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WILL_FIRE_perf_resp,
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WILL_FIRE_perf_setStatus,
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WILL_FIRE_procReq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_toParent_flush_request_get,
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WILL_FIRE_toParent_flush_response_put,
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WILL_FIRE_toParent_ldTransRsFromP_enq,
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WILL_FIRE_toParent_rqToP_deq,
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WILL_FIRE_updateVMInfo;
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// inputs to muxes for submodule ports
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wire [69 : 0] MUX_m_pendResp_0$write_1__VAL_1,
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MUX_m_pendResp_0$write_1__VAL_2,
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MUX_m_pendResp_1$write_1__VAL_1,
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MUX_m_pendResp_1$write_1__VAL_2,
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MUX_m_pendResp_2$write_1__VAL_1,
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MUX_m_pendResp_2$write_1__VAL_2,
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MUX_m_pendResp_3$write_1__VAL_1,
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MUX_m_pendResp_3$write_1__VAL_2;
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wire [31 : 0] MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1;
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wire [5 : 0] MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1,
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MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2;
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wire [3 : 0] MUX_m_pendWait_0$write_1__VAL_1,
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MUX_m_pendWait_1$write_1__VAL_1,
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MUX_m_pendWait_2$write_1__VAL_1,
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MUX_m_pendWait_3$write_1__VAL_1;
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wire [2 : 0] MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1,
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MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2,
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MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3;
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wire MUX_m_pendPoisoned_0$write_1__SEL_1,
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MUX_m_pendPoisoned_0$write_1__SEL_2,
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MUX_m_pendPoisoned_1$write_1__SEL_1,
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MUX_m_pendPoisoned_1$write_1__SEL_2,
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MUX_m_pendPoisoned_2$write_1__SEL_1,
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MUX_m_pendPoisoned_2$write_1__SEL_2,
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MUX_m_pendPoisoned_3$write_1__SEL_1,
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MUX_m_pendPoisoned_3$write_1__SEL_2,
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MUX_m_pendResp_0$write_1__SEL_1,
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MUX_m_pendResp_1$write_1__SEL_1,
|
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MUX_m_pendResp_2$write_1__SEL_1,
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MUX_m_pendResp_3$write_1__SEL_1,
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MUX_m_pendWait_0$write_1__SEL_1,
|
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MUX_m_pendWait_1$write_1__SEL_1,
|
|
MUX_m_pendWait_2$write_1__SEL_1,
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|
MUX_m_pendWait_3$write_1__SEL_1,
|
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MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1,
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MUX_m_tlb_m_validVec_0$write_1__SEL_1,
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MUX_m_tlb_m_validVec_1$write_1__SEL_1,
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MUX_m_tlb_m_validVec_10$write_1__SEL_1,
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MUX_m_tlb_m_validVec_11$write_1__SEL_1,
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MUX_m_tlb_m_validVec_12$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_13$write_1__SEL_1,
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MUX_m_tlb_m_validVec_14$write_1__SEL_1,
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MUX_m_tlb_m_validVec_15$write_1__SEL_1,
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MUX_m_tlb_m_validVec_16$write_1__SEL_1,
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MUX_m_tlb_m_validVec_17$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_18$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_19$write_1__SEL_1,
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MUX_m_tlb_m_validVec_2$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_20$write_1__SEL_1,
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|
MUX_m_tlb_m_validVec_21$write_1__SEL_1,
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|
MUX_m_tlb_m_validVec_22$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_23$write_1__SEL_1,
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|
MUX_m_tlb_m_validVec_24$write_1__SEL_1,
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|
MUX_m_tlb_m_validVec_25$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_26$write_1__SEL_1,
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|
MUX_m_tlb_m_validVec_27$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_28$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_29$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_3$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_30$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_31$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_4$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_5$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_6$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_7$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_8$write_1__SEL_1,
|
|
MUX_m_tlb_m_validVec_9$write_1__SEL_1,
|
|
MUX_m_waitFlushP$write_1__SEL_1;
|
|
|
|
// remaining internal signals
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|
reg [65 : 0] SEL_ARR_m_pendInst_0_18_BITS_440_TO_375_794_m__ETC___d3227,
|
|
x__h70669;
|
|
reg [64 : 0] x__h105564, x__h105591;
|
|
reg [63 : 0] x__h105527, x__h105582, x__h95343;
|
|
reg [55 : 0] x__h70582, x__h92837;
|
|
reg [43 : 0] CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684,
|
|
ppn__h92833;
|
|
reg [26 : 0] CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q1,
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4,
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13,
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14,
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15,
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q16,
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q17,
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q18,
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q19,
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20,
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21,
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22,
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3,
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23,
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24,
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25,
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q26,
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q27,
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q28,
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q29,
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q30,
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q31,
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q32,
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q5,
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q33,
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q34,
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q6,
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q7,
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q8,
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q9,
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q10,
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q11,
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q12,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730,
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_28_TO_2_850_m_ETC___d3858;
|
|
reg [17 : 0] SEL_ARR_m_pendInst_0_18_BITS_341_TO_324_330_m__ETC___d3335;
|
|
reg [13 : 0] SEL_ARR_m_pendInst_0_18_BITS_374_TO_361_228_m__ETC___d3233,
|
|
x__h102032,
|
|
x__h102041;
|
|
reg [11 : 0] SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3834;
|
|
reg [5 : 0] SEL_ARR_m_pendInst_0_18_BITS_135_TO_130_801_m__ETC___d3806,
|
|
SEL_ARR_m_pendInst_0_18_BITS_276_TO_271_421_m__ETC___d3426,
|
|
SEL_ARR_m_pendInst_0_18_BITS_322_TO_317_342_m__ETC___d3347,
|
|
SEL_ARR_m_pendInst_0_18_BITS_469_TO_464_085_m__ETC___d3090;
|
|
reg [4 : 0] CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q38,
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473,
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521,
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569,
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617,
|
|
SEL_ARR_m_pendInst_0_18_BITS_462_TO_458_103_m__ETC___d3108,
|
|
SEL_ARR_m_pendInst_0_18_BITS_474_TO_470_079_m__ETC___d3084;
|
|
reg [3 : 0] SEL_ARR_m_pendInst_0_18_BITS_360_TO_357_234_m__ETC___d3239,
|
|
SEL_ARR_m_pendInst_0_18_BITS_461_TO_458_109_m__ETC___d3114;
|
|
reg [2 : 0] SEL_ARR_m_pendInst_0_18_BITS_288_TO_286_365_m__ETC___d3370,
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d3072,
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627;
|
|
reg [1 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601,
|
|
SEL_ARR_m_pendInst_0_18_BITS_280_TO_279_395_m__ETC___d3400,
|
|
SEL_ARR_m_pendInst_0_18_BITS_282_TO_281_389_m__ETC___d3394,
|
|
SEL_ARR_m_pendInst_0_18_BITS_343_TO_342_324_m__ETC___d3329,
|
|
SEL_ARR_m_pendWait_0_66_BITS_1_TO_0_309_m_pend_ETC___d1876,
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_1_TO_0_859_m__ETC___d3864,
|
|
idx__h74945,
|
|
level__h38292,
|
|
level__h87878;
|
|
reg CASE_IF_m_respForOtherReq_64_BIT_2_65_THEN_m_r_ETC___d1293,
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q35,
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q36,
|
|
SEL_ARR_0_OR_NOT_m_pendWait_0_66_BITS_3_TO_2_6_ETC___d1887,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3620,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3626,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3632,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3638,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3644,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3650,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3656,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3662,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3668,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3674,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3680,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3686,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3692,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3698,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3704,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3710,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3716,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3722,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3728,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3734,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3740,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3746,
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3752,
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1874,
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1906,
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d2911,
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_m__ETC___d1956,
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_10_ETC___d641,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_9__ETC___d649,
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_265_778_779_NO_ETC___d3787,
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_277_410_411_NO_ETC___d3419,
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101,
|
|
SEL_ARR_NOT_m_pendResp_0_939_BIT_5_957_958_NOT_ETC___d2966,
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d1958,
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_4_51_m_ETC___d709,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_6_58_m_ETC___d661,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741,
|
|
SEL_ARR_m_pendInst_0_18_BIT_0_819_m_pendInst_1_ETC___d3824,
|
|
SEL_ARR_m_pendInst_0_18_BIT_278_404_m_pendInst_ETC___d3409,
|
|
SEL_ARR_m_pendInst_0_18_BIT_283_383_m_pendInst_ETC___d3388,
|
|
SEL_ARR_m_pendInst_0_18_BIT_284_377_m_pendInst_ETC___d3382,
|
|
SEL_ARR_m_pendInst_0_18_BIT_285_371_m_pendInst_ETC___d3376,
|
|
SEL_ARR_m_pendInst_0_18_BIT_323_336_m_pendInst_ETC___d3341,
|
|
SEL_ARR_m_pendInst_0_18_BIT_344_318_m_pendInst_ETC___d3323,
|
|
SEL_ARR_m_pendInst_0_18_BIT_345_306_m_pendInst_ETC___d3311,
|
|
SEL_ARR_m_pendInst_0_18_BIT_346_300_m_pendInst_ETC___d3305,
|
|
SEL_ARR_m_pendInst_0_18_BIT_347_294_m_pendInst_ETC___d3299,
|
|
SEL_ARR_m_pendInst_0_18_BIT_348_288_m_pendInst_ETC___d3293,
|
|
SEL_ARR_m_pendInst_0_18_BIT_349_282_m_pendInst_ETC___d3287,
|
|
SEL_ARR_m_pendInst_0_18_BIT_350_276_m_pendInst_ETC___d3281,
|
|
SEL_ARR_m_pendInst_0_18_BIT_351_270_m_pendInst_ETC___d3275,
|
|
SEL_ARR_m_pendInst_0_18_BIT_352_264_m_pendInst_ETC___d3269,
|
|
SEL_ARR_m_pendInst_0_18_BIT_353_258_m_pendInst_ETC___d3263,
|
|
SEL_ARR_m_pendInst_0_18_BIT_354_252_m_pendInst_ETC___d3257,
|
|
SEL_ARR_m_pendInst_0_18_BIT_355_246_m_pendInst_ETC___d3251,
|
|
SEL_ARR_m_pendInst_0_18_BIT_356_240_m_pendInst_ETC___d3245,
|
|
SEL_ARR_m_pendInst_0_18_BIT_441_221_m_pendInst_ETC___d3226,
|
|
SEL_ARR_m_pendInst_0_18_BIT_442_214_m_pendInst_ETC___d3219,
|
|
SEL_ARR_m_pendInst_0_18_BIT_443_208_m_pendInst_ETC___d3213,
|
|
SEL_ARR_m_pendInst_0_18_BIT_444_201_m_pendInst_ETC___d3206,
|
|
SEL_ARR_m_pendInst_0_18_BIT_445_195_m_pendInst_ETC___d3200,
|
|
SEL_ARR_m_pendInst_0_18_BIT_446_188_m_pendInst_ETC___d3193,
|
|
SEL_ARR_m_pendInst_0_18_BIT_447_182_m_pendInst_ETC___d3187,
|
|
SEL_ARR_m_pendInst_0_18_BIT_448_175_m_pendInst_ETC___d3180,
|
|
SEL_ARR_m_pendInst_0_18_BIT_449_169_m_pendInst_ETC___d3174,
|
|
SEL_ARR_m_pendInst_0_18_BIT_450_162_m_pendInst_ETC___d3167,
|
|
SEL_ARR_m_pendInst_0_18_BIT_451_156_m_pendInst_ETC___d3161,
|
|
SEL_ARR_m_pendInst_0_18_BIT_452_149_m_pendInst_ETC___d3154,
|
|
SEL_ARR_m_pendInst_0_18_BIT_453_143_m_pendInst_ETC___d3148,
|
|
SEL_ARR_m_pendInst_0_18_BIT_454_136_m_pendInst_ETC___d3141,
|
|
SEL_ARR_m_pendInst_0_18_BIT_455_130_m_pendInst_ETC___d3135,
|
|
SEL_ARR_m_pendInst_0_18_BIT_456_123_m_pendInst_ETC___d3128,
|
|
SEL_ARR_m_pendInst_0_18_BIT_457_117_m_pendInst_ETC___d3122,
|
|
SEL_ARR_m_pendInst_0_18_BIT_475_073_m_pendInst_ETC___d3078,
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_0__ETC___d2977,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_11_ETC___d3037,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_12_ETC___d3043,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_13_ETC___d3049,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_15_ETC___d3055,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_1__ETC___d2983,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_2__ETC___d2989,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_3__ETC___d2995,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_4__ETC___d3001,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_5__ETC___d3007,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_6__ETC___d3013,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_7__ETC___d3019,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_8__ETC___d3025,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_9__ETC___d3031,
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808,
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799,
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680,
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716;
|
|
wire [463 : 0] NOT_SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_09_ETC___d3831;
|
|
wire [69 : 0] DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1854,
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2874;
|
|
wire [63 : 0] x__h70573, x__h92828;
|
|
wire [31 : 0] INV_n__read1151__q37,
|
|
n__read__h51151,
|
|
upd__h51178,
|
|
val__h5329,
|
|
x__h5387;
|
|
wire [11 : 0] n__read__h107398,
|
|
n__read__h107529,
|
|
n__read__h107660,
|
|
n__read__h107791,
|
|
upd__h10027,
|
|
upd__h8992,
|
|
upd__h9337,
|
|
upd__h9682;
|
|
wire [8 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_10_36__ETC___d1788;
|
|
wire [5 : 0] SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_9_44_m_ETC___d1787;
|
|
wire [4 : 0] IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2480,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2482,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2484,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2486,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2488,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2490,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2492,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2494,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2496,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2498,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2500,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2502,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2504,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2506,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2508,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3755,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3757,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3759,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3761,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3763,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3765,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3767,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3769,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3771,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3773,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3775,
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3058,
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3060,
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3062,
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3064,
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3066,
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3068,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27,
|
|
IF_m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec__ETC___d1613,
|
|
IF_m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec__ETC___d1614,
|
|
IF_m_tlb_m_validVec_12_23_AND_m_tlb_m_validVec_ETC___d1603,
|
|
IF_m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_ETC___d1598,
|
|
IF_m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_ETC___d1599,
|
|
IF_m_tlb_m_validVec_20_051_AND_m_tlb_m_validVe_ETC___d1595,
|
|
IF_m_tlb_m_validVec_24_115_AND_m_tlb_m_validVe_ETC___d1591,
|
|
IF_m_tlb_m_validVec_24_115_AND_m_tlb_m_validVe_ETC___d1592,
|
|
IF_m_tlb_m_validVec_28_179_AND_m_tlb_m_validVe_ETC___d1588,
|
|
IF_m_tlb_m_validVec_4_95_AND_m_tlb_m_validVec__ETC___d1610,
|
|
IF_m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec__ETC___d1606,
|
|
IF_m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec__ETC___d1607,
|
|
addIdx__h55826,
|
|
addIdx__h60677,
|
|
idx__h87839,
|
|
v__h45598,
|
|
v__h50415,
|
|
v__h51943;
|
|
wire [3 : 0] _dfoo26, _dfoo28, _dfoo30, _dfoo32;
|
|
wire [1 : 0] IF_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70__ETC___d2905,
|
|
_theResult_____2__h13508,
|
|
_theResult_____2__h17468,
|
|
i__h73125,
|
|
i__h94049,
|
|
idx__h37917,
|
|
idx__h74557,
|
|
idx__h95690,
|
|
next_deqP___1__h13697,
|
|
next_deqP___1__h17657,
|
|
v__h13028,
|
|
v__h13179,
|
|
v__h16896,
|
|
v__h17047,
|
|
x_id__h21371;
|
|
wire IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2805,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2813,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2855,
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2862,
|
|
IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2802,
|
|
IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2810,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167,
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172,
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357,
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255,
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d1294,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d1847,
|
|
IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d718,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1935,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1936,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1937,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3839,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3840,
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3841,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2374,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2375,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2376,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2377,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2378,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2379,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2380,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2381,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2382,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2383,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2384,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2385,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2386,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2387,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2388,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2389,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2390,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2391,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2392,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2393,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2394,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2395,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2396,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2397,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2398,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2399,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2400,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2401,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2402,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2403,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_ldTra_ETC___d1291,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1718,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1720,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1722,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1724,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1726,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1728,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1730,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1732,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1734,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1736,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1738,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1740,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1742,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1744,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1746,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1748,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1750,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1752,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1754,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1756,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1758,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1760,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1762,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1764,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1766,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1768,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1770,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1772,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1774,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1776,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1778,
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1780,
|
|
IF_NOT_m_tlb_m_validVec_10_91_92_OR_NOT_m_tlb__ETC___d1271,
|
|
IF_NOT_m_tlb_m_validVec_11_07_08_OR_NOT_m_tlb__ETC___d1269,
|
|
IF_NOT_m_tlb_m_validVec_12_23_24_OR_NOT_m_tlb__ETC___d1267,
|
|
IF_NOT_m_tlb_m_validVec_13_39_40_OR_NOT_m_tlb__ETC___d1265,
|
|
IF_NOT_m_tlb_m_validVec_14_55_56_OR_NOT_m_tlb__ETC___d1263,
|
|
IF_NOT_m_tlb_m_validVec_15_71_72_OR_NOT_m_tlb__ETC___d1261,
|
|
IF_NOT_m_tlb_m_validVec_16_87_88_OR_NOT_m_tlb__ETC___d1259,
|
|
IF_NOT_m_tlb_m_validVec_17_003_004_OR_NOT_m_tl_ETC___d1257,
|
|
IF_NOT_m_tlb_m_validVec_18_019_020_OR_NOT_m_tl_ETC___d1255,
|
|
IF_NOT_m_tlb_m_validVec_19_035_036_OR_NOT_m_tl_ETC___d1253,
|
|
IF_NOT_m_tlb_m_validVec_1_47_48_OR_NOT_m_tlb_m_ETC___d1289,
|
|
IF_NOT_m_tlb_m_validVec_20_051_052_OR_NOT_m_tl_ETC___d1251,
|
|
IF_NOT_m_tlb_m_validVec_21_067_068_OR_NOT_m_tl_ETC___d1249,
|
|
IF_NOT_m_tlb_m_validVec_22_083_084_OR_NOT_m_tl_ETC___d1247,
|
|
IF_NOT_m_tlb_m_validVec_23_099_100_OR_NOT_m_tl_ETC___d1245,
|
|
IF_NOT_m_tlb_m_validVec_24_115_116_OR_NOT_m_tl_ETC___d1243,
|
|
IF_NOT_m_tlb_m_validVec_25_131_132_OR_NOT_m_tl_ETC___d1241,
|
|
IF_NOT_m_tlb_m_validVec_26_147_148_OR_NOT_m_tl_ETC___d1239,
|
|
IF_NOT_m_tlb_m_validVec_27_163_164_OR_NOT_m_tl_ETC___d1237,
|
|
IF_NOT_m_tlb_m_validVec_28_179_180_OR_NOT_m_tl_ETC___d1235,
|
|
IF_NOT_m_tlb_m_validVec_29_195_196_OR_NOT_m_tl_ETC___d1233,
|
|
IF_NOT_m_tlb_m_validVec_2_63_64_OR_NOT_m_tlb_m_ETC___d1287,
|
|
IF_NOT_m_tlb_m_validVec_30_211_212_OR_NOT_m_tl_ETC___d1231,
|
|
IF_NOT_m_tlb_m_validVec_3_79_80_OR_NOT_m_tlb_m_ETC___d1285,
|
|
IF_NOT_m_tlb_m_validVec_4_95_96_OR_NOT_m_tlb_m_ETC___d1283,
|
|
IF_NOT_m_tlb_m_validVec_5_11_12_OR_NOT_m_tlb_m_ETC___d1281,
|
|
IF_NOT_m_tlb_m_validVec_6_27_28_OR_NOT_m_tlb_m_ETC___d1279,
|
|
IF_NOT_m_tlb_m_validVec_7_43_44_OR_NOT_m_tlb_m_ETC___d1277,
|
|
IF_NOT_m_tlb_m_validVec_8_59_60_OR_NOT_m_tlb_m_ETC___d1275,
|
|
IF_NOT_m_tlb_m_validVec_9_75_76_OR_NOT_m_tlb_m_ETC___d1273,
|
|
IF_NOT_procReq_req_BITS_490_TO_488_405_EQ_1_40_ETC___d2815,
|
|
IF_NOT_procReq_req_BITS_490_TO_488_405_EQ_1_40_ETC___d2864,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d1837,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d1845,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d706,
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d716,
|
|
IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134,
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108,
|
|
IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333,
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284,
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291,
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866,
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_m_pendVali_ETC___d45,
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868,
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_m_pendVali_ETC___d52,
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870,
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_m_pendVali_ETC___d59,
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872,
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_m_pendVali_ETC___d66,
|
|
IF_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_ETC___d1333,
|
|
IF_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_ETC___d1346,
|
|
IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493,
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_NOT_SEL__ETC___d1349,
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1793,
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1811,
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1812,
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1814,
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222,
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196,
|
|
IF_m_tlb_m_entryVec_10_94_BITS_1_TO_0_98_EQ_0__ETC___d2132,
|
|
IF_m_tlb_m_entryVec_11_10_BITS_1_TO_0_14_EQ_0__ETC___d2142,
|
|
IF_m_tlb_m_entryVec_12_26_BITS_1_TO_0_30_EQ_0__ETC___d2152,
|
|
IF_m_tlb_m_entryVec_13_42_BITS_1_TO_0_46_EQ_0__ETC___d2162,
|
|
IF_m_tlb_m_entryVec_14_58_BITS_1_TO_0_62_EQ_0__ETC___d2172,
|
|
IF_m_tlb_m_entryVec_15_74_BITS_1_TO_0_78_EQ_0__ETC___d2182,
|
|
IF_m_tlb_m_entryVec_16_90_BITS_1_TO_0_94_EQ_0__ETC___d2192,
|
|
IF_m_tlb_m_entryVec_17_006_BITS_1_TO_0_010_EQ__ETC___d2202,
|
|
IF_m_tlb_m_entryVec_18_022_BITS_1_TO_0_026_EQ__ETC___d2212,
|
|
IF_m_tlb_m_entryVec_19_038_BITS_1_TO_0_042_EQ__ETC___d2222,
|
|
IF_m_tlb_m_entryVec_1_50_BITS_1_TO_0_54_EQ_0_0_ETC___d2042,
|
|
IF_m_tlb_m_entryVec_20_054_BITS_1_TO_0_058_EQ__ETC___d2232,
|
|
IF_m_tlb_m_entryVec_21_070_BITS_1_TO_0_074_EQ__ETC___d2242,
|
|
IF_m_tlb_m_entryVec_22_086_BITS_1_TO_0_090_EQ__ETC___d2252,
|
|
IF_m_tlb_m_entryVec_23_102_BITS_1_TO_0_106_EQ__ETC___d2262,
|
|
IF_m_tlb_m_entryVec_24_118_BITS_1_TO_0_122_EQ__ETC___d2272,
|
|
IF_m_tlb_m_entryVec_25_134_BITS_1_TO_0_138_EQ__ETC___d2282,
|
|
IF_m_tlb_m_entryVec_26_150_BITS_1_TO_0_154_EQ__ETC___d2292,
|
|
IF_m_tlb_m_entryVec_27_166_BITS_1_TO_0_170_EQ__ETC___d2302,
|
|
IF_m_tlb_m_entryVec_28_182_BITS_1_TO_0_186_EQ__ETC___d2312,
|
|
IF_m_tlb_m_entryVec_29_198_BITS_1_TO_0_202_EQ__ETC___d2322,
|
|
IF_m_tlb_m_entryVec_2_66_BITS_1_TO_0_70_EQ_0_0_ETC___d2052,
|
|
IF_m_tlb_m_entryVec_30_214_BITS_1_TO_0_218_EQ__ETC___d2332,
|
|
IF_m_tlb_m_entryVec_31_376_BITS_1_TO_0_380_EQ__ETC___d2342,
|
|
IF_m_tlb_m_entryVec_3_82_BITS_1_TO_0_86_EQ_0_0_ETC___d2062,
|
|
IF_m_tlb_m_entryVec_4_98_BITS_1_TO_0_02_EQ_0_0_ETC___d2072,
|
|
IF_m_tlb_m_entryVec_5_14_BITS_1_TO_0_18_EQ_0_0_ETC___d2082,
|
|
IF_m_tlb_m_entryVec_6_30_BITS_1_TO_0_34_EQ_0_0_ETC___d2092,
|
|
IF_m_tlb_m_entryVec_7_46_BITS_1_TO_0_50_EQ_0_0_ETC___d2102,
|
|
IF_m_tlb_m_entryVec_8_62_BITS_1_TO_0_66_EQ_0_1_ETC___d2112,
|
|
IF_m_tlb_m_entryVec_9_78_BITS_1_TO_0_82_EQ_0_1_ETC___d2122,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17,
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2852,
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2859,
|
|
NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BI_ETC___d707,
|
|
NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_58_ETC___d2806,
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1834,
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1842,
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1361,
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1373,
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715,
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720,
|
|
NOT_m_ldTransRsFromPQ_empty_68_05_AND_NOT_m_pe_ETC___d1331,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1924,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1928,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2950,
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2952,
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1892,
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1900,
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_71__ETC___d2903,
|
|
NOT_m_tlb_m_entryVec_0_25_BITS_79_TO_53_26_EQ__ETC___d744,
|
|
NOT_m_tlb_m_entryVec_10_94_BITS_79_TO_53_95_EQ_ETC___d905,
|
|
NOT_m_tlb_m_entryVec_11_10_BITS_79_TO_53_11_EQ_ETC___d921,
|
|
NOT_m_tlb_m_entryVec_12_26_BITS_79_TO_53_27_EQ_ETC___d937,
|
|
NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d1405,
|
|
NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d953,
|
|
NOT_m_tlb_m_entryVec_14_58_BITS_79_TO_53_59_EQ_ETC___d969,
|
|
NOT_m_tlb_m_entryVec_15_74_BITS_79_TO_53_75_EQ_ETC___d985,
|
|
NOT_m_tlb_m_entryVec_16_90_BITS_79_TO_53_91_EQ_ETC___d1001,
|
|
NOT_m_tlb_m_entryVec_17_006_BITS_79_TO_53_007__ETC___d1017,
|
|
NOT_m_tlb_m_entryVec_18_022_BITS_79_TO_53_023__ETC___d1033,
|
|
NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1049,
|
|
NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1399,
|
|
NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d1417,
|
|
NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d761,
|
|
NOT_m_tlb_m_entryVec_20_054_BITS_79_TO_53_055__ETC___d1065,
|
|
NOT_m_tlb_m_entryVec_21_070_BITS_79_TO_53_071__ETC___d1081,
|
|
NOT_m_tlb_m_entryVec_22_086_BITS_79_TO_53_087__ETC___d1097,
|
|
NOT_m_tlb_m_entryVec_23_102_BITS_79_TO_53_103__ETC___d1113,
|
|
NOT_m_tlb_m_entryVec_24_118_BITS_79_TO_53_119__ETC___d1129,
|
|
NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1145,
|
|
NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1393,
|
|
NOT_m_tlb_m_entryVec_26_150_BITS_79_TO_53_151__ETC___d1161,
|
|
NOT_m_tlb_m_entryVec_27_166_BITS_79_TO_53_167__ETC___d1177,
|
|
NOT_m_tlb_m_entryVec_28_182_BITS_79_TO_53_183__ETC___d1193,
|
|
NOT_m_tlb_m_entryVec_29_198_BITS_79_TO_53_199__ETC___d1209,
|
|
NOT_m_tlb_m_entryVec_2_66_BITS_79_TO_53_67_EQ__ETC___d777,
|
|
NOT_m_tlb_m_entryVec_30_214_BITS_79_TO_53_215__ETC___d1225,
|
|
NOT_m_tlb_m_entryVec_31_376_BITS_79_TO_53_377__ETC___d1387,
|
|
NOT_m_tlb_m_entryVec_3_82_BITS_79_TO_53_83_EQ__ETC___d793,
|
|
NOT_m_tlb_m_entryVec_4_98_BITS_79_TO_53_99_EQ__ETC___d809,
|
|
NOT_m_tlb_m_entryVec_5_14_BITS_79_TO_53_15_EQ__ETC___d825,
|
|
NOT_m_tlb_m_entryVec_6_30_BITS_79_TO_53_31_EQ__ETC___d841,
|
|
NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d1411,
|
|
NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d857,
|
|
NOT_m_tlb_m_entryVec_8_62_BITS_79_TO_53_63_EQ__ETC___d873,
|
|
NOT_m_tlb_m_entryVec_9_78_BITS_79_TO_53_79_EQ__ETC___d889,
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d721,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918,
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_va_ETC___d1561,
|
|
NOT_m_tlb_m_validVec_11_07_08_OR_NOT_m_tlb_m_e_ETC___d1703,
|
|
NOT_m_tlb_m_validVec_13_39_40_OR_NOT_m_tlb_m_e_ETC___d1701,
|
|
NOT_m_tlb_m_validVec_15_71_72_OR_NOT_m_tlb_m_e_ETC___d1699,
|
|
NOT_m_tlb_m_validVec_16_87_88_OR_NOT_m_tlb_m_v_ETC___d1576,
|
|
NOT_m_tlb_m_validVec_17_003_004_OR_NOT_m_tlb_m_ETC___d1697,
|
|
NOT_m_tlb_m_validVec_19_035_036_OR_NOT_m_tlb_m_ETC___d1695,
|
|
NOT_m_tlb_m_validVec_1_47_48_OR_NOT_m_tlb_m_en_ETC___d1713,
|
|
NOT_m_tlb_m_validVec_21_067_068_OR_NOT_m_tlb_m_ETC___d1693,
|
|
NOT_m_tlb_m_validVec_23_099_100_OR_NOT_m_tlb_m_ETC___d1691,
|
|
NOT_m_tlb_m_validVec_24_115_116_OR_NOT_m_tlb_m_ETC___d1583,
|
|
NOT_m_tlb_m_validVec_25_131_132_OR_NOT_m_tlb_m_ETC___d1689,
|
|
NOT_m_tlb_m_validVec_27_163_164_OR_NOT_m_tlb_m_ETC___d1687,
|
|
NOT_m_tlb_m_validVec_29_195_196_OR_NOT_m_tlb_m_ETC___d1685,
|
|
NOT_m_tlb_m_validVec_3_79_80_OR_NOT_m_tlb_m_en_ETC___d1711,
|
|
NOT_m_tlb_m_validVec_5_11_12_OR_NOT_m_tlb_m_en_ETC___d1709,
|
|
NOT_m_tlb_m_validVec_7_43_44_OR_NOT_m_tlb_m_en_ETC___d1707,
|
|
NOT_m_tlb_m_validVec_8_59_60_OR_NOT_m_tlb_m_va_ETC___d1568,
|
|
NOT_m_tlb_m_validVec_9_75_76_OR_NOT_m_tlb_m_en_ETC___d1705,
|
|
NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817,
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d1838,
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2856,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2821,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2822,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2823,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2824,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2869,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2870,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2871,
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2872,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d701,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d713,
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d1849,
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d1296,
|
|
_dfoo1,
|
|
_dfoo11,
|
|
_dfoo13,
|
|
_dfoo15,
|
|
_dfoo25,
|
|
_dfoo27,
|
|
_dfoo29,
|
|
_dfoo3,
|
|
_dfoo31,
|
|
_dfoo49,
|
|
_dfoo5,
|
|
_dfoo51,
|
|
_dfoo53,
|
|
_dfoo55,
|
|
_dfoo57,
|
|
_dfoo59,
|
|
_dfoo61,
|
|
_dfoo63,
|
|
_dfoo7,
|
|
_dfoo9,
|
|
_theResult_____2__h22136,
|
|
m_pendWait_0_66_BITS_1_TO_0_309_EQ_SEL_ARR_m_l_ETC___d1310,
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1308,
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1317,
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1336,
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2888,
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2912,
|
|
m_pendWait_1_73_BITS_1_TO_0_301_EQ_SEL_ARR_m_l_ETC___d1302,
|
|
m_pendWait_1_73_BITS_3_TO_2_74_EQ_0_75_OR_m_pe_ETC___d1306,
|
|
m_pendWait_2_80_BITS_1_TO_0_321_EQ_SEL_ARR_m_l_ETC___d1322,
|
|
m_pendWait_3_87_BITS_1_TO_0_340_EQ_SEL_ARR_m_l_ETC___d1341,
|
|
m_respForOtherReq_64_BIT_2_65_AND_NOT_SEL_ARR__ETC___d1880,
|
|
m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1425,
|
|
m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1550,
|
|
m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_17_ETC___d1440,
|
|
m_tlb_m_validVec_24_115_AND_m_tlb_m_validVec_2_ETC___d1447,
|
|
m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec_9_7_ETC___d1432,
|
|
next_deqP___1__h22325,
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2879,
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2882,
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2886,
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2890,
|
|
procReq_req_BITS_490_TO_488_405_EQ_1_406_OR_pr_ETC___d2866,
|
|
v__h21066,
|
|
v__h21217;
|
|
|
|
// value method flush_done
|
|
assign flush_done = !m_needFlush ;
|
|
assign RDY_flush_done = 1'd1 ;
|
|
|
|
// action method flush
|
|
assign RDY_flush = !m_needFlush ;
|
|
assign CAN_FIRE_flush = !m_needFlush ;
|
|
assign WILL_FIRE_flush = EN_flush ;
|
|
|
|
// action method updateVMInfo
|
|
assign RDY_updateVMInfo = 1'd1 ;
|
|
assign CAN_FIRE_updateVMInfo = 1'd1 ;
|
|
assign WILL_FIRE_updateVMInfo = EN_updateVMInfo ;
|
|
|
|
// value method noPendingReq
|
|
assign noPendingReq =
|
|
!m_pendValid_0_rl && !m_pendValid_1_rl && !m_pendValid_2_rl &&
|
|
!m_pendValid_3_rl ;
|
|
assign RDY_noPendingReq = 1'd1 ;
|
|
|
|
// action method procReq
|
|
assign RDY_procReq =
|
|
!m_freeQ_empty && !m_needFlush && m_ldTransRsFromPQ_empty &&
|
|
!m_rqToPQ_full &&
|
|
m_freeQInited &&
|
|
(!m_vm_info[46] ||
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d721) ;
|
|
assign CAN_FIRE_procReq = RDY_procReq ;
|
|
assign WILL_FIRE_procReq = EN_procReq ;
|
|
|
|
// value method procResp
|
|
assign procResp =
|
|
{ x__h95343,
|
|
!SEL_ARR_NOT_m_pendResp_0_939_BIT_5_957_958_NOT_ETC___d2966,
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_0__ETC___d2977 ?
|
|
5'd0 :
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3068,
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d3072,
|
|
SEL_ARR_m_pendInst_0_18_BIT_475_073_m_pendInst_ETC___d3078,
|
|
SEL_ARR_m_pendInst_0_18_BITS_474_TO_470_079_m__ETC___d3084,
|
|
SEL_ARR_m_pendInst_0_18_BITS_469_TO_464_085_m__ETC___d3090,
|
|
NOT_SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_09_ETC___d3831,
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3834 } ;
|
|
assign RDY_procResp =
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3841 &&
|
|
m_freeQInited ;
|
|
|
|
// action method deqProcResp
|
|
assign RDY_deqProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3841 &&
|
|
m_freeQInited ;
|
|
assign CAN_FIRE_deqProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3841 &&
|
|
m_freeQInited ;
|
|
assign WILL_FIRE_deqProcResp = EN_deqProcResp ;
|
|
|
|
// value method toParent_rqToP_notEmpty
|
|
assign toParent_rqToP_notEmpty = !m_rqToPQ_empty ;
|
|
assign RDY_toParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method toParent_rqToP_deq
|
|
assign RDY_toParent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_rqToP_deq = !m_rqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_rqToP_deq = EN_toParent_rqToP_deq ;
|
|
|
|
// value method toParent_rqToP_first
|
|
assign toParent_rqToP_first =
|
|
{ SEL_ARR_m_rqToPQ_data_0_849_BITS_28_TO_2_850_m_ETC___d3858,
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_1_TO_0_859_m__ETC___d3864 } ;
|
|
assign RDY_toParent_rqToP_first = !m_rqToPQ_empty ;
|
|
|
|
// value method toParent_ldTransRsFromP_notFull
|
|
assign toParent_ldTransRsFromP_notFull = !m_ldTransRsFromPQ_full ;
|
|
assign RDY_toParent_ldTransRsFromP_notFull = 1'd1 ;
|
|
|
|
// action method toParent_ldTransRsFromP_enq
|
|
assign RDY_toParent_ldTransRsFromP_enq = !m_ldTransRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_ldTransRsFromP_enq = !m_ldTransRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_ldTransRsFromP_enq =
|
|
EN_toParent_ldTransRsFromP_enq ;
|
|
|
|
// action method toParent_flush_request_get
|
|
assign RDY_toParent_flush_request_get = !m_flushRqToPQ_empty ;
|
|
assign CAN_FIRE_toParent_flush_request_get = !m_flushRqToPQ_empty ;
|
|
assign WILL_FIRE_toParent_flush_request_get =
|
|
EN_toParent_flush_request_get ;
|
|
|
|
// action method toParent_flush_response_put
|
|
assign RDY_toParent_flush_response_put = !m_flushRsFromPQ_full ;
|
|
assign CAN_FIRE_toParent_flush_response_put = !m_flushRsFromPQ_full ;
|
|
assign WILL_FIRE_toParent_flush_response_put =
|
|
EN_toParent_flush_response_put ;
|
|
|
|
// action method specUpdate_incorrectSpeculation
|
|
assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_incorrectSpeculation =
|
|
EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// action method specUpdate_correctSpeculation
|
|
assign RDY_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_specUpdate_correctSpeculation =
|
|
EN_specUpdate_correctSpeculation ;
|
|
|
|
// action method perf_setStatus
|
|
assign RDY_perf_setStatus = 1'd1 ;
|
|
assign CAN_FIRE_perf_setStatus = 1'd1 ;
|
|
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
|
|
|
|
// action method perf_req
|
|
assign RDY_perf_req = !m_perfReqQ_full ;
|
|
assign CAN_FIRE_perf_req = !m_perfReqQ_full ;
|
|
assign WILL_FIRE_perf_req = EN_perf_req ;
|
|
|
|
// actionvalue method perf_resp
|
|
assign perf_resp = { m_perfReqQ_data_0, 64'd0 } ;
|
|
assign RDY_perf_resp = !m_perfReqQ_empty ;
|
|
assign CAN_FIRE_perf_resp = !m_perfReqQ_empty ;
|
|
assign WILL_FIRE_perf_resp = EN_perf_resp ;
|
|
|
|
// value method perf_respValid
|
|
assign perf_respValid = !m_perfReqQ_empty ;
|
|
assign RDY_perf_respValid = 1'd1 ;
|
|
|
|
// rule RL_m_doStartFlush
|
|
assign CAN_FIRE_RL_m_doStartFlush =
|
|
!m_flushRqToPQ_full && m_needFlush && !m_waitFlushP &&
|
|
!m_pendValid_0_rl &&
|
|
!m_pendValid_1_rl &&
|
|
!m_pendValid_2_rl &&
|
|
!m_pendValid_3_rl ;
|
|
assign WILL_FIRE_RL_m_doStartFlush = CAN_FIRE_RL_m_doStartFlush ;
|
|
|
|
// rule RL_m_doFinishFlush
|
|
assign CAN_FIRE_RL_m_doFinishFlush =
|
|
!m_flushRsFromPQ_empty && m_needFlush && m_waitFlushP ;
|
|
assign WILL_FIRE_RL_m_doFinishFlush = CAN_FIRE_RL_m_doFinishFlush ;
|
|
|
|
// rule RL_m_doInitFreeQ
|
|
assign CAN_FIRE_RL_m_doInitFreeQ = !m_freeQ_full && !m_freeQInited ;
|
|
assign WILL_FIRE_RL_m_doInitFreeQ = CAN_FIRE_RL_m_doInitFreeQ ;
|
|
|
|
// rule RL_m_doPoisonedProcResp
|
|
assign CAN_FIRE_RL_m_doPoisonedProcResp =
|
|
!m_freeQ_full &&
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1937 &&
|
|
m_freeQInited ;
|
|
assign WILL_FIRE_RL_m_doPoisonedProcResp =
|
|
CAN_FIRE_RL_m_doPoisonedProcResp &&
|
|
!EN_specUpdate_incorrectSpeculation &&
|
|
!EN_deqProcResp ;
|
|
|
|
// rule RL_m_tlb_m_doUpdateRep
|
|
assign CAN_FIRE_RL_m_tlb_m_doUpdateRep =
|
|
!CAN_FIRE_RL_m_doStartFlush && m_tlb_m_updRepIdx_rl[5] ;
|
|
assign WILL_FIRE_RL_m_tlb_m_doUpdateRep =
|
|
CAN_FIRE_RL_m_tlb_m_doUpdateRep && !WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// rule RL_m_doPRs
|
|
assign CAN_FIRE_RL_m_doPRs =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_NOT_SEL__ETC___d1349 &&
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign WILL_FIRE_RL_m_doPRs =
|
|
CAN_FIRE_RL_m_doPRs && !WILL_FIRE_RL_m_doStartFlush &&
|
|
!EN_specUpdate_incorrectSpeculation ;
|
|
|
|
// rule RL_m_tlb_m_incRandIdx
|
|
assign CAN_FIRE_RL_m_tlb_m_incRandIdx = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_incRandIdx = 1'd1 ;
|
|
|
|
// rule RL_m_tlb_m_lruBit_canon
|
|
assign CAN_FIRE_RL_m_tlb_m_lruBit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_lruBit_canon = 1'd1 ;
|
|
|
|
// rule RL_m_tlb_m_updRepIdx_canon
|
|
assign CAN_FIRE_RL_m_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_tlb_m_updRepIdx_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_0_canon
|
|
assign CAN_FIRE_RL_m_pendValid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_1_canon
|
|
assign CAN_FIRE_RL_m_pendValid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_2_canon
|
|
assign CAN_FIRE_RL_m_pendValid_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendValid_3_canon
|
|
assign CAN_FIRE_RL_m_pendValid_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendValid_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_0_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_1_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_2_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_2_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_2_canon = 1'd1 ;
|
|
|
|
// rule RL_m_pendSpecBits_3_canon
|
|
assign CAN_FIRE_RL_m_pendSpecBits_3_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pendSpecBits_3_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_canonicalize
|
|
assign CAN_FIRE_RL_m_freeQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_freeQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_freeQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_freeQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldTransRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldTransRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRqToPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_canonicalize
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_flushRsFromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_flushRsFromPQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_m_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_m_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_m_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_pendPoisoned_0$write_1__SEL_1 =
|
|
EN_procReq && idx__h74945 == 2'd0 ;
|
|
assign MUX_m_pendPoisoned_0$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_1$write_1__SEL_1 =
|
|
EN_procReq && idx__h74945 == 2'd1 ;
|
|
assign MUX_m_pendPoisoned_1$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_2$write_1__SEL_1 =
|
|
EN_procReq && idx__h74945 == 2'd2 ;
|
|
assign MUX_m_pendPoisoned_2$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_2_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendPoisoned_3$write_1__SEL_1 =
|
|
EN_procReq && idx__h74945 == 2'd3 ;
|
|
assign MUX_m_pendPoisoned_3$write_1__SEL_2 =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
m_pendSpecBits_3_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign MUX_m_pendResp_0$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo15 ;
|
|
assign MUX_m_pendResp_1$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo13 ;
|
|
assign MUX_m_pendResp_2$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo11 ;
|
|
assign MUX_m_pendResp_3$write_1__SEL_1 = WILL_FIRE_RL_m_doPRs && _dfoo9 ;
|
|
assign MUX_m_pendWait_0$write_1__SEL_1 = EN_procReq && _dfoo63 ;
|
|
assign MUX_m_pendWait_1$write_1__SEL_1 = EN_procReq && _dfoo61 ;
|
|
assign MUX_m_pendWait_2$write_1__SEL_1 = EN_procReq && _dfoo59 ;
|
|
assign MUX_m_pendWait_3$write_1__SEL_1 = EN_procReq && _dfoo57 ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign MUX_m_tlb_m_validVec_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1718 ;
|
|
assign MUX_m_tlb_m_validVec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1720 ;
|
|
assign MUX_m_tlb_m_validVec_10$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1738 ;
|
|
assign MUX_m_tlb_m_validVec_11$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1740 ;
|
|
assign MUX_m_tlb_m_validVec_12$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1742 ;
|
|
assign MUX_m_tlb_m_validVec_13$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1744 ;
|
|
assign MUX_m_tlb_m_validVec_14$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1746 ;
|
|
assign MUX_m_tlb_m_validVec_15$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1748 ;
|
|
assign MUX_m_tlb_m_validVec_16$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1750 ;
|
|
assign MUX_m_tlb_m_validVec_17$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1752 ;
|
|
assign MUX_m_tlb_m_validVec_18$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1754 ;
|
|
assign MUX_m_tlb_m_validVec_19$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1756 ;
|
|
assign MUX_m_tlb_m_validVec_2$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1722 ;
|
|
assign MUX_m_tlb_m_validVec_20$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1758 ;
|
|
assign MUX_m_tlb_m_validVec_21$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1760 ;
|
|
assign MUX_m_tlb_m_validVec_22$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1762 ;
|
|
assign MUX_m_tlb_m_validVec_23$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1764 ;
|
|
assign MUX_m_tlb_m_validVec_24$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1766 ;
|
|
assign MUX_m_tlb_m_validVec_25$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1768 ;
|
|
assign MUX_m_tlb_m_validVec_26$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1770 ;
|
|
assign MUX_m_tlb_m_validVec_27$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1772 ;
|
|
assign MUX_m_tlb_m_validVec_28$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1774 ;
|
|
assign MUX_m_tlb_m_validVec_29$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1776 ;
|
|
assign MUX_m_tlb_m_validVec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1724 ;
|
|
assign MUX_m_tlb_m_validVec_30$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1778 ;
|
|
assign MUX_m_tlb_m_validVec_31$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1780 ;
|
|
assign MUX_m_tlb_m_validVec_4$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1726 ;
|
|
assign MUX_m_tlb_m_validVec_5$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1728 ;
|
|
assign MUX_m_tlb_m_validVec_6$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1730 ;
|
|
assign MUX_m_tlb_m_validVec_7$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1732 ;
|
|
assign MUX_m_tlb_m_validVec_8$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1734 ;
|
|
assign MUX_m_tlb_m_validVec_9$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1736 ;
|
|
assign MUX_m_waitFlushP$write_1__SEL_1 =
|
|
WILL_FIRE_RL_m_doFinishFlush || EN_flush ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, m_freeQInitIdx } ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, idx__h74557 } ;
|
|
assign MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, idx__h95690 } ;
|
|
assign MUX_m_pendResp_0$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1793 ?
|
|
{ x__h70573, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1854 ;
|
|
assign MUX_m_pendResp_0$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2821 ?
|
|
{ x__h92828, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2869 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2874 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendResp_1$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1811 ?
|
|
{ x__h70573, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1854 ;
|
|
assign MUX_m_pendResp_1$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2822 ?
|
|
{ x__h92828, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2870 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2874 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendResp_2$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1812 ?
|
|
{ x__h70573, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1854 ;
|
|
assign MUX_m_pendResp_2$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2823 ?
|
|
{ x__h92828, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2871 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2874 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendResp_3$write_1__VAL_1 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1814 ?
|
|
{ x__h70573, 6'd10 } :
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1854 ;
|
|
assign MUX_m_pendResp_3$write_1__VAL_2 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2824 ?
|
|
{ x__h92828, 6'd10 } :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2872 ?
|
|
DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2874 :
|
|
{ procReq_req[450:387], 6'd10 }) ;
|
|
assign MUX_m_pendWait_0$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2821 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2869 ?
|
|
4'd2 :
|
|
_dfoo32) ;
|
|
assign MUX_m_pendWait_1$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2822 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2870 ?
|
|
4'd2 :
|
|
_dfoo30) ;
|
|
assign MUX_m_pendWait_2$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2823 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2871 ?
|
|
4'd2 :
|
|
_dfoo28) ;
|
|
assign MUX_m_pendWait_3$write_1__VAL_1 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2824 ?
|
|
4'd2 :
|
|
(SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2872 ?
|
|
4'd2 :
|
|
_dfoo26) ;
|
|
assign MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1 =
|
|
(val__h5329 == 32'hFFFFFFFF) ? x__h5387 : val__h5329 ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 = { 1'd1, v__h45598 } ;
|
|
assign MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 = { 1'd1, idx__h87839 } ;
|
|
|
|
// inlined wires
|
|
assign m_tlb_m_lruBit_lat_0$whas =
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep || WILL_FIRE_RL_m_doStartFlush ;
|
|
assign m_tlb_m_updRepIdx_lat_0$whas =
|
|
WILL_FIRE_RL_m_doStartFlush || WILL_FIRE_RL_m_tlb_m_doUpdateRep ;
|
|
assign m_tlb_m_updRepIdx_lat_1$wget =
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__SEL_1 ?
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_1 :
|
|
MUX_m_tlb_m_updRepIdx_lat_1$wset_1__VAL_2 ;
|
|
assign m_tlb_m_updRepIdx_lat_1$whas =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ||
|
|
EN_procReq && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817 ;
|
|
assign m_pendValid_0_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h74557 == 2'd0 ||
|
|
EN_deqProcResp && idx__h95690 == 2'd0 ;
|
|
assign m_pendValid_1_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h74557 == 2'd1 ||
|
|
EN_deqProcResp && idx__h95690 == 2'd1 ;
|
|
assign m_pendValid_2_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h74557 == 2'd2 ||
|
|
EN_deqProcResp && idx__h95690 == 2'd2 ;
|
|
assign m_pendValid_3_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPoisonedProcResp && idx__h74557 == 2'd3 ||
|
|
EN_deqProcResp && idx__h95690 == 2'd3 ;
|
|
always@(WILL_FIRE_RL_m_doInitFreeQ or
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1 or
|
|
WILL_FIRE_RL_m_doPoisonedProcResp or
|
|
MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2 or
|
|
EN_deqProcResp or MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_m_doInitFreeQ:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_1;
|
|
WILL_FIRE_RL_m_doPoisonedProcResp:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_2;
|
|
EN_deqProcResp:
|
|
m_freeQ_enqReq_lat_0$wget = MUX_m_freeQ_enqReq_lat_0$wset_1__VAL_3;
|
|
default: m_freeQ_enqReq_lat_0$wget = 3'b010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign m_freeQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_doInitFreeQ ||
|
|
WILL_FIRE_RL_m_doPoisonedProcResp ||
|
|
EN_deqProcResp ;
|
|
assign m_rqToPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, procReq_req[425:399], idx__h74945 } ;
|
|
assign m_rqToPQ_enqReq_lat_0$whas =
|
|
EN_procReq && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918 ;
|
|
assign m_ldTransRsFromPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, toParent_ldTransRsFromP_enq_x } ;
|
|
assign m_ldTransRsFromPQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1336 &&
|
|
(m_pendWait_3[3:2] == 2'd0 || m_pendWait_3[3:2] == 2'd1 ||
|
|
!m_pendWait_3_87_BITS_1_TO_0_340_EQ_SEL_ARR_m_l_ETC___d1341 ||
|
|
idx__h37917 == 2'd3) ;
|
|
assign m_perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
|
|
|
|
// register m_flushRqToPQ_clearReq_rl
|
|
assign m_flushRqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_deqReq_rl
|
|
assign m_flushRqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_empty
|
|
assign m_flushRqToPQ_empty$D_IN =
|
|
m_flushRqToPQ_clearReq_rl ||
|
|
!CAN_FIRE_RL_m_doStartFlush && !m_flushRqToPQ_enqReq_rl &&
|
|
(EN_toParent_flush_request_get || m_flushRqToPQ_deqReq_rl ||
|
|
m_flushRqToPQ_empty) ;
|
|
assign m_flushRqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_enqReq_rl
|
|
assign m_flushRqToPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRqToPQ_full
|
|
assign m_flushRqToPQ_full$D_IN =
|
|
!m_flushRqToPQ_clearReq_rl &&
|
|
(CAN_FIRE_RL_m_doStartFlush || m_flushRqToPQ_enqReq_rl ||
|
|
!EN_toParent_flush_request_get && !m_flushRqToPQ_deqReq_rl &&
|
|
m_flushRqToPQ_full) ;
|
|
assign m_flushRqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_clearReq_rl
|
|
assign m_flushRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_deqReq_rl
|
|
assign m_flushRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_empty
|
|
assign m_flushRsFromPQ_empty$D_IN =
|
|
m_flushRsFromPQ_clearReq_rl ||
|
|
!EN_toParent_flush_response_put && !m_flushRsFromPQ_enqReq_rl &&
|
|
(CAN_FIRE_RL_m_doFinishFlush || m_flushRsFromPQ_deqReq_rl ||
|
|
m_flushRsFromPQ_empty) ;
|
|
assign m_flushRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_enqReq_rl
|
|
assign m_flushRsFromPQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign m_flushRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_flushRsFromPQ_full
|
|
assign m_flushRsFromPQ_full$D_IN =
|
|
!m_flushRsFromPQ_clearReq_rl &&
|
|
(EN_toParent_flush_response_put || m_flushRsFromPQ_enqReq_rl ||
|
|
!CAN_FIRE_RL_m_doFinishFlush && !m_flushRsFromPQ_deqReq_rl &&
|
|
m_flushRsFromPQ_full) ;
|
|
assign m_flushRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_freeQInitIdx
|
|
assign m_freeQInitIdx$D_IN = m_freeQInitIdx + 2'd1 ;
|
|
assign m_freeQInitIdx$EN = CAN_FIRE_RL_m_doInitFreeQ ;
|
|
|
|
// register m_freeQInited
|
|
assign m_freeQInited$D_IN = 1'd1 ;
|
|
assign m_freeQInited$EN =
|
|
WILL_FIRE_RL_m_doInitFreeQ && m_freeQInitIdx == 2'd3 ;
|
|
|
|
// register m_freeQ_clearReq_rl
|
|
assign m_freeQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_freeQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_data_0
|
|
assign m_freeQ_data_0$D_IN =
|
|
m_freeQ_enqReq_lat_0$whas ?
|
|
m_freeQ_enqReq_lat_0$wget[1:0] :
|
|
m_freeQ_enqReq_rl[1:0] ;
|
|
assign m_freeQ_data_0$EN =
|
|
m_freeQ_enqP == 2'd0 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_1
|
|
assign m_freeQ_data_1$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_1$EN =
|
|
m_freeQ_enqP == 2'd1 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_2
|
|
assign m_freeQ_data_2$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_2$EN =
|
|
m_freeQ_enqP == 2'd2 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_data_3
|
|
assign m_freeQ_data_3$D_IN = m_freeQ_data_0$D_IN ;
|
|
assign m_freeQ_data_3$EN =
|
|
m_freeQ_enqP == 2'd3 && !m_freeQ_clearReq_rl &&
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ;
|
|
|
|
// register m_freeQ_deqP
|
|
assign m_freeQ_deqP$D_IN =
|
|
m_freeQ_clearReq_rl ? 2'd0 : _theResult_____2__h13508 ;
|
|
assign m_freeQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_deqReq_rl
|
|
assign m_freeQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_freeQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_empty
|
|
assign m_freeQ_empty$D_IN =
|
|
m_freeQ_clearReq_rl ||
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172 ;
|
|
assign m_freeQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_enqP
|
|
assign m_freeQ_enqP$D_IN = m_freeQ_clearReq_rl ? 2'd0 : v__h13028 ;
|
|
assign m_freeQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_enqReq_rl
|
|
assign m_freeQ_enqReq_rl$D_IN = 3'b010 ;
|
|
assign m_freeQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_freeQ_full
|
|
assign m_freeQ_full$D_IN =
|
|
!m_freeQ_clearReq_rl &&
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167 ;
|
|
assign m_freeQ_full$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_clearReq_rl
|
|
assign m_ldTransRsFromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_ldTransRsFromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_data_0
|
|
assign m_ldTransRsFromPQ_data_0$D_IN =
|
|
{ IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 ||
|
|
(EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[82] :
|
|
m_ldTransRsFromPQ_enqReq_rl[82]),
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[81:2] :
|
|
m_ldTransRsFromPQ_enqReq_rl[81:2],
|
|
x_id__h21371 } ;
|
|
assign m_ldTransRsFromPQ_data_0$EN =
|
|
m_ldTransRsFromPQ_enqP == 1'd0 &&
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ;
|
|
|
|
// register m_ldTransRsFromPQ_data_1
|
|
assign m_ldTransRsFromPQ_data_1$D_IN = m_ldTransRsFromPQ_data_0$D_IN ;
|
|
assign m_ldTransRsFromPQ_data_1$EN =
|
|
m_ldTransRsFromPQ_enqP == 1'd1 &&
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ;
|
|
|
|
// register m_ldTransRsFromPQ_deqP
|
|
assign m_ldTransRsFromPQ_deqP$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl && _theResult_____2__h22136 ;
|
|
assign m_ldTransRsFromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_deqReq_rl
|
|
assign m_ldTransRsFromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_ldTransRsFromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_empty
|
|
assign m_ldTransRsFromPQ_empty$D_IN =
|
|
m_ldTransRsFromPQ_clearReq_rl ||
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 &&
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 &&
|
|
(IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 ||
|
|
m_ldTransRsFromPQ_empty) ;
|
|
assign m_ldTransRsFromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_enqP
|
|
assign m_ldTransRsFromPQ_enqP$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl && v__h21066 ;
|
|
assign m_ldTransRsFromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_enqReq_rl
|
|
assign m_ldTransRsFromPQ_enqReq_rl$D_IN = 84'h2AAAAAAAAAAAAAAAAAAAA ;
|
|
assign m_ldTransRsFromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_ldTransRsFromPQ_full
|
|
assign m_ldTransRsFromPQ_full$D_IN =
|
|
!m_ldTransRsFromPQ_clearReq_rl &&
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366 ;
|
|
assign m_ldTransRsFromPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_needFlush
|
|
assign m_needFlush$D_IN = !WILL_FIRE_RL_m_doFinishFlush ;
|
|
assign m_needFlush$EN = MUX_m_waitFlushP$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_0
|
|
assign m_pendInst_0$D_IN = m_pendInst_1$D_IN ;
|
|
assign m_pendInst_0$EN = MUX_m_pendPoisoned_0$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_1
|
|
assign m_pendInst_1$D_IN =
|
|
{ procReq_req[490:283],
|
|
CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q38,
|
|
procReq_req[277:12] } ;
|
|
assign m_pendInst_1$EN = MUX_m_pendPoisoned_1$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_2
|
|
assign m_pendInst_2$D_IN = m_pendInst_1$D_IN ;
|
|
assign m_pendInst_2$EN = MUX_m_pendPoisoned_2$write_1__SEL_1 ;
|
|
|
|
// register m_pendInst_3
|
|
assign m_pendInst_3$D_IN = m_pendInst_1$D_IN ;
|
|
assign m_pendInst_3$EN = MUX_m_pendPoisoned_3$write_1__SEL_1 ;
|
|
|
|
// register m_pendPoisoned_0
|
|
assign m_pendPoisoned_0$D_IN = !MUX_m_pendPoisoned_0$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_0$EN =
|
|
EN_procReq && idx__h74945 == 2'd0 ||
|
|
MUX_m_pendPoisoned_0$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_1
|
|
assign m_pendPoisoned_1$D_IN = !MUX_m_pendPoisoned_1$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_1$EN =
|
|
EN_procReq && idx__h74945 == 2'd1 ||
|
|
MUX_m_pendPoisoned_1$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_2
|
|
assign m_pendPoisoned_2$D_IN = !MUX_m_pendPoisoned_2$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_2$EN =
|
|
EN_procReq && idx__h74945 == 2'd2 ||
|
|
MUX_m_pendPoisoned_2$write_1__SEL_2 ;
|
|
|
|
// register m_pendPoisoned_3
|
|
assign m_pendPoisoned_3$D_IN = !MUX_m_pendPoisoned_3$write_1__SEL_1 ;
|
|
assign m_pendPoisoned_3$EN =
|
|
EN_procReq && idx__h74945 == 2'd3 ||
|
|
MUX_m_pendPoisoned_3$write_1__SEL_2 ;
|
|
|
|
// register m_pendResp_0
|
|
assign m_pendResp_0$D_IN =
|
|
MUX_m_pendResp_0$write_1__SEL_1 ?
|
|
MUX_m_pendResp_0$write_1__VAL_1 :
|
|
MUX_m_pendResp_0$write_1__VAL_2 ;
|
|
assign m_pendResp_0$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo15 || EN_procReq && _dfoo55 ;
|
|
|
|
// register m_pendResp_1
|
|
assign m_pendResp_1$D_IN =
|
|
MUX_m_pendResp_1$write_1__SEL_1 ?
|
|
MUX_m_pendResp_1$write_1__VAL_1 :
|
|
MUX_m_pendResp_1$write_1__VAL_2 ;
|
|
assign m_pendResp_1$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo13 || EN_procReq && _dfoo53 ;
|
|
|
|
// register m_pendResp_2
|
|
assign m_pendResp_2$D_IN =
|
|
MUX_m_pendResp_2$write_1__SEL_1 ?
|
|
MUX_m_pendResp_2$write_1__VAL_1 :
|
|
MUX_m_pendResp_2$write_1__VAL_2 ;
|
|
assign m_pendResp_2$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo11 || EN_procReq && _dfoo51 ;
|
|
|
|
// register m_pendResp_3
|
|
assign m_pendResp_3$D_IN =
|
|
MUX_m_pendResp_3$write_1__SEL_1 ?
|
|
MUX_m_pendResp_3$write_1__VAL_1 :
|
|
MUX_m_pendResp_3$write_1__VAL_2 ;
|
|
assign m_pendResp_3$EN =
|
|
WILL_FIRE_RL_m_doPRs && _dfoo9 || EN_procReq && _dfoo49 ;
|
|
|
|
// register m_pendSpecBits_0_rl
|
|
assign m_pendSpecBits_0_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h8992 :
|
|
n__read__h107398 ;
|
|
assign m_pendSpecBits_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_1_rl
|
|
assign m_pendSpecBits_1_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h9337 :
|
|
n__read__h107529 ;
|
|
assign m_pendSpecBits_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_2_rl
|
|
assign m_pendSpecBits_2_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h9682 :
|
|
n__read__h107660 ;
|
|
assign m_pendSpecBits_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendSpecBits_3_rl
|
|
assign m_pendSpecBits_3_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h10027 :
|
|
n__read__h107791 ;
|
|
assign m_pendSpecBits_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_0_rl
|
|
assign m_pendValid_0_rl$D_IN =
|
|
MUX_m_pendPoisoned_0$write_1__SEL_1 ||
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_m_pendVali_ETC___d45 ;
|
|
assign m_pendValid_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_1_rl
|
|
assign m_pendValid_1_rl$D_IN =
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1 ||
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_m_pendVali_ETC___d52 ;
|
|
assign m_pendValid_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_2_rl
|
|
assign m_pendValid_2_rl$D_IN =
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1 ||
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_m_pendVali_ETC___d59 ;
|
|
assign m_pendValid_2_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendValid_3_rl
|
|
assign m_pendValid_3_rl$D_IN =
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1 ||
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_m_pendVali_ETC___d66 ;
|
|
assign m_pendValid_3_rl$EN = 1'd1 ;
|
|
|
|
// register m_pendWait_0
|
|
assign m_pendWait_0$D_IN =
|
|
MUX_m_pendWait_0$write_1__SEL_1 ?
|
|
MUX_m_pendWait_0$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_0$EN =
|
|
EN_procReq && _dfoo63 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd0 ;
|
|
|
|
// register m_pendWait_1
|
|
assign m_pendWait_1$D_IN =
|
|
MUX_m_pendWait_1$write_1__SEL_1 ?
|
|
MUX_m_pendWait_1$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_1$EN =
|
|
EN_procReq && _dfoo61 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd1 ;
|
|
|
|
// register m_pendWait_2
|
|
assign m_pendWait_2$D_IN =
|
|
MUX_m_pendWait_2$write_1__SEL_1 ?
|
|
MUX_m_pendWait_2$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_2$EN =
|
|
EN_procReq && _dfoo59 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd2 ;
|
|
|
|
// register m_pendWait_3
|
|
assign m_pendWait_3$D_IN =
|
|
MUX_m_pendWait_3$write_1__SEL_1 ?
|
|
MUX_m_pendWait_3$write_1__VAL_1 :
|
|
4'd2 ;
|
|
assign m_pendWait_3$EN =
|
|
EN_procReq && _dfoo57 ||
|
|
WILL_FIRE_RL_m_doPRs && idx__h37917 == 2'd3 ;
|
|
|
|
// register m_perfReqQ_clearReq_rl
|
|
assign m_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_data_0
|
|
assign m_perfReqQ_data_0$D_IN =
|
|
EN_perf_req ?
|
|
m_perfReqQ_enqReq_lat_0$wget[2:0] :
|
|
m_perfReqQ_enqReq_rl[2:0] ;
|
|
assign m_perfReqQ_data_0$EN =
|
|
!m_perfReqQ_clearReq_rl &&
|
|
IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 ;
|
|
|
|
// register m_perfReqQ_deqReq_rl
|
|
assign m_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_empty
|
|
assign m_perfReqQ_empty$D_IN =
|
|
m_perfReqQ_clearReq_rl ||
|
|
(EN_perf_req ?
|
|
!m_perfReqQ_enqReq_lat_0$wget[3] :
|
|
!m_perfReqQ_enqReq_rl[3]) &&
|
|
(EN_perf_resp || m_perfReqQ_deqReq_rl || m_perfReqQ_empty) ;
|
|
assign m_perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_enqReq_rl
|
|
assign m_perfReqQ_enqReq_rl$D_IN = 4'b0010 ;
|
|
assign m_perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_perfReqQ_full
|
|
assign m_perfReqQ_full$D_IN =
|
|
!m_perfReqQ_clearReq_rl &&
|
|
(IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 ||
|
|
!EN_perf_resp && !m_perfReqQ_deqReq_rl && m_perfReqQ_full) ;
|
|
assign m_perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register m_respForOtherReq
|
|
assign m_respForOtherReq$D_IN =
|
|
{ NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1900,
|
|
i__h73125 } ;
|
|
assign m_respForOtherReq$EN = WILL_FIRE_RL_m_doPRs ;
|
|
|
|
// register m_rqToPQ_clearReq_rl
|
|
assign m_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_data_0
|
|
assign m_rqToPQ_data_0$D_IN =
|
|
m_rqToPQ_enqReq_lat_0$whas ?
|
|
m_rqToPQ_enqReq_lat_0$wget[28:0] :
|
|
m_rqToPQ_enqReq_rl[28:0] ;
|
|
assign m_rqToPQ_data_0$EN =
|
|
m_rqToPQ_enqP == 2'd0 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_1
|
|
assign m_rqToPQ_data_1$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_1$EN =
|
|
m_rqToPQ_enqP == 2'd1 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_2
|
|
assign m_rqToPQ_data_2$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_2$EN =
|
|
m_rqToPQ_enqP == 2'd2 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_data_3
|
|
assign m_rqToPQ_data_3$D_IN = m_rqToPQ_data_0$D_IN ;
|
|
assign m_rqToPQ_data_3$EN =
|
|
m_rqToPQ_enqP == 2'd3 && !m_rqToPQ_clearReq_rl &&
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ;
|
|
|
|
// register m_rqToPQ_deqP
|
|
assign m_rqToPQ_deqP$D_IN =
|
|
m_rqToPQ_clearReq_rl ? 2'd0 : _theResult_____2__h17468 ;
|
|
assign m_rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_deqReq_rl
|
|
assign m_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign m_rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_empty
|
|
assign m_rqToPQ_empty$D_IN =
|
|
m_rqToPQ_clearReq_rl ||
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260 ;
|
|
assign m_rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqP
|
|
assign m_rqToPQ_enqP$D_IN = m_rqToPQ_clearReq_rl ? 2'd0 : v__h16896 ;
|
|
assign m_rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_enqReq_rl
|
|
assign m_rqToPQ_enqReq_rl$D_IN = 30'b001010101010101010101010101010 ;
|
|
assign m_rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register m_rqToPQ_full
|
|
assign m_rqToPQ_full$D_IN =
|
|
!m_rqToPQ_clearReq_rl &&
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255 ;
|
|
assign m_rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_entryVec_0
|
|
assign m_tlb_m_entryVec_0$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_0$EN = MUX_m_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_1
|
|
assign m_tlb_m_entryVec_1$D_IN =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_10_36__ETC___d1788 } ;
|
|
assign m_tlb_m_entryVec_1$EN = MUX_m_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_10
|
|
assign m_tlb_m_entryVec_10$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_10$EN = MUX_m_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_11
|
|
assign m_tlb_m_entryVec_11$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_11$EN = MUX_m_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_12
|
|
assign m_tlb_m_entryVec_12$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_12$EN = MUX_m_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_13
|
|
assign m_tlb_m_entryVec_13$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_13$EN = MUX_m_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_14
|
|
assign m_tlb_m_entryVec_14$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_14$EN = MUX_m_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_15
|
|
assign m_tlb_m_entryVec_15$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_15$EN = MUX_m_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_16
|
|
assign m_tlb_m_entryVec_16$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_16$EN = MUX_m_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_17
|
|
assign m_tlb_m_entryVec_17$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_17$EN = MUX_m_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_18
|
|
assign m_tlb_m_entryVec_18$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_18$EN = MUX_m_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_19
|
|
assign m_tlb_m_entryVec_19$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_19$EN = MUX_m_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_2
|
|
assign m_tlb_m_entryVec_2$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_2$EN = MUX_m_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_20
|
|
assign m_tlb_m_entryVec_20$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_20$EN = MUX_m_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_21
|
|
assign m_tlb_m_entryVec_21$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_21$EN = MUX_m_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_22
|
|
assign m_tlb_m_entryVec_22$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_22$EN = MUX_m_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_23
|
|
assign m_tlb_m_entryVec_23$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_23$EN = MUX_m_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_24
|
|
assign m_tlb_m_entryVec_24$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_24$EN = MUX_m_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_25
|
|
assign m_tlb_m_entryVec_25$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_25$EN = MUX_m_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_26
|
|
assign m_tlb_m_entryVec_26$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_26$EN = MUX_m_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_27
|
|
assign m_tlb_m_entryVec_27$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_27$EN = MUX_m_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_28
|
|
assign m_tlb_m_entryVec_28$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_28$EN = MUX_m_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_29
|
|
assign m_tlb_m_entryVec_29$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_29$EN = MUX_m_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_3
|
|
assign m_tlb_m_entryVec_3$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_3$EN = MUX_m_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_30
|
|
assign m_tlb_m_entryVec_30$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_30$EN = MUX_m_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_31
|
|
assign m_tlb_m_entryVec_31$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_31$EN = MUX_m_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_4
|
|
assign m_tlb_m_entryVec_4$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_4$EN = MUX_m_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_5
|
|
assign m_tlb_m_entryVec_5$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_5$EN = MUX_m_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_6
|
|
assign m_tlb_m_entryVec_6$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_6$EN = MUX_m_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_7
|
|
assign m_tlb_m_entryVec_7$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_7$EN = MUX_m_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_8
|
|
assign m_tlb_m_entryVec_8$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_8$EN = MUX_m_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_entryVec_9
|
|
assign m_tlb_m_entryVec_9$D_IN = m_tlb_m_entryVec_1$D_IN ;
|
|
assign m_tlb_m_entryVec_9$EN = MUX_m_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
|
|
// register m_tlb_m_lruBit_rl
|
|
assign m_tlb_m_lruBit_rl$D_IN = n__read__h51151 ;
|
|
assign m_tlb_m_lruBit_rl$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_randIdx
|
|
assign m_tlb_m_randIdx$D_IN = m_tlb_m_randIdx + 5'd1 ;
|
|
assign m_tlb_m_randIdx$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_updRepIdx_rl
|
|
assign m_tlb_m_updRepIdx_rl$D_IN =
|
|
{ IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17,
|
|
IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27 } ;
|
|
assign m_tlb_m_updRepIdx_rl$EN = 1'd1 ;
|
|
|
|
// register m_tlb_m_validVec_0
|
|
assign m_tlb_m_validVec_0$D_IN = MUX_m_tlb_m_validVec_0$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_0$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1718 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_1
|
|
assign m_tlb_m_validVec_1$D_IN = MUX_m_tlb_m_validVec_1$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_1$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1720 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_10
|
|
assign m_tlb_m_validVec_10$D_IN = MUX_m_tlb_m_validVec_10$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_10$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1738 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_11
|
|
assign m_tlb_m_validVec_11$D_IN = MUX_m_tlb_m_validVec_11$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_11$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1740 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_12
|
|
assign m_tlb_m_validVec_12$D_IN = MUX_m_tlb_m_validVec_12$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_12$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1742 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_13
|
|
assign m_tlb_m_validVec_13$D_IN = MUX_m_tlb_m_validVec_13$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_13$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1744 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_14
|
|
assign m_tlb_m_validVec_14$D_IN = MUX_m_tlb_m_validVec_14$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_14$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1746 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_15
|
|
assign m_tlb_m_validVec_15$D_IN = MUX_m_tlb_m_validVec_15$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_15$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1748 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_16
|
|
assign m_tlb_m_validVec_16$D_IN = MUX_m_tlb_m_validVec_16$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_16$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1750 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_17
|
|
assign m_tlb_m_validVec_17$D_IN = MUX_m_tlb_m_validVec_17$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_17$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1752 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_18
|
|
assign m_tlb_m_validVec_18$D_IN = MUX_m_tlb_m_validVec_18$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_18$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1754 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_19
|
|
assign m_tlb_m_validVec_19$D_IN = MUX_m_tlb_m_validVec_19$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_19$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1756 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_2
|
|
assign m_tlb_m_validVec_2$D_IN = MUX_m_tlb_m_validVec_2$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_2$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1722 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_20
|
|
assign m_tlb_m_validVec_20$D_IN = MUX_m_tlb_m_validVec_20$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_20$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1758 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_21
|
|
assign m_tlb_m_validVec_21$D_IN = MUX_m_tlb_m_validVec_21$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_21$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1760 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_22
|
|
assign m_tlb_m_validVec_22$D_IN = MUX_m_tlb_m_validVec_22$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_22$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1762 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_23
|
|
assign m_tlb_m_validVec_23$D_IN = MUX_m_tlb_m_validVec_23$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_23$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1764 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_24
|
|
assign m_tlb_m_validVec_24$D_IN = MUX_m_tlb_m_validVec_24$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_24$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1766 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_25
|
|
assign m_tlb_m_validVec_25$D_IN = MUX_m_tlb_m_validVec_25$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_25$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1768 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_26
|
|
assign m_tlb_m_validVec_26$D_IN = MUX_m_tlb_m_validVec_26$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_26$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1770 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_27
|
|
assign m_tlb_m_validVec_27$D_IN = MUX_m_tlb_m_validVec_27$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_27$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1772 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_28
|
|
assign m_tlb_m_validVec_28$D_IN = MUX_m_tlb_m_validVec_28$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_28$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1774 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_29
|
|
assign m_tlb_m_validVec_29$D_IN = MUX_m_tlb_m_validVec_29$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_29$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1776 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_3
|
|
assign m_tlb_m_validVec_3$D_IN = MUX_m_tlb_m_validVec_3$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_3$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1724 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_30
|
|
assign m_tlb_m_validVec_30$D_IN = MUX_m_tlb_m_validVec_30$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_30$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1778 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_31
|
|
assign m_tlb_m_validVec_31$D_IN = MUX_m_tlb_m_validVec_31$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_31$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1780 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_4
|
|
assign m_tlb_m_validVec_4$D_IN = MUX_m_tlb_m_validVec_4$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_4$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1726 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_5
|
|
assign m_tlb_m_validVec_5$D_IN = MUX_m_tlb_m_validVec_5$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_5$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1728 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_6
|
|
assign m_tlb_m_validVec_6$D_IN = MUX_m_tlb_m_validVec_6$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_6$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1730 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_7
|
|
assign m_tlb_m_validVec_7$D_IN = MUX_m_tlb_m_validVec_7$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_7$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1732 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_8
|
|
assign m_tlb_m_validVec_8$D_IN = MUX_m_tlb_m_validVec_8$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_8$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1734 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_tlb_m_validVec_9
|
|
assign m_tlb_m_validVec_9$D_IN = MUX_m_tlb_m_validVec_9$write_1__SEL_1 ;
|
|
assign m_tlb_m_validVec_9$EN =
|
|
WILL_FIRE_RL_m_doPRs &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1736 ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// register m_vm_info
|
|
assign m_vm_info$D_IN = updateVMInfo_vm ;
|
|
assign m_vm_info$EN = EN_updateVMInfo ;
|
|
|
|
// register m_waitFlushP
|
|
assign m_waitFlushP$D_IN = !MUX_m_waitFlushP$write_1__SEL_1 ;
|
|
assign m_waitFlushP$EN =
|
|
WILL_FIRE_RL_m_doFinishFlush || EN_flush ||
|
|
WILL_FIRE_RL_m_doStartFlush ;
|
|
|
|
// remaining internal signals
|
|
assign DONTCARE_CONCAT_1_CONCAT_IF_NOT_SEL_ARR_m_pend_ETC___d1854 =
|
|
{ 65'h15555555555555555,
|
|
(SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd4) ?
|
|
5'd13 :
|
|
5'd15 } ;
|
|
assign DONTCARE_CONCAT_1_CONCAT_IF_NOT_procReq_req_BI_ETC___d2874 =
|
|
{ 65'h15555555555555555,
|
|
(procReq_req[490:488] != 3'd1 &&
|
|
procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
5'd13 :
|
|
5'd15 } ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2805 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2802 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2802 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2813 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2810 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2810 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2855 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2852 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2852 ;
|
|
assign IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2862 =
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2859 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2859 ;
|
|
assign IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2802 =
|
|
(level__h87878 == 2'd0 ||
|
|
((level__h87878 == 2'd1) ?
|
|
ppn__h92833[8:0] == 9'd0 :
|
|
level__h87878 == 2'd2 && ppn__h92833[17:0] == 18'd0)) &&
|
|
(!SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 ||
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645) ;
|
|
assign IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_ETC___d2810 =
|
|
(level__h87878 == 2'd0 ||
|
|
((level__h87878 == 2'd1) ?
|
|
ppn__h92833[8:0] == 9'd0 :
|
|
level__h87878 == 2'd2 && ppn__h92833[17:0] == 18'd0)) &&
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 =
|
|
_theResult_____2__h13508 == v__h13028 ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d167 =
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 &&
|
|
(IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ||
|
|
!EN_procReq && !m_freeQ_deqReq_rl && m_freeQ_full) ;
|
|
assign IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d172 =
|
|
IF_IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_fre_ETC___d158 &&
|
|
(m_freeQ_enqReq_lat_0$whas ?
|
|
!m_freeQ_enqReq_lat_0$wget[2] :
|
|
!m_freeQ_enqReq_rl[2]) &&
|
|
(IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 ||
|
|
m_freeQ_empty) ;
|
|
assign IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 =
|
|
_theResult_____2__h22136 == v__h21066 ;
|
|
assign IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d366 =
|
|
IF_IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27__ETC___d357 &&
|
|
(IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ||
|
|
!m_ldTransRsFromPQ_deqReq_lat_0$whas &&
|
|
!m_ldTransRsFromPQ_deqReq_rl &&
|
|
m_ldTransRsFromPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 =
|
|
_theResult_____2__h17468 == v__h16896 ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d255 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 &&
|
|
(IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ||
|
|
!EN_toParent_rqToP_deq && !m_rqToPQ_deqReq_rl &&
|
|
m_rqToPQ_full) ;
|
|
assign IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d260 =
|
|
IF_IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rq_ETC___d246 &&
|
|
(m_rqToPQ_enqReq_lat_0$whas ?
|
|
!m_rqToPQ_enqReq_lat_0$wget[29] :
|
|
!m_rqToPQ_enqReq_rl[29]) &&
|
|
(IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 ||
|
|
m_rqToPQ_empty) ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d1294 =
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 ?
|
|
NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d721 &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_ldTra_ETC___d1291 :
|
|
CASE_IF_m_respForOtherReq_64_BIT_2_65_THEN_m_r_ETC___d1293 ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d1847 =
|
|
(SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd4) ?
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d1838 :
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_4_51_m_ETC___d709 ||
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696 ||
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d1845 ;
|
|
assign IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d718 =
|
|
(SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd4) ?
|
|
NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BI_ETC___d707 :
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_4_51_m_ETC___d709 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696 &&
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d716 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1935 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) ?
|
|
m_pendValid_1_rl && m_pendWait_1[3:2] == 2'd0 &&
|
|
m_pendPoisoned_1 :
|
|
m_pendValid_0_rl ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1936 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1924 ?
|
|
m_pendValid_2_rl && m_pendWait_2[3:2] == 2'd0 &&
|
|
m_pendPoisoned_2 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1935 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1937 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1928 ?
|
|
m_pendValid_3_rl && m_pendWait_3[3:2] == 2'd0 &&
|
|
m_pendPoisoned_3 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d1936 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3839 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) ?
|
|
m_pendValid_1_rl && m_pendWait_1[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_1 :
|
|
m_pendValid_0_rl ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3840 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2950 ?
|
|
m_pendValid_2_rl && m_pendWait_2[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_2 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3839 ;
|
|
assign IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3841 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2952 ?
|
|
m_pendValid_3_rl && m_pendWait_3[3:2] == 2'd0 &&
|
|
!m_pendPoisoned_3 :
|
|
IF_NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_ETC___d3840 ;
|
|
assign IF_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70__ETC___d2905 =
|
|
((m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2879) &&
|
|
(m_pendWait_1[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2882)) ?
|
|
2'd2 :
|
|
((m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2879) ?
|
|
2'd1 :
|
|
2'd0) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2374 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035 ?
|
|
m_tlb_m_validVec_1 &&
|
|
IF_m_tlb_m_entryVec_1_50_BITS_1_TO_0_54_EQ_0_0_ETC___d2042 :
|
|
m_tlb_m_validVec_0 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2375 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_50_BITS_1_TO_0_54_EQ_0_0_ETC___d2042)) ?
|
|
m_tlb_m_validVec_2 &&
|
|
IF_m_tlb_m_entryVec_2_66_BITS_1_TO_0_70_EQ_0_0_ETC___d2052 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2374 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2376 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055 ?
|
|
m_tlb_m_validVec_3 &&
|
|
IF_m_tlb_m_entryVec_3_82_BITS_1_TO_0_86_EQ_0_0_ETC___d2062 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2375 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2377 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_82_BITS_1_TO_0_86_EQ_0_0_ETC___d2062)) ?
|
|
m_tlb_m_validVec_4 &&
|
|
IF_m_tlb_m_entryVec_4_98_BITS_1_TO_0_02_EQ_0_0_ETC___d2072 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2376 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2378 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075 ?
|
|
m_tlb_m_validVec_5 &&
|
|
IF_m_tlb_m_entryVec_5_14_BITS_1_TO_0_18_EQ_0_0_ETC___d2082 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2377 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2379 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_14_BITS_1_TO_0_18_EQ_0_0_ETC___d2082)) ?
|
|
m_tlb_m_validVec_6 &&
|
|
IF_m_tlb_m_entryVec_6_30_BITS_1_TO_0_34_EQ_0_0_ETC___d2092 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2378 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2380 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095 ?
|
|
m_tlb_m_validVec_7 &&
|
|
IF_m_tlb_m_entryVec_7_46_BITS_1_TO_0_50_EQ_0_0_ETC___d2102 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2379 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2381 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_46_BITS_1_TO_0_50_EQ_0_0_ETC___d2102)) ?
|
|
m_tlb_m_validVec_8 &&
|
|
IF_m_tlb_m_entryVec_8_62_BITS_1_TO_0_66_EQ_0_1_ETC___d2112 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2380 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2382 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115 ?
|
|
m_tlb_m_validVec_9 &&
|
|
IF_m_tlb_m_entryVec_9_78_BITS_1_TO_0_82_EQ_0_1_ETC___d2122 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2381 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2383 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_78_BITS_1_TO_0_82_EQ_0_1_ETC___d2122)) ?
|
|
m_tlb_m_validVec_10 &&
|
|
IF_m_tlb_m_entryVec_10_94_BITS_1_TO_0_98_EQ_0__ETC___d2132 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2382 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2384 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135 ?
|
|
m_tlb_m_validVec_11 &&
|
|
IF_m_tlb_m_entryVec_11_10_BITS_1_TO_0_14_EQ_0__ETC___d2142 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2383 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2385 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_10_BITS_1_TO_0_14_EQ_0__ETC___d2142)) ?
|
|
m_tlb_m_validVec_12 &&
|
|
IF_m_tlb_m_entryVec_12_26_BITS_1_TO_0_30_EQ_0__ETC___d2152 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2384 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2386 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155 ?
|
|
m_tlb_m_validVec_13 &&
|
|
IF_m_tlb_m_entryVec_13_42_BITS_1_TO_0_46_EQ_0__ETC___d2162 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2385 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2387 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_42_BITS_1_TO_0_46_EQ_0__ETC___d2162)) ?
|
|
m_tlb_m_validVec_14 &&
|
|
IF_m_tlb_m_entryVec_14_58_BITS_1_TO_0_62_EQ_0__ETC___d2172 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2386 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2388 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175 ?
|
|
m_tlb_m_validVec_15 &&
|
|
IF_m_tlb_m_entryVec_15_74_BITS_1_TO_0_78_EQ_0__ETC___d2182 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2387 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2389 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_74_BITS_1_TO_0_78_EQ_0__ETC___d2182)) ?
|
|
m_tlb_m_validVec_16 &&
|
|
IF_m_tlb_m_entryVec_16_90_BITS_1_TO_0_94_EQ_0__ETC___d2192 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2388 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2390 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195 ?
|
|
m_tlb_m_validVec_17 &&
|
|
IF_m_tlb_m_entryVec_17_006_BITS_1_TO_0_010_EQ__ETC___d2202 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2389 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2391 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_006_BITS_1_TO_0_010_EQ__ETC___d2202)) ?
|
|
m_tlb_m_validVec_18 &&
|
|
IF_m_tlb_m_entryVec_18_022_BITS_1_TO_0_026_EQ__ETC___d2212 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2390 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2392 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215 ?
|
|
m_tlb_m_validVec_19 &&
|
|
IF_m_tlb_m_entryVec_19_038_BITS_1_TO_0_042_EQ__ETC___d2222 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2391 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2393 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_038_BITS_1_TO_0_042_EQ__ETC___d2222)) ?
|
|
m_tlb_m_validVec_20 &&
|
|
IF_m_tlb_m_entryVec_20_054_BITS_1_TO_0_058_EQ__ETC___d2232 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2392 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2394 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235 ?
|
|
m_tlb_m_validVec_21 &&
|
|
IF_m_tlb_m_entryVec_21_070_BITS_1_TO_0_074_EQ__ETC___d2242 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2393 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2395 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_070_BITS_1_TO_0_074_EQ__ETC___d2242)) ?
|
|
m_tlb_m_validVec_22 &&
|
|
IF_m_tlb_m_entryVec_22_086_BITS_1_TO_0_090_EQ__ETC___d2252 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2394 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2396 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255 ?
|
|
m_tlb_m_validVec_23 &&
|
|
IF_m_tlb_m_entryVec_23_102_BITS_1_TO_0_106_EQ__ETC___d2262 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2395 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2397 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_102_BITS_1_TO_0_106_EQ__ETC___d2262)) ?
|
|
m_tlb_m_validVec_24 &&
|
|
IF_m_tlb_m_entryVec_24_118_BITS_1_TO_0_122_EQ__ETC___d2272 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2396 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2398 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275 ?
|
|
m_tlb_m_validVec_25 &&
|
|
IF_m_tlb_m_entryVec_25_134_BITS_1_TO_0_138_EQ__ETC___d2282 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2397 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2399 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_134_BITS_1_TO_0_138_EQ__ETC___d2282)) ?
|
|
m_tlb_m_validVec_26 &&
|
|
IF_m_tlb_m_entryVec_26_150_BITS_1_TO_0_154_EQ__ETC___d2292 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2398 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2400 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295 ?
|
|
m_tlb_m_validVec_27 &&
|
|
IF_m_tlb_m_entryVec_27_166_BITS_1_TO_0_170_EQ__ETC___d2302 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2399 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2401 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_166_BITS_1_TO_0_170_EQ__ETC___d2302)) ?
|
|
m_tlb_m_validVec_28 &&
|
|
IF_m_tlb_m_entryVec_28_182_BITS_1_TO_0_186_EQ__ETC___d2312 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2400 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2402 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315 ?
|
|
m_tlb_m_validVec_29 &&
|
|
IF_m_tlb_m_entryVec_29_198_BITS_1_TO_0_202_EQ__ETC___d2322 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2401 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2403 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_198_BITS_1_TO_0_202_EQ__ETC___d2322)) ?
|
|
m_tlb_m_validVec_30 &&
|
|
IF_m_tlb_m_entryVec_30_214_BITS_1_TO_0_218_EQ__ETC___d2332 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2402 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335 ?
|
|
m_tlb_m_validVec_31 &&
|
|
IF_m_tlb_m_entryVec_31_376_BITS_1_TO_0_380_EQ__ETC___d2342 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2403 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2480 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_50_BITS_1_TO_0_54_EQ_0_0_ETC___d2042)) ?
|
|
5'd2 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035 ?
|
|
5'd1 :
|
|
5'd0) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2482 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_82_BITS_1_TO_0_86_EQ_0_0_ETC___d2062)) ?
|
|
5'd4 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055 ?
|
|
5'd3 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2480) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2484 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_14_BITS_1_TO_0_18_EQ_0_0_ETC___d2082)) ?
|
|
5'd6 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075 ?
|
|
5'd5 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2482) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2486 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_46_BITS_1_TO_0_50_EQ_0_0_ETC___d2102)) ?
|
|
5'd8 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095 ?
|
|
5'd7 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2484) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2488 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_78_BITS_1_TO_0_82_EQ_0_1_ETC___d2122)) ?
|
|
5'd10 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115 ?
|
|
5'd9 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2486) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2490 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_10_BITS_1_TO_0_14_EQ_0__ETC___d2142)) ?
|
|
5'd12 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135 ?
|
|
5'd11 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2488) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2492 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_42_BITS_1_TO_0_46_EQ_0__ETC___d2162)) ?
|
|
5'd14 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155 ?
|
|
5'd13 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2490) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2494 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_74_BITS_1_TO_0_78_EQ_0__ETC___d2182)) ?
|
|
5'd16 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175 ?
|
|
5'd15 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2492) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2496 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_006_BITS_1_TO_0_010_EQ__ETC___d2202)) ?
|
|
5'd18 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195 ?
|
|
5'd17 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2494) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2498 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_038_BITS_1_TO_0_042_EQ__ETC___d2222)) ?
|
|
5'd20 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215 ?
|
|
5'd19 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2496) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2500 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_070_BITS_1_TO_0_074_EQ__ETC___d2242)) ?
|
|
5'd22 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235 ?
|
|
5'd21 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2498) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2502 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_102_BITS_1_TO_0_106_EQ__ETC___d2262)) ?
|
|
5'd24 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255 ?
|
|
5'd23 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2500) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2504 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_134_BITS_1_TO_0_138_EQ__ETC___d2282)) ?
|
|
5'd26 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275 ?
|
|
5'd25 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2502) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2506 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_166_BITS_1_TO_0_170_EQ__ETC___d2302)) ?
|
|
5'd28 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295 ?
|
|
5'd27 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2504) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2508 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_198_BITS_1_TO_0_202_EQ__ETC___d2322)) ?
|
|
5'd30 :
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315 ?
|
|
5'd29 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2506) ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_ldTra_ETC___d1291 =
|
|
((!m_tlb_m_validVec_0 || !m_ldTransRsFromPQ_empty) &&
|
|
(!m_tlb_m_validVec_0 ||
|
|
NOT_m_tlb_m_entryVec_0_25_BITS_79_TO_53_26_EQ__ETC___d744)) ?
|
|
(!m_tlb_m_validVec_1 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_1_47_48_OR_NOT_m_tlb_m_ETC___d1289 :
|
|
!m_tlb_m_validVec_0 || !m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1718 =
|
|
v__h45598 == 5'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1720 =
|
|
v__h45598 == 5'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1722 =
|
|
v__h45598 == 5'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1724 =
|
|
v__h45598 == 5'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1726 =
|
|
v__h45598 == 5'd4 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1728 =
|
|
v__h45598 == 5'd5 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1730 =
|
|
v__h45598 == 5'd6 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1732 =
|
|
v__h45598 == 5'd7 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1734 =
|
|
v__h45598 == 5'd8 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1736 =
|
|
v__h45598 == 5'd9 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1738 =
|
|
v__h45598 == 5'd10 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1740 =
|
|
v__h45598 == 5'd11 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1742 =
|
|
v__h45598 == 5'd12 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1744 =
|
|
v__h45598 == 5'd13 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1746 =
|
|
v__h45598 == 5'd14 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1748 =
|
|
v__h45598 == 5'd15 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1750 =
|
|
v__h45598 == 5'd16 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1752 =
|
|
v__h45598 == 5'd17 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1754 =
|
|
v__h45598 == 5'd18 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1756 =
|
|
v__h45598 == 5'd19 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1758 =
|
|
v__h45598 == 5'd20 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1760 =
|
|
v__h45598 == 5'd21 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1762 =
|
|
v__h45598 == 5'd22 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1764 =
|
|
v__h45598 == 5'd23 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1766 =
|
|
v__h45598 == 5'd24 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1768 =
|
|
v__h45598 == 5'd25 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1770 =
|
|
v__h45598 == 5'd26 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1772 =
|
|
v__h45598 == 5'd27 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1774 =
|
|
v__h45598 == 5'd28 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1776 =
|
|
v__h45598 == 5'd29 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1778 =
|
|
v__h45598 == 5'd30 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_ETC___d1780 =
|
|
v__h45598 == 5'd31 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 ;
|
|
assign IF_NOT_m_tlb_m_validVec_10_91_92_OR_NOT_m_tlb__ETC___d1271 =
|
|
(!m_tlb_m_validVec_10 ||
|
|
NOT_m_tlb_m_entryVec_10_94_BITS_79_TO_53_95_EQ_ETC___d905) ?
|
|
(!m_tlb_m_validVec_11 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_11_07_08_OR_NOT_m_tlb__ETC___d1269 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_11_07_08_OR_NOT_m_tlb__ETC___d1269 =
|
|
(!m_tlb_m_validVec_11 ||
|
|
NOT_m_tlb_m_entryVec_11_10_BITS_79_TO_53_11_EQ_ETC___d921) ?
|
|
(!m_tlb_m_validVec_12 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_12_23_24_OR_NOT_m_tlb__ETC___d1267 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_12_23_24_OR_NOT_m_tlb__ETC___d1267 =
|
|
(!m_tlb_m_validVec_12 ||
|
|
NOT_m_tlb_m_entryVec_12_26_BITS_79_TO_53_27_EQ_ETC___d937) ?
|
|
(!m_tlb_m_validVec_13 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_13_39_40_OR_NOT_m_tlb__ETC___d1265 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_13_39_40_OR_NOT_m_tlb__ETC___d1265 =
|
|
(!m_tlb_m_validVec_13 ||
|
|
NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d953) ?
|
|
(!m_tlb_m_validVec_14 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_14_55_56_OR_NOT_m_tlb__ETC___d1263 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_14_55_56_OR_NOT_m_tlb__ETC___d1263 =
|
|
(!m_tlb_m_validVec_14 ||
|
|
NOT_m_tlb_m_entryVec_14_58_BITS_79_TO_53_59_EQ_ETC___d969) ?
|
|
(!m_tlb_m_validVec_15 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_15_71_72_OR_NOT_m_tlb__ETC___d1261 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_15_71_72_OR_NOT_m_tlb__ETC___d1261 =
|
|
(!m_tlb_m_validVec_15 ||
|
|
NOT_m_tlb_m_entryVec_15_74_BITS_79_TO_53_75_EQ_ETC___d985) ?
|
|
(!m_tlb_m_validVec_16 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_16_87_88_OR_NOT_m_tlb__ETC___d1259 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_16_87_88_OR_NOT_m_tlb__ETC___d1259 =
|
|
(!m_tlb_m_validVec_16 ||
|
|
NOT_m_tlb_m_entryVec_16_90_BITS_79_TO_53_91_EQ_ETC___d1001) ?
|
|
(!m_tlb_m_validVec_17 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_17_003_004_OR_NOT_m_tl_ETC___d1257 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_17_003_004_OR_NOT_m_tl_ETC___d1257 =
|
|
(!m_tlb_m_validVec_17 ||
|
|
NOT_m_tlb_m_entryVec_17_006_BITS_79_TO_53_007__ETC___d1017) ?
|
|
(!m_tlb_m_validVec_18 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_18_019_020_OR_NOT_m_tl_ETC___d1255 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_18_019_020_OR_NOT_m_tl_ETC___d1255 =
|
|
(!m_tlb_m_validVec_18 ||
|
|
NOT_m_tlb_m_entryVec_18_022_BITS_79_TO_53_023__ETC___d1033) ?
|
|
(!m_tlb_m_validVec_19 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_19_035_036_OR_NOT_m_tl_ETC___d1253 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_19_035_036_OR_NOT_m_tl_ETC___d1253 =
|
|
(!m_tlb_m_validVec_19 ||
|
|
NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1049) ?
|
|
(!m_tlb_m_validVec_20 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_20_051_052_OR_NOT_m_tl_ETC___d1251 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_1_47_48_OR_NOT_m_tlb_m_ETC___d1289 =
|
|
(!m_tlb_m_validVec_1 ||
|
|
NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d761) ?
|
|
(!m_tlb_m_validVec_2 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_2_63_64_OR_NOT_m_tlb_m_ETC___d1287 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_20_051_052_OR_NOT_m_tl_ETC___d1251 =
|
|
(!m_tlb_m_validVec_20 ||
|
|
NOT_m_tlb_m_entryVec_20_054_BITS_79_TO_53_055__ETC___d1065) ?
|
|
(!m_tlb_m_validVec_21 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_21_067_068_OR_NOT_m_tl_ETC___d1249 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_21_067_068_OR_NOT_m_tl_ETC___d1249 =
|
|
(!m_tlb_m_validVec_21 ||
|
|
NOT_m_tlb_m_entryVec_21_070_BITS_79_TO_53_071__ETC___d1081) ?
|
|
(!m_tlb_m_validVec_22 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_22_083_084_OR_NOT_m_tl_ETC___d1247 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_22_083_084_OR_NOT_m_tl_ETC___d1247 =
|
|
(!m_tlb_m_validVec_22 ||
|
|
NOT_m_tlb_m_entryVec_22_086_BITS_79_TO_53_087__ETC___d1097) ?
|
|
(!m_tlb_m_validVec_23 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_23_099_100_OR_NOT_m_tl_ETC___d1245 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_23_099_100_OR_NOT_m_tl_ETC___d1245 =
|
|
(!m_tlb_m_validVec_23 ||
|
|
NOT_m_tlb_m_entryVec_23_102_BITS_79_TO_53_103__ETC___d1113) ?
|
|
(!m_tlb_m_validVec_24 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_24_115_116_OR_NOT_m_tl_ETC___d1243 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_24_115_116_OR_NOT_m_tl_ETC___d1243 =
|
|
(!m_tlb_m_validVec_24 ||
|
|
NOT_m_tlb_m_entryVec_24_118_BITS_79_TO_53_119__ETC___d1129) ?
|
|
(!m_tlb_m_validVec_25 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_25_131_132_OR_NOT_m_tl_ETC___d1241 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_25_131_132_OR_NOT_m_tl_ETC___d1241 =
|
|
(!m_tlb_m_validVec_25 ||
|
|
NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1145) ?
|
|
(!m_tlb_m_validVec_26 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_26_147_148_OR_NOT_m_tl_ETC___d1239 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_26_147_148_OR_NOT_m_tl_ETC___d1239 =
|
|
(!m_tlb_m_validVec_26 ||
|
|
NOT_m_tlb_m_entryVec_26_150_BITS_79_TO_53_151__ETC___d1161) ?
|
|
(!m_tlb_m_validVec_27 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_27_163_164_OR_NOT_m_tl_ETC___d1237 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_27_163_164_OR_NOT_m_tl_ETC___d1237 =
|
|
(!m_tlb_m_validVec_27 ||
|
|
NOT_m_tlb_m_entryVec_27_166_BITS_79_TO_53_167__ETC___d1177) ?
|
|
(!m_tlb_m_validVec_28 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_28_179_180_OR_NOT_m_tl_ETC___d1235 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_28_179_180_OR_NOT_m_tl_ETC___d1235 =
|
|
(!m_tlb_m_validVec_28 ||
|
|
NOT_m_tlb_m_entryVec_28_182_BITS_79_TO_53_183__ETC___d1193) ?
|
|
(!m_tlb_m_validVec_29 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_29_195_196_OR_NOT_m_tl_ETC___d1233 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_29_195_196_OR_NOT_m_tl_ETC___d1233 =
|
|
(!m_tlb_m_validVec_29 ||
|
|
NOT_m_tlb_m_entryVec_29_198_BITS_79_TO_53_199__ETC___d1209) ?
|
|
(!m_tlb_m_validVec_30 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_30_211_212_OR_NOT_m_tl_ETC___d1231 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_2_63_64_OR_NOT_m_tlb_m_ETC___d1287 =
|
|
(!m_tlb_m_validVec_2 ||
|
|
NOT_m_tlb_m_entryVec_2_66_BITS_79_TO_53_67_EQ__ETC___d777) ?
|
|
(!m_tlb_m_validVec_3 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_3_79_80_OR_NOT_m_tlb_m_ETC___d1285 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_30_211_212_OR_NOT_m_tl_ETC___d1231 =
|
|
(!m_tlb_m_validVec_30 ||
|
|
NOT_m_tlb_m_entryVec_30_214_BITS_79_TO_53_215__ETC___d1225) ?
|
|
!m_tlb_m_validVec_31 || !m_ldTransRsFromPQ_empty :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_3_79_80_OR_NOT_m_tlb_m_ETC___d1285 =
|
|
(!m_tlb_m_validVec_3 ||
|
|
NOT_m_tlb_m_entryVec_3_82_BITS_79_TO_53_83_EQ__ETC___d793) ?
|
|
(!m_tlb_m_validVec_4 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_4_95_96_OR_NOT_m_tlb_m_ETC___d1283 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_4_95_96_OR_NOT_m_tlb_m_ETC___d1283 =
|
|
(!m_tlb_m_validVec_4 ||
|
|
NOT_m_tlb_m_entryVec_4_98_BITS_79_TO_53_99_EQ__ETC___d809) ?
|
|
(!m_tlb_m_validVec_5 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_5_11_12_OR_NOT_m_tlb_m_ETC___d1281 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_5_11_12_OR_NOT_m_tlb_m_ETC___d1281 =
|
|
(!m_tlb_m_validVec_5 ||
|
|
NOT_m_tlb_m_entryVec_5_14_BITS_79_TO_53_15_EQ__ETC___d825) ?
|
|
(!m_tlb_m_validVec_6 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_6_27_28_OR_NOT_m_tlb_m_ETC___d1279 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_6_27_28_OR_NOT_m_tlb_m_ETC___d1279 =
|
|
(!m_tlb_m_validVec_6 ||
|
|
NOT_m_tlb_m_entryVec_6_30_BITS_79_TO_53_31_EQ__ETC___d841) ?
|
|
(!m_tlb_m_validVec_7 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_7_43_44_OR_NOT_m_tlb_m_ETC___d1277 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_7_43_44_OR_NOT_m_tlb_m_ETC___d1277 =
|
|
(!m_tlb_m_validVec_7 ||
|
|
NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d857) ?
|
|
(!m_tlb_m_validVec_8 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_8_59_60_OR_NOT_m_tlb_m_ETC___d1275 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_8_59_60_OR_NOT_m_tlb_m_ETC___d1275 =
|
|
(!m_tlb_m_validVec_8 ||
|
|
NOT_m_tlb_m_entryVec_8_62_BITS_79_TO_53_63_EQ__ETC___d873) ?
|
|
(!m_tlb_m_validVec_9 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_9_75_76_OR_NOT_m_tlb_m_ETC___d1273 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_m_tlb_m_validVec_9_75_76_OR_NOT_m_tlb_m_ETC___d1273 =
|
|
(!m_tlb_m_validVec_9 ||
|
|
NOT_m_tlb_m_entryVec_9_78_BITS_79_TO_53_79_EQ__ETC___d889) ?
|
|
(!m_tlb_m_validVec_10 || !m_ldTransRsFromPQ_empty) &&
|
|
IF_NOT_m_tlb_m_validVec_10_91_92_OR_NOT_m_tlb__ETC___d1271 :
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign IF_NOT_procReq_req_BITS_490_TO_488_405_EQ_1_40_ETC___d2815 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_58_ETC___d2806 :
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 &&
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 &&
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2813 ;
|
|
assign IF_NOT_procReq_req_BITS_490_TO_488_405_EQ_1_40_ETC___d2864 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4) ?
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2856 :
|
|
!SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 ||
|
|
!SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 ||
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2862 ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3755 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3740 ?
|
|
5'd24 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3746 ?
|
|
5'd25 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3752 ?
|
|
5'd26 :
|
|
5'd27)) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3757 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3728 ?
|
|
5'd22 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3734 ?
|
|
5'd23 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3755) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3759 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3716 ?
|
|
5'd20 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3722 ?
|
|
5'd21 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3757) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3761 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3704 ?
|
|
5'd18 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3710 ?
|
|
5'd19 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3759) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3763 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3692 ?
|
|
5'd16 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3698 ?
|
|
5'd17 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3761) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3765 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3680 ?
|
|
5'd10 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3686 ?
|
|
5'd11 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3763) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3767 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3668 ?
|
|
5'd8 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3674 ?
|
|
5'd9 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3765) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3769 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3656 ?
|
|
5'd6 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3662 ?
|
|
5'd7 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3767) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3771 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3644 ?
|
|
5'd4 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3650 ?
|
|
5'd5 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3769) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3773 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3632 ?
|
|
5'd2 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3638 ?
|
|
5'd3 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3771) ;
|
|
assign IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3775 =
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3620 ?
|
|
5'd0 :
|
|
(SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3626 ?
|
|
5'd1 :
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3773) ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d1837 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1834 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1834 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d1845 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669 ?
|
|
m_vm_info[48:47] == 2'd1 && !m_vm_info[44] ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1842 :
|
|
m_vm_info[48:47] == 2'd0 ||
|
|
NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1842 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d706 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d701 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d701 ;
|
|
assign IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d716 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669 ?
|
|
(m_vm_info[48:47] != 2'd1 || m_vm_info[44]) &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d713 :
|
|
m_vm_info[48:47] != 2'd0 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d713 ;
|
|
assign IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3058 =
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_12_ETC___d3043 ?
|
|
5'd12 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_13_ETC___d3049 ?
|
|
5'd13 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_15_ETC___d3055 ?
|
|
5'd15 :
|
|
5'd28)) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3060 =
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_9__ETC___d3031 ?
|
|
5'd9 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_11_ETC___d3037 ?
|
|
5'd11 :
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3058) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3062 =
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_7__ETC___d3019 ?
|
|
5'd7 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_8__ETC___d3025 ?
|
|
5'd8 :
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3060) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3064 =
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_5__ETC___d3007 ?
|
|
5'd5 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_6__ETC___d3013 ?
|
|
5'd6 :
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3062) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3066 =
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_3__ETC___d2995 ?
|
|
5'd3 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_4__ETC___d3001 ?
|
|
5'd4 :
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3064) ;
|
|
assign IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3068 =
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_1__ETC___d2983 ?
|
|
5'd1 :
|
|
(SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_2__ETC___d2989 ?
|
|
5'd2 :
|
|
IF_SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_ETC___d3066) ;
|
|
assign IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 =
|
|
EN_procReq || m_freeQ_deqReq_rl ;
|
|
assign IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 =
|
|
m_freeQ_enqReq_lat_0$whas ?
|
|
m_freeQ_enqReq_lat_0$wget[2] :
|
|
m_freeQ_enqReq_rl[2] ;
|
|
assign IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 =
|
|
m_ldTransRsFromPQ_deqReq_lat_0$whas ||
|
|
m_ldTransRsFromPQ_deqReq_rl ;
|
|
assign IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[83] :
|
|
m_ldTransRsFromPQ_enqReq_rl[83] ;
|
|
assign IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d291 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
!m_ldTransRsFromPQ_enqReq_lat_0$wget[83] :
|
|
!m_ldTransRsFromPQ_enqReq_rl[83] ;
|
|
assign IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866 =
|
|
m_pendValid_0_lat_0$whas ? !1'd0 : !m_pendValid_0_rl ;
|
|
assign IF_m_pendValid_0_lat_0_whas__2_THEN_m_pendVali_ETC___d45 =
|
|
m_pendValid_0_lat_0$whas ? 1'd0 : m_pendValid_0_rl ;
|
|
assign IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868 =
|
|
m_pendValid_1_lat_0$whas ? !1'd0 : !m_pendValid_1_rl ;
|
|
assign IF_m_pendValid_1_lat_0_whas__9_THEN_m_pendVali_ETC___d52 =
|
|
m_pendValid_1_lat_0$whas ? 1'd0 : m_pendValid_1_rl ;
|
|
assign IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870 =
|
|
m_pendValid_2_lat_0$whas ? !1'd0 : !m_pendValid_2_rl ;
|
|
assign IF_m_pendValid_2_lat_0_whas__6_THEN_m_pendVali_ETC___d59 =
|
|
m_pendValid_2_lat_0$whas ? 1'd0 : m_pendValid_2_rl ;
|
|
assign IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872 =
|
|
m_pendValid_3_lat_0$whas ? !1'd0 : !m_pendValid_3_rl ;
|
|
assign IF_m_pendValid_3_lat_0_whas__3_THEN_m_pendVali_ETC___d66 =
|
|
m_pendValid_3_lat_0$whas ? 1'd0 : m_pendValid_3_rl ;
|
|
assign IF_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_ETC___d1333 =
|
|
(m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1308 &&
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1317) ?
|
|
m_pendWait_2[3:2] == 2'd0 || m_pendWait_2[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
NOT_m_ldTransRsFromPQ_empty_68_05_AND_NOT_m_pe_ETC___d1331 ;
|
|
assign IF_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_ETC___d1346 =
|
|
(m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1308 &&
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1336) ?
|
|
m_pendWait_3[3:2] == 2'd0 || m_pendWait_3[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
NOT_m_ldTransRsFromPQ_empty_68_05_AND_NOT_m_pe_ETC___d1331 ;
|
|
assign IF_m_perfReqQ_enqReq_lat_1_whas__84_THEN_m_per_ETC___d493 =
|
|
EN_perf_req ?
|
|
m_perfReqQ_enqReq_lat_0$wget[3] :
|
|
m_perfReqQ_enqReq_rl[3] ;
|
|
assign IF_m_respForOtherReq_64_BIT_2_65_THEN_NOT_SEL__ETC___d1349 =
|
|
(m_respForOtherReq[2] ?
|
|
!SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603 ||
|
|
!m_ldTransRsFromPQ_empty :
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d1296 &&
|
|
IF_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_ETC___d1333 &&
|
|
IF_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_ETC___d1346 ;
|
|
assign IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1793 =
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 ;
|
|
assign IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1811 =
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 ;
|
|
assign IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1812 =
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 ;
|
|
assign IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1814 =
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 ;
|
|
assign IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 =
|
|
EN_toParent_rqToP_deq || m_rqToPQ_deqReq_rl ;
|
|
assign IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 =
|
|
m_rqToPQ_enqReq_lat_0$whas ?
|
|
m_rqToPQ_enqReq_lat_0$wget[29] :
|
|
m_rqToPQ_enqReq_rl[29] ;
|
|
assign IF_m_tlb_m_entryVec_10_94_BITS_1_TO_0_98_EQ_0__ETC___d2132 =
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13 ==
|
|
m_tlb_m_entryVec_10[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_11_10_BITS_1_TO_0_14_EQ_0__ETC___d2142 =
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14 ==
|
|
m_tlb_m_entryVec_11[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_12_26_BITS_1_TO_0_30_EQ_0__ETC___d2152 =
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15 ==
|
|
m_tlb_m_entryVec_12[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_13_42_BITS_1_TO_0_46_EQ_0__ETC___d2162 =
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q16 ==
|
|
m_tlb_m_entryVec_13[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_14_58_BITS_1_TO_0_62_EQ_0__ETC___d2172 =
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q17 ==
|
|
m_tlb_m_entryVec_14[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_15_74_BITS_1_TO_0_78_EQ_0__ETC___d2182 =
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q18 ==
|
|
m_tlb_m_entryVec_15[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_16_90_BITS_1_TO_0_94_EQ_0__ETC___d2192 =
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q19 ==
|
|
m_tlb_m_entryVec_16[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_17_006_BITS_1_TO_0_010_EQ__ETC___d2202 =
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20 ==
|
|
m_tlb_m_entryVec_17[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_18_022_BITS_1_TO_0_026_EQ__ETC___d2212 =
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21 ==
|
|
m_tlb_m_entryVec_18[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_19_038_BITS_1_TO_0_042_EQ__ETC___d2222 =
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22 ==
|
|
m_tlb_m_entryVec_19[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_1_50_BITS_1_TO_0_54_EQ_0_0_ETC___d2042 =
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 ==
|
|
m_tlb_m_entryVec_1[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_20_054_BITS_1_TO_0_058_EQ__ETC___d2232 =
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23 ==
|
|
m_tlb_m_entryVec_20[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_21_070_BITS_1_TO_0_074_EQ__ETC___d2242 =
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24 ==
|
|
m_tlb_m_entryVec_21[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_22_086_BITS_1_TO_0_090_EQ__ETC___d2252 =
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25 ==
|
|
m_tlb_m_entryVec_22[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_23_102_BITS_1_TO_0_106_EQ__ETC___d2262 =
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q26 ==
|
|
m_tlb_m_entryVec_23[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_24_118_BITS_1_TO_0_122_EQ__ETC___d2272 =
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q27 ==
|
|
m_tlb_m_entryVec_24[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_25_134_BITS_1_TO_0_138_EQ__ETC___d2282 =
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q28 ==
|
|
m_tlb_m_entryVec_25[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_26_150_BITS_1_TO_0_154_EQ__ETC___d2292 =
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q29 ==
|
|
m_tlb_m_entryVec_26[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_27_166_BITS_1_TO_0_170_EQ__ETC___d2302 =
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q30 ==
|
|
m_tlb_m_entryVec_27[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_28_182_BITS_1_TO_0_186_EQ__ETC___d2312 =
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q31 ==
|
|
m_tlb_m_entryVec_28[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_29_198_BITS_1_TO_0_202_EQ__ETC___d2322 =
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q32 ==
|
|
m_tlb_m_entryVec_29[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_2_66_BITS_1_TO_0_70_EQ_0_0_ETC___d2052 =
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q5 ==
|
|
m_tlb_m_entryVec_2[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_30_214_BITS_1_TO_0_218_EQ__ETC___d2332 =
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q33 ==
|
|
m_tlb_m_entryVec_30[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_31_376_BITS_1_TO_0_380_EQ__ETC___d2342 =
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q34 ==
|
|
m_tlb_m_entryVec_31[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_3_82_BITS_1_TO_0_86_EQ_0_0_ETC___d2062 =
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q6 ==
|
|
m_tlb_m_entryVec_3[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_4_98_BITS_1_TO_0_02_EQ_0_0_ETC___d2072 =
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q7 ==
|
|
m_tlb_m_entryVec_4[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_5_14_BITS_1_TO_0_18_EQ_0_0_ETC___d2082 =
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q8 ==
|
|
m_tlb_m_entryVec_5[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_6_30_BITS_1_TO_0_34_EQ_0_0_ETC___d2092 =
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q9 ==
|
|
m_tlb_m_entryVec_6[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_7_46_BITS_1_TO_0_50_EQ_0_0_ETC___d2102 =
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q10 ==
|
|
m_tlb_m_entryVec_7[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_8_62_BITS_1_TO_0_66_EQ_0_1_ETC___d2112 =
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q11 ==
|
|
m_tlb_m_entryVec_8[79:53] ;
|
|
assign IF_m_tlb_m_entryVec_9_78_BITS_1_TO_0_82_EQ_0_1_ETC___d2122 =
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q12 ==
|
|
m_tlb_m_entryVec_9[79:53] ;
|
|
assign IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d17 =
|
|
m_tlb_m_updRepIdx_lat_1$whas ?
|
|
m_tlb_m_updRepIdx_lat_1$wget[5] :
|
|
!m_tlb_m_updRepIdx_lat_0$whas && m_tlb_m_updRepIdx_rl[5] ;
|
|
assign IF_m_tlb_m_updRepIdx_lat_1_whas_THEN_m_tlb_m_u_ETC___d27 =
|
|
m_tlb_m_updRepIdx_lat_1$whas ?
|
|
m_tlb_m_updRepIdx_lat_1$wget[4:0] :
|
|
(m_tlb_m_updRepIdx_lat_0$whas ?
|
|
5'b01010 :
|
|
m_tlb_m_updRepIdx_rl[4:0]) ;
|
|
assign IF_m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec__ETC___d1613 =
|
|
(m_tlb_m_validVec_0 && m_tlb_m_validVec_1) ?
|
|
(m_tlb_m_validVec_2 ? 5'd3 : 5'd2) :
|
|
(m_tlb_m_validVec_0 ? 5'd1 : 5'd0) ;
|
|
assign IF_m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec__ETC___d1614 =
|
|
(m_tlb_m_validVec_0 && m_tlb_m_validVec_1 &&
|
|
m_tlb_m_validVec_2 &&
|
|
m_tlb_m_validVec_3) ?
|
|
IF_m_tlb_m_validVec_4_95_AND_m_tlb_m_validVec__ETC___d1610 :
|
|
IF_m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec__ETC___d1613 ;
|
|
assign IF_m_tlb_m_validVec_12_23_AND_m_tlb_m_validVec_ETC___d1603 =
|
|
(m_tlb_m_validVec_12 && m_tlb_m_validVec_13) ?
|
|
(m_tlb_m_validVec_14 ? 5'd15 : 5'd14) :
|
|
(m_tlb_m_validVec_12 ? 5'd13 : 5'd12) ;
|
|
assign IF_m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_ETC___d1598 =
|
|
(m_tlb_m_validVec_16 && m_tlb_m_validVec_17) ?
|
|
(m_tlb_m_validVec_18 ? 5'd19 : 5'd18) :
|
|
(m_tlb_m_validVec_16 ? 5'd17 : 5'd16) ;
|
|
assign IF_m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_ETC___d1599 =
|
|
(m_tlb_m_validVec_16 && m_tlb_m_validVec_17 &&
|
|
m_tlb_m_validVec_18 &&
|
|
m_tlb_m_validVec_19) ?
|
|
IF_m_tlb_m_validVec_20_051_AND_m_tlb_m_validVe_ETC___d1595 :
|
|
IF_m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_ETC___d1598 ;
|
|
assign IF_m_tlb_m_validVec_20_051_AND_m_tlb_m_validVe_ETC___d1595 =
|
|
(m_tlb_m_validVec_20 && m_tlb_m_validVec_21) ?
|
|
(m_tlb_m_validVec_22 ? 5'd23 : 5'd22) :
|
|
(m_tlb_m_validVec_20 ? 5'd21 : 5'd20) ;
|
|
assign IF_m_tlb_m_validVec_24_115_AND_m_tlb_m_validVe_ETC___d1591 =
|
|
(m_tlb_m_validVec_24 && m_tlb_m_validVec_25) ?
|
|
(m_tlb_m_validVec_26 ? 5'd27 : 5'd26) :
|
|
(m_tlb_m_validVec_24 ? 5'd25 : 5'd24) ;
|
|
assign IF_m_tlb_m_validVec_24_115_AND_m_tlb_m_validVe_ETC___d1592 =
|
|
(m_tlb_m_validVec_24 && m_tlb_m_validVec_25 &&
|
|
m_tlb_m_validVec_26 &&
|
|
m_tlb_m_validVec_27) ?
|
|
IF_m_tlb_m_validVec_28_179_AND_m_tlb_m_validVe_ETC___d1588 :
|
|
IF_m_tlb_m_validVec_24_115_AND_m_tlb_m_validVe_ETC___d1591 ;
|
|
assign IF_m_tlb_m_validVec_28_179_AND_m_tlb_m_validVe_ETC___d1588 =
|
|
(m_tlb_m_validVec_28 && m_tlb_m_validVec_29) ?
|
|
(m_tlb_m_validVec_30 ? 5'd31 : 5'd30) :
|
|
(m_tlb_m_validVec_28 ? 5'd29 : 5'd28) ;
|
|
assign IF_m_tlb_m_validVec_4_95_AND_m_tlb_m_validVec__ETC___d1610 =
|
|
(m_tlb_m_validVec_4 && m_tlb_m_validVec_5) ?
|
|
(m_tlb_m_validVec_6 ? 5'd7 : 5'd6) :
|
|
(m_tlb_m_validVec_4 ? 5'd5 : 5'd4) ;
|
|
assign IF_m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec__ETC___d1606 =
|
|
(m_tlb_m_validVec_8 && m_tlb_m_validVec_9) ?
|
|
(m_tlb_m_validVec_10 ? 5'd11 : 5'd10) :
|
|
(m_tlb_m_validVec_8 ? 5'd9 : 5'd8) ;
|
|
assign IF_m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec__ETC___d1607 =
|
|
(m_tlb_m_validVec_8 && m_tlb_m_validVec_9 &&
|
|
m_tlb_m_validVec_10 &&
|
|
m_tlb_m_validVec_11) ?
|
|
IF_m_tlb_m_validVec_12_23_AND_m_tlb_m_validVec_ETC___d1603 :
|
|
IF_m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec__ETC___d1606 ;
|
|
assign INV_n__read1151__q37 = ~n__read__h51151 ;
|
|
assign NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2852 =
|
|
level__h87878 != 2'd0 &&
|
|
((level__h87878 == 2'd1) ?
|
|
ppn__h92833[8:0] != 9'd0 :
|
|
level__h87878 != 2'd2 || ppn__h92833[17:0] != 18'd0) ||
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 &&
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 ;
|
|
assign NOT_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT__ETC___d2859 =
|
|
level__h87878 != 2'd0 &&
|
|
((level__h87878 == 2'd1) ?
|
|
ppn__h92833[8:0] != 9'd0 :
|
|
level__h87878 != 2'd2 || ppn__h92833[17:0] != 18'd0) ||
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 ;
|
|
assign NOT_SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BI_ETC___d707 =
|
|
(!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_6_58_m_ETC___d661 &&
|
|
m_vm_info[45]) &&
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d706 ;
|
|
assign NOT_SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_09_ETC___d3831 =
|
|
{ !SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101,
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101 ?
|
|
SEL_ARR_m_pendInst_0_18_BITS_462_TO_458_103_m__ETC___d3108 :
|
|
{ 1'h0,
|
|
SEL_ARR_m_pendInst_0_18_BITS_461_TO_458_109_m__ETC___d3114 },
|
|
SEL_ARR_m_pendInst_0_18_BIT_457_117_m_pendInst_ETC___d3122,
|
|
SEL_ARR_m_pendInst_0_18_BIT_456_123_m_pendInst_ETC___d3128,
|
|
SEL_ARR_m_pendInst_0_18_BIT_455_130_m_pendInst_ETC___d3135,
|
|
SEL_ARR_m_pendInst_0_18_BIT_454_136_m_pendInst_ETC___d3141,
|
|
SEL_ARR_m_pendInst_0_18_BIT_453_143_m_pendInst_ETC___d3148,
|
|
SEL_ARR_m_pendInst_0_18_BIT_452_149_m_pendInst_ETC___d3154,
|
|
SEL_ARR_m_pendInst_0_18_BIT_451_156_m_pendInst_ETC___d3161,
|
|
SEL_ARR_m_pendInst_0_18_BIT_450_162_m_pendInst_ETC___d3167,
|
|
SEL_ARR_m_pendInst_0_18_BIT_449_169_m_pendInst_ETC___d3174,
|
|
SEL_ARR_m_pendInst_0_18_BIT_448_175_m_pendInst_ETC___d3180,
|
|
SEL_ARR_m_pendInst_0_18_BIT_447_182_m_pendInst_ETC___d3187,
|
|
SEL_ARR_m_pendInst_0_18_BIT_446_188_m_pendInst_ETC___d3193,
|
|
SEL_ARR_m_pendInst_0_18_BIT_445_195_m_pendInst_ETC___d3200,
|
|
SEL_ARR_m_pendInst_0_18_BIT_444_201_m_pendInst_ETC___d3206,
|
|
SEL_ARR_m_pendInst_0_18_BIT_443_208_m_pendInst_ETC___d3213,
|
|
SEL_ARR_m_pendInst_0_18_BIT_442_214_m_pendInst_ETC___d3219,
|
|
SEL_ARR_m_pendInst_0_18_BIT_441_221_m_pendInst_ETC___d3226,
|
|
SEL_ARR_m_pendInst_0_18_BITS_440_TO_375_794_m__ETC___d3227,
|
|
SEL_ARR_m_pendInst_0_18_BITS_374_TO_361_228_m__ETC___d3233,
|
|
SEL_ARR_m_pendInst_0_18_BITS_360_TO_357_234_m__ETC___d3239,
|
|
SEL_ARR_m_pendInst_0_18_BIT_356_240_m_pendInst_ETC___d3245,
|
|
SEL_ARR_m_pendInst_0_18_BIT_355_246_m_pendInst_ETC___d3251,
|
|
SEL_ARR_m_pendInst_0_18_BIT_354_252_m_pendInst_ETC___d3257,
|
|
SEL_ARR_m_pendInst_0_18_BIT_353_258_m_pendInst_ETC___d3263,
|
|
SEL_ARR_m_pendInst_0_18_BIT_352_264_m_pendInst_ETC___d3269,
|
|
SEL_ARR_m_pendInst_0_18_BIT_351_270_m_pendInst_ETC___d3275,
|
|
SEL_ARR_m_pendInst_0_18_BIT_350_276_m_pendInst_ETC___d3281,
|
|
SEL_ARR_m_pendInst_0_18_BIT_349_282_m_pendInst_ETC___d3287,
|
|
SEL_ARR_m_pendInst_0_18_BIT_348_288_m_pendInst_ETC___d3293,
|
|
SEL_ARR_m_pendInst_0_18_BIT_347_294_m_pendInst_ETC___d3299,
|
|
SEL_ARR_m_pendInst_0_18_BIT_346_300_m_pendInst_ETC___d3305,
|
|
SEL_ARR_m_pendInst_0_18_BIT_345_306_m_pendInst_ETC___d3311,
|
|
SEL_ARR_m_pendInst_0_18_BIT_344_318_m_pendInst_ETC___d3323,
|
|
SEL_ARR_m_pendInst_0_18_BITS_343_TO_342_324_m__ETC___d3329,
|
|
SEL_ARR_m_pendInst_0_18_BITS_341_TO_324_330_m__ETC___d3335,
|
|
SEL_ARR_m_pendInst_0_18_BIT_323_336_m_pendInst_ETC___d3341,
|
|
SEL_ARR_m_pendInst_0_18_BITS_322_TO_317_342_m__ETC___d3347,
|
|
x__h102032,
|
|
x__h102041,
|
|
SEL_ARR_m_pendInst_0_18_BITS_288_TO_286_365_m__ETC___d3370,
|
|
SEL_ARR_m_pendInst_0_18_BIT_285_371_m_pendInst_ETC___d3376,
|
|
SEL_ARR_m_pendInst_0_18_BIT_284_377_m_pendInst_ETC___d3382,
|
|
SEL_ARR_m_pendInst_0_18_BIT_283_383_m_pendInst_ETC___d3388,
|
|
SEL_ARR_m_pendInst_0_18_BITS_282_TO_281_389_m__ETC___d3394,
|
|
SEL_ARR_m_pendInst_0_18_BITS_280_TO_279_395_m__ETC___d3400,
|
|
SEL_ARR_m_pendInst_0_18_BIT_278_404_m_pendInst_ETC___d3409,
|
|
!SEL_ARR_NOT_m_pendInst_0_18_BIT_277_410_411_NO_ETC___d3419,
|
|
SEL_ARR_m_pendInst_0_18_BITS_276_TO_271_421_m__ETC___d3426,
|
|
IF_SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266__ETC___d3775,
|
|
!SEL_ARR_NOT_m_pendInst_0_18_BIT_265_778_779_NO_ETC___d3787,
|
|
x__h105527,
|
|
x__h105564,
|
|
SEL_ARR_m_pendInst_0_18_BITS_135_TO_130_801_m__ETC___d3806,
|
|
x__h105582,
|
|
x__h105591,
|
|
SEL_ARR_m_pendInst_0_18_BIT_0_819_m_pendInst_1_ETC___d3824 } ;
|
|
assign NOT_SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_58_ETC___d2806 =
|
|
(!SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 ||
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 &&
|
|
m_vm_info[45]) &&
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2805 ;
|
|
assign NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1834 =
|
|
level__h38292 != 2'd0 &&
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[8:0] !=
|
|
9'd0 :
|
|
level__h38292 != 2'd2 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696 &&
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 ||
|
|
!m_vm_info[46] ;
|
|
assign NOT_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_ETC___d1842 =
|
|
level__h38292 != 2'd0 &&
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[8:0] !=
|
|
9'd0 :
|
|
level__h38292 != 2'd2 ||
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[17:0] !=
|
|
18'd0) ||
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 ||
|
|
!m_vm_info[46] ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1361 =
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684 !=
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2 ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1373 =
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 !=
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q1 ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1715 =
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 &&
|
|
(!m_tlb_m_validVec_0 ||
|
|
NOT_m_tlb_m_entryVec_0_25_BITS_79_TO_53_26_EQ__ETC___d744) &&
|
|
NOT_m_tlb_m_validVec_1_47_48_OR_NOT_m_tlb_m_en_ETC___d1713 ;
|
|
assign NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 =
|
|
(SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd1 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd3 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 !=
|
|
3'd4 ||
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_10_ETC___d641) &&
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_9__ETC___d649 &&
|
|
IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d718 ;
|
|
assign NOT_m_ldTransRsFromPQ_empty_68_05_AND_NOT_m_pe_ETC___d1331 =
|
|
!m_ldTransRsFromPQ_empty && m_pendWait_0[3:2] != 2'd0 &&
|
|
m_pendWait_0[3:2] != 2'd1 &&
|
|
m_pendWait_0_66_BITS_1_TO_0_309_EQ_SEL_ARR_m_l_ETC___d1310 &&
|
|
idx__h37917 != 2'd0 ||
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
m_pendWait_1_73_BITS_3_TO_2_74_EQ_0_75_OR_m_pe_ETC___d1306 ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1924 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) &&
|
|
(!m_pendValid_1_rl || m_pendWait_1[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_1) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1928 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1924 &&
|
|
(!m_pendValid_2_rl || m_pendWait_2[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_2) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2950 =
|
|
(!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) &&
|
|
(!m_pendValid_1_rl || m_pendWait_1[3:2] != 2'd0 ||
|
|
m_pendPoisoned_1) ;
|
|
assign NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2952 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2950 &&
|
|
(!m_pendValid_2_rl || m_pendWait_2[3:2] != 2'd0 ||
|
|
m_pendPoisoned_2) ;
|
|
assign NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1892 =
|
|
m_pendWait_0[3:2] != 2'd0 && m_pendWait_0[3:2] != 2'd1 &&
|
|
m_pendWait_0_66_BITS_1_TO_0_309_EQ_SEL_ARR_m_l_ETC___d1310 &&
|
|
idx__h37917 != 2'd0 ||
|
|
m_pendWait_1[3:2] != 2'd0 && m_pendWait_1[3:2] != 2'd1 &&
|
|
m_pendWait_1_73_BITS_1_TO_0_301_EQ_SEL_ARR_m_l_ETC___d1302 &&
|
|
idx__h37917 != 2'd1 ;
|
|
assign NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1900 =
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1892 ||
|
|
m_pendWait_2[3:2] != 2'd0 && m_pendWait_2[3:2] != 2'd1 &&
|
|
m_pendWait_2_80_BITS_1_TO_0_321_EQ_SEL_ARR_m_l_ETC___d1322 &&
|
|
idx__h37917 != 2'd2 ||
|
|
m_pendWait_3[3:2] != 2'd0 && m_pendWait_3[3:2] != 2'd1 &&
|
|
m_pendWait_3_87_BITS_1_TO_0_340_EQ_SEL_ARR_m_l_ETC___d1341 &&
|
|
idx__h37917 != 2'd3 ;
|
|
assign NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_71__ETC___d2903 =
|
|
(m_pendWait_0[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2879) &&
|
|
(m_pendWait_1[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2882) &&
|
|
(m_pendWait_2[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2886) ;
|
|
assign NOT_m_tlb_m_entryVec_0_25_BITS_79_TO_53_26_EQ__ETC___d744 =
|
|
m_tlb_m_entryVec_0[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_0[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_0[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_10_94_BITS_79_TO_53_95_EQ_ETC___d905 =
|
|
m_tlb_m_entryVec_10[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_10[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_10[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_11_10_BITS_79_TO_53_11_EQ_ETC___d921 =
|
|
m_tlb_m_entryVec_11[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_11[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_11[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_12_26_BITS_79_TO_53_27_EQ_ETC___d937 =
|
|
m_tlb_m_entryVec_12[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_12[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_12[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d1405 =
|
|
NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d953 &&
|
|
NOT_m_tlb_m_entryVec_14_58_BITS_79_TO_53_59_EQ_ETC___d969 &&
|
|
NOT_m_tlb_m_entryVec_15_74_BITS_79_TO_53_75_EQ_ETC___d985 &&
|
|
NOT_m_tlb_m_entryVec_16_90_BITS_79_TO_53_91_EQ_ETC___d1001 &&
|
|
NOT_m_tlb_m_entryVec_17_006_BITS_79_TO_53_007__ETC___d1017 &&
|
|
NOT_m_tlb_m_entryVec_18_022_BITS_79_TO_53_023__ETC___d1033 &&
|
|
NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1399 ;
|
|
assign NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d953 =
|
|
m_tlb_m_entryVec_13[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_13[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_13[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_14_58_BITS_79_TO_53_59_EQ_ETC___d969 =
|
|
m_tlb_m_entryVec_14[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_14[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_14[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_15_74_BITS_79_TO_53_75_EQ_ETC___d985 =
|
|
m_tlb_m_entryVec_15[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_15[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_15[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_16_90_BITS_79_TO_53_91_EQ_ETC___d1001 =
|
|
m_tlb_m_entryVec_16[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_16[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_16[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_17_006_BITS_79_TO_53_007__ETC___d1017 =
|
|
m_tlb_m_entryVec_17[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_17[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_17[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_18_022_BITS_79_TO_53_023__ETC___d1033 =
|
|
m_tlb_m_entryVec_18[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_18[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_18[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1049 =
|
|
m_tlb_m_entryVec_19[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_19[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_19[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1399 =
|
|
NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1049 &&
|
|
NOT_m_tlb_m_entryVec_20_054_BITS_79_TO_53_055__ETC___d1065 &&
|
|
NOT_m_tlb_m_entryVec_21_070_BITS_79_TO_53_071__ETC___d1081 &&
|
|
NOT_m_tlb_m_entryVec_22_086_BITS_79_TO_53_087__ETC___d1097 &&
|
|
NOT_m_tlb_m_entryVec_23_102_BITS_79_TO_53_103__ETC___d1113 &&
|
|
NOT_m_tlb_m_entryVec_24_118_BITS_79_TO_53_119__ETC___d1129 &&
|
|
NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1393 ;
|
|
assign NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d1417 =
|
|
NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d761 &&
|
|
NOT_m_tlb_m_entryVec_2_66_BITS_79_TO_53_67_EQ__ETC___d777 &&
|
|
NOT_m_tlb_m_entryVec_3_82_BITS_79_TO_53_83_EQ__ETC___d793 &&
|
|
NOT_m_tlb_m_entryVec_4_98_BITS_79_TO_53_99_EQ__ETC___d809 &&
|
|
NOT_m_tlb_m_entryVec_5_14_BITS_79_TO_53_15_EQ__ETC___d825 &&
|
|
NOT_m_tlb_m_entryVec_6_30_BITS_79_TO_53_31_EQ__ETC___d841 &&
|
|
NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d1411 ;
|
|
assign NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d761 =
|
|
m_tlb_m_entryVec_1[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_1[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_1[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_20_054_BITS_79_TO_53_055__ETC___d1065 =
|
|
m_tlb_m_entryVec_20[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_20[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_20[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_21_070_BITS_79_TO_53_071__ETC___d1081 =
|
|
m_tlb_m_entryVec_21[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_21[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_21[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_22_086_BITS_79_TO_53_087__ETC___d1097 =
|
|
m_tlb_m_entryVec_22[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_22[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_22[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_23_102_BITS_79_TO_53_103__ETC___d1113 =
|
|
m_tlb_m_entryVec_23[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_23[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_23[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_24_118_BITS_79_TO_53_119__ETC___d1129 =
|
|
m_tlb_m_entryVec_24[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_24[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_24[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1145 =
|
|
m_tlb_m_entryVec_25[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_25[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_25[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1393 =
|
|
NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1145 &&
|
|
NOT_m_tlb_m_entryVec_26_150_BITS_79_TO_53_151__ETC___d1161 &&
|
|
NOT_m_tlb_m_entryVec_27_166_BITS_79_TO_53_167__ETC___d1177 &&
|
|
NOT_m_tlb_m_entryVec_28_182_BITS_79_TO_53_183__ETC___d1193 &&
|
|
NOT_m_tlb_m_entryVec_29_198_BITS_79_TO_53_199__ETC___d1209 &&
|
|
NOT_m_tlb_m_entryVec_30_214_BITS_79_TO_53_215__ETC___d1225 &&
|
|
NOT_m_tlb_m_entryVec_31_376_BITS_79_TO_53_377__ETC___d1387 ;
|
|
assign NOT_m_tlb_m_entryVec_26_150_BITS_79_TO_53_151__ETC___d1161 =
|
|
m_tlb_m_entryVec_26[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_26[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_26[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_27_166_BITS_79_TO_53_167__ETC___d1177 =
|
|
m_tlb_m_entryVec_27[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_27[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_27[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_28_182_BITS_79_TO_53_183__ETC___d1193 =
|
|
m_tlb_m_entryVec_28[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_28[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_28[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_29_198_BITS_79_TO_53_199__ETC___d1209 =
|
|
m_tlb_m_entryVec_29[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_29[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_29[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_2_66_BITS_79_TO_53_67_EQ__ETC___d777 =
|
|
m_tlb_m_entryVec_2[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_2[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_2[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_30_214_BITS_79_TO_53_215__ETC___d1225 =
|
|
m_tlb_m_entryVec_30[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_30[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_30[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_31_376_BITS_79_TO_53_377__ETC___d1387 =
|
|
m_tlb_m_entryVec_31[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_31[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_31[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_3_82_BITS_79_TO_53_83_EQ__ETC___d793 =
|
|
m_tlb_m_entryVec_3[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_3[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_3[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_4_98_BITS_79_TO_53_99_EQ__ETC___d809 =
|
|
m_tlb_m_entryVec_4[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_4[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_4[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_5_14_BITS_79_TO_53_15_EQ__ETC___d825 =
|
|
m_tlb_m_entryVec_5[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_5[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_5[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_6_30_BITS_79_TO_53_31_EQ__ETC___d841 =
|
|
m_tlb_m_entryVec_6[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_6[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_6[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d1411 =
|
|
NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d857 &&
|
|
NOT_m_tlb_m_entryVec_8_62_BITS_79_TO_53_63_EQ__ETC___d873 &&
|
|
NOT_m_tlb_m_entryVec_9_78_BITS_79_TO_53_79_EQ__ETC___d889 &&
|
|
NOT_m_tlb_m_entryVec_10_94_BITS_79_TO_53_95_EQ_ETC___d905 &&
|
|
NOT_m_tlb_m_entryVec_11_10_BITS_79_TO_53_11_EQ_ETC___d921 &&
|
|
NOT_m_tlb_m_entryVec_12_26_BITS_79_TO_53_27_EQ_ETC___d937 &&
|
|
NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d1405 ;
|
|
assign NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d857 =
|
|
m_tlb_m_entryVec_7[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_7[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_7[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_8_62_BITS_79_TO_53_63_EQ__ETC___d873 =
|
|
m_tlb_m_entryVec_8[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_8[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_8[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_entryVec_9_78_BITS_79_TO_53_79_EQ__ETC___d889 =
|
|
m_tlb_m_entryVec_9[79:53] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 ||
|
|
m_tlb_m_entryVec_9[1:0] != level__h38292 ||
|
|
m_tlb_m_entryVec_9[6] !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 ;
|
|
assign NOT_m_tlb_m_flushEn_whas__2_3_AND_IF_m_tlb_m_u_ETC___d721 =
|
|
!CAN_FIRE_RL_m_doStartFlush &&
|
|
(m_tlb_m_updRepIdx_lat_0$whas || !m_tlb_m_updRepIdx_rl[5]) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035 =
|
|
!m_tlb_m_validVec_0 ||
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 !=
|
|
m_tlb_m_entryVec_0[79:53] ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2035 &&
|
|
(!m_tlb_m_validVec_1 ||
|
|
!IF_m_tlb_m_entryVec_1_50_BITS_1_TO_0_54_EQ_0_0_ETC___d2042) &&
|
|
(!m_tlb_m_validVec_2 ||
|
|
!IF_m_tlb_m_entryVec_2_66_BITS_1_TO_0_70_EQ_0_0_ETC___d2052) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2055 &&
|
|
(!m_tlb_m_validVec_3 ||
|
|
!IF_m_tlb_m_entryVec_3_82_BITS_1_TO_0_86_EQ_0_0_ETC___d2062) &&
|
|
(!m_tlb_m_validVec_4 ||
|
|
!IF_m_tlb_m_entryVec_4_98_BITS_1_TO_0_02_EQ_0_0_ETC___d2072) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2075 &&
|
|
(!m_tlb_m_validVec_5 ||
|
|
!IF_m_tlb_m_entryVec_5_14_BITS_1_TO_0_18_EQ_0_0_ETC___d2082) &&
|
|
(!m_tlb_m_validVec_6 ||
|
|
!IF_m_tlb_m_entryVec_6_30_BITS_1_TO_0_34_EQ_0_0_ETC___d2092) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2095 &&
|
|
(!m_tlb_m_validVec_7 ||
|
|
!IF_m_tlb_m_entryVec_7_46_BITS_1_TO_0_50_EQ_0_0_ETC___d2102) &&
|
|
(!m_tlb_m_validVec_8 ||
|
|
!IF_m_tlb_m_entryVec_8_62_BITS_1_TO_0_66_EQ_0_1_ETC___d2112) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2115 &&
|
|
(!m_tlb_m_validVec_9 ||
|
|
!IF_m_tlb_m_entryVec_9_78_BITS_1_TO_0_82_EQ_0_1_ETC___d2122) &&
|
|
(!m_tlb_m_validVec_10 ||
|
|
!IF_m_tlb_m_entryVec_10_94_BITS_1_TO_0_98_EQ_0__ETC___d2132) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2135 &&
|
|
(!m_tlb_m_validVec_11 ||
|
|
!IF_m_tlb_m_entryVec_11_10_BITS_1_TO_0_14_EQ_0__ETC___d2142) &&
|
|
(!m_tlb_m_validVec_12 ||
|
|
!IF_m_tlb_m_entryVec_12_26_BITS_1_TO_0_30_EQ_0__ETC___d2152) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2155 &&
|
|
(!m_tlb_m_validVec_13 ||
|
|
!IF_m_tlb_m_entryVec_13_42_BITS_1_TO_0_46_EQ_0__ETC___d2162) &&
|
|
(!m_tlb_m_validVec_14 ||
|
|
!IF_m_tlb_m_entryVec_14_58_BITS_1_TO_0_62_EQ_0__ETC___d2172) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2175 &&
|
|
(!m_tlb_m_validVec_15 ||
|
|
!IF_m_tlb_m_entryVec_15_74_BITS_1_TO_0_78_EQ_0__ETC___d2182) &&
|
|
(!m_tlb_m_validVec_16 ||
|
|
!IF_m_tlb_m_entryVec_16_90_BITS_1_TO_0_94_EQ_0__ETC___d2192) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2195 &&
|
|
(!m_tlb_m_validVec_17 ||
|
|
!IF_m_tlb_m_entryVec_17_006_BITS_1_TO_0_010_EQ__ETC___d2202) &&
|
|
(!m_tlb_m_validVec_18 ||
|
|
!IF_m_tlb_m_entryVec_18_022_BITS_1_TO_0_026_EQ__ETC___d2212) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2215 &&
|
|
(!m_tlb_m_validVec_19 ||
|
|
!IF_m_tlb_m_entryVec_19_038_BITS_1_TO_0_042_EQ__ETC___d2222) &&
|
|
(!m_tlb_m_validVec_20 ||
|
|
!IF_m_tlb_m_entryVec_20_054_BITS_1_TO_0_058_EQ__ETC___d2232) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2235 &&
|
|
(!m_tlb_m_validVec_21 ||
|
|
!IF_m_tlb_m_entryVec_21_070_BITS_1_TO_0_074_EQ__ETC___d2242) &&
|
|
(!m_tlb_m_validVec_22 ||
|
|
!IF_m_tlb_m_entryVec_22_086_BITS_1_TO_0_090_EQ__ETC___d2252) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2255 &&
|
|
(!m_tlb_m_validVec_23 ||
|
|
!IF_m_tlb_m_entryVec_23_102_BITS_1_TO_0_106_EQ__ETC___d2262) &&
|
|
(!m_tlb_m_validVec_24 ||
|
|
!IF_m_tlb_m_entryVec_24_118_BITS_1_TO_0_122_EQ__ETC___d2272) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2275 &&
|
|
(!m_tlb_m_validVec_25 ||
|
|
!IF_m_tlb_m_entryVec_25_134_BITS_1_TO_0_138_EQ__ETC___d2282) &&
|
|
(!m_tlb_m_validVec_26 ||
|
|
!IF_m_tlb_m_entryVec_26_150_BITS_1_TO_0_154_EQ__ETC___d2292) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2295 &&
|
|
(!m_tlb_m_validVec_27 ||
|
|
!IF_m_tlb_m_entryVec_27_166_BITS_1_TO_0_170_EQ__ETC___d2302) &&
|
|
(!m_tlb_m_validVec_28 ||
|
|
!IF_m_tlb_m_entryVec_28_182_BITS_1_TO_0_186_EQ__ETC___d2312) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2315 &&
|
|
(!m_tlb_m_validVec_29 ||
|
|
!IF_m_tlb_m_entryVec_29_198_BITS_1_TO_0_202_EQ__ETC___d2322) &&
|
|
(!m_tlb_m_validVec_30 ||
|
|
!IF_m_tlb_m_entryVec_30_214_BITS_1_TO_0_218_EQ__ETC___d2332) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_376_BITS_1_TO_0_380_EQ__ETC___d2342) &&
|
|
(m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2888 ||
|
|
m_pendWait_3[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2890) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_376_BITS_1_TO_0_380_EQ__ETC___d2342) &&
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_71__ETC___d2903 &&
|
|
(m_pendWait_3[3:2] != 2'd1 ||
|
|
!procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2890) ;
|
|
assign NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_va_ETC___d1561 =
|
|
!m_tlb_m_validVec_0 || !m_tlb_m_validVec_1 ||
|
|
!m_tlb_m_validVec_2 ||
|
|
!m_tlb_m_validVec_3 ||
|
|
!m_tlb_m_validVec_4 ||
|
|
!m_tlb_m_validVec_5 ||
|
|
!m_tlb_m_validVec_6 ||
|
|
!m_tlb_m_validVec_7 ;
|
|
assign NOT_m_tlb_m_validVec_11_07_08_OR_NOT_m_tlb_m_e_ETC___d1703 =
|
|
(!m_tlb_m_validVec_11 ||
|
|
NOT_m_tlb_m_entryVec_11_10_BITS_79_TO_53_11_EQ_ETC___d921) &&
|
|
(!m_tlb_m_validVec_12 ||
|
|
NOT_m_tlb_m_entryVec_12_26_BITS_79_TO_53_27_EQ_ETC___d937) &&
|
|
NOT_m_tlb_m_validVec_13_39_40_OR_NOT_m_tlb_m_e_ETC___d1701 ;
|
|
assign NOT_m_tlb_m_validVec_13_39_40_OR_NOT_m_tlb_m_e_ETC___d1701 =
|
|
(!m_tlb_m_validVec_13 ||
|
|
NOT_m_tlb_m_entryVec_13_42_BITS_79_TO_53_43_EQ_ETC___d953) &&
|
|
(!m_tlb_m_validVec_14 ||
|
|
NOT_m_tlb_m_entryVec_14_58_BITS_79_TO_53_59_EQ_ETC___d969) &&
|
|
NOT_m_tlb_m_validVec_15_71_72_OR_NOT_m_tlb_m_e_ETC___d1699 ;
|
|
assign NOT_m_tlb_m_validVec_15_71_72_OR_NOT_m_tlb_m_e_ETC___d1699 =
|
|
(!m_tlb_m_validVec_15 ||
|
|
NOT_m_tlb_m_entryVec_15_74_BITS_79_TO_53_75_EQ_ETC___d985) &&
|
|
(!m_tlb_m_validVec_16 ||
|
|
NOT_m_tlb_m_entryVec_16_90_BITS_79_TO_53_91_EQ_ETC___d1001) &&
|
|
NOT_m_tlb_m_validVec_17_003_004_OR_NOT_m_tlb_m_ETC___d1697 ;
|
|
assign NOT_m_tlb_m_validVec_16_87_88_OR_NOT_m_tlb_m_v_ETC___d1576 =
|
|
!m_tlb_m_validVec_16 || !m_tlb_m_validVec_17 ||
|
|
!m_tlb_m_validVec_18 ||
|
|
!m_tlb_m_validVec_19 ||
|
|
!m_tlb_m_validVec_20 ||
|
|
!m_tlb_m_validVec_21 ||
|
|
!m_tlb_m_validVec_22 ||
|
|
!m_tlb_m_validVec_23 ;
|
|
assign NOT_m_tlb_m_validVec_17_003_004_OR_NOT_m_tlb_m_ETC___d1697 =
|
|
(!m_tlb_m_validVec_17 ||
|
|
NOT_m_tlb_m_entryVec_17_006_BITS_79_TO_53_007__ETC___d1017) &&
|
|
(!m_tlb_m_validVec_18 ||
|
|
NOT_m_tlb_m_entryVec_18_022_BITS_79_TO_53_023__ETC___d1033) &&
|
|
NOT_m_tlb_m_validVec_19_035_036_OR_NOT_m_tlb_m_ETC___d1695 ;
|
|
assign NOT_m_tlb_m_validVec_19_035_036_OR_NOT_m_tlb_m_ETC___d1695 =
|
|
(!m_tlb_m_validVec_19 ||
|
|
NOT_m_tlb_m_entryVec_19_038_BITS_79_TO_53_039__ETC___d1049) &&
|
|
(!m_tlb_m_validVec_20 ||
|
|
NOT_m_tlb_m_entryVec_20_054_BITS_79_TO_53_055__ETC___d1065) &&
|
|
NOT_m_tlb_m_validVec_21_067_068_OR_NOT_m_tlb_m_ETC___d1693 ;
|
|
assign NOT_m_tlb_m_validVec_1_47_48_OR_NOT_m_tlb_m_en_ETC___d1713 =
|
|
(!m_tlb_m_validVec_1 ||
|
|
NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d761) &&
|
|
(!m_tlb_m_validVec_2 ||
|
|
NOT_m_tlb_m_entryVec_2_66_BITS_79_TO_53_67_EQ__ETC___d777) &&
|
|
NOT_m_tlb_m_validVec_3_79_80_OR_NOT_m_tlb_m_en_ETC___d1711 ;
|
|
assign NOT_m_tlb_m_validVec_21_067_068_OR_NOT_m_tlb_m_ETC___d1693 =
|
|
(!m_tlb_m_validVec_21 ||
|
|
NOT_m_tlb_m_entryVec_21_070_BITS_79_TO_53_071__ETC___d1081) &&
|
|
(!m_tlb_m_validVec_22 ||
|
|
NOT_m_tlb_m_entryVec_22_086_BITS_79_TO_53_087__ETC___d1097) &&
|
|
NOT_m_tlb_m_validVec_23_099_100_OR_NOT_m_tlb_m_ETC___d1691 ;
|
|
assign NOT_m_tlb_m_validVec_23_099_100_OR_NOT_m_tlb_m_ETC___d1691 =
|
|
(!m_tlb_m_validVec_23 ||
|
|
NOT_m_tlb_m_entryVec_23_102_BITS_79_TO_53_103__ETC___d1113) &&
|
|
(!m_tlb_m_validVec_24 ||
|
|
NOT_m_tlb_m_entryVec_24_118_BITS_79_TO_53_119__ETC___d1129) &&
|
|
NOT_m_tlb_m_validVec_25_131_132_OR_NOT_m_tlb_m_ETC___d1689 ;
|
|
assign NOT_m_tlb_m_validVec_24_115_116_OR_NOT_m_tlb_m_ETC___d1583 =
|
|
!m_tlb_m_validVec_24 || !m_tlb_m_validVec_25 ||
|
|
!m_tlb_m_validVec_26 ||
|
|
!m_tlb_m_validVec_27 ||
|
|
!m_tlb_m_validVec_28 ||
|
|
!m_tlb_m_validVec_29 ||
|
|
!m_tlb_m_validVec_30 ||
|
|
!m_tlb_m_validVec_31 ;
|
|
assign NOT_m_tlb_m_validVec_25_131_132_OR_NOT_m_tlb_m_ETC___d1689 =
|
|
(!m_tlb_m_validVec_25 ||
|
|
NOT_m_tlb_m_entryVec_25_134_BITS_79_TO_53_135__ETC___d1145) &&
|
|
(!m_tlb_m_validVec_26 ||
|
|
NOT_m_tlb_m_entryVec_26_150_BITS_79_TO_53_151__ETC___d1161) &&
|
|
NOT_m_tlb_m_validVec_27_163_164_OR_NOT_m_tlb_m_ETC___d1687 ;
|
|
assign NOT_m_tlb_m_validVec_27_163_164_OR_NOT_m_tlb_m_ETC___d1687 =
|
|
(!m_tlb_m_validVec_27 ||
|
|
NOT_m_tlb_m_entryVec_27_166_BITS_79_TO_53_167__ETC___d1177) &&
|
|
(!m_tlb_m_validVec_28 ||
|
|
NOT_m_tlb_m_entryVec_28_182_BITS_79_TO_53_183__ETC___d1193) &&
|
|
NOT_m_tlb_m_validVec_29_195_196_OR_NOT_m_tlb_m_ETC___d1685 ;
|
|
assign NOT_m_tlb_m_validVec_29_195_196_OR_NOT_m_tlb_m_ETC___d1685 =
|
|
(!m_tlb_m_validVec_29 ||
|
|
NOT_m_tlb_m_entryVec_29_198_BITS_79_TO_53_199__ETC___d1209) &&
|
|
(!m_tlb_m_validVec_30 ||
|
|
NOT_m_tlb_m_entryVec_30_214_BITS_79_TO_53_215__ETC___d1225) &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
NOT_m_tlb_m_entryVec_31_376_BITS_79_TO_53_377__ETC___d1387) ;
|
|
assign NOT_m_tlb_m_validVec_3_79_80_OR_NOT_m_tlb_m_en_ETC___d1711 =
|
|
(!m_tlb_m_validVec_3 ||
|
|
NOT_m_tlb_m_entryVec_3_82_BITS_79_TO_53_83_EQ__ETC___d793) &&
|
|
(!m_tlb_m_validVec_4 ||
|
|
NOT_m_tlb_m_entryVec_4_98_BITS_79_TO_53_99_EQ__ETC___d809) &&
|
|
NOT_m_tlb_m_validVec_5_11_12_OR_NOT_m_tlb_m_en_ETC___d1709 ;
|
|
assign NOT_m_tlb_m_validVec_5_11_12_OR_NOT_m_tlb_m_en_ETC___d1709 =
|
|
(!m_tlb_m_validVec_5 ||
|
|
NOT_m_tlb_m_entryVec_5_14_BITS_79_TO_53_15_EQ__ETC___d825) &&
|
|
(!m_tlb_m_validVec_6 ||
|
|
NOT_m_tlb_m_entryVec_6_30_BITS_79_TO_53_31_EQ__ETC___d841) &&
|
|
NOT_m_tlb_m_validVec_7_43_44_OR_NOT_m_tlb_m_en_ETC___d1707 ;
|
|
assign NOT_m_tlb_m_validVec_7_43_44_OR_NOT_m_tlb_m_en_ETC___d1707 =
|
|
(!m_tlb_m_validVec_7 ||
|
|
NOT_m_tlb_m_entryVec_7_46_BITS_79_TO_53_47_EQ__ETC___d857) &&
|
|
(!m_tlb_m_validVec_8 ||
|
|
NOT_m_tlb_m_entryVec_8_62_BITS_79_TO_53_63_EQ__ETC___d873) &&
|
|
NOT_m_tlb_m_validVec_9_75_76_OR_NOT_m_tlb_m_en_ETC___d1705 ;
|
|
assign NOT_m_tlb_m_validVec_8_59_60_OR_NOT_m_tlb_m_va_ETC___d1568 =
|
|
!m_tlb_m_validVec_8 || !m_tlb_m_validVec_9 ||
|
|
!m_tlb_m_validVec_10 ||
|
|
!m_tlb_m_validVec_11 ||
|
|
!m_tlb_m_validVec_12 ||
|
|
!m_tlb_m_validVec_13 ||
|
|
!m_tlb_m_validVec_14 ||
|
|
!m_tlb_m_validVec_15 ;
|
|
assign NOT_m_tlb_m_validVec_9_75_76_OR_NOT_m_tlb_m_en_ETC___d1705 =
|
|
(!m_tlb_m_validVec_9 ||
|
|
NOT_m_tlb_m_entryVec_9_78_BITS_79_TO_53_79_EQ__ETC___d889) &&
|
|
(!m_tlb_m_validVec_10 ||
|
|
NOT_m_tlb_m_entryVec_10_94_BITS_79_TO_53_95_EQ_ETC___d905) &&
|
|
NOT_m_tlb_m_validVec_11_07_08_OR_NOT_m_tlb_m_e_ETC___d1703 ;
|
|
assign NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817 =
|
|
(procReq_req[490:488] != 3'd1 && procReq_req[490:488] != 3'd3 &&
|
|
procReq_req[490:488] != 3'd4 ||
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510) &&
|
|
!SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 &&
|
|
IF_NOT_procReq_req_BITS_490_TO_488_405_EQ_1_40_ETC___d2815 ;
|
|
assign SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d1838 =
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 &&
|
|
(!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_6_58_m_ETC___d661 ||
|
|
!m_vm_info[45]) ||
|
|
IF_SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_6_ETC___d1837 ;
|
|
assign SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2856 =
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 &&
|
|
(!SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 ||
|
|
!m_vm_info[45]) ||
|
|
IF_IF_IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_I_ETC___d2855 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2821 =
|
|
idx__h74945 == 2'd0 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2822 =
|
|
idx__h74945 == 2'd1 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2823 =
|
|
idx__h74945 == 2'd2 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2824 =
|
|
idx__h74945 == 2'd3 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
NOT_procReq_req_BITS_490_TO_488_405_EQ_1_406_4_ETC___d2817 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2869 =
|
|
idx__h74945 == 2'd0 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
procReq_req_BITS_490_TO_488_405_EQ_1_406_OR_pr_ETC___d2866 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2870 =
|
|
idx__h74945 == 2'd1 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
procReq_req_BITS_490_TO_488_405_EQ_1_406_OR_pr_ETC___d2866 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2871 =
|
|
idx__h74945 == 2'd2 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
procReq_req_BITS_490_TO_488_405_EQ_1_406_OR_pr_ETC___d2866 ;
|
|
assign SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2872 =
|
|
idx__h74945 == 2'd3 && m_vm_info[46] &&
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2404 &&
|
|
procReq_req_BITS_490_TO_488_405_EQ_1_406_OR_pr_ETC___d2866 ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d701 =
|
|
(level__h38292 == 2'd0 ||
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[8:0] ==
|
|
9'd0 :
|
|
level__h38292 == 2'd2 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[17:0] ==
|
|
18'd0)) &&
|
|
(!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696 ||
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656) &&
|
|
m_vm_info[46] ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_3_TO__ETC___d713 =
|
|
(level__h38292 == 2'd0 ||
|
|
((level__h38292 == 2'd1) ?
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[8:0] ==
|
|
9'd0 :
|
|
level__h38292 == 2'd2 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[17:0] ==
|
|
18'd0)) &&
|
|
!SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 &&
|
|
m_vm_info[46] ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_10_36__ETC___d1788 =
|
|
{ CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q36,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_9_44_m_ETC___d1787,
|
|
level__h38292 } ;
|
|
assign SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_9_44_m_ETC___d1787 =
|
|
{ CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q35,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_6_58_m_ETC___d661,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696,
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_4_51_m_ETC___d709 } ;
|
|
assign SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d1849 =
|
|
(SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 ==
|
|
3'd1 ||
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 ==
|
|
3'd3 ||
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 ==
|
|
3'd4) &&
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_10_ETC___d641 ||
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_9__ETC___d649 ||
|
|
IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d1847 ;
|
|
assign SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d1296 =
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 ||
|
|
(SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 ?
|
|
IF_NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_ETC___d1294 :
|
|
CASE_IF_m_respForOtherReq_64_BIT_2_65_THEN_m_r_ETC___d1293) ;
|
|
assign _dfoo1 =
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d1849 ||
|
|
idx__h37917 == 2'd3 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 ;
|
|
assign _dfoo11 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1812 ||
|
|
_dfoo3 ;
|
|
assign _dfoo13 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1811 ||
|
|
_dfoo5 ;
|
|
assign _dfoo15 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1793 ||
|
|
_dfoo7 ;
|
|
assign _dfoo25 =
|
|
idx__h74945 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893 ||
|
|
idx__h74945 == 2'd3 &&
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo26 =
|
|
(idx__h74945 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893) ?
|
|
{ 2'd2, i__h94049 } :
|
|
((idx__h74945 == 2'd3 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo27 =
|
|
idx__h74945 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893 ||
|
|
idx__h74945 == 2'd2 &&
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo28 =
|
|
(idx__h74945 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893) ?
|
|
{ 2'd2, i__h94049 } :
|
|
((idx__h74945 == 2'd2 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo29 =
|
|
idx__h74945 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893 ||
|
|
idx__h74945 == 2'd1 &&
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo3 =
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d1849 ||
|
|
idx__h37917 == 2'd2 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 ;
|
|
assign _dfoo30 =
|
|
(idx__h74945 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893) ?
|
|
{ 2'd2, i__h94049 } :
|
|
((idx__h74945 == 2'd1 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo31 =
|
|
idx__h74945 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893 ||
|
|
idx__h74945 == 2'd0 &&
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918 ||
|
|
!m_vm_info[46]) ;
|
|
assign _dfoo32 =
|
|
(idx__h74945 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2893) ?
|
|
{ 2'd2, i__h94049 } :
|
|
((idx__h74945 == 2'd0 && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2918) ?
|
|
4'd6 :
|
|
4'd2) ;
|
|
assign _dfoo49 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2824 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2872 ||
|
|
idx__h74945 == 2'd3 && !m_vm_info[46] ;
|
|
assign _dfoo5 =
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d1849 ||
|
|
idx__h37917 == 2'd1 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 ;
|
|
assign _dfoo51 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2823 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2871 ||
|
|
idx__h74945 == 2'd2 && !m_vm_info[46] ;
|
|
assign _dfoo53 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2822 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2870 ||
|
|
idx__h74945 == 2'd1 && !m_vm_info[46] ;
|
|
assign _dfoo55 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2821 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2869 ||
|
|
idx__h74945 == 2'd0 && !m_vm_info[46] ;
|
|
assign _dfoo57 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2824 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2872 ||
|
|
_dfoo25 ;
|
|
assign _dfoo59 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2823 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2871 ||
|
|
_dfoo27 ;
|
|
assign _dfoo61 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2822 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2870 ||
|
|
_dfoo29 ;
|
|
assign _dfoo63 =
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2821 ||
|
|
SEL_ARR_m_freeQ_data_0_950_m_freeQ_data_1_951__ETC___d2869 ||
|
|
_dfoo31 ;
|
|
assign _dfoo7 =
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d1849 ||
|
|
idx__h37917 == 2'd0 &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
!SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 ;
|
|
assign _dfoo9 =
|
|
IF_m_respForOtherReq_64_BIT_2_65_THEN_m_respFo_ETC___d1814 ||
|
|
_dfoo1 ;
|
|
assign _theResult_____2__h13508 =
|
|
IF_m_freeQ_deqReq_lat_1_whas__28_THEN_m_freeQ__ETC___d134 ?
|
|
next_deqP___1__h13697 :
|
|
m_freeQ_deqP ;
|
|
assign _theResult_____2__h17468 =
|
|
IF_m_rqToPQ_deqReq_lat_1_whas__16_THEN_m_rqToP_ETC___d222 ?
|
|
next_deqP___1__h17657 :
|
|
m_rqToPQ_deqP ;
|
|
assign _theResult_____2__h22136 =
|
|
IF_m_ldTransRsFromPQ_deqReq_lat_1_whas__27_THE_ETC___d333 ?
|
|
next_deqP___1__h22325 :
|
|
m_ldTransRsFromPQ_deqP ;
|
|
assign addIdx__h55826 =
|
|
(!INV_n__read1151__q37[0] && !INV_n__read1151__q37[1] &&
|
|
!INV_n__read1151__q37[2] &&
|
|
!INV_n__read1151__q37[3] &&
|
|
!INV_n__read1151__q37[4] &&
|
|
!INV_n__read1151__q37[5] &&
|
|
!INV_n__read1151__q37[6] &&
|
|
!INV_n__read1151__q37[7] &&
|
|
!INV_n__read1151__q37[8] &&
|
|
!INV_n__read1151__q37[9] &&
|
|
!INV_n__read1151__q37[10] &&
|
|
!INV_n__read1151__q37[11] &&
|
|
!INV_n__read1151__q37[12] &&
|
|
!INV_n__read1151__q37[13] &&
|
|
!INV_n__read1151__q37[14] &&
|
|
!INV_n__read1151__q37[15]) ?
|
|
((!INV_n__read1151__q37[16] && !INV_n__read1151__q37[17] &&
|
|
!INV_n__read1151__q37[18] &&
|
|
!INV_n__read1151__q37[19] &&
|
|
!INV_n__read1151__q37[20] &&
|
|
!INV_n__read1151__q37[21] &&
|
|
!INV_n__read1151__q37[22] &&
|
|
!INV_n__read1151__q37[23]) ?
|
|
((!INV_n__read1151__q37[24] && !INV_n__read1151__q37[25] &&
|
|
!INV_n__read1151__q37[26] &&
|
|
!INV_n__read1151__q37[27]) ?
|
|
((!INV_n__read1151__q37[28] &&
|
|
!INV_n__read1151__q37[29]) ?
|
|
(INV_n__read1151__q37[30] ? 5'd30 : 5'd31) :
|
|
(INV_n__read1151__q37[28] ? 5'd28 : 5'd29)) :
|
|
((!INV_n__read1151__q37[24] &&
|
|
!INV_n__read1151__q37[25]) ?
|
|
(INV_n__read1151__q37[26] ? 5'd26 : 5'd27) :
|
|
(INV_n__read1151__q37[24] ? 5'd24 : 5'd25))) :
|
|
((!INV_n__read1151__q37[16] && !INV_n__read1151__q37[17] &&
|
|
!INV_n__read1151__q37[18] &&
|
|
!INV_n__read1151__q37[19]) ?
|
|
((!INV_n__read1151__q37[20] &&
|
|
!INV_n__read1151__q37[21]) ?
|
|
(INV_n__read1151__q37[22] ? 5'd22 : 5'd23) :
|
|
(INV_n__read1151__q37[20] ? 5'd20 : 5'd21)) :
|
|
((!INV_n__read1151__q37[16] &&
|
|
!INV_n__read1151__q37[17]) ?
|
|
(INV_n__read1151__q37[18] ? 5'd18 : 5'd19) :
|
|
(INV_n__read1151__q37[16] ? 5'd16 : 5'd17)))) :
|
|
((!INV_n__read1151__q37[0] && !INV_n__read1151__q37[1] &&
|
|
!INV_n__read1151__q37[2] &&
|
|
!INV_n__read1151__q37[3] &&
|
|
!INV_n__read1151__q37[4] &&
|
|
!INV_n__read1151__q37[5] &&
|
|
!INV_n__read1151__q37[6] &&
|
|
!INV_n__read1151__q37[7]) ?
|
|
((!INV_n__read1151__q37[8] && !INV_n__read1151__q37[9] &&
|
|
!INV_n__read1151__q37[10] &&
|
|
!INV_n__read1151__q37[11]) ?
|
|
((!INV_n__read1151__q37[12] &&
|
|
!INV_n__read1151__q37[13]) ?
|
|
(INV_n__read1151__q37[14] ? 5'd14 : 5'd15) :
|
|
(INV_n__read1151__q37[12] ? 5'd12 : 5'd13)) :
|
|
((!INV_n__read1151__q37[8] && !INV_n__read1151__q37[9]) ?
|
|
(INV_n__read1151__q37[10] ? 5'd10 : 5'd11) :
|
|
(INV_n__read1151__q37[8] ? 5'd8 : 5'd9))) :
|
|
((!INV_n__read1151__q37[0] && !INV_n__read1151__q37[1] &&
|
|
!INV_n__read1151__q37[2] &&
|
|
!INV_n__read1151__q37[3]) ?
|
|
((!INV_n__read1151__q37[4] && !INV_n__read1151__q37[5]) ?
|
|
(INV_n__read1151__q37[6] ? 5'd6 : 5'd7) :
|
|
(INV_n__read1151__q37[4] ? 5'd4 : 5'd5)) :
|
|
((!INV_n__read1151__q37[0] && !INV_n__read1151__q37[1]) ?
|
|
(INV_n__read1151__q37[2] ? 5'd2 : 5'd3) :
|
|
(INV_n__read1151__q37[0] ? 5'd0 : 5'd1)))) ;
|
|
assign addIdx__h60677 =
|
|
(m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1425 &&
|
|
m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec_9_7_ETC___d1432) ?
|
|
(m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_17_ETC___d1440 ?
|
|
IF_m_tlb_m_validVec_24_115_AND_m_tlb_m_validVe_ETC___d1592 :
|
|
IF_m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_ETC___d1599) :
|
|
(m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1425 ?
|
|
IF_m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec__ETC___d1607 :
|
|
IF_m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec__ETC___d1614) ;
|
|
assign i__h73125 =
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1336 ?
|
|
2'd3 :
|
|
(m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1317 ?
|
|
2'd2 :
|
|
((m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_pendWait_0_66_BITS_1_TO_0_309_EQ_SEL_ARR_m_l_ETC___d1310 ||
|
|
idx__h37917 == 2'd0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign i__h94049 =
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_71__ETC___d2903 ?
|
|
2'd3 :
|
|
IF_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70__ETC___d2905 ;
|
|
assign idx__h37917 =
|
|
m_respForOtherReq[2] ?
|
|
m_respForOtherReq[1:0] :
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 ;
|
|
assign idx__h74557 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1928 ?
|
|
2'd3 :
|
|
(NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d1924 ?
|
|
2'd2 :
|
|
((!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
!m_pendPoisoned_0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign idx__h87839 =
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335 ?
|
|
5'd31 :
|
|
IF_NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tl_ETC___d2508 ;
|
|
assign idx__h95690 =
|
|
NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2952 ?
|
|
2'd3 :
|
|
(NOT_m_pendValid_0_rl_4_52_OR_NOT_m_pendWait_0__ETC___d2950 ?
|
|
2'd2 :
|
|
((!m_pendValid_0_rl || m_pendWait_0[3:2] != 2'd0 ||
|
|
m_pendPoisoned_0) ?
|
|
2'd1 :
|
|
2'd0)) ;
|
|
assign m_pendWait_0_66_BITS_1_TO_0_309_EQ_SEL_ARR_m_l_ETC___d1310 =
|
|
m_pendWait_0[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 ;
|
|
assign m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1308 =
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_ldTransRsFromPQ_empty) &&
|
|
m_pendWait_1_73_BITS_3_TO_2_74_EQ_0_75_OR_m_pe_ETC___d1306 ;
|
|
assign m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1317 =
|
|
(m_pendWait_0[3:2] == 2'd0 || m_pendWait_0[3:2] == 2'd1 ||
|
|
!m_pendWait_0_66_BITS_1_TO_0_309_EQ_SEL_ARR_m_l_ETC___d1310 ||
|
|
idx__h37917 == 2'd0) &&
|
|
(m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_pendWait_1_73_BITS_1_TO_0_301_EQ_SEL_ARR_m_l_ETC___d1302 ||
|
|
idx__h37917 == 2'd1) ;
|
|
assign m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1336 =
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_OR_m_pe_ETC___d1317 &&
|
|
(m_pendWait_2[3:2] == 2'd0 || m_pendWait_2[3:2] == 2'd1 ||
|
|
!m_pendWait_2_80_BITS_1_TO_0_321_EQ_SEL_ARR_m_l_ETC___d1322 ||
|
|
idx__h37917 == 2'd2) ;
|
|
assign m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2888 =
|
|
m_pendWait_0[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2879 ||
|
|
m_pendWait_1[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2882 ||
|
|
m_pendWait_2[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2886 ;
|
|
assign m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2912 =
|
|
(m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2888 ||
|
|
m_pendWait_3[3:2] == 2'd1 &&
|
|
procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2890) &&
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d2911 ;
|
|
assign m_pendWait_1_73_BITS_1_TO_0_301_EQ_SEL_ARR_m_l_ETC___d1302 =
|
|
m_pendWait_1[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 ;
|
|
assign m_pendWait_1_73_BITS_3_TO_2_74_EQ_0_75_OR_m_pe_ETC___d1306 =
|
|
m_pendWait_1[3:2] == 2'd0 || m_pendWait_1[3:2] == 2'd1 ||
|
|
!m_pendWait_1_73_BITS_1_TO_0_301_EQ_SEL_ARR_m_l_ETC___d1302 ||
|
|
m_respForOtherReq[2] ||
|
|
!m_ldTransRsFromPQ_empty ;
|
|
assign m_pendWait_2_80_BITS_1_TO_0_321_EQ_SEL_ARR_m_l_ETC___d1322 =
|
|
m_pendWait_2[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 ;
|
|
assign m_pendWait_3_87_BITS_1_TO_0_340_EQ_SEL_ARR_m_l_ETC___d1341 =
|
|
m_pendWait_3[1:0] ==
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 ;
|
|
assign m_respForOtherReq_64_BIT_2_65_AND_NOT_SEL_ARR__ETC___d1880 =
|
|
m_respForOtherReq[2] &&
|
|
(!SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603 ||
|
|
SEL_ARR_m_pendWait_0_66_BITS_1_TO_0_309_m_pend_ETC___d1876 !=
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601) ;
|
|
assign m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1425 =
|
|
m_tlb_m_validVec_0 && m_tlb_m_validVec_1 && m_tlb_m_validVec_2 &&
|
|
m_tlb_m_validVec_3 &&
|
|
m_tlb_m_validVec_4 &&
|
|
m_tlb_m_validVec_5 &&
|
|
m_tlb_m_validVec_6 &&
|
|
m_tlb_m_validVec_7 ;
|
|
assign m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1550 =
|
|
m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1425 &&
|
|
m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec_9_7_ETC___d1432 &&
|
|
m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_17_ETC___d1440 &&
|
|
m_tlb_m_validVec_24_115_AND_m_tlb_m_validVec_2_ETC___d1447 &&
|
|
!SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 &&
|
|
!INV_n__read1151__q37[0] &&
|
|
!INV_n__read1151__q37[1] &&
|
|
!INV_n__read1151__q37[2] &&
|
|
!INV_n__read1151__q37[3] &&
|
|
!INV_n__read1151__q37[4] &&
|
|
!INV_n__read1151__q37[5] &&
|
|
!INV_n__read1151__q37[6] &&
|
|
!INV_n__read1151__q37[7] &&
|
|
!INV_n__read1151__q37[8] &&
|
|
!INV_n__read1151__q37[9] &&
|
|
!INV_n__read1151__q37[10] &&
|
|
!INV_n__read1151__q37[11] &&
|
|
!INV_n__read1151__q37[12] &&
|
|
!INV_n__read1151__q37[13] &&
|
|
!INV_n__read1151__q37[14] &&
|
|
!INV_n__read1151__q37[15] &&
|
|
!INV_n__read1151__q37[16] &&
|
|
!INV_n__read1151__q37[17] &&
|
|
!INV_n__read1151__q37[18] &&
|
|
!INV_n__read1151__q37[19] &&
|
|
!INV_n__read1151__q37[20] &&
|
|
!INV_n__read1151__q37[21] &&
|
|
!INV_n__read1151__q37[22] &&
|
|
!INV_n__read1151__q37[23] &&
|
|
!INV_n__read1151__q37[24] &&
|
|
!INV_n__read1151__q37[25] &&
|
|
!INV_n__read1151__q37[26] &&
|
|
!INV_n__read1151__q37[27] &&
|
|
!INV_n__read1151__q37[28] &&
|
|
!INV_n__read1151__q37[29] &&
|
|
!INV_n__read1151__q37[30] &&
|
|
!INV_n__read1151__q37[31] ;
|
|
assign m_tlb_m_validVec_16_87_AND_m_tlb_m_validVec_17_ETC___d1440 =
|
|
m_tlb_m_validVec_16 && m_tlb_m_validVec_17 &&
|
|
m_tlb_m_validVec_18 &&
|
|
m_tlb_m_validVec_19 &&
|
|
m_tlb_m_validVec_20 &&
|
|
m_tlb_m_validVec_21 &&
|
|
m_tlb_m_validVec_22 &&
|
|
m_tlb_m_validVec_23 ;
|
|
assign m_tlb_m_validVec_24_115_AND_m_tlb_m_validVec_2_ETC___d1447 =
|
|
m_tlb_m_validVec_24 && m_tlb_m_validVec_25 &&
|
|
m_tlb_m_validVec_26 &&
|
|
m_tlb_m_validVec_27 &&
|
|
m_tlb_m_validVec_28 &&
|
|
m_tlb_m_validVec_29 &&
|
|
m_tlb_m_validVec_30 &&
|
|
m_tlb_m_validVec_31 ;
|
|
assign m_tlb_m_validVec_8_59_AND_m_tlb_m_validVec_9_7_ETC___d1432 =
|
|
m_tlb_m_validVec_8 && m_tlb_m_validVec_9 &&
|
|
m_tlb_m_validVec_10 &&
|
|
m_tlb_m_validVec_11 &&
|
|
m_tlb_m_validVec_12 &&
|
|
m_tlb_m_validVec_13 &&
|
|
m_tlb_m_validVec_14 &&
|
|
m_tlb_m_validVec_15 ;
|
|
assign n__read__h107398 =
|
|
MUX_m_pendPoisoned_0$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_0_rl ;
|
|
assign n__read__h107529 =
|
|
MUX_m_pendPoisoned_1$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_1_rl ;
|
|
assign n__read__h107660 =
|
|
MUX_m_pendPoisoned_2$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_2_rl ;
|
|
assign n__read__h107791 =
|
|
MUX_m_pendPoisoned_3$write_1__SEL_1 ?
|
|
procReq_req[11:0] :
|
|
m_pendSpecBits_3_rl ;
|
|
assign n__read__h51151 =
|
|
m_tlb_m_lruBit_lat_0$whas ? upd__h51178 : m_tlb_m_lruBit_rl ;
|
|
assign next_deqP___1__h13697 =
|
|
(m_freeQ_deqP == 2'd3) ? 2'd0 : m_freeQ_deqP + 2'd1 ;
|
|
assign next_deqP___1__h17657 =
|
|
(m_rqToPQ_deqP == 2'd3) ? 2'd0 : m_rqToPQ_deqP + 2'd1 ;
|
|
assign next_deqP___1__h22325 = m_ldTransRsFromPQ_deqP + 1'd1 ;
|
|
assign procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2879 =
|
|
procReq_req[425:399] == m_pendInst_0[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2882 =
|
|
procReq_req[425:399] == m_pendInst_1[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2886 =
|
|
procReq_req[425:399] == m_pendInst_2[413:387] ;
|
|
assign procReq_req_BITS_425_TO_399_023_EQ_m_pendInst__ETC___d2890 =
|
|
procReq_req[425:399] == m_pendInst_3[413:387] ;
|
|
assign procReq_req_BITS_490_TO_488_405_EQ_1_406_OR_pr_ETC___d2866 =
|
|
(procReq_req[490:488] == 3'd1 || procReq_req[490:488] == 3'd3 ||
|
|
procReq_req[490:488] == 3'd4) &&
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 ||
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 ||
|
|
IF_NOT_procReq_req_BITS_490_TO_488_405_EQ_1_40_ETC___d2864 ;
|
|
assign upd__h10027 = n__read__h107791 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h51178 =
|
|
WILL_FIRE_RL_m_tlb_m_doUpdateRep ?
|
|
MUX_m_tlb_m_lruBit_lat_0$wset_1__VAL_1 :
|
|
32'd0 ;
|
|
assign upd__h8992 = n__read__h107398 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h9337 = n__read__h107529 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h9682 = n__read__h107660 & specUpdate_correctSpeculation_mask ;
|
|
assign v__h13028 =
|
|
IF_m_freeQ_enqReq_lat_1_whas__9_THEN_m_freeQ_e_ETC___d108 ?
|
|
v__h13179 :
|
|
m_freeQ_enqP ;
|
|
assign v__h13179 = (m_freeQ_enqP == 2'd3) ? 2'd0 : m_freeQ_enqP + 2'd1 ;
|
|
assign v__h16896 =
|
|
IF_m_rqToPQ_enqReq_lat_1_whas__87_THEN_m_rqToP_ETC___d196 ?
|
|
v__h17047 :
|
|
m_rqToPQ_enqP ;
|
|
assign v__h17047 = (m_rqToPQ_enqP == 2'd3) ? 2'd0 : m_rqToPQ_enqP + 2'd1 ;
|
|
assign v__h21066 =
|
|
IF_m_ldTransRsFromPQ_enqReq_lat_1_whas__75_THE_ETC___d284 ?
|
|
v__h21217 :
|
|
m_ldTransRsFromPQ_enqP ;
|
|
assign v__h21217 = m_ldTransRsFromPQ_enqP + 1'd1 ;
|
|
assign v__h45598 =
|
|
(NOT_m_tlb_m_validVec_0_22_23_OR_NOT_m_tlb_m_va_ETC___d1561 ||
|
|
NOT_m_tlb_m_validVec_8_59_60_OR_NOT_m_tlb_m_va_ETC___d1568 ||
|
|
NOT_m_tlb_m_validVec_16_87_88_OR_NOT_m_tlb_m_v_ETC___d1576 ||
|
|
NOT_m_tlb_m_validVec_24_115_116_OR_NOT_m_tlb_m_ETC___d1583) ?
|
|
addIdx__h60677 :
|
|
v__h50415 ;
|
|
assign v__h50415 =
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 ?
|
|
m_tlb_m_randIdx :
|
|
v__h51943 ;
|
|
assign v__h51943 =
|
|
(INV_n__read1151__q37[0] || INV_n__read1151__q37[1] ||
|
|
INV_n__read1151__q37[2] ||
|
|
INV_n__read1151__q37[3] ||
|
|
INV_n__read1151__q37[4] ||
|
|
INV_n__read1151__q37[5] ||
|
|
INV_n__read1151__q37[6] ||
|
|
INV_n__read1151__q37[7] ||
|
|
INV_n__read1151__q37[8] ||
|
|
INV_n__read1151__q37[9] ||
|
|
INV_n__read1151__q37[10] ||
|
|
INV_n__read1151__q37[11] ||
|
|
INV_n__read1151__q37[12] ||
|
|
INV_n__read1151__q37[13] ||
|
|
INV_n__read1151__q37[14] ||
|
|
INV_n__read1151__q37[15] ||
|
|
INV_n__read1151__q37[16] ||
|
|
INV_n__read1151__q37[17] ||
|
|
INV_n__read1151__q37[18] ||
|
|
INV_n__read1151__q37[19] ||
|
|
INV_n__read1151__q37[20] ||
|
|
INV_n__read1151__q37[21] ||
|
|
INV_n__read1151__q37[22] ||
|
|
INV_n__read1151__q37[23] ||
|
|
INV_n__read1151__q37[24] ||
|
|
INV_n__read1151__q37[25] ||
|
|
INV_n__read1151__q37[26] ||
|
|
INV_n__read1151__q37[27] ||
|
|
INV_n__read1151__q37[28] ||
|
|
INV_n__read1151__q37[29] ||
|
|
INV_n__read1151__q37[30] ||
|
|
INV_n__read1151__q37[31]) ?
|
|
addIdx__h55826 :
|
|
5'd0 ;
|
|
assign val__h5329 = m_tlb_m_lruBit_rl | x__h5387 ;
|
|
assign x__h5387 = 32'd1 << m_tlb_m_updRepIdx_rl[4:0] ;
|
|
assign x__h70573 = { 8'd0, x__h70582 } ;
|
|
assign x__h92828 = { 8'd0, x__h92837 } ;
|
|
assign x_id__h21371 =
|
|
EN_toParent_ldTransRsFromP_enq ?
|
|
m_ldTransRsFromPQ_enqReq_lat_0$wget[1:0] :
|
|
m_ldTransRsFromPQ_enqReq_rl[1:0] ;
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0: level__h38292 = m_ldTransRsFromPQ_data_0[3:2];
|
|
1'd1: level__h38292 = m_ldTransRsFromPQ_data_1[3:2];
|
|
endcase
|
|
end
|
|
always@(m_freeQ_deqP or
|
|
m_freeQ_data_0 or
|
|
m_freeQ_data_1 or m_freeQ_data_2 or m_freeQ_data_3)
|
|
begin
|
|
case (m_freeQ_deqP)
|
|
2'd0: idx__h74945 = m_freeQ_data_0;
|
|
2'd1: idx__h74945 = m_freeQ_data_1;
|
|
2'd2: idx__h74945 = m_freeQ_data_2;
|
|
2'd3: idx__h74945 = m_freeQ_data_3;
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 =
|
|
m_ldTransRsFromPQ_data_0[1:0];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_1_TO__ETC___d601 =
|
|
m_ldTransRsFromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0: x__h70669 = m_pendInst_0[440:375];
|
|
2'd1: x__h70669 = m_pendInst_1[440:375];
|
|
2'd2: x__h70669 = m_pendInst_2[440:375];
|
|
2'd3: x__h70669 = m_pendInst_3[440:375];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendWait_0 or m_pendWait_1 or m_pendWait_2 or m_pendWait_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603 =
|
|
m_pendWait_0[3:2] != 2'd0 && m_pendWait_0[3:2] != 2'd1;
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603 =
|
|
m_pendWait_1[3:2] != 2'd0 && m_pendWait_1[3:2] != 2'd1;
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603 =
|
|
m_pendWait_2[3:2] != 2'd0 && m_pendWait_2[3:2] != 2'd1;
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d603 =
|
|
m_pendWait_3[3:2] != 2'd0 && m_pendWait_3[3:2] != 2'd1;
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 =
|
|
m_pendInst_0[478:476];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 =
|
|
m_pendInst_1[478:476];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 =
|
|
m_pendInst_2[478:476];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d627 =
|
|
m_pendInst_3[478:476];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_10_ETC___d641 =
|
|
!m_ldTransRsFromPQ_data_0[10];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_10_ETC___d641 =
|
|
!m_ldTransRsFromPQ_data_1[10];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_9__ETC___d649 =
|
|
!m_ldTransRsFromPQ_data_0[9];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_9__ETC___d649 =
|
|
!m_ldTransRsFromPQ_data_1[9];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 =
|
|
!m_ldTransRsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_NOT_m_ldTransRsFromPQ_data_0_96_BIT_4__ETC___d656 =
|
|
!m_ldTransRsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_6_58_m_ETC___d661 =
|
|
m_ldTransRsFromPQ_data_0[6];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_6_58_m_ETC___d661 =
|
|
m_ldTransRsFromPQ_data_1[6];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696 =
|
|
m_ldTransRsFromPQ_data_0[5];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_5_93_m_ETC___d696 =
|
|
m_ldTransRsFromPQ_data_1[5];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669 =
|
|
m_ldTransRsFromPQ_data_0[7];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_7_66_m_ETC___d669 =
|
|
m_ldTransRsFromPQ_data_1[7];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684 =
|
|
m_ldTransRsFromPQ_data_0[54:11];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684 =
|
|
m_ldTransRsFromPQ_data_1[54:11];
|
|
endcase
|
|
end
|
|
always@(level__h38292 or
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684 or
|
|
x__h70669)
|
|
begin
|
|
case (level__h38292)
|
|
2'd0:
|
|
x__h70582 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684,
|
|
x__h70669[11:0] };
|
|
2'd1:
|
|
x__h70582 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[43:9],
|
|
x__h70669[20:0] };
|
|
2'd2:
|
|
x__h70582 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[43:18],
|
|
x__h70669[29:0] };
|
|
2'd3: x__h70582 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_4_51_m_ETC___d709 =
|
|
m_ldTransRsFromPQ_data_0[4];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_4_51_m_ETC___d709 =
|
|
m_ldTransRsFromPQ_data_1[4];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 =
|
|
m_ldTransRsFromPQ_data_0[81:55];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730 =
|
|
m_ldTransRsFromPQ_data_1[81:55];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 =
|
|
m_ldTransRsFromPQ_data_0[8];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_8_38_m_ETC___d741 =
|
|
m_ldTransRsFromPQ_data_1[8];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 =
|
|
m_ldTransRsFromPQ_data_0[82];
|
|
1'd1:
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 =
|
|
m_ldTransRsFromPQ_data_1[82];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendPoisoned_0 or
|
|
m_pendPoisoned_1 or m_pendPoisoned_2 or m_pendPoisoned_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 =
|
|
m_pendPoisoned_0;
|
|
2'd1:
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 =
|
|
m_pendPoisoned_1;
|
|
2'd2:
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 =
|
|
m_pendPoisoned_2;
|
|
2'd3:
|
|
SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 =
|
|
m_pendPoisoned_3;
|
|
endcase
|
|
end
|
|
always@(idx__h37917)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0, 2'd1, 2'd2, 2'd3:
|
|
CASE_IF_m_respForOtherReq_64_BIT_2_65_THEN_m_r_ETC___d1293 = 1'd1;
|
|
endcase
|
|
end
|
|
always@(level__h38292 or
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730)
|
|
begin
|
|
case (level__h38292)
|
|
2'd0:
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q1 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730;
|
|
2'd1:
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q1 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730[26:9],
|
|
9'd0 };
|
|
2'd2:
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q1 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_81_TO_ETC___d730[26:18],
|
|
18'd0 };
|
|
2'd3: CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q1 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(level__h38292 or
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684)
|
|
begin
|
|
case (level__h38292)
|
|
2'd0:
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2 =
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684;
|
|
2'd1:
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[43:9],
|
|
9'd0 };
|
|
2'd2:
|
|
CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2 =
|
|
{ SEL_ARR_m_ldTransRsFromPQ_data_0_96_BITS_54_TO_ETC___d684[43:18],
|
|
18'd0 };
|
|
2'd3: CASE_level8292_0_SEL_ARR_m_ldTransRsFromPQ_dat_ETC__q2 = 44'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendWait_0 or m_pendWait_1 or m_pendWait_2 or m_pendWait_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_m_pendWait_0_66_BITS_1_TO_0_309_m_pend_ETC___d1876 =
|
|
m_pendWait_0[1:0];
|
|
2'd1:
|
|
SEL_ARR_m_pendWait_0_66_BITS_1_TO_0_309_m_pend_ETC___d1876 =
|
|
m_pendWait_1[1:0];
|
|
2'd2:
|
|
SEL_ARR_m_pendWait_0_66_BITS_1_TO_0_309_m_pend_ETC___d1876 =
|
|
m_pendWait_2[1:0];
|
|
2'd3:
|
|
SEL_ARR_m_pendWait_0_66_BITS_1_TO_0_309_m_pend_ETC___d1876 =
|
|
m_pendWait_3[1:0];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_1 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_1[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_1_BITS_1_TO_0_0_procReq__ETC__q3 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_0 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_0[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_0_BITS_1_TO_0_0_procReq__ETC__q4 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_2 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_2[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q5 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_2_BITS_1_TO_0_0_procReq__ETC__q5 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_3 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_3[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q6 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_3_BITS_1_TO_0_0_procReq__ETC__q6 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_4 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_4[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q7 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_4_BITS_1_TO_0_0_procReq__ETC__q7 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_5 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_5[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q8 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_5_BITS_1_TO_0_0_procReq__ETC__q8 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_6 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_6[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q9 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_6_BITS_1_TO_0_0_procReq__ETC__q9 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_7 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_7[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q10 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_7_BITS_1_TO_0_0_procReq__ETC__q10 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_8 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_8[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q11 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q11 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q11 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_8_BITS_1_TO_0_0_procReq__ETC__q11 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_9 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_9[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q12 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q12 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q12 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_9_BITS_1_TO_0_0_procReq__ETC__q12 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_10 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_10[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_10_BITS_1_TO_0_0_procReq_ETC__q13 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_11 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_11[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_11_BITS_1_TO_0_0_procReq_ETC__q14 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_12 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_12[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_12_BITS_1_TO_0_0_procReq_ETC__q15 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_13 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_13[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q16 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_13_BITS_1_TO_0_0_procReq_ETC__q16 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_14 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_14[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q17 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_14_BITS_1_TO_0_0_procReq_ETC__q17 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_15 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_15[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q18 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_15_BITS_1_TO_0_0_procReq_ETC__q18 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_16 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_16[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q19 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_16_BITS_1_TO_0_0_procReq_ETC__q19 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_17 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_17[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_17_BITS_1_TO_0_0_procReq_ETC__q20 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_18 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_18[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_18_BITS_1_TO_0_0_procReq_ETC__q21 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_19 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_19[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_19_BITS_1_TO_0_0_procReq_ETC__q22 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_20 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_20[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_20_BITS_1_TO_0_0_procReq_ETC__q23 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_21 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_21[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_21_BITS_1_TO_0_0_procReq_ETC__q24 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_22 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_22[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_22_BITS_1_TO_0_0_procReq_ETC__q25 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_23 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_23[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q26 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_23_BITS_1_TO_0_0_procReq_ETC__q26 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_24 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_24[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q27 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_24_BITS_1_TO_0_0_procReq_ETC__q27 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_25 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_25[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q28 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_25_BITS_1_TO_0_0_procReq_ETC__q28 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_26 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_26[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q29 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_26_BITS_1_TO_0_0_procReq_ETC__q29 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_27 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_27[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q30 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_27_BITS_1_TO_0_0_procReq_ETC__q30 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_28 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_28[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q31 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_28_BITS_1_TO_0_0_procReq_ETC__q31 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_29 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_29[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q32 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_29_BITS_1_TO_0_0_procReq_ETC__q32 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_30 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_30[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q33 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q33 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q33 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_30_BITS_1_TO_0_0_procReq_ETC__q33 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0: ppn__h92833 = m_tlb_m_entryVec_0[52:9];
|
|
5'd1: ppn__h92833 = m_tlb_m_entryVec_1[52:9];
|
|
5'd2: ppn__h92833 = m_tlb_m_entryVec_2[52:9];
|
|
5'd3: ppn__h92833 = m_tlb_m_entryVec_3[52:9];
|
|
5'd4: ppn__h92833 = m_tlb_m_entryVec_4[52:9];
|
|
5'd5: ppn__h92833 = m_tlb_m_entryVec_5[52:9];
|
|
5'd6: ppn__h92833 = m_tlb_m_entryVec_6[52:9];
|
|
5'd7: ppn__h92833 = m_tlb_m_entryVec_7[52:9];
|
|
5'd8: ppn__h92833 = m_tlb_m_entryVec_8[52:9];
|
|
5'd9: ppn__h92833 = m_tlb_m_entryVec_9[52:9];
|
|
5'd10: ppn__h92833 = m_tlb_m_entryVec_10[52:9];
|
|
5'd11: ppn__h92833 = m_tlb_m_entryVec_11[52:9];
|
|
5'd12: ppn__h92833 = m_tlb_m_entryVec_12[52:9];
|
|
5'd13: ppn__h92833 = m_tlb_m_entryVec_13[52:9];
|
|
5'd14: ppn__h92833 = m_tlb_m_entryVec_14[52:9];
|
|
5'd15: ppn__h92833 = m_tlb_m_entryVec_15[52:9];
|
|
5'd16: ppn__h92833 = m_tlb_m_entryVec_16[52:9];
|
|
5'd17: ppn__h92833 = m_tlb_m_entryVec_17[52:9];
|
|
5'd18: ppn__h92833 = m_tlb_m_entryVec_18[52:9];
|
|
5'd19: ppn__h92833 = m_tlb_m_entryVec_19[52:9];
|
|
5'd20: ppn__h92833 = m_tlb_m_entryVec_20[52:9];
|
|
5'd21: ppn__h92833 = m_tlb_m_entryVec_21[52:9];
|
|
5'd22: ppn__h92833 = m_tlb_m_entryVec_22[52:9];
|
|
5'd23: ppn__h92833 = m_tlb_m_entryVec_23[52:9];
|
|
5'd24: ppn__h92833 = m_tlb_m_entryVec_24[52:9];
|
|
5'd25: ppn__h92833 = m_tlb_m_entryVec_25[52:9];
|
|
5'd26: ppn__h92833 = m_tlb_m_entryVec_26[52:9];
|
|
5'd27: ppn__h92833 = m_tlb_m_entryVec_27[52:9];
|
|
5'd28: ppn__h92833 = m_tlb_m_entryVec_28[52:9];
|
|
5'd29: ppn__h92833 = m_tlb_m_entryVec_29[52:9];
|
|
5'd30: ppn__h92833 = m_tlb_m_entryVec_30[52:9];
|
|
5'd31: ppn__h92833 = m_tlb_m_entryVec_31[52:9];
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0: level__h87878 = m_tlb_m_entryVec_0[1:0];
|
|
5'd1: level__h87878 = m_tlb_m_entryVec_1[1:0];
|
|
5'd2: level__h87878 = m_tlb_m_entryVec_2[1:0];
|
|
5'd3: level__h87878 = m_tlb_m_entryVec_3[1:0];
|
|
5'd4: level__h87878 = m_tlb_m_entryVec_4[1:0];
|
|
5'd5: level__h87878 = m_tlb_m_entryVec_5[1:0];
|
|
5'd6: level__h87878 = m_tlb_m_entryVec_6[1:0];
|
|
5'd7: level__h87878 = m_tlb_m_entryVec_7[1:0];
|
|
5'd8: level__h87878 = m_tlb_m_entryVec_8[1:0];
|
|
5'd9: level__h87878 = m_tlb_m_entryVec_9[1:0];
|
|
5'd10: level__h87878 = m_tlb_m_entryVec_10[1:0];
|
|
5'd11: level__h87878 = m_tlb_m_entryVec_11[1:0];
|
|
5'd12: level__h87878 = m_tlb_m_entryVec_12[1:0];
|
|
5'd13: level__h87878 = m_tlb_m_entryVec_13[1:0];
|
|
5'd14: level__h87878 = m_tlb_m_entryVec_14[1:0];
|
|
5'd15: level__h87878 = m_tlb_m_entryVec_15[1:0];
|
|
5'd16: level__h87878 = m_tlb_m_entryVec_16[1:0];
|
|
5'd17: level__h87878 = m_tlb_m_entryVec_17[1:0];
|
|
5'd18: level__h87878 = m_tlb_m_entryVec_18[1:0];
|
|
5'd19: level__h87878 = m_tlb_m_entryVec_19[1:0];
|
|
5'd20: level__h87878 = m_tlb_m_entryVec_20[1:0];
|
|
5'd21: level__h87878 = m_tlb_m_entryVec_21[1:0];
|
|
5'd22: level__h87878 = m_tlb_m_entryVec_22[1:0];
|
|
5'd23: level__h87878 = m_tlb_m_entryVec_23[1:0];
|
|
5'd24: level__h87878 = m_tlb_m_entryVec_24[1:0];
|
|
5'd25: level__h87878 = m_tlb_m_entryVec_25[1:0];
|
|
5'd26: level__h87878 = m_tlb_m_entryVec_26[1:0];
|
|
5'd27: level__h87878 = m_tlb_m_entryVec_27[1:0];
|
|
5'd28: level__h87878 = m_tlb_m_entryVec_28[1:0];
|
|
5'd29: level__h87878 = m_tlb_m_entryVec_29[1:0];
|
|
5'd30: level__h87878 = m_tlb_m_entryVec_30[1:0];
|
|
5'd31: level__h87878 = m_tlb_m_entryVec_31[1:0];
|
|
endcase
|
|
end
|
|
always@(level__h87878 or ppn__h92833 or procReq_req)
|
|
begin
|
|
case (level__h87878)
|
|
2'd0: x__h92837 = { ppn__h92833, procReq_req[398:387] };
|
|
2'd1: x__h92837 = { ppn__h92833[43:9], procReq_req[407:387] };
|
|
2'd2: x__h92837 = { ppn__h92833[43:18], procReq_req[416:387] };
|
|
2'd3: x__h92837 = 56'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_0[8];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_1[8];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_2[8];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_3[8];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_4[8];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_5[8];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_6[8];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_7[8];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_8[8];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_9[8];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_10[8];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_11[8];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_12[8];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_13[8];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_14[8];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_15[8];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_16[8];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_17[8];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_18[8];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_19[8];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_20[8];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_21[8];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_22[8];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_23[8];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_24[8];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_25[8];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_26[8];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_27[8];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_28[8];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_29[8];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_30[8];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_8_414_41_ETC___d2510 =
|
|
!m_tlb_m_entryVec_31[8];
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_0[7];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_1[7];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_2[7];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_3[7];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_4[7];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_5[7];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_6[7];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_7[7];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_8[7];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_9[7];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_10[7];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_11[7];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_12[7];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_13[7];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_14[7];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_15[7];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_16[7];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_17[7];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_18[7];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_19[7];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_20[7];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_21[7];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_22[7];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_23[7];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_24[7];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_25[7];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_26[7];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_27[7];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_28[7];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_29[7];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_30[7];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_7_513_51_ETC___d2578 =
|
|
!m_tlb_m_entryVec_31[7];
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_NOT_m_tlb_m_entryVec_0_25_BIT_2_580_58_ETC___d2645 =
|
|
!m_tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_0[4];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_1[4];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_2[4];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_3[4];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_4[4];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_5[4];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_6[4];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_7[4];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_8[4];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_9[4];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_10[4];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_11[4];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_12[4];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_13[4];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_14[4];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_15[4];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_16[4];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_17[4];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_18[4];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_19[4];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_20[4];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_21[4];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_22[4];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_23[4];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_24[4];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_25[4];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_26[4];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_27[4];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_28[4];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_29[4];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_30[4];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_4_647_m_tlb__ETC___d2680 =
|
|
m_tlb_m_entryVec_31[4];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_entryVec_31 or procReq_req)
|
|
begin
|
|
case (m_tlb_m_entryVec_31[1:0])
|
|
2'd0:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q34 =
|
|
procReq_req[425:399];
|
|
2'd1:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q34 =
|
|
{ procReq_req[425:408], 9'd0 };
|
|
2'd2:
|
|
CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q34 =
|
|
{ procReq_req[425:417], 18'd0 };
|
|
2'd3: CASE_m_tlb_m_entryVec_31_BITS_1_TO_0_0_procReq_ETC__q34 = 27'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_0[3];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_1[3];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_2[3];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_3[3];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_4[3];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_5[3];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_6[3];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_7[3];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_8[3];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_9[3];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_10[3];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_11[3];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_12[3];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_13[3];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_14[3];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_15[3];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_16[3];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_17[3];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_18[3];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_19[3];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_20[3];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_21[3];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_22[3];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_23[3];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_24[3];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_25[3];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_26[3];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_27[3];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_28[3];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_29[3];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_30[3];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_3_766_m_tlb__ETC___d2799 =
|
|
m_tlb_m_entryVec_31[3];
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_0[5];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_1[5];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_2[5];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_3[5];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_4[5];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_5[5];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_6[5];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_7[5];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_8[5];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_9[5];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_10[5];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_11[5];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_12[5];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_13[5];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_14[5];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_15[5];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_16[5];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_17[5];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_18[5];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_19[5];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_20[5];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_21[5];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_22[5];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_23[5];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_24[5];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_25[5];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_26[5];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_27[5];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_28[5];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_29[5];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_30[5];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_5_683_m_tlb__ETC___d2716 =
|
|
m_tlb_m_entryVec_31[5];
|
|
endcase
|
|
end
|
|
always@(idx__h87839 or
|
|
m_tlb_m_entryVec_0 or
|
|
m_tlb_m_entryVec_1 or
|
|
m_tlb_m_entryVec_2 or
|
|
m_tlb_m_entryVec_3 or
|
|
m_tlb_m_entryVec_4 or
|
|
m_tlb_m_entryVec_5 or
|
|
m_tlb_m_entryVec_6 or
|
|
m_tlb_m_entryVec_7 or
|
|
m_tlb_m_entryVec_8 or
|
|
m_tlb_m_entryVec_9 or
|
|
m_tlb_m_entryVec_10 or
|
|
m_tlb_m_entryVec_11 or
|
|
m_tlb_m_entryVec_12 or
|
|
m_tlb_m_entryVec_13 or
|
|
m_tlb_m_entryVec_14 or
|
|
m_tlb_m_entryVec_15 or
|
|
m_tlb_m_entryVec_16 or
|
|
m_tlb_m_entryVec_17 or
|
|
m_tlb_m_entryVec_18 or
|
|
m_tlb_m_entryVec_19 or
|
|
m_tlb_m_entryVec_20 or
|
|
m_tlb_m_entryVec_21 or
|
|
m_tlb_m_entryVec_22 or
|
|
m_tlb_m_entryVec_23 or
|
|
m_tlb_m_entryVec_24 or
|
|
m_tlb_m_entryVec_25 or
|
|
m_tlb_m_entryVec_26 or
|
|
m_tlb_m_entryVec_27 or
|
|
m_tlb_m_entryVec_28 or
|
|
m_tlb_m_entryVec_29 or m_tlb_m_entryVec_30 or m_tlb_m_entryVec_31)
|
|
begin
|
|
case (idx__h87839)
|
|
5'd0:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_0[2];
|
|
5'd1:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_1[2];
|
|
5'd2:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_2[2];
|
|
5'd3:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_3[2];
|
|
5'd4:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_4[2];
|
|
5'd5:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_5[2];
|
|
5'd6:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_6[2];
|
|
5'd7:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_7[2];
|
|
5'd8:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_8[2];
|
|
5'd9:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_9[2];
|
|
5'd10:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_10[2];
|
|
5'd11:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_11[2];
|
|
5'd12:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_12[2];
|
|
5'd13:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_13[2];
|
|
5'd14:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_14[2];
|
|
5'd15:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_15[2];
|
|
5'd16:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_16[2];
|
|
5'd17:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_17[2];
|
|
5'd18:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_18[2];
|
|
5'd19:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_19[2];
|
|
5'd20:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_20[2];
|
|
5'd21:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_21[2];
|
|
5'd22:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_22[2];
|
|
5'd23:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_23[2];
|
|
5'd24:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_24[2];
|
|
5'd25:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_25[2];
|
|
5'd26:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_26[2];
|
|
5'd27:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_27[2];
|
|
5'd28:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_28[2];
|
|
5'd29:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_29[2];
|
|
5'd30:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_30[2];
|
|
5'd31:
|
|
SEL_ARR_m_tlb_m_entryVec_0_25_BIT_2_580_m_tlb__ETC___d2808 =
|
|
m_tlb_m_entryVec_31[2];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h95343 = m_pendResp_0[69:6];
|
|
2'd1: x__h95343 = m_pendResp_1[69:6];
|
|
2'd2: x__h95343 = m_pendResp_2[69:6];
|
|
2'd3: x__h95343 = m_pendResp_3[69:6];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h102032 = m_pendInst_0[316:303];
|
|
2'd1: x__h102032 = m_pendInst_1[316:303];
|
|
2'd2: x__h102032 = m_pendInst_2[316:303];
|
|
2'd3: x__h102032 = m_pendInst_3[316:303];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h102041 = m_pendInst_0[302:289];
|
|
2'd1: x__h102041 = m_pendInst_1[302:289];
|
|
2'd2: x__h102041 = m_pendInst_2[302:289];
|
|
2'd3: x__h102041 = m_pendInst_3[302:289];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h105527 = m_pendInst_0[264:201];
|
|
2'd1: x__h105527 = m_pendInst_1[264:201];
|
|
2'd2: x__h105527 = m_pendInst_2[264:201];
|
|
2'd3: x__h105527 = m_pendInst_3[264:201];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h105564 = m_pendInst_0[200:136];
|
|
2'd1: x__h105564 = m_pendInst_1[200:136];
|
|
2'd2: x__h105564 = m_pendInst_2[200:136];
|
|
2'd3: x__h105564 = m_pendInst_3[200:136];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h105591 = m_pendInst_0[65:1];
|
|
2'd1: x__h105591 = m_pendInst_1[65:1];
|
|
2'd2: x__h105591 = m_pendInst_2[65:1];
|
|
2'd3: x__h105591 = m_pendInst_3[65:1];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0: x__h105582 = m_pendInst_0[129:66];
|
|
2'd1: x__h105582 = m_pendInst_1[129:66];
|
|
2'd2: x__h105582 = m_pendInst_2[129:66];
|
|
2'd3: x__h105582 = m_pendInst_3[129:66];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendResp_0_939_BIT_5_957_958_NOT_ETC___d2966 =
|
|
!m_pendResp_0[5];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendResp_0_939_BIT_5_957_958_NOT_ETC___d2966 =
|
|
!m_pendResp_1[5];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendResp_0_939_BIT_5_957_958_NOT_ETC___d2966 =
|
|
!m_pendResp_2[5];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendResp_0_939_BIT_5_957_958_NOT_ETC___d2966 =
|
|
!m_pendResp_3[5];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_15_ETC___d3055 =
|
|
m_pendResp_0[4:0] == 5'd15;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_15_ETC___d3055 =
|
|
m_pendResp_1[4:0] == 5'd15;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_15_ETC___d3055 =
|
|
m_pendResp_2[4:0] == 5'd15;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_15_ETC___d3055 =
|
|
m_pendResp_3[4:0] == 5'd15;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_13_ETC___d3049 =
|
|
m_pendResp_0[4:0] == 5'd13;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_13_ETC___d3049 =
|
|
m_pendResp_1[4:0] == 5'd13;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_13_ETC___d3049 =
|
|
m_pendResp_2[4:0] == 5'd13;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_13_ETC___d3049 =
|
|
m_pendResp_3[4:0] == 5'd13;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_12_ETC___d3043 =
|
|
m_pendResp_0[4:0] == 5'd12;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_12_ETC___d3043 =
|
|
m_pendResp_1[4:0] == 5'd12;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_12_ETC___d3043 =
|
|
m_pendResp_2[4:0] == 5'd12;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_12_ETC___d3043 =
|
|
m_pendResp_3[4:0] == 5'd12;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_9__ETC___d3031 =
|
|
m_pendResp_0[4:0] == 5'd9;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_9__ETC___d3031 =
|
|
m_pendResp_1[4:0] == 5'd9;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_9__ETC___d3031 =
|
|
m_pendResp_2[4:0] == 5'd9;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_9__ETC___d3031 =
|
|
m_pendResp_3[4:0] == 5'd9;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_11_ETC___d3037 =
|
|
m_pendResp_0[4:0] == 5'd11;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_11_ETC___d3037 =
|
|
m_pendResp_1[4:0] == 5'd11;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_11_ETC___d3037 =
|
|
m_pendResp_2[4:0] == 5'd11;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_11_ETC___d3037 =
|
|
m_pendResp_3[4:0] == 5'd11;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_8__ETC___d3025 =
|
|
m_pendResp_0[4:0] == 5'd8;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_8__ETC___d3025 =
|
|
m_pendResp_1[4:0] == 5'd8;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_8__ETC___d3025 =
|
|
m_pendResp_2[4:0] == 5'd8;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_8__ETC___d3025 =
|
|
m_pendResp_3[4:0] == 5'd8;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_7__ETC___d3019 =
|
|
m_pendResp_0[4:0] == 5'd7;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_7__ETC___d3019 =
|
|
m_pendResp_1[4:0] == 5'd7;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_7__ETC___d3019 =
|
|
m_pendResp_2[4:0] == 5'd7;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_7__ETC___d3019 =
|
|
m_pendResp_3[4:0] == 5'd7;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_6__ETC___d3013 =
|
|
m_pendResp_0[4:0] == 5'd6;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_6__ETC___d3013 =
|
|
m_pendResp_1[4:0] == 5'd6;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_6__ETC___d3013 =
|
|
m_pendResp_2[4:0] == 5'd6;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_6__ETC___d3013 =
|
|
m_pendResp_3[4:0] == 5'd6;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_4__ETC___d3001 =
|
|
m_pendResp_0[4:0] == 5'd4;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_4__ETC___d3001 =
|
|
m_pendResp_1[4:0] == 5'd4;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_4__ETC___d3001 =
|
|
m_pendResp_2[4:0] == 5'd4;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_4__ETC___d3001 =
|
|
m_pendResp_3[4:0] == 5'd4;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_5__ETC___d3007 =
|
|
m_pendResp_0[4:0] == 5'd5;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_5__ETC___d3007 =
|
|
m_pendResp_1[4:0] == 5'd5;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_5__ETC___d3007 =
|
|
m_pendResp_2[4:0] == 5'd5;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_5__ETC___d3007 =
|
|
m_pendResp_3[4:0] == 5'd5;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_3__ETC___d2995 =
|
|
m_pendResp_0[4:0] == 5'd3;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_3__ETC___d2995 =
|
|
m_pendResp_1[4:0] == 5'd3;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_3__ETC___d2995 =
|
|
m_pendResp_2[4:0] == 5'd3;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_3__ETC___d2995 =
|
|
m_pendResp_3[4:0] == 5'd3;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_2__ETC___d2989 =
|
|
m_pendResp_0[4:0] == 5'd2;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_2__ETC___d2989 =
|
|
m_pendResp_1[4:0] == 5'd2;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_2__ETC___d2989 =
|
|
m_pendResp_2[4:0] == 5'd2;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_2__ETC___d2989 =
|
|
m_pendResp_3[4:0] == 5'd2;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_1__ETC___d2983 =
|
|
m_pendResp_0[4:0] == 5'd1;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_1__ETC___d2983 =
|
|
m_pendResp_1[4:0] == 5'd1;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_1__ETC___d2983 =
|
|
m_pendResp_2[4:0] == 5'd1;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_1__ETC___d2983 =
|
|
m_pendResp_3[4:0] == 5'd1;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendResp_0 or m_pendResp_1 or m_pendResp_2 or m_pendResp_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_0__ETC___d2977 =
|
|
m_pendResp_0[4:0] == 5'd0;
|
|
2'd1:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_0__ETC___d2977 =
|
|
m_pendResp_1[4:0] == 5'd0;
|
|
2'd2:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_0__ETC___d2977 =
|
|
m_pendResp_2[4:0] == 5'd0;
|
|
2'd3:
|
|
SEL_ARR_m_pendResp_0_939_BITS_4_TO_0_968_EQ_0__ETC___d2977 =
|
|
m_pendResp_3[4:0] == 5'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101 =
|
|
!m_pendInst_0[463];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101 =
|
|
!m_pendInst_1[463];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101 =
|
|
!m_pendInst_2[463];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_463_092_093_NO_ETC___d3101 =
|
|
!m_pendInst_3[463];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_475_073_m_pendInst_ETC___d3078 =
|
|
m_pendInst_0[475];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_475_073_m_pendInst_ETC___d3078 =
|
|
m_pendInst_1[475];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_475_073_m_pendInst_ETC___d3078 =
|
|
m_pendInst_2[475];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_475_073_m_pendInst_ETC___d3078 =
|
|
m_pendInst_3[475];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_457_117_m_pendInst_ETC___d3122 =
|
|
m_pendInst_0[457];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_457_117_m_pendInst_ETC___d3122 =
|
|
m_pendInst_1[457];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_457_117_m_pendInst_ETC___d3122 =
|
|
m_pendInst_2[457];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_457_117_m_pendInst_ETC___d3122 =
|
|
m_pendInst_3[457];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_347_294_m_pendInst_ETC___d3299 =
|
|
m_pendInst_0[347];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_347_294_m_pendInst_ETC___d3299 =
|
|
m_pendInst_1[347];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_347_294_m_pendInst_ETC___d3299 =
|
|
m_pendInst_2[347];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_347_294_m_pendInst_ETC___d3299 =
|
|
m_pendInst_3[347];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_353_258_m_pendInst_ETC___d3263 =
|
|
m_pendInst_0[353];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_353_258_m_pendInst_ETC___d3263 =
|
|
m_pendInst_1[353];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_353_258_m_pendInst_ETC___d3263 =
|
|
m_pendInst_2[353];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_353_258_m_pendInst_ETC___d3263 =
|
|
m_pendInst_3[353];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_282_TO_281_389_m__ETC___d3394 =
|
|
m_pendInst_0[282:281];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_282_TO_281_389_m__ETC___d3394 =
|
|
m_pendInst_1[282:281];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_282_TO_281_389_m__ETC___d3394 =
|
|
m_pendInst_2[282:281];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_282_TO_281_389_m__ETC___d3394 =
|
|
m_pendInst_3[282:281];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_456_123_m_pendInst_ETC___d3128 =
|
|
m_pendInst_0[456];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_456_123_m_pendInst_ETC___d3128 =
|
|
m_pendInst_1[456];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_456_123_m_pendInst_ETC___d3128 =
|
|
m_pendInst_2[456];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_456_123_m_pendInst_ETC___d3128 =
|
|
m_pendInst_3[456];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_284_377_m_pendInst_ETC___d3382 =
|
|
m_pendInst_0[284];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_284_377_m_pendInst_ETC___d3382 =
|
|
m_pendInst_1[284];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_284_377_m_pendInst_ETC___d3382 =
|
|
m_pendInst_2[284];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_284_377_m_pendInst_ETC___d3382 =
|
|
m_pendInst_3[284];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_277_410_411_NO_ETC___d3419 =
|
|
!m_pendInst_0[277];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_277_410_411_NO_ETC___d3419 =
|
|
!m_pendInst_1[277];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_277_410_411_NO_ETC___d3419 =
|
|
!m_pendInst_2[277];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_277_410_411_NO_ETC___d3419 =
|
|
!m_pendInst_3[277];
|
|
endcase
|
|
end
|
|
always@(m_pendInst_0)
|
|
begin
|
|
case (m_pendInst_0[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 =
|
|
m_pendInst_0[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 = 5'd22;
|
|
default: IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(m_pendInst_1)
|
|
begin
|
|
case (m_pendInst_1[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 =
|
|
m_pendInst_1[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 = 5'd22;
|
|
default: IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(m_pendInst_2)
|
|
begin
|
|
case (m_pendInst_2[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 =
|
|
m_pendInst_2[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 = 5'd22;
|
|
default: IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(m_pendInst_3)
|
|
begin
|
|
case (m_pendInst_3[270:266])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 =
|
|
m_pendInst_3[270:266];
|
|
5'd16:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd12;
|
|
5'd17:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd13;
|
|
5'd18:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd14;
|
|
5'd19:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd15;
|
|
5'd20:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd16;
|
|
5'd21:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd17;
|
|
5'd22:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd18;
|
|
5'd23:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd19;
|
|
5'd24:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd20;
|
|
5'd25:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd21;
|
|
5'd26:
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 = 5'd22;
|
|
default: IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 =
|
|
5'd23;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3752 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd22;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3752 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd22;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3752 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd22;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3752 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd22;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3746 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd21;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3746 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd21;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3746 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd21;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3746 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd21;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3740 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd20;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3740 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd20;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3740 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd20;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3740 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd20;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3734 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd19;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3734 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd19;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3734 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd19;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3734 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd19;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3728 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd18;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3728 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd18;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3728 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd18;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3728 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd18;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3722 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd17;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3722 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd17;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3722 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd17;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3722 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd17;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3716 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd16;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3716 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd16;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3716 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd16;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3716 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd16;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3710 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd15;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3710 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd15;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3710 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd15;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3710 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd15;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3704 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd14;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3704 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd14;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3704 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd14;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3704 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd14;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3698 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd13;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3698 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd13;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3698 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd13;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3698 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd13;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3692 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd12;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3692 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd12;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3692 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd12;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3692 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd12;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3680 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd10;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3680 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd10;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3680 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd10;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3680 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd10;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3686 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd11;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3686 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd11;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3686 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd11;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3686 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd11;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3674 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd9;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3674 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd9;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3674 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd9;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3674 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd9;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3668 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd8;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3668 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd8;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3668 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd8;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3668 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd8;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3662 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd7;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3662 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd7;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3662 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd7;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3662 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd7;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3656 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd6;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3656 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd6;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3656 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd6;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3656 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd6;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3650 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd5;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3650 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd5;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3650 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd5;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3650 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd5;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3644 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd4;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3644 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd4;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3644 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd4;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3644 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd4;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3638 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd3;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3638 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd3;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3638 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd3;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3638 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd3;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3632 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd2;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3632 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd2;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3632 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd2;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3632 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd2;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3626 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd1;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3626 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd1;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3626 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd1;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3626 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd1;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_276_TO_271_421_m__ETC___d3426 =
|
|
m_pendInst_0[276:271];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_276_TO_271_421_m__ETC___d3426 =
|
|
m_pendInst_1[276:271];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_276_TO_271_421_m__ETC___d3426 =
|
|
m_pendInst_2[276:271];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_276_TO_271_421_m__ETC___d3426 =
|
|
m_pendInst_3[276:271];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 or
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 or
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 or
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3620 =
|
|
IF_m_pendInst_0_18_BITS_270_TO_266_427_EQ_0_42_ETC___d3473 ==
|
|
5'd0;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3620 =
|
|
IF_m_pendInst_1_20_BITS_270_TO_266_475_EQ_0_47_ETC___d3521 ==
|
|
5'd0;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3620 =
|
|
IF_m_pendInst_2_22_BITS_270_TO_266_523_EQ_0_52_ETC___d3569 ==
|
|
5'd0;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendInst_0_18_BITS_270_TO_266_427_ETC___d3620 =
|
|
IF_m_pendInst_3_24_BITS_270_TO_266_571_EQ_0_57_ETC___d3617 ==
|
|
5'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_265_778_779_NO_ETC___d3787 =
|
|
!m_pendInst_0[265];
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_265_778_779_NO_ETC___d3787 =
|
|
!m_pendInst_1[265];
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_265_778_779_NO_ETC___d3787 =
|
|
!m_pendInst_2[265];
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendInst_0_18_BIT_265_778_779_NO_ETC___d3787 =
|
|
!m_pendInst_3[265];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q35 =
|
|
m_ldTransRsFromPQ_data_0[9];
|
|
1'd1:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q35 =
|
|
m_ldTransRsFromPQ_data_1[9];
|
|
endcase
|
|
end
|
|
always@(m_ldTransRsFromPQ_deqP or
|
|
m_ldTransRsFromPQ_data_0 or m_ldTransRsFromPQ_data_1)
|
|
begin
|
|
case (m_ldTransRsFromPQ_deqP)
|
|
1'd0:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q36 =
|
|
m_ldTransRsFromPQ_data_0[10];
|
|
1'd1:
|
|
CASE_m_ldTransRsFromPQ_deqP_0_m_ldTransRsFromP_ETC__q36 =
|
|
m_ldTransRsFromPQ_data_1[10];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_346_300_m_pendInst_ETC___d3305 =
|
|
m_pendInst_0[346];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_346_300_m_pendInst_ETC___d3305 =
|
|
m_pendInst_1[346];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_346_300_m_pendInst_ETC___d3305 =
|
|
m_pendInst_2[346];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_346_300_m_pendInst_ETC___d3305 =
|
|
m_pendInst_3[346];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_345_306_m_pendInst_ETC___d3311 =
|
|
m_pendInst_0[345];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_345_306_m_pendInst_ETC___d3311 =
|
|
m_pendInst_1[345];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_345_306_m_pendInst_ETC___d3311 =
|
|
m_pendInst_2[345];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_345_306_m_pendInst_ETC___d3311 =
|
|
m_pendInst_3[345];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_455_130_m_pendInst_ETC___d3135 =
|
|
m_pendInst_0[455];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_455_130_m_pendInst_ETC___d3135 =
|
|
m_pendInst_1[455];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_455_130_m_pendInst_ETC___d3135 =
|
|
m_pendInst_2[455];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_455_130_m_pendInst_ETC___d3135 =
|
|
m_pendInst_3[455];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_280_TO_279_395_m__ETC___d3400 =
|
|
m_pendInst_0[280:279];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_280_TO_279_395_m__ETC___d3400 =
|
|
m_pendInst_1[280:279];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_280_TO_279_395_m__ETC___d3400 =
|
|
m_pendInst_2[280:279];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_280_TO_279_395_m__ETC___d3400 =
|
|
m_pendInst_3[280:279];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_454_136_m_pendInst_ETC___d3141 =
|
|
m_pendInst_0[454];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_454_136_m_pendInst_ETC___d3141 =
|
|
m_pendInst_1[454];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_454_136_m_pendInst_ETC___d3141 =
|
|
m_pendInst_2[454];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_454_136_m_pendInst_ETC___d3141 =
|
|
m_pendInst_3[454];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_348_288_m_pendInst_ETC___d3293 =
|
|
m_pendInst_0[348];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_348_288_m_pendInst_ETC___d3293 =
|
|
m_pendInst_1[348];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_348_288_m_pendInst_ETC___d3293 =
|
|
m_pendInst_2[348];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_348_288_m_pendInst_ETC___d3293 =
|
|
m_pendInst_3[348];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_349_282_m_pendInst_ETC___d3287 =
|
|
m_pendInst_0[349];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_349_282_m_pendInst_ETC___d3287 =
|
|
m_pendInst_1[349];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_349_282_m_pendInst_ETC___d3287 =
|
|
m_pendInst_2[349];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_349_282_m_pendInst_ETC___d3287 =
|
|
m_pendInst_3[349];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_461_TO_458_109_m__ETC___d3114 =
|
|
m_pendInst_0[461:458];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_461_TO_458_109_m__ETC___d3114 =
|
|
m_pendInst_1[461:458];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_461_TO_458_109_m__ETC___d3114 =
|
|
m_pendInst_2[461:458];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_461_TO_458_109_m__ETC___d3114 =
|
|
m_pendInst_3[461:458];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_283_383_m_pendInst_ETC___d3388 =
|
|
m_pendInst_0[283];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_283_383_m_pendInst_ETC___d3388 =
|
|
m_pendInst_1[283];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_283_383_m_pendInst_ETC___d3388 =
|
|
m_pendInst_2[283];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_283_383_m_pendInst_ETC___d3388 =
|
|
m_pendInst_3[283];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_453_143_m_pendInst_ETC___d3148 =
|
|
m_pendInst_0[453];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_453_143_m_pendInst_ETC___d3148 =
|
|
m_pendInst_1[453];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_453_143_m_pendInst_ETC___d3148 =
|
|
m_pendInst_2[453];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_453_143_m_pendInst_ETC___d3148 =
|
|
m_pendInst_3[453];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_452_149_m_pendInst_ETC___d3154 =
|
|
m_pendInst_0[452];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_452_149_m_pendInst_ETC___d3154 =
|
|
m_pendInst_1[452];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_452_149_m_pendInst_ETC___d3154 =
|
|
m_pendInst_2[452];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_452_149_m_pendInst_ETC___d3154 =
|
|
m_pendInst_3[452];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_351_270_m_pendInst_ETC___d3275 =
|
|
m_pendInst_0[351];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_351_270_m_pendInst_ETC___d3275 =
|
|
m_pendInst_1[351];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_351_270_m_pendInst_ETC___d3275 =
|
|
m_pendInst_2[351];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_351_270_m_pendInst_ETC___d3275 =
|
|
m_pendInst_3[351];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_451_156_m_pendInst_ETC___d3161 =
|
|
m_pendInst_0[451];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_451_156_m_pendInst_ETC___d3161 =
|
|
m_pendInst_1[451];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_451_156_m_pendInst_ETC___d3161 =
|
|
m_pendInst_2[451];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_451_156_m_pendInst_ETC___d3161 =
|
|
m_pendInst_3[451];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_350_276_m_pendInst_ETC___d3281 =
|
|
m_pendInst_0[350];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_350_276_m_pendInst_ETC___d3281 =
|
|
m_pendInst_1[350];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_350_276_m_pendInst_ETC___d3281 =
|
|
m_pendInst_2[350];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_350_276_m_pendInst_ETC___d3281 =
|
|
m_pendInst_3[350];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_450_162_m_pendInst_ETC___d3167 =
|
|
m_pendInst_0[450];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_450_162_m_pendInst_ETC___d3167 =
|
|
m_pendInst_1[450];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_450_162_m_pendInst_ETC___d3167 =
|
|
m_pendInst_2[450];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_450_162_m_pendInst_ETC___d3167 =
|
|
m_pendInst_3[450];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_352_264_m_pendInst_ETC___d3269 =
|
|
m_pendInst_0[352];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_352_264_m_pendInst_ETC___d3269 =
|
|
m_pendInst_1[352];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_352_264_m_pendInst_ETC___d3269 =
|
|
m_pendInst_2[352];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_352_264_m_pendInst_ETC___d3269 =
|
|
m_pendInst_3[352];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_288_TO_286_365_m__ETC___d3370 =
|
|
m_pendInst_0[288:286];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_288_TO_286_365_m__ETC___d3370 =
|
|
m_pendInst_1[288:286];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_288_TO_286_365_m__ETC___d3370 =
|
|
m_pendInst_2[288:286];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_288_TO_286_365_m__ETC___d3370 =
|
|
m_pendInst_3[288:286];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_285_371_m_pendInst_ETC___d3376 =
|
|
m_pendInst_0[285];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_285_371_m_pendInst_ETC___d3376 =
|
|
m_pendInst_1[285];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_285_371_m_pendInst_ETC___d3376 =
|
|
m_pendInst_2[285];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_285_371_m_pendInst_ETC___d3376 =
|
|
m_pendInst_3[285];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_448_175_m_pendInst_ETC___d3180 =
|
|
m_pendInst_0[448];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_448_175_m_pendInst_ETC___d3180 =
|
|
m_pendInst_1[448];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_448_175_m_pendInst_ETC___d3180 =
|
|
m_pendInst_2[448];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_448_175_m_pendInst_ETC___d3180 =
|
|
m_pendInst_3[448];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_449_169_m_pendInst_ETC___d3174 =
|
|
m_pendInst_0[449];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_449_169_m_pendInst_ETC___d3174 =
|
|
m_pendInst_1[449];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_449_169_m_pendInst_ETC___d3174 =
|
|
m_pendInst_2[449];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_449_169_m_pendInst_ETC___d3174 =
|
|
m_pendInst_3[449];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_355_246_m_pendInst_ETC___d3251 =
|
|
m_pendInst_0[355];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_355_246_m_pendInst_ETC___d3251 =
|
|
m_pendInst_1[355];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_355_246_m_pendInst_ETC___d3251 =
|
|
m_pendInst_2[355];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_355_246_m_pendInst_ETC___d3251 =
|
|
m_pendInst_3[355];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_354_252_m_pendInst_ETC___d3257 =
|
|
m_pendInst_0[354];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_354_252_m_pendInst_ETC___d3257 =
|
|
m_pendInst_1[354];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_354_252_m_pendInst_ETC___d3257 =
|
|
m_pendInst_2[354];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_354_252_m_pendInst_ETC___d3257 =
|
|
m_pendInst_3[354];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_474_TO_470_079_m__ETC___d3084 =
|
|
m_pendInst_0[474:470];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_474_TO_470_079_m__ETC___d3084 =
|
|
m_pendInst_1[474:470];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_474_TO_470_079_m__ETC___d3084 =
|
|
m_pendInst_2[474:470];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_474_TO_470_079_m__ETC___d3084 =
|
|
m_pendInst_3[474:470];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_469_TO_464_085_m__ETC___d3090 =
|
|
m_pendInst_0[469:464];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_469_TO_464_085_m__ETC___d3090 =
|
|
m_pendInst_1[469:464];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_469_TO_464_085_m__ETC___d3090 =
|
|
m_pendInst_2[469:464];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_469_TO_464_085_m__ETC___d3090 =
|
|
m_pendInst_3[469:464];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_447_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_0[447];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_447_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_1[447];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_447_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_2[447];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_447_182_m_pendInst_ETC___d3187 =
|
|
m_pendInst_3[447];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_445_195_m_pendInst_ETC___d3200 =
|
|
m_pendInst_0[445];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_445_195_m_pendInst_ETC___d3200 =
|
|
m_pendInst_1[445];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_445_195_m_pendInst_ETC___d3200 =
|
|
m_pendInst_2[445];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_445_195_m_pendInst_ETC___d3200 =
|
|
m_pendInst_3[445];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_446_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_0[446];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_446_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_1[446];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_446_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_2[446];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_446_188_m_pendInst_ETC___d3193 =
|
|
m_pendInst_3[446];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_444_201_m_pendInst_ETC___d3206 =
|
|
m_pendInst_0[444];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_444_201_m_pendInst_ETC___d3206 =
|
|
m_pendInst_1[444];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_444_201_m_pendInst_ETC___d3206 =
|
|
m_pendInst_2[444];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_444_201_m_pendInst_ETC___d3206 =
|
|
m_pendInst_3[444];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_360_TO_357_234_m__ETC___d3239 =
|
|
m_pendInst_0[360:357];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_360_TO_357_234_m__ETC___d3239 =
|
|
m_pendInst_1[360:357];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_360_TO_357_234_m__ETC___d3239 =
|
|
m_pendInst_2[360:357];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_360_TO_357_234_m__ETC___d3239 =
|
|
m_pendInst_3[360:357];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_356_240_m_pendInst_ETC___d3245 =
|
|
m_pendInst_0[356];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_356_240_m_pendInst_ETC___d3245 =
|
|
m_pendInst_1[356];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_356_240_m_pendInst_ETC___d3245 =
|
|
m_pendInst_2[356];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_356_240_m_pendInst_ETC___d3245 =
|
|
m_pendInst_3[356];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_443_208_m_pendInst_ETC___d3213 =
|
|
m_pendInst_0[443];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_443_208_m_pendInst_ETC___d3213 =
|
|
m_pendInst_1[443];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_443_208_m_pendInst_ETC___d3213 =
|
|
m_pendInst_2[443];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_443_208_m_pendInst_ETC___d3213 =
|
|
m_pendInst_3[443];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_322_TO_317_342_m__ETC___d3347 =
|
|
m_pendInst_0[322:317];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_322_TO_317_342_m__ETC___d3347 =
|
|
m_pendInst_1[322:317];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_322_TO_317_342_m__ETC___d3347 =
|
|
m_pendInst_2[322:317];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_322_TO_317_342_m__ETC___d3347 =
|
|
m_pendInst_3[322:317];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_442_214_m_pendInst_ETC___d3219 =
|
|
m_pendInst_0[442];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_442_214_m_pendInst_ETC___d3219 =
|
|
m_pendInst_1[442];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_442_214_m_pendInst_ETC___d3219 =
|
|
m_pendInst_2[442];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_442_214_m_pendInst_ETC___d3219 =
|
|
m_pendInst_3[442];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_341_TO_324_330_m__ETC___d3335 =
|
|
m_pendInst_0[341:324];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_341_TO_324_330_m__ETC___d3335 =
|
|
m_pendInst_1[341:324];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_341_TO_324_330_m__ETC___d3335 =
|
|
m_pendInst_2[341:324];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_341_TO_324_330_m__ETC___d3335 =
|
|
m_pendInst_3[341:324];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_344_318_m_pendInst_ETC___d3323 =
|
|
m_pendInst_0[344];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_344_318_m_pendInst_ETC___d3323 =
|
|
m_pendInst_1[344];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_344_318_m_pendInst_ETC___d3323 =
|
|
m_pendInst_2[344];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_344_318_m_pendInst_ETC___d3323 =
|
|
m_pendInst_3[344];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_323_336_m_pendInst_ETC___d3341 =
|
|
m_pendInst_0[323];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_323_336_m_pendInst_ETC___d3341 =
|
|
m_pendInst_1[323];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_323_336_m_pendInst_ETC___d3341 =
|
|
m_pendInst_2[323];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_323_336_m_pendInst_ETC___d3341 =
|
|
m_pendInst_3[323];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_343_TO_342_324_m__ETC___d3329 =
|
|
m_pendInst_0[343:342];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_343_TO_342_324_m__ETC___d3329 =
|
|
m_pendInst_1[343:342];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_343_TO_342_324_m__ETC___d3329 =
|
|
m_pendInst_2[343:342];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_343_TO_342_324_m__ETC___d3329 =
|
|
m_pendInst_3[343:342];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_374_TO_361_228_m__ETC___d3233 =
|
|
m_pendInst_0[374:361];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_374_TO_361_228_m__ETC___d3233 =
|
|
m_pendInst_1[374:361];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_374_TO_361_228_m__ETC___d3233 =
|
|
m_pendInst_2[374:361];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_374_TO_361_228_m__ETC___d3233 =
|
|
m_pendInst_3[374:361];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_0_819_m_pendInst_1_ETC___d3824 =
|
|
m_pendInst_0[0];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_0_819_m_pendInst_1_ETC___d3824 =
|
|
m_pendInst_1[0];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_0_819_m_pendInst_1_ETC___d3824 =
|
|
m_pendInst_2[0];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_0_819_m_pendInst_1_ETC___d3824 =
|
|
m_pendInst_3[0];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_135_TO_130_801_m__ETC___d3806 =
|
|
m_pendInst_0[135:130];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_135_TO_130_801_m__ETC___d3806 =
|
|
m_pendInst_1[135:130];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_135_TO_130_801_m__ETC___d3806 =
|
|
m_pendInst_2[135:130];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_135_TO_130_801_m__ETC___d3806 =
|
|
m_pendInst_3[135:130];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_441_221_m_pendInst_ETC___d3226 =
|
|
m_pendInst_0[441];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_441_221_m_pendInst_ETC___d3226 =
|
|
m_pendInst_1[441];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_441_221_m_pendInst_ETC___d3226 =
|
|
m_pendInst_2[441];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_441_221_m_pendInst_ETC___d3226 =
|
|
m_pendInst_3[441];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_440_TO_375_794_m__ETC___d3227 =
|
|
m_pendInst_0[440:375];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_440_TO_375_794_m__ETC___d3227 =
|
|
m_pendInst_1[440:375];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_440_TO_375_794_m__ETC___d3227 =
|
|
m_pendInst_2[440:375];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_440_TO_375_794_m__ETC___d3227 =
|
|
m_pendInst_3[440:375];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BIT_278_404_m_pendInst_ETC___d3409 =
|
|
m_pendInst_0[278];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BIT_278_404_m_pendInst_ETC___d3409 =
|
|
m_pendInst_1[278];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BIT_278_404_m_pendInst_ETC___d3409 =
|
|
m_pendInst_2[278];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BIT_278_404_m_pendInst_ETC___d3409 =
|
|
m_pendInst_3[278];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_462_TO_458_103_m__ETC___d3108 =
|
|
m_pendInst_0[462:458];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_462_TO_458_103_m__ETC___d3108 =
|
|
m_pendInst_1[462:458];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_462_TO_458_103_m__ETC___d3108 =
|
|
m_pendInst_2[462:458];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_462_TO_458_103_m__ETC___d3108 =
|
|
m_pendInst_3[462:458];
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendInst_0 or m_pendInst_1 or m_pendInst_2 or m_pendInst_3)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d3072 =
|
|
m_pendInst_0[478:476];
|
|
2'd1:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d3072 =
|
|
m_pendInst_1[478:476];
|
|
2'd2:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d3072 =
|
|
m_pendInst_2[478:476];
|
|
2'd3:
|
|
SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_m_p_ETC___d3072 =
|
|
m_pendInst_3[478:476];
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
m_pendWait_0 or m_pendWait_1 or m_pendWait_2 or m_pendWait_3)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_0_OR_NOT_m_pendWait_0_66_BITS_3_TO_2_6_ETC___d1887 =
|
|
m_pendWait_0[3:2] != 2'd1;
|
|
2'd1:
|
|
SEL_ARR_0_OR_NOT_m_pendWait_0_66_BITS_3_TO_2_6_ETC___d1887 =
|
|
m_pendWait_1[3:2] != 2'd1;
|
|
2'd2:
|
|
SEL_ARR_0_OR_NOT_m_pendWait_0_66_BITS_3_TO_2_6_ETC___d1887 =
|
|
m_pendWait_2[3:2] != 2'd1;
|
|
2'd3:
|
|
SEL_ARR_0_OR_NOT_m_pendWait_0_66_BITS_3_TO_2_6_ETC___d1887 =
|
|
m_pendWait_3[3:2] != 2'd1;
|
|
endcase
|
|
end
|
|
always@(idx__h74945 or
|
|
m_pendWait_0 or m_pendWait_1 or m_pendWait_2 or m_pendWait_3)
|
|
begin
|
|
case (idx__h74945)
|
|
2'd0:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d1958 =
|
|
m_pendWait_0[3:2] != 2'd0;
|
|
2'd1:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d1958 =
|
|
m_pendWait_1[3:2] != 2'd0;
|
|
2'd2:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d1958 =
|
|
m_pendWait_2[3:2] != 2'd0;
|
|
2'd3:
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d1958 =
|
|
m_pendWait_3[3:2] != 2'd0;
|
|
endcase
|
|
end
|
|
always@(idx__h95690 or
|
|
m_pendSpecBits_0_rl or
|
|
m_pendSpecBits_1_rl or m_pendSpecBits_2_rl or m_pendSpecBits_3_rl)
|
|
begin
|
|
case (idx__h95690)
|
|
2'd0:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3834 =
|
|
m_pendSpecBits_0_rl;
|
|
2'd1:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3834 =
|
|
m_pendSpecBits_1_rl;
|
|
2'd2:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3834 =
|
|
m_pendSpecBits_2_rl;
|
|
2'd3:
|
|
SEL_ARR_m_pendSpecBits_0_rl_2_m_pendSpecBits_1_ETC___d3834 =
|
|
m_pendSpecBits_3_rl;
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or
|
|
m_rqToPQ_data_0 or
|
|
m_rqToPQ_data_1 or m_rqToPQ_data_2 or m_rqToPQ_data_3)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_1_TO_0_859_m__ETC___d3864 =
|
|
m_rqToPQ_data_0[1:0];
|
|
2'd1:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_1_TO_0_859_m__ETC___d3864 =
|
|
m_rqToPQ_data_1[1:0];
|
|
2'd2:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_1_TO_0_859_m__ETC___d3864 =
|
|
m_rqToPQ_data_2[1:0];
|
|
2'd3:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_1_TO_0_859_m__ETC___d3864 =
|
|
m_rqToPQ_data_3[1:0];
|
|
endcase
|
|
end
|
|
always@(m_rqToPQ_deqP or
|
|
m_rqToPQ_data_0 or
|
|
m_rqToPQ_data_1 or m_rqToPQ_data_2 or m_rqToPQ_data_3)
|
|
begin
|
|
case (m_rqToPQ_deqP)
|
|
2'd0:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_28_TO_2_850_m_ETC___d3858 =
|
|
m_rqToPQ_data_0[28:2];
|
|
2'd1:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_28_TO_2_850_m_ETC___d3858 =
|
|
m_rqToPQ_data_1[28:2];
|
|
2'd2:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_28_TO_2_850_m_ETC___d3858 =
|
|
m_rqToPQ_data_2[28:2];
|
|
2'd3:
|
|
SEL_ARR_m_rqToPQ_data_0_849_BITS_28_TO_2_850_m_ETC___d3858 =
|
|
m_rqToPQ_data_3[28:2];
|
|
endcase
|
|
end
|
|
always@(m_tlb_m_randIdx or INV_n__read1151__q37)
|
|
begin
|
|
case (m_tlb_m_randIdx)
|
|
5'd0:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[0];
|
|
5'd1:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[1];
|
|
5'd2:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[2];
|
|
5'd3:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[3];
|
|
5'd4:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[4];
|
|
5'd5:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[5];
|
|
5'd6:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[6];
|
|
5'd7:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[7];
|
|
5'd8:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[8];
|
|
5'd9:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[9];
|
|
5'd10:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[10];
|
|
5'd11:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[11];
|
|
5'd12:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[12];
|
|
5'd13:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[13];
|
|
5'd14:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[14];
|
|
5'd15:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[15];
|
|
5'd16:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[16];
|
|
5'd17:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[17];
|
|
5'd18:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[18];
|
|
5'd19:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[19];
|
|
5'd20:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[20];
|
|
5'd21:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[21];
|
|
5'd22:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[22];
|
|
5'd23:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[23];
|
|
5'd24:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[24];
|
|
5'd25:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[25];
|
|
5'd26:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[26];
|
|
5'd27:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[27];
|
|
5'd28:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[28];
|
|
5'd29:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[29];
|
|
5'd30:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[30];
|
|
5'd31:
|
|
SEL_ARR_INV_IF_m_tlb_m_lruBit_lat_0_whas_THEN__ETC___d1484 =
|
|
INV_n__read1151__q37[31];
|
|
endcase
|
|
end
|
|
always@(i__h94049 or
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866 or
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868 or
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870 or
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872)
|
|
begin
|
|
case (i__h94049)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d2911 =
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d2911 =
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d2911 =
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d2911 =
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872;
|
|
endcase
|
|
end
|
|
always@(i__h73125 or
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866 or
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868 or
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870 or
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872)
|
|
begin
|
|
case (i__h73125)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1906 =
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1906 =
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1906 =
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1906 =
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872;
|
|
endcase
|
|
end
|
|
always@(idx__h37917 or
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866 or
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868 or
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870 or
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872)
|
|
begin
|
|
case (idx__h37917)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1874 =
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_NOT_m_pend_ETC___d1866;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1874 =
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_NOT_m_pend_ETC___d1868;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1874 =
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_NOT_m_pend_ETC___d1870;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1874 =
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_NOT_m_pend_ETC___d1872;
|
|
endcase
|
|
end
|
|
always@(idx__h74945 or
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_m_pendVali_ETC___d45 or
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_m_pendVali_ETC___d52 or
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_m_pendVali_ETC___d59 or
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_m_pendVali_ETC___d66)
|
|
begin
|
|
case (idx__h74945)
|
|
2'd0:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_m__ETC___d1956 =
|
|
IF_m_pendValid_0_lat_0_whas__2_THEN_m_pendVali_ETC___d45;
|
|
2'd1:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_m__ETC___d1956 =
|
|
IF_m_pendValid_1_lat_0_whas__9_THEN_m_pendVali_ETC___d52;
|
|
2'd2:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_m__ETC___d1956 =
|
|
IF_m_pendValid_2_lat_0_whas__6_THEN_m_pendVali_ETC___d59;
|
|
2'd3:
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_m__ETC___d1956 =
|
|
IF_m_pendValid_3_lat_0_whas__3_THEN_m_pendVali_ETC___d66;
|
|
endcase
|
|
end
|
|
always@(procReq_req)
|
|
begin
|
|
case (procReq_req[282:278])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q38 =
|
|
procReq_req[282:278];
|
|
default: CASE_procReq_req_BITS_282_TO_278_0_procReq_req_ETC__q38 =
|
|
5'd27;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQInitIdx <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQInited <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_data_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_2 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_data_3 <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_freeQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_freeQ_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_freeQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 3'd2;
|
|
m_freeQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
83'h2AAAAAAAAAAAAAAAAAAA8;
|
|
m_ldTransRsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
83'h2AAAAAAAAAAAAAAAAAAA8;
|
|
m_ldTransRsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_ldTransRsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_ldTransRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
84'h2AAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_needFlush <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendSpecBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendSpecBits_1_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendSpecBits_2_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendSpecBits_3_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendValid_3_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_pendWait_0 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_pendWait_1 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_pendWait_2 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_pendWait_3 <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
m_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 4'd2;
|
|
m_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_respForOtherReq <= `BSV_ASSIGNMENT_DELAY 3'd2;
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_2 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_data_3 <= `BSV_ASSIGNMENT_DELAY 29'd0;
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 30'd178956970;
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
m_tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
m_tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY 6'd10;
|
|
m_tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_vm_info <= `BSV_ASSIGNMENT_DELAY 49'h1800000000000;
|
|
m_waitFlushP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_flushRqToPQ_clearReq_rl$EN)
|
|
m_flushRqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_clearReq_rl$D_IN;
|
|
if (m_flushRqToPQ_deqReq_rl$EN)
|
|
m_flushRqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_deqReq_rl$D_IN;
|
|
if (m_flushRqToPQ_empty$EN)
|
|
m_flushRqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_empty$D_IN;
|
|
if (m_flushRqToPQ_enqReq_rl$EN)
|
|
m_flushRqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRqToPQ_enqReq_rl$D_IN;
|
|
if (m_flushRqToPQ_full$EN)
|
|
m_flushRqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_flushRqToPQ_full$D_IN;
|
|
if (m_flushRsFromPQ_clearReq_rl$EN)
|
|
m_flushRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_clearReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_deqReq_rl$EN)
|
|
m_flushRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_deqReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_empty$EN)
|
|
m_flushRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_empty$D_IN;
|
|
if (m_flushRsFromPQ_enqReq_rl$EN)
|
|
m_flushRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_enqReq_rl$D_IN;
|
|
if (m_flushRsFromPQ_full$EN)
|
|
m_flushRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
m_flushRsFromPQ_full$D_IN;
|
|
if (m_freeQInitIdx$EN)
|
|
m_freeQInitIdx <= `BSV_ASSIGNMENT_DELAY m_freeQInitIdx$D_IN;
|
|
if (m_freeQInited$EN)
|
|
m_freeQInited <= `BSV_ASSIGNMENT_DELAY m_freeQInited$D_IN;
|
|
if (m_freeQ_clearReq_rl$EN)
|
|
m_freeQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_freeQ_clearReq_rl$D_IN;
|
|
if (m_freeQ_data_0$EN)
|
|
m_freeQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_0$D_IN;
|
|
if (m_freeQ_data_1$EN)
|
|
m_freeQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_1$D_IN;
|
|
if (m_freeQ_data_2$EN)
|
|
m_freeQ_data_2 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_2$D_IN;
|
|
if (m_freeQ_data_3$EN)
|
|
m_freeQ_data_3 <= `BSV_ASSIGNMENT_DELAY m_freeQ_data_3$D_IN;
|
|
if (m_freeQ_deqP$EN)
|
|
m_freeQ_deqP <= `BSV_ASSIGNMENT_DELAY m_freeQ_deqP$D_IN;
|
|
if (m_freeQ_deqReq_rl$EN)
|
|
m_freeQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_freeQ_deqReq_rl$D_IN;
|
|
if (m_freeQ_empty$EN)
|
|
m_freeQ_empty <= `BSV_ASSIGNMENT_DELAY m_freeQ_empty$D_IN;
|
|
if (m_freeQ_enqP$EN)
|
|
m_freeQ_enqP <= `BSV_ASSIGNMENT_DELAY m_freeQ_enqP$D_IN;
|
|
if (m_freeQ_enqReq_rl$EN)
|
|
m_freeQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_freeQ_enqReq_rl$D_IN;
|
|
if (m_freeQ_full$EN)
|
|
m_freeQ_full <= `BSV_ASSIGNMENT_DELAY m_freeQ_full$D_IN;
|
|
if (m_ldTransRsFromPQ_clearReq_rl$EN)
|
|
m_ldTransRsFromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_clearReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_data_0$EN)
|
|
m_ldTransRsFromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_data_0$D_IN;
|
|
if (m_ldTransRsFromPQ_data_1$EN)
|
|
m_ldTransRsFromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_data_1$D_IN;
|
|
if (m_ldTransRsFromPQ_deqP$EN)
|
|
m_ldTransRsFromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_deqP$D_IN;
|
|
if (m_ldTransRsFromPQ_deqReq_rl$EN)
|
|
m_ldTransRsFromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_deqReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_empty$EN)
|
|
m_ldTransRsFromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_empty$D_IN;
|
|
if (m_ldTransRsFromPQ_enqP$EN)
|
|
m_ldTransRsFromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_enqP$D_IN;
|
|
if (m_ldTransRsFromPQ_enqReq_rl$EN)
|
|
m_ldTransRsFromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_enqReq_rl$D_IN;
|
|
if (m_ldTransRsFromPQ_full$EN)
|
|
m_ldTransRsFromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
m_ldTransRsFromPQ_full$D_IN;
|
|
if (m_needFlush$EN)
|
|
m_needFlush <= `BSV_ASSIGNMENT_DELAY m_needFlush$D_IN;
|
|
if (m_pendSpecBits_0_rl$EN)
|
|
m_pendSpecBits_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_0_rl$D_IN;
|
|
if (m_pendSpecBits_1_rl$EN)
|
|
m_pendSpecBits_1_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_1_rl$D_IN;
|
|
if (m_pendSpecBits_2_rl$EN)
|
|
m_pendSpecBits_2_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_2_rl$D_IN;
|
|
if (m_pendSpecBits_3_rl$EN)
|
|
m_pendSpecBits_3_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_pendSpecBits_3_rl$D_IN;
|
|
if (m_pendValid_0_rl$EN)
|
|
m_pendValid_0_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_0_rl$D_IN;
|
|
if (m_pendValid_1_rl$EN)
|
|
m_pendValid_1_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_1_rl$D_IN;
|
|
if (m_pendValid_2_rl$EN)
|
|
m_pendValid_2_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_2_rl$D_IN;
|
|
if (m_pendValid_3_rl$EN)
|
|
m_pendValid_3_rl <= `BSV_ASSIGNMENT_DELAY m_pendValid_3_rl$D_IN;
|
|
if (m_pendWait_0$EN)
|
|
m_pendWait_0 <= `BSV_ASSIGNMENT_DELAY m_pendWait_0$D_IN;
|
|
if (m_pendWait_1$EN)
|
|
m_pendWait_1 <= `BSV_ASSIGNMENT_DELAY m_pendWait_1$D_IN;
|
|
if (m_pendWait_2$EN)
|
|
m_pendWait_2 <= `BSV_ASSIGNMENT_DELAY m_pendWait_2$D_IN;
|
|
if (m_pendWait_3$EN)
|
|
m_pendWait_3 <= `BSV_ASSIGNMENT_DELAY m_pendWait_3$D_IN;
|
|
if (m_perfReqQ_clearReq_rl$EN)
|
|
m_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_clearReq_rl$D_IN;
|
|
if (m_perfReqQ_data_0$EN)
|
|
m_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_data_0$D_IN;
|
|
if (m_perfReqQ_deqReq_rl$EN)
|
|
m_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_deqReq_rl$D_IN;
|
|
if (m_perfReqQ_empty$EN)
|
|
m_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_empty$D_IN;
|
|
if (m_perfReqQ_enqReq_rl$EN)
|
|
m_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_perfReqQ_enqReq_rl$D_IN;
|
|
if (m_perfReqQ_full$EN)
|
|
m_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY m_perfReqQ_full$D_IN;
|
|
if (m_respForOtherReq$EN)
|
|
m_respForOtherReq <= `BSV_ASSIGNMENT_DELAY m_respForOtherReq$D_IN;
|
|
if (m_rqToPQ_clearReq_rl$EN)
|
|
m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rqToPQ_clearReq_rl$D_IN;
|
|
if (m_rqToPQ_data_0$EN)
|
|
m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_0$D_IN;
|
|
if (m_rqToPQ_data_1$EN)
|
|
m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_1$D_IN;
|
|
if (m_rqToPQ_data_2$EN)
|
|
m_rqToPQ_data_2 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_2$D_IN;
|
|
if (m_rqToPQ_data_3$EN)
|
|
m_rqToPQ_data_3 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_3$D_IN;
|
|
if (m_rqToPQ_deqP$EN)
|
|
m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqP$D_IN;
|
|
if (m_rqToPQ_deqReq_rl$EN)
|
|
m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqReq_rl$D_IN;
|
|
if (m_rqToPQ_empty$EN)
|
|
m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_empty$D_IN;
|
|
if (m_rqToPQ_enqP$EN)
|
|
m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqP$D_IN;
|
|
if (m_rqToPQ_enqReq_rl$EN)
|
|
m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqReq_rl$D_IN;
|
|
if (m_rqToPQ_full$EN)
|
|
m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_full$D_IN;
|
|
if (m_tlb_m_lruBit_rl$EN)
|
|
m_tlb_m_lruBit_rl <= `BSV_ASSIGNMENT_DELAY m_tlb_m_lruBit_rl$D_IN;
|
|
if (m_tlb_m_randIdx$EN)
|
|
m_tlb_m_randIdx <= `BSV_ASSIGNMENT_DELAY m_tlb_m_randIdx$D_IN;
|
|
if (m_tlb_m_updRepIdx_rl$EN)
|
|
m_tlb_m_updRepIdx_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_updRepIdx_rl$D_IN;
|
|
if (m_tlb_m_validVec_0$EN)
|
|
m_tlb_m_validVec_0 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_0$D_IN;
|
|
if (m_tlb_m_validVec_1$EN)
|
|
m_tlb_m_validVec_1 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_1$D_IN;
|
|
if (m_tlb_m_validVec_10$EN)
|
|
m_tlb_m_validVec_10 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_10$D_IN;
|
|
if (m_tlb_m_validVec_11$EN)
|
|
m_tlb_m_validVec_11 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_11$D_IN;
|
|
if (m_tlb_m_validVec_12$EN)
|
|
m_tlb_m_validVec_12 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_12$D_IN;
|
|
if (m_tlb_m_validVec_13$EN)
|
|
m_tlb_m_validVec_13 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_13$D_IN;
|
|
if (m_tlb_m_validVec_14$EN)
|
|
m_tlb_m_validVec_14 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_14$D_IN;
|
|
if (m_tlb_m_validVec_15$EN)
|
|
m_tlb_m_validVec_15 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_15$D_IN;
|
|
if (m_tlb_m_validVec_16$EN)
|
|
m_tlb_m_validVec_16 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_16$D_IN;
|
|
if (m_tlb_m_validVec_17$EN)
|
|
m_tlb_m_validVec_17 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_17$D_IN;
|
|
if (m_tlb_m_validVec_18$EN)
|
|
m_tlb_m_validVec_18 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_18$D_IN;
|
|
if (m_tlb_m_validVec_19$EN)
|
|
m_tlb_m_validVec_19 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_19$D_IN;
|
|
if (m_tlb_m_validVec_2$EN)
|
|
m_tlb_m_validVec_2 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_2$D_IN;
|
|
if (m_tlb_m_validVec_20$EN)
|
|
m_tlb_m_validVec_20 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_20$D_IN;
|
|
if (m_tlb_m_validVec_21$EN)
|
|
m_tlb_m_validVec_21 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_21$D_IN;
|
|
if (m_tlb_m_validVec_22$EN)
|
|
m_tlb_m_validVec_22 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_22$D_IN;
|
|
if (m_tlb_m_validVec_23$EN)
|
|
m_tlb_m_validVec_23 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_23$D_IN;
|
|
if (m_tlb_m_validVec_24$EN)
|
|
m_tlb_m_validVec_24 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_24$D_IN;
|
|
if (m_tlb_m_validVec_25$EN)
|
|
m_tlb_m_validVec_25 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_25$D_IN;
|
|
if (m_tlb_m_validVec_26$EN)
|
|
m_tlb_m_validVec_26 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_26$D_IN;
|
|
if (m_tlb_m_validVec_27$EN)
|
|
m_tlb_m_validVec_27 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_27$D_IN;
|
|
if (m_tlb_m_validVec_28$EN)
|
|
m_tlb_m_validVec_28 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_28$D_IN;
|
|
if (m_tlb_m_validVec_29$EN)
|
|
m_tlb_m_validVec_29 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_29$D_IN;
|
|
if (m_tlb_m_validVec_3$EN)
|
|
m_tlb_m_validVec_3 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_3$D_IN;
|
|
if (m_tlb_m_validVec_30$EN)
|
|
m_tlb_m_validVec_30 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_30$D_IN;
|
|
if (m_tlb_m_validVec_31$EN)
|
|
m_tlb_m_validVec_31 <= `BSV_ASSIGNMENT_DELAY
|
|
m_tlb_m_validVec_31$D_IN;
|
|
if (m_tlb_m_validVec_4$EN)
|
|
m_tlb_m_validVec_4 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_4$D_IN;
|
|
if (m_tlb_m_validVec_5$EN)
|
|
m_tlb_m_validVec_5 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_5$D_IN;
|
|
if (m_tlb_m_validVec_6$EN)
|
|
m_tlb_m_validVec_6 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_6$D_IN;
|
|
if (m_tlb_m_validVec_7$EN)
|
|
m_tlb_m_validVec_7 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_7$D_IN;
|
|
if (m_tlb_m_validVec_8$EN)
|
|
m_tlb_m_validVec_8 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_8$D_IN;
|
|
if (m_tlb_m_validVec_9$EN)
|
|
m_tlb_m_validVec_9 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_validVec_9$D_IN;
|
|
if (m_vm_info$EN) m_vm_info <= `BSV_ASSIGNMENT_DELAY m_vm_info$D_IN;
|
|
if (m_waitFlushP$EN)
|
|
m_waitFlushP <= `BSV_ASSIGNMENT_DELAY m_waitFlushP$D_IN;
|
|
end
|
|
if (m_pendInst_0$EN)
|
|
m_pendInst_0 <= `BSV_ASSIGNMENT_DELAY m_pendInst_0$D_IN;
|
|
if (m_pendInst_1$EN)
|
|
m_pendInst_1 <= `BSV_ASSIGNMENT_DELAY m_pendInst_1$D_IN;
|
|
if (m_pendInst_2$EN)
|
|
m_pendInst_2 <= `BSV_ASSIGNMENT_DELAY m_pendInst_2$D_IN;
|
|
if (m_pendInst_3$EN)
|
|
m_pendInst_3 <= `BSV_ASSIGNMENT_DELAY m_pendInst_3$D_IN;
|
|
if (m_pendPoisoned_0$EN)
|
|
m_pendPoisoned_0 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_0$D_IN;
|
|
if (m_pendPoisoned_1$EN)
|
|
m_pendPoisoned_1 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_1$D_IN;
|
|
if (m_pendPoisoned_2$EN)
|
|
m_pendPoisoned_2 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_2$D_IN;
|
|
if (m_pendPoisoned_3$EN)
|
|
m_pendPoisoned_3 <= `BSV_ASSIGNMENT_DELAY m_pendPoisoned_3$D_IN;
|
|
if (m_pendResp_0$EN)
|
|
m_pendResp_0 <= `BSV_ASSIGNMENT_DELAY m_pendResp_0$D_IN;
|
|
if (m_pendResp_1$EN)
|
|
m_pendResp_1 <= `BSV_ASSIGNMENT_DELAY m_pendResp_1$D_IN;
|
|
if (m_pendResp_2$EN)
|
|
m_pendResp_2 <= `BSV_ASSIGNMENT_DELAY m_pendResp_2$D_IN;
|
|
if (m_pendResp_3$EN)
|
|
m_pendResp_3 <= `BSV_ASSIGNMENT_DELAY m_pendResp_3$D_IN;
|
|
if (m_tlb_m_entryVec_0$EN)
|
|
m_tlb_m_entryVec_0 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_0$D_IN;
|
|
if (m_tlb_m_entryVec_1$EN)
|
|
m_tlb_m_entryVec_1 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_1$D_IN;
|
|
if (m_tlb_m_entryVec_10$EN)
|
|
m_tlb_m_entryVec_10 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_10$D_IN;
|
|
if (m_tlb_m_entryVec_11$EN)
|
|
m_tlb_m_entryVec_11 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_11$D_IN;
|
|
if (m_tlb_m_entryVec_12$EN)
|
|
m_tlb_m_entryVec_12 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_12$D_IN;
|
|
if (m_tlb_m_entryVec_13$EN)
|
|
m_tlb_m_entryVec_13 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_13$D_IN;
|
|
if (m_tlb_m_entryVec_14$EN)
|
|
m_tlb_m_entryVec_14 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_14$D_IN;
|
|
if (m_tlb_m_entryVec_15$EN)
|
|
m_tlb_m_entryVec_15 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_15$D_IN;
|
|
if (m_tlb_m_entryVec_16$EN)
|
|
m_tlb_m_entryVec_16 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_16$D_IN;
|
|
if (m_tlb_m_entryVec_17$EN)
|
|
m_tlb_m_entryVec_17 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_17$D_IN;
|
|
if (m_tlb_m_entryVec_18$EN)
|
|
m_tlb_m_entryVec_18 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_18$D_IN;
|
|
if (m_tlb_m_entryVec_19$EN)
|
|
m_tlb_m_entryVec_19 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_19$D_IN;
|
|
if (m_tlb_m_entryVec_2$EN)
|
|
m_tlb_m_entryVec_2 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_2$D_IN;
|
|
if (m_tlb_m_entryVec_20$EN)
|
|
m_tlb_m_entryVec_20 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_20$D_IN;
|
|
if (m_tlb_m_entryVec_21$EN)
|
|
m_tlb_m_entryVec_21 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_21$D_IN;
|
|
if (m_tlb_m_entryVec_22$EN)
|
|
m_tlb_m_entryVec_22 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_22$D_IN;
|
|
if (m_tlb_m_entryVec_23$EN)
|
|
m_tlb_m_entryVec_23 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_23$D_IN;
|
|
if (m_tlb_m_entryVec_24$EN)
|
|
m_tlb_m_entryVec_24 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_24$D_IN;
|
|
if (m_tlb_m_entryVec_25$EN)
|
|
m_tlb_m_entryVec_25 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_25$D_IN;
|
|
if (m_tlb_m_entryVec_26$EN)
|
|
m_tlb_m_entryVec_26 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_26$D_IN;
|
|
if (m_tlb_m_entryVec_27$EN)
|
|
m_tlb_m_entryVec_27 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_27$D_IN;
|
|
if (m_tlb_m_entryVec_28$EN)
|
|
m_tlb_m_entryVec_28 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_28$D_IN;
|
|
if (m_tlb_m_entryVec_29$EN)
|
|
m_tlb_m_entryVec_29 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_29$D_IN;
|
|
if (m_tlb_m_entryVec_3$EN)
|
|
m_tlb_m_entryVec_3 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_3$D_IN;
|
|
if (m_tlb_m_entryVec_30$EN)
|
|
m_tlb_m_entryVec_30 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_30$D_IN;
|
|
if (m_tlb_m_entryVec_31$EN)
|
|
m_tlb_m_entryVec_31 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_31$D_IN;
|
|
if (m_tlb_m_entryVec_4$EN)
|
|
m_tlb_m_entryVec_4 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_4$D_IN;
|
|
if (m_tlb_m_entryVec_5$EN)
|
|
m_tlb_m_entryVec_5 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_5$D_IN;
|
|
if (m_tlb_m_entryVec_6$EN)
|
|
m_tlb_m_entryVec_6 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_6$D_IN;
|
|
if (m_tlb_m_entryVec_7$EN)
|
|
m_tlb_m_entryVec_7 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_7$D_IN;
|
|
if (m_tlb_m_entryVec_8$EN)
|
|
m_tlb_m_entryVec_8 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_8$D_IN;
|
|
if (m_tlb_m_entryVec_9$EN)
|
|
m_tlb_m_entryVec_9 <= `BSV_ASSIGNMENT_DELAY m_tlb_m_entryVec_9$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_flushRqToPQ_clearReq_rl = 1'h0;
|
|
m_flushRqToPQ_deqReq_rl = 1'h0;
|
|
m_flushRqToPQ_empty = 1'h0;
|
|
m_flushRqToPQ_enqReq_rl = 1'h0;
|
|
m_flushRqToPQ_full = 1'h0;
|
|
m_flushRsFromPQ_clearReq_rl = 1'h0;
|
|
m_flushRsFromPQ_deqReq_rl = 1'h0;
|
|
m_flushRsFromPQ_empty = 1'h0;
|
|
m_flushRsFromPQ_enqReq_rl = 1'h0;
|
|
m_flushRsFromPQ_full = 1'h0;
|
|
m_freeQInitIdx = 2'h2;
|
|
m_freeQInited = 1'h0;
|
|
m_freeQ_clearReq_rl = 1'h0;
|
|
m_freeQ_data_0 = 2'h2;
|
|
m_freeQ_data_1 = 2'h2;
|
|
m_freeQ_data_2 = 2'h2;
|
|
m_freeQ_data_3 = 2'h2;
|
|
m_freeQ_deqP = 2'h2;
|
|
m_freeQ_deqReq_rl = 1'h0;
|
|
m_freeQ_empty = 1'h0;
|
|
m_freeQ_enqP = 2'h2;
|
|
m_freeQ_enqReq_rl = 3'h2;
|
|
m_freeQ_full = 1'h0;
|
|
m_ldTransRsFromPQ_clearReq_rl = 1'h0;
|
|
m_ldTransRsFromPQ_data_0 = 83'h2AAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_data_1 = 83'h2AAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_deqP = 1'h0;
|
|
m_ldTransRsFromPQ_deqReq_rl = 1'h0;
|
|
m_ldTransRsFromPQ_empty = 1'h0;
|
|
m_ldTransRsFromPQ_enqP = 1'h0;
|
|
m_ldTransRsFromPQ_enqReq_rl = 84'hAAAAAAAAAAAAAAAAAAAAA;
|
|
m_ldTransRsFromPQ_full = 1'h0;
|
|
m_needFlush = 1'h0;
|
|
m_pendInst_0 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendInst_1 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendInst_2 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendInst_3 =
|
|
479'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_pendPoisoned_0 = 1'h0;
|
|
m_pendPoisoned_1 = 1'h0;
|
|
m_pendPoisoned_2 = 1'h0;
|
|
m_pendPoisoned_3 = 1'h0;
|
|
m_pendResp_0 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_1 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_2 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendResp_3 = 70'h2AAAAAAAAAAAAAAAAA;
|
|
m_pendSpecBits_0_rl = 12'hAAA;
|
|
m_pendSpecBits_1_rl = 12'hAAA;
|
|
m_pendSpecBits_2_rl = 12'hAAA;
|
|
m_pendSpecBits_3_rl = 12'hAAA;
|
|
m_pendValid_0_rl = 1'h0;
|
|
m_pendValid_1_rl = 1'h0;
|
|
m_pendValid_2_rl = 1'h0;
|
|
m_pendValid_3_rl = 1'h0;
|
|
m_pendWait_0 = 4'hA;
|
|
m_pendWait_1 = 4'hA;
|
|
m_pendWait_2 = 4'hA;
|
|
m_pendWait_3 = 4'hA;
|
|
m_perfReqQ_clearReq_rl = 1'h0;
|
|
m_perfReqQ_data_0 = 3'h2;
|
|
m_perfReqQ_deqReq_rl = 1'h0;
|
|
m_perfReqQ_empty = 1'h0;
|
|
m_perfReqQ_enqReq_rl = 4'hA;
|
|
m_perfReqQ_full = 1'h0;
|
|
m_respForOtherReq = 3'h2;
|
|
m_rqToPQ_clearReq_rl = 1'h0;
|
|
m_rqToPQ_data_0 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_1 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_2 = 29'h0AAAAAAA;
|
|
m_rqToPQ_data_3 = 29'h0AAAAAAA;
|
|
m_rqToPQ_deqP = 2'h2;
|
|
m_rqToPQ_deqReq_rl = 1'h0;
|
|
m_rqToPQ_empty = 1'h0;
|
|
m_rqToPQ_enqP = 2'h2;
|
|
m_rqToPQ_enqReq_rl = 30'h2AAAAAAA;
|
|
m_rqToPQ_full = 1'h0;
|
|
m_tlb_m_entryVec_0 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_1 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_10 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_11 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_12 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_13 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_14 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_15 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_16 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_17 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_18 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_19 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_2 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_20 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_21 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_22 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_23 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_24 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_25 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_26 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_27 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_28 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_29 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_3 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_30 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_31 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_4 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_5 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_6 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_7 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_8 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_entryVec_9 = 80'hAAAAAAAAAAAAAAAAAAAA;
|
|
m_tlb_m_lruBit_rl = 32'hAAAAAAAA;
|
|
m_tlb_m_randIdx = 5'h0A;
|
|
m_tlb_m_updRepIdx_rl = 6'h2A;
|
|
m_tlb_m_validVec_0 = 1'h0;
|
|
m_tlb_m_validVec_1 = 1'h0;
|
|
m_tlb_m_validVec_10 = 1'h0;
|
|
m_tlb_m_validVec_11 = 1'h0;
|
|
m_tlb_m_validVec_12 = 1'h0;
|
|
m_tlb_m_validVec_13 = 1'h0;
|
|
m_tlb_m_validVec_14 = 1'h0;
|
|
m_tlb_m_validVec_15 = 1'h0;
|
|
m_tlb_m_validVec_16 = 1'h0;
|
|
m_tlb_m_validVec_17 = 1'h0;
|
|
m_tlb_m_validVec_18 = 1'h0;
|
|
m_tlb_m_validVec_19 = 1'h0;
|
|
m_tlb_m_validVec_2 = 1'h0;
|
|
m_tlb_m_validVec_20 = 1'h0;
|
|
m_tlb_m_validVec_21 = 1'h0;
|
|
m_tlb_m_validVec_22 = 1'h0;
|
|
m_tlb_m_validVec_23 = 1'h0;
|
|
m_tlb_m_validVec_24 = 1'h0;
|
|
m_tlb_m_validVec_25 = 1'h0;
|
|
m_tlb_m_validVec_26 = 1'h0;
|
|
m_tlb_m_validVec_27 = 1'h0;
|
|
m_tlb_m_validVec_28 = 1'h0;
|
|
m_tlb_m_validVec_29 = 1'h0;
|
|
m_tlb_m_validVec_3 = 1'h0;
|
|
m_tlb_m_validVec_30 = 1'h0;
|
|
m_tlb_m_validVec_31 = 1'h0;
|
|
m_tlb_m_validVec_4 = 1'h0;
|
|
m_tlb_m_validVec_5 = 1'h0;
|
|
m_tlb_m_validVec_6 = 1'h0;
|
|
m_tlb_m_validVec_7 = 1'h0;
|
|
m_tlb_m_validVec_8 = 1'h0;
|
|
m_tlb_m_validVec_9 = 1'h0;
|
|
m_vm_info = 49'h0AAAAAAAAAAAA;
|
|
m_waitFlushP = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_procReq &&
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_m__ETC___d1956)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_procReq &&
|
|
SEL_ARR_NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ__ETC___d1958)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_procReq && m_vm_info[46] &&
|
|
NOT_m_tlb_m_validVec_0_22_23_OR_NOT_IF_m_tlb_m_ETC___d2335 &&
|
|
(!m_tlb_m_validVec_31 ||
|
|
!IF_m_tlb_m_entryVec_31_376_BITS_1_TO_0_380_EQ__ETC___d2342) &&
|
|
m_pendWait_0_66_BITS_3_TO_2_67_EQ_1_70_AND_pro_ETC___d2912)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1361)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d1373)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs &&
|
|
!SEL_ARR_m_pendPoisoned_0_08_m_pendPoisoned_1_0_ETC___d613 &&
|
|
SEL_ARR_m_ldTransRsFromPQ_data_0_96_BIT_82_14__ETC___d617 &&
|
|
NOT_SEL_ARR_m_pendInst_0_18_BITS_478_TO_476_19_ETC___d720 &&
|
|
NOT_m_tlb_m_entryVec_0_25_BITS_79_TO_53_26_EQ__ETC___d744 &&
|
|
NOT_m_tlb_m_entryVec_1_50_BITS_79_TO_53_51_EQ__ETC___d1417 &&
|
|
m_tlb_m_validVec_0_22_AND_m_tlb_m_validVec_1_4_ETC___d1550)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs &&
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1874)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs &&
|
|
m_respForOtherReq_64_BIT_2_65_AND_NOT_SEL_ARR__ETC___d1880)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs && !m_respForOtherReq[2] &&
|
|
SEL_ARR_0_OR_NOT_m_pendWait_0_66_BITS_3_TO_2_6_ETC___d1887)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_m_doPRs &&
|
|
NOT_m_pendWait_0_66_BITS_3_TO_2_67_EQ_0_68_69__ETC___d1900 &&
|
|
SEL_ARR_IF_m_pendValid_0_lat_0_whas__2_THEN_NO_ETC___d1906)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkDTlbSynth
|
|
|