4091 lines
150 KiB
Verilog
4091 lines
150 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Mon Jul 13 18:34:31 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_request_put O 1
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// response_get O 69 reg
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// RDY_response_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// request_put I 131 reg
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// EN_request_put I 1
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// EN_response_get I 1
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//
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// Combinational paths from inputs to outputs:
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// EN_response_get -> RDY_request_put
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDoubleDiv(CLK,
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RST_N,
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request_put,
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EN_request_put,
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RDY_request_put,
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EN_response_get,
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response_get,
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RDY_response_get);
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input CLK;
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input RST_N;
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// action method request_put
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input [130 : 0] request_put;
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input EN_request_put;
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output RDY_request_put;
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// actionvalue method response_get
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input EN_response_get;
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output [68 : 0] response_get;
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output RDY_response_get;
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// signals for module outputs
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wire [68 : 0] response_get;
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wire RDY_request_put, RDY_response_get;
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// ports of submodule fpu_fOperands_S0
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wire [130 : 0] fpu_fOperands_S0$D_IN, fpu_fOperands_S0$D_OUT;
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wire fpu_fOperands_S0$CLR,
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fpu_fOperands_S0$DEQ,
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fpu_fOperands_S0$EMPTY_N,
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fpu_fOperands_S0$ENQ,
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fpu_fOperands_S0$FULL_N;
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// ports of submodule fpu_fResult_S5
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wire [68 : 0] fpu_fResult_S5$D_IN, fpu_fResult_S5$D_OUT;
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wire fpu_fResult_S5$CLR,
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fpu_fResult_S5$DEQ,
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fpu_fResult_S5$EMPTY_N,
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fpu_fResult_S5$ENQ,
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fpu_fResult_S5$FULL_N;
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// ports of submodule fpu_fState_S1
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wire [318 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT;
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wire fpu_fState_S1$CLR,
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fpu_fState_S1$DEQ,
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fpu_fState_S1$EMPTY_N,
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fpu_fState_S1$ENQ,
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fpu_fState_S1$FULL_N;
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// ports of submodule fpu_fState_S2
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wire [147 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT;
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wire fpu_fState_S2$CLR,
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fpu_fState_S2$DEQ,
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fpu_fState_S2$EMPTY_N,
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fpu_fState_S2$ENQ,
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fpu_fState_S2$FULL_N;
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// ports of submodule fpu_fState_S3
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wire [194 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT;
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wire fpu_fState_S3$CLR,
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fpu_fState_S3$DEQ,
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fpu_fState_S3$EMPTY_N,
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fpu_fState_S3$ENQ,
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fpu_fState_S3$FULL_N;
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// ports of submodule fpu_fState_S4
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wire [138 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT;
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wire fpu_fState_S4$CLR,
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fpu_fState_S4$DEQ,
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fpu_fState_S4$EMPTY_N,
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fpu_fState_S4$ENQ,
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fpu_fState_S4$FULL_N;
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// ports of submodule int_div_fFirst
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wire [231 : 0] int_div_fFirst$D_IN, int_div_fFirst$D_OUT;
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wire int_div_fFirst$CLR,
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int_div_fFirst$DEQ,
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int_div_fFirst$EMPTY_N,
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int_div_fFirst$ENQ,
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int_div_fFirst$FULL_N;
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// ports of submodule int_div_fNext_0
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wire [231 : 0] int_div_fNext_0$D_IN, int_div_fNext_0$D_OUT;
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wire int_div_fNext_0$CLR,
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int_div_fNext_0$DEQ,
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int_div_fNext_0$EMPTY_N,
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int_div_fNext_0$ENQ,
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int_div_fNext_0$FULL_N;
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// ports of submodule int_div_fNext_1
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wire [231 : 0] int_div_fNext_1$D_IN, int_div_fNext_1$D_OUT;
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wire int_div_fNext_1$CLR,
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int_div_fNext_1$DEQ,
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int_div_fNext_1$EMPTY_N,
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int_div_fNext_1$ENQ,
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int_div_fNext_1$FULL_N;
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// ports of submodule int_div_fNext_10
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wire [231 : 0] int_div_fNext_10$D_IN, int_div_fNext_10$D_OUT;
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wire int_div_fNext_10$CLR,
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int_div_fNext_10$DEQ,
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int_div_fNext_10$EMPTY_N,
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int_div_fNext_10$ENQ,
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int_div_fNext_10$FULL_N;
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// ports of submodule int_div_fNext_11
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wire [231 : 0] int_div_fNext_11$D_IN, int_div_fNext_11$D_OUT;
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wire int_div_fNext_11$CLR,
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int_div_fNext_11$DEQ,
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int_div_fNext_11$EMPTY_N,
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int_div_fNext_11$ENQ,
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int_div_fNext_11$FULL_N;
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// ports of submodule int_div_fNext_12
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wire [231 : 0] int_div_fNext_12$D_IN, int_div_fNext_12$D_OUT;
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wire int_div_fNext_12$CLR,
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int_div_fNext_12$DEQ,
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int_div_fNext_12$EMPTY_N,
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int_div_fNext_12$ENQ,
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int_div_fNext_12$FULL_N;
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// ports of submodule int_div_fNext_13
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wire [231 : 0] int_div_fNext_13$D_IN, int_div_fNext_13$D_OUT;
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wire int_div_fNext_13$CLR,
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int_div_fNext_13$DEQ,
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int_div_fNext_13$EMPTY_N,
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int_div_fNext_13$ENQ,
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int_div_fNext_13$FULL_N;
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// ports of submodule int_div_fNext_14
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wire [231 : 0] int_div_fNext_14$D_IN, int_div_fNext_14$D_OUT;
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wire int_div_fNext_14$CLR,
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int_div_fNext_14$DEQ,
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int_div_fNext_14$EMPTY_N,
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int_div_fNext_14$ENQ,
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int_div_fNext_14$FULL_N;
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// ports of submodule int_div_fNext_15
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wire [231 : 0] int_div_fNext_15$D_IN, int_div_fNext_15$D_OUT;
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wire int_div_fNext_15$CLR,
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int_div_fNext_15$DEQ,
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int_div_fNext_15$EMPTY_N,
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int_div_fNext_15$ENQ,
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int_div_fNext_15$FULL_N;
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// ports of submodule int_div_fNext_16
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wire [231 : 0] int_div_fNext_16$D_IN, int_div_fNext_16$D_OUT;
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wire int_div_fNext_16$CLR,
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int_div_fNext_16$DEQ,
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int_div_fNext_16$EMPTY_N,
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int_div_fNext_16$ENQ,
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int_div_fNext_16$FULL_N;
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// ports of submodule int_div_fNext_17
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wire [231 : 0] int_div_fNext_17$D_IN, int_div_fNext_17$D_OUT;
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wire int_div_fNext_17$CLR,
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int_div_fNext_17$DEQ,
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int_div_fNext_17$EMPTY_N,
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int_div_fNext_17$ENQ,
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int_div_fNext_17$FULL_N;
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// ports of submodule int_div_fNext_18
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wire [231 : 0] int_div_fNext_18$D_IN, int_div_fNext_18$D_OUT;
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wire int_div_fNext_18$CLR,
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int_div_fNext_18$DEQ,
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int_div_fNext_18$EMPTY_N,
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int_div_fNext_18$ENQ,
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int_div_fNext_18$FULL_N;
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// ports of submodule int_div_fNext_19
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wire [231 : 0] int_div_fNext_19$D_IN, int_div_fNext_19$D_OUT;
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wire int_div_fNext_19$CLR,
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int_div_fNext_19$DEQ,
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int_div_fNext_19$EMPTY_N,
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int_div_fNext_19$ENQ,
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int_div_fNext_19$FULL_N;
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// ports of submodule int_div_fNext_2
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wire [231 : 0] int_div_fNext_2$D_IN, int_div_fNext_2$D_OUT;
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wire int_div_fNext_2$CLR,
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int_div_fNext_2$DEQ,
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int_div_fNext_2$EMPTY_N,
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int_div_fNext_2$ENQ,
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int_div_fNext_2$FULL_N;
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// ports of submodule int_div_fNext_20
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wire [231 : 0] int_div_fNext_20$D_IN, int_div_fNext_20$D_OUT;
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wire int_div_fNext_20$CLR,
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int_div_fNext_20$DEQ,
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int_div_fNext_20$EMPTY_N,
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int_div_fNext_20$ENQ,
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int_div_fNext_20$FULL_N;
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// ports of submodule int_div_fNext_21
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wire [231 : 0] int_div_fNext_21$D_IN, int_div_fNext_21$D_OUT;
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wire int_div_fNext_21$CLR,
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int_div_fNext_21$DEQ,
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int_div_fNext_21$EMPTY_N,
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int_div_fNext_21$ENQ,
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int_div_fNext_21$FULL_N;
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// ports of submodule int_div_fNext_22
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wire [231 : 0] int_div_fNext_22$D_IN, int_div_fNext_22$D_OUT;
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wire int_div_fNext_22$CLR,
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int_div_fNext_22$DEQ,
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int_div_fNext_22$EMPTY_N,
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int_div_fNext_22$ENQ,
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int_div_fNext_22$FULL_N;
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// ports of submodule int_div_fNext_23
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wire [231 : 0] int_div_fNext_23$D_IN, int_div_fNext_23$D_OUT;
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wire int_div_fNext_23$CLR,
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int_div_fNext_23$DEQ,
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int_div_fNext_23$EMPTY_N,
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int_div_fNext_23$ENQ,
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int_div_fNext_23$FULL_N;
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// ports of submodule int_div_fNext_24
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wire [231 : 0] int_div_fNext_24$D_IN, int_div_fNext_24$D_OUT;
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wire int_div_fNext_24$CLR,
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int_div_fNext_24$DEQ,
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int_div_fNext_24$EMPTY_N,
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int_div_fNext_24$ENQ,
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int_div_fNext_24$FULL_N;
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// ports of submodule int_div_fNext_25
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wire [231 : 0] int_div_fNext_25$D_IN, int_div_fNext_25$D_OUT;
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wire int_div_fNext_25$CLR,
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int_div_fNext_25$DEQ,
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int_div_fNext_25$EMPTY_N,
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int_div_fNext_25$ENQ,
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int_div_fNext_25$FULL_N;
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// ports of submodule int_div_fNext_26
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wire [231 : 0] int_div_fNext_26$D_IN, int_div_fNext_26$D_OUT;
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wire int_div_fNext_26$CLR,
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int_div_fNext_26$DEQ,
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int_div_fNext_26$EMPTY_N,
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int_div_fNext_26$ENQ,
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int_div_fNext_26$FULL_N;
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// ports of submodule int_div_fNext_27
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wire [231 : 0] int_div_fNext_27$D_IN, int_div_fNext_27$D_OUT;
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wire int_div_fNext_27$CLR,
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int_div_fNext_27$DEQ,
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int_div_fNext_27$EMPTY_N,
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int_div_fNext_27$ENQ,
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int_div_fNext_27$FULL_N;
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// ports of submodule int_div_fNext_28
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wire [231 : 0] int_div_fNext_28$D_IN, int_div_fNext_28$D_OUT;
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wire int_div_fNext_28$CLR,
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int_div_fNext_28$DEQ,
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int_div_fNext_28$EMPTY_N,
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int_div_fNext_28$ENQ,
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int_div_fNext_28$FULL_N;
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// ports of submodule int_div_fNext_29
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wire [231 : 0] int_div_fNext_29$D_IN, int_div_fNext_29$D_OUT;
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wire int_div_fNext_29$CLR,
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int_div_fNext_29$DEQ,
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int_div_fNext_29$EMPTY_N,
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int_div_fNext_29$ENQ,
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int_div_fNext_29$FULL_N;
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// ports of submodule int_div_fNext_3
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wire [231 : 0] int_div_fNext_3$D_IN, int_div_fNext_3$D_OUT;
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wire int_div_fNext_3$CLR,
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int_div_fNext_3$DEQ,
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int_div_fNext_3$EMPTY_N,
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int_div_fNext_3$ENQ,
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int_div_fNext_3$FULL_N;
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// ports of submodule int_div_fNext_30
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wire [231 : 0] int_div_fNext_30$D_IN, int_div_fNext_30$D_OUT;
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wire int_div_fNext_30$CLR,
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int_div_fNext_30$DEQ,
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int_div_fNext_30$EMPTY_N,
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int_div_fNext_30$ENQ,
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int_div_fNext_30$FULL_N;
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// ports of submodule int_div_fNext_31
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wire [231 : 0] int_div_fNext_31$D_IN, int_div_fNext_31$D_OUT;
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wire int_div_fNext_31$CLR,
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int_div_fNext_31$DEQ,
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int_div_fNext_31$EMPTY_N,
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int_div_fNext_31$ENQ,
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int_div_fNext_31$FULL_N;
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// ports of submodule int_div_fNext_32
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wire [231 : 0] int_div_fNext_32$D_IN, int_div_fNext_32$D_OUT;
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wire int_div_fNext_32$CLR,
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int_div_fNext_32$DEQ,
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int_div_fNext_32$EMPTY_N,
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int_div_fNext_32$ENQ,
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int_div_fNext_32$FULL_N;
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// ports of submodule int_div_fNext_33
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wire [231 : 0] int_div_fNext_33$D_IN, int_div_fNext_33$D_OUT;
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wire int_div_fNext_33$CLR,
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int_div_fNext_33$DEQ,
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int_div_fNext_33$EMPTY_N,
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int_div_fNext_33$ENQ,
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int_div_fNext_33$FULL_N;
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// ports of submodule int_div_fNext_34
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wire [231 : 0] int_div_fNext_34$D_IN, int_div_fNext_34$D_OUT;
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wire int_div_fNext_34$CLR,
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int_div_fNext_34$DEQ,
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int_div_fNext_34$EMPTY_N,
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int_div_fNext_34$ENQ,
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int_div_fNext_34$FULL_N;
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// ports of submodule int_div_fNext_35
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wire [231 : 0] int_div_fNext_35$D_IN, int_div_fNext_35$D_OUT;
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wire int_div_fNext_35$CLR,
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int_div_fNext_35$DEQ,
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int_div_fNext_35$EMPTY_N,
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int_div_fNext_35$ENQ,
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int_div_fNext_35$FULL_N;
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// ports of submodule int_div_fNext_36
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wire [231 : 0] int_div_fNext_36$D_IN, int_div_fNext_36$D_OUT;
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wire int_div_fNext_36$CLR,
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int_div_fNext_36$DEQ,
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int_div_fNext_36$EMPTY_N,
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int_div_fNext_36$ENQ,
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int_div_fNext_36$FULL_N;
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// ports of submodule int_div_fNext_37
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wire [231 : 0] int_div_fNext_37$D_IN, int_div_fNext_37$D_OUT;
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wire int_div_fNext_37$CLR,
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int_div_fNext_37$DEQ,
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int_div_fNext_37$EMPTY_N,
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int_div_fNext_37$ENQ,
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int_div_fNext_37$FULL_N;
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// ports of submodule int_div_fNext_38
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wire [231 : 0] int_div_fNext_38$D_IN, int_div_fNext_38$D_OUT;
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wire int_div_fNext_38$CLR,
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int_div_fNext_38$DEQ,
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int_div_fNext_38$EMPTY_N,
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int_div_fNext_38$ENQ,
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int_div_fNext_38$FULL_N;
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// ports of submodule int_div_fNext_39
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wire [231 : 0] int_div_fNext_39$D_IN, int_div_fNext_39$D_OUT;
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wire int_div_fNext_39$CLR,
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int_div_fNext_39$DEQ,
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int_div_fNext_39$EMPTY_N,
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int_div_fNext_39$ENQ,
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int_div_fNext_39$FULL_N;
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// ports of submodule int_div_fNext_4
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wire [231 : 0] int_div_fNext_4$D_IN, int_div_fNext_4$D_OUT;
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wire int_div_fNext_4$CLR,
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int_div_fNext_4$DEQ,
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int_div_fNext_4$EMPTY_N,
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int_div_fNext_4$ENQ,
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int_div_fNext_4$FULL_N;
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// ports of submodule int_div_fNext_40
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wire [231 : 0] int_div_fNext_40$D_IN, int_div_fNext_40$D_OUT;
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wire int_div_fNext_40$CLR,
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int_div_fNext_40$DEQ,
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int_div_fNext_40$EMPTY_N,
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int_div_fNext_40$ENQ,
|
|
int_div_fNext_40$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_41
|
|
wire [231 : 0] int_div_fNext_41$D_IN, int_div_fNext_41$D_OUT;
|
|
wire int_div_fNext_41$CLR,
|
|
int_div_fNext_41$DEQ,
|
|
int_div_fNext_41$EMPTY_N,
|
|
int_div_fNext_41$ENQ,
|
|
int_div_fNext_41$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_42
|
|
wire [231 : 0] int_div_fNext_42$D_IN, int_div_fNext_42$D_OUT;
|
|
wire int_div_fNext_42$CLR,
|
|
int_div_fNext_42$DEQ,
|
|
int_div_fNext_42$EMPTY_N,
|
|
int_div_fNext_42$ENQ,
|
|
int_div_fNext_42$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_43
|
|
wire [231 : 0] int_div_fNext_43$D_IN, int_div_fNext_43$D_OUT;
|
|
wire int_div_fNext_43$CLR,
|
|
int_div_fNext_43$DEQ,
|
|
int_div_fNext_43$EMPTY_N,
|
|
int_div_fNext_43$ENQ,
|
|
int_div_fNext_43$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_44
|
|
wire [231 : 0] int_div_fNext_44$D_IN, int_div_fNext_44$D_OUT;
|
|
wire int_div_fNext_44$CLR,
|
|
int_div_fNext_44$DEQ,
|
|
int_div_fNext_44$EMPTY_N,
|
|
int_div_fNext_44$ENQ,
|
|
int_div_fNext_44$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_45
|
|
wire [231 : 0] int_div_fNext_45$D_IN, int_div_fNext_45$D_OUT;
|
|
wire int_div_fNext_45$CLR,
|
|
int_div_fNext_45$DEQ,
|
|
int_div_fNext_45$EMPTY_N,
|
|
int_div_fNext_45$ENQ,
|
|
int_div_fNext_45$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_46
|
|
wire [231 : 0] int_div_fNext_46$D_IN, int_div_fNext_46$D_OUT;
|
|
wire int_div_fNext_46$CLR,
|
|
int_div_fNext_46$DEQ,
|
|
int_div_fNext_46$EMPTY_N,
|
|
int_div_fNext_46$ENQ,
|
|
int_div_fNext_46$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_47
|
|
wire [231 : 0] int_div_fNext_47$D_IN, int_div_fNext_47$D_OUT;
|
|
wire int_div_fNext_47$CLR,
|
|
int_div_fNext_47$DEQ,
|
|
int_div_fNext_47$EMPTY_N,
|
|
int_div_fNext_47$ENQ,
|
|
int_div_fNext_47$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_48
|
|
wire [231 : 0] int_div_fNext_48$D_IN, int_div_fNext_48$D_OUT;
|
|
wire int_div_fNext_48$CLR,
|
|
int_div_fNext_48$DEQ,
|
|
int_div_fNext_48$EMPTY_N,
|
|
int_div_fNext_48$ENQ,
|
|
int_div_fNext_48$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_49
|
|
wire [231 : 0] int_div_fNext_49$D_IN, int_div_fNext_49$D_OUT;
|
|
wire int_div_fNext_49$CLR,
|
|
int_div_fNext_49$DEQ,
|
|
int_div_fNext_49$EMPTY_N,
|
|
int_div_fNext_49$ENQ,
|
|
int_div_fNext_49$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_5
|
|
wire [231 : 0] int_div_fNext_5$D_IN, int_div_fNext_5$D_OUT;
|
|
wire int_div_fNext_5$CLR,
|
|
int_div_fNext_5$DEQ,
|
|
int_div_fNext_5$EMPTY_N,
|
|
int_div_fNext_5$ENQ,
|
|
int_div_fNext_5$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_50
|
|
wire [231 : 0] int_div_fNext_50$D_IN, int_div_fNext_50$D_OUT;
|
|
wire int_div_fNext_50$CLR,
|
|
int_div_fNext_50$DEQ,
|
|
int_div_fNext_50$EMPTY_N,
|
|
int_div_fNext_50$ENQ,
|
|
int_div_fNext_50$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_51
|
|
wire [231 : 0] int_div_fNext_51$D_IN, int_div_fNext_51$D_OUT;
|
|
wire int_div_fNext_51$CLR,
|
|
int_div_fNext_51$DEQ,
|
|
int_div_fNext_51$EMPTY_N,
|
|
int_div_fNext_51$ENQ,
|
|
int_div_fNext_51$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_52
|
|
wire [231 : 0] int_div_fNext_52$D_IN, int_div_fNext_52$D_OUT;
|
|
wire int_div_fNext_52$CLR,
|
|
int_div_fNext_52$DEQ,
|
|
int_div_fNext_52$EMPTY_N,
|
|
int_div_fNext_52$ENQ,
|
|
int_div_fNext_52$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_53
|
|
wire [231 : 0] int_div_fNext_53$D_IN, int_div_fNext_53$D_OUT;
|
|
wire int_div_fNext_53$CLR,
|
|
int_div_fNext_53$DEQ,
|
|
int_div_fNext_53$EMPTY_N,
|
|
int_div_fNext_53$ENQ,
|
|
int_div_fNext_53$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_54
|
|
wire [231 : 0] int_div_fNext_54$D_IN, int_div_fNext_54$D_OUT;
|
|
wire int_div_fNext_54$CLR,
|
|
int_div_fNext_54$DEQ,
|
|
int_div_fNext_54$EMPTY_N,
|
|
int_div_fNext_54$ENQ,
|
|
int_div_fNext_54$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_55
|
|
wire [231 : 0] int_div_fNext_55$D_IN, int_div_fNext_55$D_OUT;
|
|
wire int_div_fNext_55$CLR,
|
|
int_div_fNext_55$DEQ,
|
|
int_div_fNext_55$EMPTY_N,
|
|
int_div_fNext_55$ENQ,
|
|
int_div_fNext_55$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_56
|
|
wire [231 : 0] int_div_fNext_56$D_IN, int_div_fNext_56$D_OUT;
|
|
wire int_div_fNext_56$CLR,
|
|
int_div_fNext_56$DEQ,
|
|
int_div_fNext_56$EMPTY_N,
|
|
int_div_fNext_56$ENQ,
|
|
int_div_fNext_56$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_57
|
|
wire [231 : 0] int_div_fNext_57$D_IN, int_div_fNext_57$D_OUT;
|
|
wire int_div_fNext_57$CLR,
|
|
int_div_fNext_57$DEQ,
|
|
int_div_fNext_57$EMPTY_N,
|
|
int_div_fNext_57$ENQ,
|
|
int_div_fNext_57$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_6
|
|
wire [231 : 0] int_div_fNext_6$D_IN, int_div_fNext_6$D_OUT;
|
|
wire int_div_fNext_6$CLR,
|
|
int_div_fNext_6$DEQ,
|
|
int_div_fNext_6$EMPTY_N,
|
|
int_div_fNext_6$ENQ,
|
|
int_div_fNext_6$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_7
|
|
wire [231 : 0] int_div_fNext_7$D_IN, int_div_fNext_7$D_OUT;
|
|
wire int_div_fNext_7$CLR,
|
|
int_div_fNext_7$DEQ,
|
|
int_div_fNext_7$EMPTY_N,
|
|
int_div_fNext_7$ENQ,
|
|
int_div_fNext_7$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_8
|
|
wire [231 : 0] int_div_fNext_8$D_IN, int_div_fNext_8$D_OUT;
|
|
wire int_div_fNext_8$CLR,
|
|
int_div_fNext_8$DEQ,
|
|
int_div_fNext_8$EMPTY_N,
|
|
int_div_fNext_8$ENQ,
|
|
int_div_fNext_8$FULL_N;
|
|
|
|
// ports of submodule int_div_fNext_9
|
|
wire [231 : 0] int_div_fNext_9$D_IN, int_div_fNext_9$D_OUT;
|
|
wire int_div_fNext_9$CLR,
|
|
int_div_fNext_9$DEQ,
|
|
int_div_fNext_9$EMPTY_N,
|
|
int_div_fNext_9$ENQ,
|
|
int_div_fNext_9$FULL_N;
|
|
|
|
// ports of submodule int_div_fRequest
|
|
wire [170 : 0] int_div_fRequest$D_IN, int_div_fRequest$D_OUT;
|
|
wire int_div_fRequest$CLR,
|
|
int_div_fRequest$DEQ,
|
|
int_div_fRequest$EMPTY_N,
|
|
int_div_fRequest$ENQ,
|
|
int_div_fRequest$FULL_N;
|
|
|
|
// ports of submodule int_div_fResponse
|
|
wire [113 : 0] int_div_fResponse$D_IN, int_div_fResponse$D_OUT;
|
|
wire int_div_fResponse$CLR,
|
|
int_div_fResponse$DEQ,
|
|
int_div_fResponse$EMPTY_N,
|
|
int_div_fResponse$ENQ,
|
|
int_div_fResponse$FULL_N;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_fpu_s1_stage,
|
|
CAN_FIRE_RL_fpu_s2_stage,
|
|
CAN_FIRE_RL_fpu_s3_stage,
|
|
CAN_FIRE_RL_fpu_s4_stage,
|
|
CAN_FIRE_RL_fpu_s5_stage,
|
|
CAN_FIRE_RL_int_div_finish,
|
|
CAN_FIRE_RL_int_div_start,
|
|
CAN_FIRE_RL_int_div_work,
|
|
CAN_FIRE_RL_int_div_work_1,
|
|
CAN_FIRE_RL_int_div_work_10,
|
|
CAN_FIRE_RL_int_div_work_11,
|
|
CAN_FIRE_RL_int_div_work_12,
|
|
CAN_FIRE_RL_int_div_work_13,
|
|
CAN_FIRE_RL_int_div_work_14,
|
|
CAN_FIRE_RL_int_div_work_15,
|
|
CAN_FIRE_RL_int_div_work_16,
|
|
CAN_FIRE_RL_int_div_work_17,
|
|
CAN_FIRE_RL_int_div_work_18,
|
|
CAN_FIRE_RL_int_div_work_19,
|
|
CAN_FIRE_RL_int_div_work_2,
|
|
CAN_FIRE_RL_int_div_work_20,
|
|
CAN_FIRE_RL_int_div_work_21,
|
|
CAN_FIRE_RL_int_div_work_22,
|
|
CAN_FIRE_RL_int_div_work_23,
|
|
CAN_FIRE_RL_int_div_work_24,
|
|
CAN_FIRE_RL_int_div_work_25,
|
|
CAN_FIRE_RL_int_div_work_26,
|
|
CAN_FIRE_RL_int_div_work_27,
|
|
CAN_FIRE_RL_int_div_work_28,
|
|
CAN_FIRE_RL_int_div_work_29,
|
|
CAN_FIRE_RL_int_div_work_3,
|
|
CAN_FIRE_RL_int_div_work_30,
|
|
CAN_FIRE_RL_int_div_work_31,
|
|
CAN_FIRE_RL_int_div_work_32,
|
|
CAN_FIRE_RL_int_div_work_33,
|
|
CAN_FIRE_RL_int_div_work_34,
|
|
CAN_FIRE_RL_int_div_work_35,
|
|
CAN_FIRE_RL_int_div_work_36,
|
|
CAN_FIRE_RL_int_div_work_37,
|
|
CAN_FIRE_RL_int_div_work_38,
|
|
CAN_FIRE_RL_int_div_work_39,
|
|
CAN_FIRE_RL_int_div_work_4,
|
|
CAN_FIRE_RL_int_div_work_40,
|
|
CAN_FIRE_RL_int_div_work_41,
|
|
CAN_FIRE_RL_int_div_work_42,
|
|
CAN_FIRE_RL_int_div_work_43,
|
|
CAN_FIRE_RL_int_div_work_44,
|
|
CAN_FIRE_RL_int_div_work_45,
|
|
CAN_FIRE_RL_int_div_work_46,
|
|
CAN_FIRE_RL_int_div_work_47,
|
|
CAN_FIRE_RL_int_div_work_48,
|
|
CAN_FIRE_RL_int_div_work_49,
|
|
CAN_FIRE_RL_int_div_work_5,
|
|
CAN_FIRE_RL_int_div_work_50,
|
|
CAN_FIRE_RL_int_div_work_51,
|
|
CAN_FIRE_RL_int_div_work_52,
|
|
CAN_FIRE_RL_int_div_work_53,
|
|
CAN_FIRE_RL_int_div_work_54,
|
|
CAN_FIRE_RL_int_div_work_55,
|
|
CAN_FIRE_RL_int_div_work_56,
|
|
CAN_FIRE_RL_int_div_work_57,
|
|
CAN_FIRE_RL_int_div_work_6,
|
|
CAN_FIRE_RL_int_div_work_7,
|
|
CAN_FIRE_RL_int_div_work_8,
|
|
CAN_FIRE_RL_int_div_work_9,
|
|
CAN_FIRE_request_put,
|
|
CAN_FIRE_response_get,
|
|
WILL_FIRE_RL_fpu_s1_stage,
|
|
WILL_FIRE_RL_fpu_s2_stage,
|
|
WILL_FIRE_RL_fpu_s3_stage,
|
|
WILL_FIRE_RL_fpu_s4_stage,
|
|
WILL_FIRE_RL_fpu_s5_stage,
|
|
WILL_FIRE_RL_int_div_finish,
|
|
WILL_FIRE_RL_int_div_start,
|
|
WILL_FIRE_RL_int_div_work,
|
|
WILL_FIRE_RL_int_div_work_1,
|
|
WILL_FIRE_RL_int_div_work_10,
|
|
WILL_FIRE_RL_int_div_work_11,
|
|
WILL_FIRE_RL_int_div_work_12,
|
|
WILL_FIRE_RL_int_div_work_13,
|
|
WILL_FIRE_RL_int_div_work_14,
|
|
WILL_FIRE_RL_int_div_work_15,
|
|
WILL_FIRE_RL_int_div_work_16,
|
|
WILL_FIRE_RL_int_div_work_17,
|
|
WILL_FIRE_RL_int_div_work_18,
|
|
WILL_FIRE_RL_int_div_work_19,
|
|
WILL_FIRE_RL_int_div_work_2,
|
|
WILL_FIRE_RL_int_div_work_20,
|
|
WILL_FIRE_RL_int_div_work_21,
|
|
WILL_FIRE_RL_int_div_work_22,
|
|
WILL_FIRE_RL_int_div_work_23,
|
|
WILL_FIRE_RL_int_div_work_24,
|
|
WILL_FIRE_RL_int_div_work_25,
|
|
WILL_FIRE_RL_int_div_work_26,
|
|
WILL_FIRE_RL_int_div_work_27,
|
|
WILL_FIRE_RL_int_div_work_28,
|
|
WILL_FIRE_RL_int_div_work_29,
|
|
WILL_FIRE_RL_int_div_work_3,
|
|
WILL_FIRE_RL_int_div_work_30,
|
|
WILL_FIRE_RL_int_div_work_31,
|
|
WILL_FIRE_RL_int_div_work_32,
|
|
WILL_FIRE_RL_int_div_work_33,
|
|
WILL_FIRE_RL_int_div_work_34,
|
|
WILL_FIRE_RL_int_div_work_35,
|
|
WILL_FIRE_RL_int_div_work_36,
|
|
WILL_FIRE_RL_int_div_work_37,
|
|
WILL_FIRE_RL_int_div_work_38,
|
|
WILL_FIRE_RL_int_div_work_39,
|
|
WILL_FIRE_RL_int_div_work_4,
|
|
WILL_FIRE_RL_int_div_work_40,
|
|
WILL_FIRE_RL_int_div_work_41,
|
|
WILL_FIRE_RL_int_div_work_42,
|
|
WILL_FIRE_RL_int_div_work_43,
|
|
WILL_FIRE_RL_int_div_work_44,
|
|
WILL_FIRE_RL_int_div_work_45,
|
|
WILL_FIRE_RL_int_div_work_46,
|
|
WILL_FIRE_RL_int_div_work_47,
|
|
WILL_FIRE_RL_int_div_work_48,
|
|
WILL_FIRE_RL_int_div_work_49,
|
|
WILL_FIRE_RL_int_div_work_5,
|
|
WILL_FIRE_RL_int_div_work_50,
|
|
WILL_FIRE_RL_int_div_work_51,
|
|
WILL_FIRE_RL_int_div_work_52,
|
|
WILL_FIRE_RL_int_div_work_53,
|
|
WILL_FIRE_RL_int_div_work_54,
|
|
WILL_FIRE_RL_int_div_work_55,
|
|
WILL_FIRE_RL_int_div_work_56,
|
|
WILL_FIRE_RL_int_div_work_57,
|
|
WILL_FIRE_RL_int_div_work_6,
|
|
WILL_FIRE_RL_int_div_work_7,
|
|
WILL_FIRE_RL_int_div_work_8,
|
|
WILL_FIRE_RL_int_div_work_9,
|
|
WILL_FIRE_request_put,
|
|
WILL_FIRE_response_get;
|
|
|
|
// remaining internal signals
|
|
reg [63 : 0] CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16;
|
|
reg [62 : 0] CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14,
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12;
|
|
reg [51 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2,
|
|
_theResult___fst_sfd__h37218,
|
|
_theResult___fst_sfd__h37707,
|
|
_theResult___fst_sfd__h60989;
|
|
reg [10 : 0] CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9,
|
|
_theResult___fst_exp__h37217,
|
|
_theResult___fst_exp__h60988;
|
|
reg CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5,
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13,
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11;
|
|
wire [115 : 0] b__h10163,
|
|
b__h10487,
|
|
b__h10811,
|
|
b__h1091,
|
|
b__h11135,
|
|
b__h11459,
|
|
b__h11783,
|
|
b__h12107,
|
|
b__h12431,
|
|
b__h12755,
|
|
b__h13079,
|
|
b__h13403,
|
|
b__h13727,
|
|
b__h14051,
|
|
b__h1415,
|
|
b__h14375,
|
|
b__h14699,
|
|
b__h15023,
|
|
b__h15347,
|
|
b__h15671,
|
|
b__h15995,
|
|
b__h16319,
|
|
b__h16643,
|
|
b__h16967,
|
|
b__h17291,
|
|
b__h1739,
|
|
b__h17615,
|
|
b__h17939,
|
|
b__h18263,
|
|
b__h18587,
|
|
b__h18911,
|
|
b__h19235,
|
|
b__h19482,
|
|
b__h2063,
|
|
b__h2387,
|
|
b__h2711,
|
|
b__h3035,
|
|
b__h3359,
|
|
b__h3683,
|
|
b__h4007,
|
|
b__h4331,
|
|
b__h4655,
|
|
b__h4979,
|
|
b__h5303,
|
|
b__h5627,
|
|
b__h5951,
|
|
b__h6275,
|
|
b__h6599,
|
|
b__h6923,
|
|
b__h7247,
|
|
b__h7571,
|
|
b__h767,
|
|
b__h7895,
|
|
b__h8219,
|
|
b__h8543,
|
|
b__h8867,
|
|
b__h9191,
|
|
b__h9515,
|
|
b__h9839,
|
|
value__h19447;
|
|
wire [113 : 0] x__h49176;
|
|
wire [63 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308,
|
|
NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305,
|
|
fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780;
|
|
wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824,
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773;
|
|
wire [57 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7,
|
|
IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19,
|
|
_theResult____h50063,
|
|
_theResult___snd__h52150,
|
|
_theResult___snd__h59785,
|
|
_theResult___snd__h59800,
|
|
_theResult___snd__h59802,
|
|
_theResult___snd__h59815,
|
|
_theResult___snd__h59821,
|
|
_theResult___snd__h59839,
|
|
_theResult___snd__h59844,
|
|
_theResult___snd_snd_snd__h51398,
|
|
b__h378,
|
|
int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945,
|
|
result__h50077,
|
|
result__h50108,
|
|
result__h50258,
|
|
sfdin__h51553,
|
|
sfdin__h59762,
|
|
x__h50197,
|
|
x__h50487;
|
|
wire [56 : 0] value__h50121, x__h49237;
|
|
wire [53 : 0] sfd__h60417, value__h49179;
|
|
wire [52 : 0] sfdA__h19785, sfdA__h19789, sfdB__h19786, sfdB__h19791;
|
|
wire [51 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303,
|
|
_theResult___fst_sfd__h60992,
|
|
_theResult___sfd__h60911,
|
|
_theResult___snd_fst_sfd__h49112,
|
|
out_sfd__h60914,
|
|
sfd__h36684,
|
|
sfd__h36687;
|
|
wire [12 : 0] IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205,
|
|
value__h49124,
|
|
value__h49300;
|
|
wire [11 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487,
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726;
|
|
wire [10 : 0] IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286,
|
|
IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821,
|
|
_theResult___exp__h60910,
|
|
_theResult___fst__h49072,
|
|
_theResult___fst_exp__h59719,
|
|
_theResult___fst_exp__h59722,
|
|
_theResult___fst_exp__h59725,
|
|
_theResult___fst_exp__h59768,
|
|
_theResult___fst_exp__h59771,
|
|
_theResult___fst_exp__h59791,
|
|
_theResult___fst_exp__h59807,
|
|
_theResult___fst_exp__h59846,
|
|
_theResult___fst_exp__h59852,
|
|
_theResult___fst_exp__h59855,
|
|
_theResult___fst_exp__h60991,
|
|
_theResult___snd_fst_exp__h49084,
|
|
_theResult___snd_fst_exp__h49087,
|
|
_theResult___snd_fst_exp__h49111,
|
|
din_inc___2_exp__h61001,
|
|
fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3,
|
|
fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4,
|
|
out_exp__h60913,
|
|
theResult___fst_exp9725_MINUS_1023__q6,
|
|
x__h49291,
|
|
x__h50204;
|
|
wire [5 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724,
|
|
b__h21789,
|
|
b__h29207;
|
|
wire [4 : 0] IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770,
|
|
IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765;
|
|
wire [1 : 0] IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8,
|
|
_theResult___snd_fst__h59874,
|
|
guard__h51381,
|
|
x__h60140;
|
|
wire IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206,
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208,
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352,
|
|
IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275,
|
|
IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441,
|
|
NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253,
|
|
NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334,
|
|
NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341,
|
|
_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727,
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216,
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254,
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289,
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351,
|
|
fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212,
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258,
|
|
sfdlsb__h50103;
|
|
|
|
// action method request_put
|
|
assign RDY_request_put = fpu_fOperands_S0$FULL_N ;
|
|
assign CAN_FIRE_request_put = fpu_fOperands_S0$FULL_N ;
|
|
assign WILL_FIRE_request_put = EN_request_put ;
|
|
|
|
// actionvalue method response_get
|
|
assign response_get = fpu_fResult_S5$D_OUT ;
|
|
assign RDY_response_get = fpu_fResult_S5$EMPTY_N ;
|
|
assign CAN_FIRE_response_get = fpu_fResult_S5$EMPTY_N ;
|
|
assign WILL_FIRE_response_get = EN_response_get ;
|
|
|
|
// submodule fpu_fOperands_S0
|
|
FIFOL1 #(.width(32'd131)) fpu_fOperands_S0(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fOperands_S0$D_IN),
|
|
.ENQ(fpu_fOperands_S0$ENQ),
|
|
.DEQ(fpu_fOperands_S0$DEQ),
|
|
.CLR(fpu_fOperands_S0$CLR),
|
|
.D_OUT(fpu_fOperands_S0$D_OUT),
|
|
.FULL_N(fpu_fOperands_S0$FULL_N),
|
|
.EMPTY_N(fpu_fOperands_S0$EMPTY_N));
|
|
|
|
// submodule fpu_fResult_S5
|
|
FIFOL1 #(.width(32'd69)) fpu_fResult_S5(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fResult_S5$D_IN),
|
|
.ENQ(fpu_fResult_S5$ENQ),
|
|
.DEQ(fpu_fResult_S5$DEQ),
|
|
.CLR(fpu_fResult_S5$CLR),
|
|
.D_OUT(fpu_fResult_S5$D_OUT),
|
|
.FULL_N(fpu_fResult_S5$FULL_N),
|
|
.EMPTY_N(fpu_fResult_S5$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S1
|
|
FIFOL1 #(.width(32'd319)) fpu_fState_S1(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S1$D_IN),
|
|
.ENQ(fpu_fState_S1$ENQ),
|
|
.DEQ(fpu_fState_S1$DEQ),
|
|
.CLR(fpu_fState_S1$CLR),
|
|
.D_OUT(fpu_fState_S1$D_OUT),
|
|
.FULL_N(fpu_fState_S1$FULL_N),
|
|
.EMPTY_N(fpu_fState_S1$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S2
|
|
FIFOL1 #(.width(32'd148)) fpu_fState_S2(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S2$D_IN),
|
|
.ENQ(fpu_fState_S2$ENQ),
|
|
.DEQ(fpu_fState_S2$DEQ),
|
|
.CLR(fpu_fState_S2$CLR),
|
|
.D_OUT(fpu_fState_S2$D_OUT),
|
|
.FULL_N(fpu_fState_S2$FULL_N),
|
|
.EMPTY_N(fpu_fState_S2$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S3
|
|
FIFOL1 #(.width(32'd195)) fpu_fState_S3(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S3$D_IN),
|
|
.ENQ(fpu_fState_S3$ENQ),
|
|
.DEQ(fpu_fState_S3$DEQ),
|
|
.CLR(fpu_fState_S3$CLR),
|
|
.D_OUT(fpu_fState_S3$D_OUT),
|
|
.FULL_N(fpu_fState_S3$FULL_N),
|
|
.EMPTY_N(fpu_fState_S3$EMPTY_N));
|
|
|
|
// submodule fpu_fState_S4
|
|
FIFOL1 #(.width(32'd139)) fpu_fState_S4(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(fpu_fState_S4$D_IN),
|
|
.ENQ(fpu_fState_S4$ENQ),
|
|
.DEQ(fpu_fState_S4$DEQ),
|
|
.CLR(fpu_fState_S4$CLR),
|
|
.D_OUT(fpu_fState_S4$D_OUT),
|
|
.FULL_N(fpu_fState_S4$FULL_N),
|
|
.EMPTY_N(fpu_fState_S4$EMPTY_N));
|
|
|
|
// submodule int_div_fFirst
|
|
FIFOL1 #(.width(32'd232)) int_div_fFirst(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fFirst$D_IN),
|
|
.ENQ(int_div_fFirst$ENQ),
|
|
.DEQ(int_div_fFirst$DEQ),
|
|
.CLR(int_div_fFirst$CLR),
|
|
.D_OUT(int_div_fFirst$D_OUT),
|
|
.FULL_N(int_div_fFirst$FULL_N),
|
|
.EMPTY_N(int_div_fFirst$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_0
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_0(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_0$D_IN),
|
|
.ENQ(int_div_fNext_0$ENQ),
|
|
.DEQ(int_div_fNext_0$DEQ),
|
|
.CLR(int_div_fNext_0$CLR),
|
|
.D_OUT(int_div_fNext_0$D_OUT),
|
|
.FULL_N(int_div_fNext_0$FULL_N),
|
|
.EMPTY_N(int_div_fNext_0$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_1
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_1(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_1$D_IN),
|
|
.ENQ(int_div_fNext_1$ENQ),
|
|
.DEQ(int_div_fNext_1$DEQ),
|
|
.CLR(int_div_fNext_1$CLR),
|
|
.D_OUT(int_div_fNext_1$D_OUT),
|
|
.FULL_N(int_div_fNext_1$FULL_N),
|
|
.EMPTY_N(int_div_fNext_1$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_10
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_10(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_10$D_IN),
|
|
.ENQ(int_div_fNext_10$ENQ),
|
|
.DEQ(int_div_fNext_10$DEQ),
|
|
.CLR(int_div_fNext_10$CLR),
|
|
.D_OUT(int_div_fNext_10$D_OUT),
|
|
.FULL_N(int_div_fNext_10$FULL_N),
|
|
.EMPTY_N(int_div_fNext_10$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_11
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_11(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_11$D_IN),
|
|
.ENQ(int_div_fNext_11$ENQ),
|
|
.DEQ(int_div_fNext_11$DEQ),
|
|
.CLR(int_div_fNext_11$CLR),
|
|
.D_OUT(int_div_fNext_11$D_OUT),
|
|
.FULL_N(int_div_fNext_11$FULL_N),
|
|
.EMPTY_N(int_div_fNext_11$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_12
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_12(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_12$D_IN),
|
|
.ENQ(int_div_fNext_12$ENQ),
|
|
.DEQ(int_div_fNext_12$DEQ),
|
|
.CLR(int_div_fNext_12$CLR),
|
|
.D_OUT(int_div_fNext_12$D_OUT),
|
|
.FULL_N(int_div_fNext_12$FULL_N),
|
|
.EMPTY_N(int_div_fNext_12$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_13
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_13(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_13$D_IN),
|
|
.ENQ(int_div_fNext_13$ENQ),
|
|
.DEQ(int_div_fNext_13$DEQ),
|
|
.CLR(int_div_fNext_13$CLR),
|
|
.D_OUT(int_div_fNext_13$D_OUT),
|
|
.FULL_N(int_div_fNext_13$FULL_N),
|
|
.EMPTY_N(int_div_fNext_13$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_14
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_14(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_14$D_IN),
|
|
.ENQ(int_div_fNext_14$ENQ),
|
|
.DEQ(int_div_fNext_14$DEQ),
|
|
.CLR(int_div_fNext_14$CLR),
|
|
.D_OUT(int_div_fNext_14$D_OUT),
|
|
.FULL_N(int_div_fNext_14$FULL_N),
|
|
.EMPTY_N(int_div_fNext_14$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_15
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_15(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_15$D_IN),
|
|
.ENQ(int_div_fNext_15$ENQ),
|
|
.DEQ(int_div_fNext_15$DEQ),
|
|
.CLR(int_div_fNext_15$CLR),
|
|
.D_OUT(int_div_fNext_15$D_OUT),
|
|
.FULL_N(int_div_fNext_15$FULL_N),
|
|
.EMPTY_N(int_div_fNext_15$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_16
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_16(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_16$D_IN),
|
|
.ENQ(int_div_fNext_16$ENQ),
|
|
.DEQ(int_div_fNext_16$DEQ),
|
|
.CLR(int_div_fNext_16$CLR),
|
|
.D_OUT(int_div_fNext_16$D_OUT),
|
|
.FULL_N(int_div_fNext_16$FULL_N),
|
|
.EMPTY_N(int_div_fNext_16$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_17
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_17(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_17$D_IN),
|
|
.ENQ(int_div_fNext_17$ENQ),
|
|
.DEQ(int_div_fNext_17$DEQ),
|
|
.CLR(int_div_fNext_17$CLR),
|
|
.D_OUT(int_div_fNext_17$D_OUT),
|
|
.FULL_N(int_div_fNext_17$FULL_N),
|
|
.EMPTY_N(int_div_fNext_17$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_18
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_18(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_18$D_IN),
|
|
.ENQ(int_div_fNext_18$ENQ),
|
|
.DEQ(int_div_fNext_18$DEQ),
|
|
.CLR(int_div_fNext_18$CLR),
|
|
.D_OUT(int_div_fNext_18$D_OUT),
|
|
.FULL_N(int_div_fNext_18$FULL_N),
|
|
.EMPTY_N(int_div_fNext_18$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_19
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_19(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_19$D_IN),
|
|
.ENQ(int_div_fNext_19$ENQ),
|
|
.DEQ(int_div_fNext_19$DEQ),
|
|
.CLR(int_div_fNext_19$CLR),
|
|
.D_OUT(int_div_fNext_19$D_OUT),
|
|
.FULL_N(int_div_fNext_19$FULL_N),
|
|
.EMPTY_N(int_div_fNext_19$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_2
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_2(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_2$D_IN),
|
|
.ENQ(int_div_fNext_2$ENQ),
|
|
.DEQ(int_div_fNext_2$DEQ),
|
|
.CLR(int_div_fNext_2$CLR),
|
|
.D_OUT(int_div_fNext_2$D_OUT),
|
|
.FULL_N(int_div_fNext_2$FULL_N),
|
|
.EMPTY_N(int_div_fNext_2$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_20
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_20(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_20$D_IN),
|
|
.ENQ(int_div_fNext_20$ENQ),
|
|
.DEQ(int_div_fNext_20$DEQ),
|
|
.CLR(int_div_fNext_20$CLR),
|
|
.D_OUT(int_div_fNext_20$D_OUT),
|
|
.FULL_N(int_div_fNext_20$FULL_N),
|
|
.EMPTY_N(int_div_fNext_20$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_21
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_21(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_21$D_IN),
|
|
.ENQ(int_div_fNext_21$ENQ),
|
|
.DEQ(int_div_fNext_21$DEQ),
|
|
.CLR(int_div_fNext_21$CLR),
|
|
.D_OUT(int_div_fNext_21$D_OUT),
|
|
.FULL_N(int_div_fNext_21$FULL_N),
|
|
.EMPTY_N(int_div_fNext_21$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_22
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_22(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_22$D_IN),
|
|
.ENQ(int_div_fNext_22$ENQ),
|
|
.DEQ(int_div_fNext_22$DEQ),
|
|
.CLR(int_div_fNext_22$CLR),
|
|
.D_OUT(int_div_fNext_22$D_OUT),
|
|
.FULL_N(int_div_fNext_22$FULL_N),
|
|
.EMPTY_N(int_div_fNext_22$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_23
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_23(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_23$D_IN),
|
|
.ENQ(int_div_fNext_23$ENQ),
|
|
.DEQ(int_div_fNext_23$DEQ),
|
|
.CLR(int_div_fNext_23$CLR),
|
|
.D_OUT(int_div_fNext_23$D_OUT),
|
|
.FULL_N(int_div_fNext_23$FULL_N),
|
|
.EMPTY_N(int_div_fNext_23$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_24
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_24(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_24$D_IN),
|
|
.ENQ(int_div_fNext_24$ENQ),
|
|
.DEQ(int_div_fNext_24$DEQ),
|
|
.CLR(int_div_fNext_24$CLR),
|
|
.D_OUT(int_div_fNext_24$D_OUT),
|
|
.FULL_N(int_div_fNext_24$FULL_N),
|
|
.EMPTY_N(int_div_fNext_24$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_25
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_25(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_25$D_IN),
|
|
.ENQ(int_div_fNext_25$ENQ),
|
|
.DEQ(int_div_fNext_25$DEQ),
|
|
.CLR(int_div_fNext_25$CLR),
|
|
.D_OUT(int_div_fNext_25$D_OUT),
|
|
.FULL_N(int_div_fNext_25$FULL_N),
|
|
.EMPTY_N(int_div_fNext_25$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_26
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_26(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_26$D_IN),
|
|
.ENQ(int_div_fNext_26$ENQ),
|
|
.DEQ(int_div_fNext_26$DEQ),
|
|
.CLR(int_div_fNext_26$CLR),
|
|
.D_OUT(int_div_fNext_26$D_OUT),
|
|
.FULL_N(int_div_fNext_26$FULL_N),
|
|
.EMPTY_N(int_div_fNext_26$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_27
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_27(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_27$D_IN),
|
|
.ENQ(int_div_fNext_27$ENQ),
|
|
.DEQ(int_div_fNext_27$DEQ),
|
|
.CLR(int_div_fNext_27$CLR),
|
|
.D_OUT(int_div_fNext_27$D_OUT),
|
|
.FULL_N(int_div_fNext_27$FULL_N),
|
|
.EMPTY_N(int_div_fNext_27$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_28
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_28(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_28$D_IN),
|
|
.ENQ(int_div_fNext_28$ENQ),
|
|
.DEQ(int_div_fNext_28$DEQ),
|
|
.CLR(int_div_fNext_28$CLR),
|
|
.D_OUT(int_div_fNext_28$D_OUT),
|
|
.FULL_N(int_div_fNext_28$FULL_N),
|
|
.EMPTY_N(int_div_fNext_28$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_29
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_29(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_29$D_IN),
|
|
.ENQ(int_div_fNext_29$ENQ),
|
|
.DEQ(int_div_fNext_29$DEQ),
|
|
.CLR(int_div_fNext_29$CLR),
|
|
.D_OUT(int_div_fNext_29$D_OUT),
|
|
.FULL_N(int_div_fNext_29$FULL_N),
|
|
.EMPTY_N(int_div_fNext_29$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_3
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_3(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_3$D_IN),
|
|
.ENQ(int_div_fNext_3$ENQ),
|
|
.DEQ(int_div_fNext_3$DEQ),
|
|
.CLR(int_div_fNext_3$CLR),
|
|
.D_OUT(int_div_fNext_3$D_OUT),
|
|
.FULL_N(int_div_fNext_3$FULL_N),
|
|
.EMPTY_N(int_div_fNext_3$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_30
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_30(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_30$D_IN),
|
|
.ENQ(int_div_fNext_30$ENQ),
|
|
.DEQ(int_div_fNext_30$DEQ),
|
|
.CLR(int_div_fNext_30$CLR),
|
|
.D_OUT(int_div_fNext_30$D_OUT),
|
|
.FULL_N(int_div_fNext_30$FULL_N),
|
|
.EMPTY_N(int_div_fNext_30$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_31
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_31(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_31$D_IN),
|
|
.ENQ(int_div_fNext_31$ENQ),
|
|
.DEQ(int_div_fNext_31$DEQ),
|
|
.CLR(int_div_fNext_31$CLR),
|
|
.D_OUT(int_div_fNext_31$D_OUT),
|
|
.FULL_N(int_div_fNext_31$FULL_N),
|
|
.EMPTY_N(int_div_fNext_31$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_32
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_32(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_32$D_IN),
|
|
.ENQ(int_div_fNext_32$ENQ),
|
|
.DEQ(int_div_fNext_32$DEQ),
|
|
.CLR(int_div_fNext_32$CLR),
|
|
.D_OUT(int_div_fNext_32$D_OUT),
|
|
.FULL_N(int_div_fNext_32$FULL_N),
|
|
.EMPTY_N(int_div_fNext_32$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_33
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_33(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_33$D_IN),
|
|
.ENQ(int_div_fNext_33$ENQ),
|
|
.DEQ(int_div_fNext_33$DEQ),
|
|
.CLR(int_div_fNext_33$CLR),
|
|
.D_OUT(int_div_fNext_33$D_OUT),
|
|
.FULL_N(int_div_fNext_33$FULL_N),
|
|
.EMPTY_N(int_div_fNext_33$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_34
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_34(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_34$D_IN),
|
|
.ENQ(int_div_fNext_34$ENQ),
|
|
.DEQ(int_div_fNext_34$DEQ),
|
|
.CLR(int_div_fNext_34$CLR),
|
|
.D_OUT(int_div_fNext_34$D_OUT),
|
|
.FULL_N(int_div_fNext_34$FULL_N),
|
|
.EMPTY_N(int_div_fNext_34$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_35
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_35(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_35$D_IN),
|
|
.ENQ(int_div_fNext_35$ENQ),
|
|
.DEQ(int_div_fNext_35$DEQ),
|
|
.CLR(int_div_fNext_35$CLR),
|
|
.D_OUT(int_div_fNext_35$D_OUT),
|
|
.FULL_N(int_div_fNext_35$FULL_N),
|
|
.EMPTY_N(int_div_fNext_35$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_36
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_36(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_36$D_IN),
|
|
.ENQ(int_div_fNext_36$ENQ),
|
|
.DEQ(int_div_fNext_36$DEQ),
|
|
.CLR(int_div_fNext_36$CLR),
|
|
.D_OUT(int_div_fNext_36$D_OUT),
|
|
.FULL_N(int_div_fNext_36$FULL_N),
|
|
.EMPTY_N(int_div_fNext_36$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_37
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_37(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_37$D_IN),
|
|
.ENQ(int_div_fNext_37$ENQ),
|
|
.DEQ(int_div_fNext_37$DEQ),
|
|
.CLR(int_div_fNext_37$CLR),
|
|
.D_OUT(int_div_fNext_37$D_OUT),
|
|
.FULL_N(int_div_fNext_37$FULL_N),
|
|
.EMPTY_N(int_div_fNext_37$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_38
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_38(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_38$D_IN),
|
|
.ENQ(int_div_fNext_38$ENQ),
|
|
.DEQ(int_div_fNext_38$DEQ),
|
|
.CLR(int_div_fNext_38$CLR),
|
|
.D_OUT(int_div_fNext_38$D_OUT),
|
|
.FULL_N(int_div_fNext_38$FULL_N),
|
|
.EMPTY_N(int_div_fNext_38$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_39
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_39(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_39$D_IN),
|
|
.ENQ(int_div_fNext_39$ENQ),
|
|
.DEQ(int_div_fNext_39$DEQ),
|
|
.CLR(int_div_fNext_39$CLR),
|
|
.D_OUT(int_div_fNext_39$D_OUT),
|
|
.FULL_N(int_div_fNext_39$FULL_N),
|
|
.EMPTY_N(int_div_fNext_39$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_4
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_4(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_4$D_IN),
|
|
.ENQ(int_div_fNext_4$ENQ),
|
|
.DEQ(int_div_fNext_4$DEQ),
|
|
.CLR(int_div_fNext_4$CLR),
|
|
.D_OUT(int_div_fNext_4$D_OUT),
|
|
.FULL_N(int_div_fNext_4$FULL_N),
|
|
.EMPTY_N(int_div_fNext_4$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_40
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_40(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_40$D_IN),
|
|
.ENQ(int_div_fNext_40$ENQ),
|
|
.DEQ(int_div_fNext_40$DEQ),
|
|
.CLR(int_div_fNext_40$CLR),
|
|
.D_OUT(int_div_fNext_40$D_OUT),
|
|
.FULL_N(int_div_fNext_40$FULL_N),
|
|
.EMPTY_N(int_div_fNext_40$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_41
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_41(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_41$D_IN),
|
|
.ENQ(int_div_fNext_41$ENQ),
|
|
.DEQ(int_div_fNext_41$DEQ),
|
|
.CLR(int_div_fNext_41$CLR),
|
|
.D_OUT(int_div_fNext_41$D_OUT),
|
|
.FULL_N(int_div_fNext_41$FULL_N),
|
|
.EMPTY_N(int_div_fNext_41$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_42
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_42(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_42$D_IN),
|
|
.ENQ(int_div_fNext_42$ENQ),
|
|
.DEQ(int_div_fNext_42$DEQ),
|
|
.CLR(int_div_fNext_42$CLR),
|
|
.D_OUT(int_div_fNext_42$D_OUT),
|
|
.FULL_N(int_div_fNext_42$FULL_N),
|
|
.EMPTY_N(int_div_fNext_42$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_43
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_43(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_43$D_IN),
|
|
.ENQ(int_div_fNext_43$ENQ),
|
|
.DEQ(int_div_fNext_43$DEQ),
|
|
.CLR(int_div_fNext_43$CLR),
|
|
.D_OUT(int_div_fNext_43$D_OUT),
|
|
.FULL_N(int_div_fNext_43$FULL_N),
|
|
.EMPTY_N(int_div_fNext_43$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_44
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_44(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_44$D_IN),
|
|
.ENQ(int_div_fNext_44$ENQ),
|
|
.DEQ(int_div_fNext_44$DEQ),
|
|
.CLR(int_div_fNext_44$CLR),
|
|
.D_OUT(int_div_fNext_44$D_OUT),
|
|
.FULL_N(int_div_fNext_44$FULL_N),
|
|
.EMPTY_N(int_div_fNext_44$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_45
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_45(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_45$D_IN),
|
|
.ENQ(int_div_fNext_45$ENQ),
|
|
.DEQ(int_div_fNext_45$DEQ),
|
|
.CLR(int_div_fNext_45$CLR),
|
|
.D_OUT(int_div_fNext_45$D_OUT),
|
|
.FULL_N(int_div_fNext_45$FULL_N),
|
|
.EMPTY_N(int_div_fNext_45$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_46
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_46(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_46$D_IN),
|
|
.ENQ(int_div_fNext_46$ENQ),
|
|
.DEQ(int_div_fNext_46$DEQ),
|
|
.CLR(int_div_fNext_46$CLR),
|
|
.D_OUT(int_div_fNext_46$D_OUT),
|
|
.FULL_N(int_div_fNext_46$FULL_N),
|
|
.EMPTY_N(int_div_fNext_46$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_47
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_47(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_47$D_IN),
|
|
.ENQ(int_div_fNext_47$ENQ),
|
|
.DEQ(int_div_fNext_47$DEQ),
|
|
.CLR(int_div_fNext_47$CLR),
|
|
.D_OUT(int_div_fNext_47$D_OUT),
|
|
.FULL_N(int_div_fNext_47$FULL_N),
|
|
.EMPTY_N(int_div_fNext_47$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_48
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_48(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_48$D_IN),
|
|
.ENQ(int_div_fNext_48$ENQ),
|
|
.DEQ(int_div_fNext_48$DEQ),
|
|
.CLR(int_div_fNext_48$CLR),
|
|
.D_OUT(int_div_fNext_48$D_OUT),
|
|
.FULL_N(int_div_fNext_48$FULL_N),
|
|
.EMPTY_N(int_div_fNext_48$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_49
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_49(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_49$D_IN),
|
|
.ENQ(int_div_fNext_49$ENQ),
|
|
.DEQ(int_div_fNext_49$DEQ),
|
|
.CLR(int_div_fNext_49$CLR),
|
|
.D_OUT(int_div_fNext_49$D_OUT),
|
|
.FULL_N(int_div_fNext_49$FULL_N),
|
|
.EMPTY_N(int_div_fNext_49$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_5
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_5(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_5$D_IN),
|
|
.ENQ(int_div_fNext_5$ENQ),
|
|
.DEQ(int_div_fNext_5$DEQ),
|
|
.CLR(int_div_fNext_5$CLR),
|
|
.D_OUT(int_div_fNext_5$D_OUT),
|
|
.FULL_N(int_div_fNext_5$FULL_N),
|
|
.EMPTY_N(int_div_fNext_5$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_50
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_50(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_50$D_IN),
|
|
.ENQ(int_div_fNext_50$ENQ),
|
|
.DEQ(int_div_fNext_50$DEQ),
|
|
.CLR(int_div_fNext_50$CLR),
|
|
.D_OUT(int_div_fNext_50$D_OUT),
|
|
.FULL_N(int_div_fNext_50$FULL_N),
|
|
.EMPTY_N(int_div_fNext_50$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_51
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_51(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_51$D_IN),
|
|
.ENQ(int_div_fNext_51$ENQ),
|
|
.DEQ(int_div_fNext_51$DEQ),
|
|
.CLR(int_div_fNext_51$CLR),
|
|
.D_OUT(int_div_fNext_51$D_OUT),
|
|
.FULL_N(int_div_fNext_51$FULL_N),
|
|
.EMPTY_N(int_div_fNext_51$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_52
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_52(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_52$D_IN),
|
|
.ENQ(int_div_fNext_52$ENQ),
|
|
.DEQ(int_div_fNext_52$DEQ),
|
|
.CLR(int_div_fNext_52$CLR),
|
|
.D_OUT(int_div_fNext_52$D_OUT),
|
|
.FULL_N(int_div_fNext_52$FULL_N),
|
|
.EMPTY_N(int_div_fNext_52$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_53
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_53(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_53$D_IN),
|
|
.ENQ(int_div_fNext_53$ENQ),
|
|
.DEQ(int_div_fNext_53$DEQ),
|
|
.CLR(int_div_fNext_53$CLR),
|
|
.D_OUT(int_div_fNext_53$D_OUT),
|
|
.FULL_N(int_div_fNext_53$FULL_N),
|
|
.EMPTY_N(int_div_fNext_53$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_54
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_54(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_54$D_IN),
|
|
.ENQ(int_div_fNext_54$ENQ),
|
|
.DEQ(int_div_fNext_54$DEQ),
|
|
.CLR(int_div_fNext_54$CLR),
|
|
.D_OUT(int_div_fNext_54$D_OUT),
|
|
.FULL_N(int_div_fNext_54$FULL_N),
|
|
.EMPTY_N(int_div_fNext_54$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_55
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_55(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_55$D_IN),
|
|
.ENQ(int_div_fNext_55$ENQ),
|
|
.DEQ(int_div_fNext_55$DEQ),
|
|
.CLR(int_div_fNext_55$CLR),
|
|
.D_OUT(int_div_fNext_55$D_OUT),
|
|
.FULL_N(int_div_fNext_55$FULL_N),
|
|
.EMPTY_N(int_div_fNext_55$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_56
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_56(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_56$D_IN),
|
|
.ENQ(int_div_fNext_56$ENQ),
|
|
.DEQ(int_div_fNext_56$DEQ),
|
|
.CLR(int_div_fNext_56$CLR),
|
|
.D_OUT(int_div_fNext_56$D_OUT),
|
|
.FULL_N(int_div_fNext_56$FULL_N),
|
|
.EMPTY_N(int_div_fNext_56$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_57
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_57(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_57$D_IN),
|
|
.ENQ(int_div_fNext_57$ENQ),
|
|
.DEQ(int_div_fNext_57$DEQ),
|
|
.CLR(int_div_fNext_57$CLR),
|
|
.D_OUT(int_div_fNext_57$D_OUT),
|
|
.FULL_N(int_div_fNext_57$FULL_N),
|
|
.EMPTY_N(int_div_fNext_57$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_6
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_6(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_6$D_IN),
|
|
.ENQ(int_div_fNext_6$ENQ),
|
|
.DEQ(int_div_fNext_6$DEQ),
|
|
.CLR(int_div_fNext_6$CLR),
|
|
.D_OUT(int_div_fNext_6$D_OUT),
|
|
.FULL_N(int_div_fNext_6$FULL_N),
|
|
.EMPTY_N(int_div_fNext_6$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_7
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_7(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_7$D_IN),
|
|
.ENQ(int_div_fNext_7$ENQ),
|
|
.DEQ(int_div_fNext_7$DEQ),
|
|
.CLR(int_div_fNext_7$CLR),
|
|
.D_OUT(int_div_fNext_7$D_OUT),
|
|
.FULL_N(int_div_fNext_7$FULL_N),
|
|
.EMPTY_N(int_div_fNext_7$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_8
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_8(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_8$D_IN),
|
|
.ENQ(int_div_fNext_8$ENQ),
|
|
.DEQ(int_div_fNext_8$DEQ),
|
|
.CLR(int_div_fNext_8$CLR),
|
|
.D_OUT(int_div_fNext_8$D_OUT),
|
|
.FULL_N(int_div_fNext_8$FULL_N),
|
|
.EMPTY_N(int_div_fNext_8$EMPTY_N));
|
|
|
|
// submodule int_div_fNext_9
|
|
FIFOL1 #(.width(32'd232)) int_div_fNext_9(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fNext_9$D_IN),
|
|
.ENQ(int_div_fNext_9$ENQ),
|
|
.DEQ(int_div_fNext_9$DEQ),
|
|
.CLR(int_div_fNext_9$CLR),
|
|
.D_OUT(int_div_fNext_9$D_OUT),
|
|
.FULL_N(int_div_fNext_9$FULL_N),
|
|
.EMPTY_N(int_div_fNext_9$EMPTY_N));
|
|
|
|
// submodule int_div_fRequest
|
|
FIFOL1 #(.width(32'd171)) int_div_fRequest(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fRequest$D_IN),
|
|
.ENQ(int_div_fRequest$ENQ),
|
|
.DEQ(int_div_fRequest$DEQ),
|
|
.CLR(int_div_fRequest$CLR),
|
|
.D_OUT(int_div_fRequest$D_OUT),
|
|
.FULL_N(int_div_fRequest$FULL_N),
|
|
.EMPTY_N(int_div_fRequest$EMPTY_N));
|
|
|
|
// submodule int_div_fResponse
|
|
FIFOL1 #(.width(32'd114)) int_div_fResponse(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(int_div_fResponse$D_IN),
|
|
.ENQ(int_div_fResponse$ENQ),
|
|
.DEQ(int_div_fResponse$DEQ),
|
|
.CLR(int_div_fResponse$CLR),
|
|
.D_OUT(int_div_fResponse$D_OUT),
|
|
.FULL_N(int_div_fResponse$FULL_N),
|
|
.EMPTY_N(int_div_fResponse$EMPTY_N));
|
|
|
|
// rule RL_fpu_s5_stage
|
|
assign CAN_FIRE_RL_fpu_s5_stage =
|
|
fpu_fState_S4$EMPTY_N && fpu_fResult_S5$FULL_N ;
|
|
assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ;
|
|
|
|
// rule RL_fpu_s4_stage
|
|
assign CAN_FIRE_RL_fpu_s4_stage =
|
|
fpu_fState_S3$EMPTY_N && fpu_fState_S4$FULL_N ;
|
|
assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ;
|
|
|
|
// rule RL_fpu_s3_stage
|
|
assign CAN_FIRE_RL_fpu_s3_stage =
|
|
fpu_fState_S2$EMPTY_N && fpu_fState_S3$FULL_N &&
|
|
(fpu_fState_S2$D_OUT[147] || int_div_fResponse$EMPTY_N) ;
|
|
assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ;
|
|
|
|
// rule RL_int_div_finish
|
|
assign CAN_FIRE_RL_int_div_finish =
|
|
int_div_fNext_57$EMPTY_N && int_div_fResponse$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_finish = CAN_FIRE_RL_int_div_finish ;
|
|
|
|
// rule RL_int_div_work_57
|
|
assign CAN_FIRE_RL_int_div_work_57 =
|
|
int_div_fNext_56$EMPTY_N && int_div_fNext_57$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_57 = CAN_FIRE_RL_int_div_work_57 ;
|
|
|
|
// rule RL_int_div_work_56
|
|
assign CAN_FIRE_RL_int_div_work_56 =
|
|
int_div_fNext_55$EMPTY_N && int_div_fNext_56$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_56 = CAN_FIRE_RL_int_div_work_56 ;
|
|
|
|
// rule RL_int_div_work_55
|
|
assign CAN_FIRE_RL_int_div_work_55 =
|
|
int_div_fNext_54$EMPTY_N && int_div_fNext_55$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_55 = CAN_FIRE_RL_int_div_work_55 ;
|
|
|
|
// rule RL_int_div_work_54
|
|
assign CAN_FIRE_RL_int_div_work_54 =
|
|
int_div_fNext_53$EMPTY_N && int_div_fNext_54$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_54 = CAN_FIRE_RL_int_div_work_54 ;
|
|
|
|
// rule RL_int_div_work_53
|
|
assign CAN_FIRE_RL_int_div_work_53 =
|
|
int_div_fNext_52$EMPTY_N && int_div_fNext_53$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_53 = CAN_FIRE_RL_int_div_work_53 ;
|
|
|
|
// rule RL_int_div_work_52
|
|
assign CAN_FIRE_RL_int_div_work_52 =
|
|
int_div_fNext_51$EMPTY_N && int_div_fNext_52$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_52 = CAN_FIRE_RL_int_div_work_52 ;
|
|
|
|
// rule RL_int_div_work_51
|
|
assign CAN_FIRE_RL_int_div_work_51 =
|
|
int_div_fNext_50$EMPTY_N && int_div_fNext_51$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_51 = CAN_FIRE_RL_int_div_work_51 ;
|
|
|
|
// rule RL_int_div_work_50
|
|
assign CAN_FIRE_RL_int_div_work_50 =
|
|
int_div_fNext_49$EMPTY_N && int_div_fNext_50$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_50 = CAN_FIRE_RL_int_div_work_50 ;
|
|
|
|
// rule RL_int_div_work_49
|
|
assign CAN_FIRE_RL_int_div_work_49 =
|
|
int_div_fNext_48$EMPTY_N && int_div_fNext_49$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_49 = CAN_FIRE_RL_int_div_work_49 ;
|
|
|
|
// rule RL_int_div_work_48
|
|
assign CAN_FIRE_RL_int_div_work_48 =
|
|
int_div_fNext_47$EMPTY_N && int_div_fNext_48$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_48 = CAN_FIRE_RL_int_div_work_48 ;
|
|
|
|
// rule RL_int_div_work_47
|
|
assign CAN_FIRE_RL_int_div_work_47 =
|
|
int_div_fNext_46$EMPTY_N && int_div_fNext_47$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_47 = CAN_FIRE_RL_int_div_work_47 ;
|
|
|
|
// rule RL_int_div_work_46
|
|
assign CAN_FIRE_RL_int_div_work_46 =
|
|
int_div_fNext_45$EMPTY_N && int_div_fNext_46$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_46 = CAN_FIRE_RL_int_div_work_46 ;
|
|
|
|
// rule RL_int_div_work_45
|
|
assign CAN_FIRE_RL_int_div_work_45 =
|
|
int_div_fNext_44$EMPTY_N && int_div_fNext_45$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_45 = CAN_FIRE_RL_int_div_work_45 ;
|
|
|
|
// rule RL_int_div_work_44
|
|
assign CAN_FIRE_RL_int_div_work_44 =
|
|
int_div_fNext_43$EMPTY_N && int_div_fNext_44$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_44 = CAN_FIRE_RL_int_div_work_44 ;
|
|
|
|
// rule RL_int_div_work_43
|
|
assign CAN_FIRE_RL_int_div_work_43 =
|
|
int_div_fNext_42$EMPTY_N && int_div_fNext_43$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_43 = CAN_FIRE_RL_int_div_work_43 ;
|
|
|
|
// rule RL_int_div_work_42
|
|
assign CAN_FIRE_RL_int_div_work_42 =
|
|
int_div_fNext_41$EMPTY_N && int_div_fNext_42$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_42 = CAN_FIRE_RL_int_div_work_42 ;
|
|
|
|
// rule RL_int_div_work_41
|
|
assign CAN_FIRE_RL_int_div_work_41 =
|
|
int_div_fNext_40$EMPTY_N && int_div_fNext_41$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_41 = CAN_FIRE_RL_int_div_work_41 ;
|
|
|
|
// rule RL_int_div_work_40
|
|
assign CAN_FIRE_RL_int_div_work_40 =
|
|
int_div_fNext_39$EMPTY_N && int_div_fNext_40$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_40 = CAN_FIRE_RL_int_div_work_40 ;
|
|
|
|
// rule RL_int_div_work_39
|
|
assign CAN_FIRE_RL_int_div_work_39 =
|
|
int_div_fNext_38$EMPTY_N && int_div_fNext_39$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_39 = CAN_FIRE_RL_int_div_work_39 ;
|
|
|
|
// rule RL_int_div_work_38
|
|
assign CAN_FIRE_RL_int_div_work_38 =
|
|
int_div_fNext_37$EMPTY_N && int_div_fNext_38$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_38 = CAN_FIRE_RL_int_div_work_38 ;
|
|
|
|
// rule RL_int_div_work_37
|
|
assign CAN_FIRE_RL_int_div_work_37 =
|
|
int_div_fNext_36$EMPTY_N && int_div_fNext_37$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_37 = CAN_FIRE_RL_int_div_work_37 ;
|
|
|
|
// rule RL_int_div_work_36
|
|
assign CAN_FIRE_RL_int_div_work_36 =
|
|
int_div_fNext_35$EMPTY_N && int_div_fNext_36$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_36 = CAN_FIRE_RL_int_div_work_36 ;
|
|
|
|
// rule RL_int_div_work_35
|
|
assign CAN_FIRE_RL_int_div_work_35 =
|
|
int_div_fNext_34$EMPTY_N && int_div_fNext_35$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_35 = CAN_FIRE_RL_int_div_work_35 ;
|
|
|
|
// rule RL_int_div_work_34
|
|
assign CAN_FIRE_RL_int_div_work_34 =
|
|
int_div_fNext_33$EMPTY_N && int_div_fNext_34$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_34 = CAN_FIRE_RL_int_div_work_34 ;
|
|
|
|
// rule RL_int_div_work_33
|
|
assign CAN_FIRE_RL_int_div_work_33 =
|
|
int_div_fNext_32$EMPTY_N && int_div_fNext_33$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_33 = CAN_FIRE_RL_int_div_work_33 ;
|
|
|
|
// rule RL_int_div_work_32
|
|
assign CAN_FIRE_RL_int_div_work_32 =
|
|
int_div_fNext_31$EMPTY_N && int_div_fNext_32$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_32 = CAN_FIRE_RL_int_div_work_32 ;
|
|
|
|
// rule RL_int_div_work_31
|
|
assign CAN_FIRE_RL_int_div_work_31 =
|
|
int_div_fNext_30$EMPTY_N && int_div_fNext_31$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_31 = CAN_FIRE_RL_int_div_work_31 ;
|
|
|
|
// rule RL_int_div_work_30
|
|
assign CAN_FIRE_RL_int_div_work_30 =
|
|
int_div_fNext_29$EMPTY_N && int_div_fNext_30$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_30 = CAN_FIRE_RL_int_div_work_30 ;
|
|
|
|
// rule RL_int_div_work_29
|
|
assign CAN_FIRE_RL_int_div_work_29 =
|
|
int_div_fNext_28$EMPTY_N && int_div_fNext_29$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_29 = CAN_FIRE_RL_int_div_work_29 ;
|
|
|
|
// rule RL_int_div_work_28
|
|
assign CAN_FIRE_RL_int_div_work_28 =
|
|
int_div_fNext_27$EMPTY_N && int_div_fNext_28$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_28 = CAN_FIRE_RL_int_div_work_28 ;
|
|
|
|
// rule RL_int_div_work_27
|
|
assign CAN_FIRE_RL_int_div_work_27 =
|
|
int_div_fNext_26$EMPTY_N && int_div_fNext_27$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_27 = CAN_FIRE_RL_int_div_work_27 ;
|
|
|
|
// rule RL_int_div_work_26
|
|
assign CAN_FIRE_RL_int_div_work_26 =
|
|
int_div_fNext_25$EMPTY_N && int_div_fNext_26$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_26 = CAN_FIRE_RL_int_div_work_26 ;
|
|
|
|
// rule RL_int_div_work_25
|
|
assign CAN_FIRE_RL_int_div_work_25 =
|
|
int_div_fNext_24$EMPTY_N && int_div_fNext_25$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_25 = CAN_FIRE_RL_int_div_work_25 ;
|
|
|
|
// rule RL_int_div_work_24
|
|
assign CAN_FIRE_RL_int_div_work_24 =
|
|
int_div_fNext_23$EMPTY_N && int_div_fNext_24$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_24 = CAN_FIRE_RL_int_div_work_24 ;
|
|
|
|
// rule RL_int_div_work_23
|
|
assign CAN_FIRE_RL_int_div_work_23 =
|
|
int_div_fNext_22$EMPTY_N && int_div_fNext_23$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_23 = CAN_FIRE_RL_int_div_work_23 ;
|
|
|
|
// rule RL_int_div_work_22
|
|
assign CAN_FIRE_RL_int_div_work_22 =
|
|
int_div_fNext_21$EMPTY_N && int_div_fNext_22$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_22 = CAN_FIRE_RL_int_div_work_22 ;
|
|
|
|
// rule RL_int_div_work_21
|
|
assign CAN_FIRE_RL_int_div_work_21 =
|
|
int_div_fNext_20$EMPTY_N && int_div_fNext_21$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_21 = CAN_FIRE_RL_int_div_work_21 ;
|
|
|
|
// rule RL_int_div_work_20
|
|
assign CAN_FIRE_RL_int_div_work_20 =
|
|
int_div_fNext_19$EMPTY_N && int_div_fNext_20$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_20 = CAN_FIRE_RL_int_div_work_20 ;
|
|
|
|
// rule RL_int_div_work_19
|
|
assign CAN_FIRE_RL_int_div_work_19 =
|
|
int_div_fNext_18$EMPTY_N && int_div_fNext_19$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_19 = CAN_FIRE_RL_int_div_work_19 ;
|
|
|
|
// rule RL_int_div_work_18
|
|
assign CAN_FIRE_RL_int_div_work_18 =
|
|
int_div_fNext_17$EMPTY_N && int_div_fNext_18$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_18 = CAN_FIRE_RL_int_div_work_18 ;
|
|
|
|
// rule RL_int_div_work_17
|
|
assign CAN_FIRE_RL_int_div_work_17 =
|
|
int_div_fNext_16$EMPTY_N && int_div_fNext_17$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_17 = CAN_FIRE_RL_int_div_work_17 ;
|
|
|
|
// rule RL_int_div_work_16
|
|
assign CAN_FIRE_RL_int_div_work_16 =
|
|
int_div_fNext_15$EMPTY_N && int_div_fNext_16$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_16 = CAN_FIRE_RL_int_div_work_16 ;
|
|
|
|
// rule RL_int_div_work_15
|
|
assign CAN_FIRE_RL_int_div_work_15 =
|
|
int_div_fNext_14$EMPTY_N && int_div_fNext_15$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_15 = CAN_FIRE_RL_int_div_work_15 ;
|
|
|
|
// rule RL_int_div_work_14
|
|
assign CAN_FIRE_RL_int_div_work_14 =
|
|
int_div_fNext_13$EMPTY_N && int_div_fNext_14$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_14 = CAN_FIRE_RL_int_div_work_14 ;
|
|
|
|
// rule RL_int_div_work_13
|
|
assign CAN_FIRE_RL_int_div_work_13 =
|
|
int_div_fNext_12$EMPTY_N && int_div_fNext_13$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_13 = CAN_FIRE_RL_int_div_work_13 ;
|
|
|
|
// rule RL_int_div_work_12
|
|
assign CAN_FIRE_RL_int_div_work_12 =
|
|
int_div_fNext_11$EMPTY_N && int_div_fNext_12$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_12 = CAN_FIRE_RL_int_div_work_12 ;
|
|
|
|
// rule RL_int_div_work_11
|
|
assign CAN_FIRE_RL_int_div_work_11 =
|
|
int_div_fNext_10$EMPTY_N && int_div_fNext_11$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_11 = CAN_FIRE_RL_int_div_work_11 ;
|
|
|
|
// rule RL_int_div_work_10
|
|
assign CAN_FIRE_RL_int_div_work_10 =
|
|
int_div_fNext_9$EMPTY_N && int_div_fNext_10$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_10 = CAN_FIRE_RL_int_div_work_10 ;
|
|
|
|
// rule RL_int_div_work_9
|
|
assign CAN_FIRE_RL_int_div_work_9 =
|
|
int_div_fNext_8$EMPTY_N && int_div_fNext_9$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_9 = CAN_FIRE_RL_int_div_work_9 ;
|
|
|
|
// rule RL_int_div_work_8
|
|
assign CAN_FIRE_RL_int_div_work_8 =
|
|
int_div_fNext_7$EMPTY_N && int_div_fNext_8$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_8 = CAN_FIRE_RL_int_div_work_8 ;
|
|
|
|
// rule RL_int_div_work_7
|
|
assign CAN_FIRE_RL_int_div_work_7 =
|
|
int_div_fNext_6$EMPTY_N && int_div_fNext_7$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_7 = CAN_FIRE_RL_int_div_work_7 ;
|
|
|
|
// rule RL_int_div_work_6
|
|
assign CAN_FIRE_RL_int_div_work_6 =
|
|
int_div_fNext_5$EMPTY_N && int_div_fNext_6$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_6 = CAN_FIRE_RL_int_div_work_6 ;
|
|
|
|
// rule RL_int_div_work_5
|
|
assign CAN_FIRE_RL_int_div_work_5 =
|
|
int_div_fNext_4$EMPTY_N && int_div_fNext_5$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_5 = CAN_FIRE_RL_int_div_work_5 ;
|
|
|
|
// rule RL_int_div_work_4
|
|
assign CAN_FIRE_RL_int_div_work_4 =
|
|
int_div_fNext_3$EMPTY_N && int_div_fNext_4$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_4 = CAN_FIRE_RL_int_div_work_4 ;
|
|
|
|
// rule RL_int_div_work_3
|
|
assign CAN_FIRE_RL_int_div_work_3 =
|
|
int_div_fNext_2$EMPTY_N && int_div_fNext_3$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_3 = CAN_FIRE_RL_int_div_work_3 ;
|
|
|
|
// rule RL_int_div_work_2
|
|
assign CAN_FIRE_RL_int_div_work_2 =
|
|
int_div_fNext_1$EMPTY_N && int_div_fNext_2$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_2 = CAN_FIRE_RL_int_div_work_2 ;
|
|
|
|
// rule RL_int_div_work_1
|
|
assign CAN_FIRE_RL_int_div_work_1 =
|
|
int_div_fNext_0$EMPTY_N && int_div_fNext_1$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work_1 = CAN_FIRE_RL_int_div_work_1 ;
|
|
|
|
// rule RL_int_div_work
|
|
assign CAN_FIRE_RL_int_div_work =
|
|
int_div_fFirst$EMPTY_N && int_div_fNext_0$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_work = CAN_FIRE_RL_int_div_work ;
|
|
|
|
// rule RL_int_div_start
|
|
assign CAN_FIRE_RL_int_div_start =
|
|
int_div_fRequest$EMPTY_N && int_div_fFirst$FULL_N ;
|
|
assign WILL_FIRE_RL_int_div_start = CAN_FIRE_RL_int_div_start ;
|
|
|
|
// rule RL_fpu_s2_stage
|
|
assign CAN_FIRE_RL_fpu_s2_stage =
|
|
fpu_fState_S1$EMPTY_N && fpu_fState_S2$FULL_N &&
|
|
(fpu_fState_S1$D_OUT[318] || int_div_fRequest$FULL_N) ;
|
|
assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ;
|
|
|
|
// rule RL_fpu_s1_stage
|
|
assign CAN_FIRE_RL_fpu_s1_stage =
|
|
fpu_fOperands_S0$EMPTY_N && fpu_fState_S1$FULL_N ;
|
|
assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ;
|
|
|
|
// submodule fpu_fOperands_S0
|
|
assign fpu_fOperands_S0$D_IN = request_put ;
|
|
assign fpu_fOperands_S0$ENQ = EN_request_put ;
|
|
assign fpu_fOperands_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ;
|
|
assign fpu_fOperands_S0$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fResult_S5
|
|
assign fpu_fResult_S5$D_IN =
|
|
fpu_fState_S4$D_OUT[138] ?
|
|
fpu_fState_S4$D_OUT[137:69] :
|
|
{ (fpu_fState_S4$D_OUT[64:54] == 11'd2047) ?
|
|
fpu_fState_S4$D_OUT[65:2] :
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16,
|
|
fpu_fState_S4$D_OUT[73:69] |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h60991 == 11'd2047 &&
|
|
_theResult___fst_sfd__h60992 == 52'd0,
|
|
1'd0,
|
|
fpu_fState_S4$D_OUT[64:54] != 11'd2047 &&
|
|
fpu_fState_S4$D_OUT[1:0] != 2'b0 } } ;
|
|
assign fpu_fResult_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ;
|
|
assign fpu_fResult_S5$DEQ = EN_response_get ;
|
|
assign fpu_fResult_S5$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S1
|
|
assign fpu_fState_S1$D_IN =
|
|
{ fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216,
|
|
(fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[118]) ?
|
|
{ fpu_fOperands_S0$D_OUT[130:119], sfd__h36684 } :
|
|
IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308,
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[118] ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[54] ||
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[54]) &&
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289,
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[118]) &&
|
|
NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 &&
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0),
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54]) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[54]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206,
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54]) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[54]) &&
|
|
NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334,
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54]) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[118]) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
!fpu_fOperands_S0$D_OUT[54]) &&
|
|
NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341,
|
|
fpu_fOperands_S0$D_OUT[2:0],
|
|
!fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258,
|
|
_theResult___snd_fst_exp__h49111,
|
|
_theResult___snd_fst_sfd__h49112,
|
|
x__h49176,
|
|
x__h49237,
|
|
x__h49291 } ;
|
|
assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ;
|
|
assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ;
|
|
assign fpu_fState_S1$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S2
|
|
assign fpu_fState_S2$D_IN =
|
|
{ fpu_fState_S1$D_OUT[318:182], fpu_fState_S1$D_OUT[10:0] } ;
|
|
assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ;
|
|
assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ;
|
|
assign fpu_fState_S2$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S3
|
|
assign fpu_fState_S3$D_IN = { fpu_fState_S2$D_OUT[147:11], x__h50487 } ;
|
|
assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ;
|
|
assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ;
|
|
assign fpu_fState_S3$CLR = 1'b0 ;
|
|
|
|
// submodule fpu_fState_S4
|
|
assign fpu_fState_S4$D_IN =
|
|
{ (fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
fpu_fState_S3$D_OUT[57:56] != 2'b0 ||
|
|
fpu_fState_S3$D_OUT[194] :
|
|
fpu_fState_S3$D_OUT[194],
|
|
(fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
((fpu_fState_S3$D_OUT[57:56] == 2'b0) ?
|
|
fpu_fState_S3$D_OUT[193:130] :
|
|
{ CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17,
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 }) :
|
|
fpu_fState_S3$D_OUT[193:130],
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770,
|
|
fpu_fState_S3$D_OUT[124:122],
|
|
fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780,
|
|
x__h60140 } ;
|
|
assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ;
|
|
assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ;
|
|
assign fpu_fState_S4$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fFirst
|
|
assign int_div_fFirst$D_IN =
|
|
{ b__h378, 60'd0, int_div_fRequest$D_OUT[170:57] } ;
|
|
assign int_div_fFirst$ENQ = CAN_FIRE_RL_int_div_start ;
|
|
assign int_div_fFirst$DEQ = CAN_FIRE_RL_int_div_work ;
|
|
assign int_div_fFirst$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_0
|
|
assign int_div_fNext_0$D_IN =
|
|
{ int_div_fFirst$D_OUT[231:174],
|
|
int_div_fFirst$D_OUT[172:116],
|
|
!int_div_fFirst$D_OUT[115],
|
|
int_div_fFirst$D_OUT[115] ?
|
|
{ int_div_fFirst$D_OUT[114:0], 1'd0 } + b__h767 :
|
|
{ int_div_fFirst$D_OUT[114:0], 1'd0 } - b__h767 } ;
|
|
assign int_div_fNext_0$ENQ = CAN_FIRE_RL_int_div_work ;
|
|
assign int_div_fNext_0$DEQ = CAN_FIRE_RL_int_div_work_1 ;
|
|
assign int_div_fNext_0$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_1
|
|
assign int_div_fNext_1$D_IN =
|
|
{ int_div_fNext_0$D_OUT[231:174],
|
|
int_div_fNext_0$D_OUT[172:116],
|
|
!int_div_fNext_0$D_OUT[115],
|
|
int_div_fNext_0$D_OUT[115] ?
|
|
{ int_div_fNext_0$D_OUT[114:0], 1'd0 } + b__h1091 :
|
|
{ int_div_fNext_0$D_OUT[114:0], 1'd0 } - b__h1091 } ;
|
|
assign int_div_fNext_1$ENQ = CAN_FIRE_RL_int_div_work_1 ;
|
|
assign int_div_fNext_1$DEQ = CAN_FIRE_RL_int_div_work_2 ;
|
|
assign int_div_fNext_1$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_10
|
|
assign int_div_fNext_10$D_IN =
|
|
{ int_div_fNext_9$D_OUT[231:174],
|
|
int_div_fNext_9$D_OUT[172:116],
|
|
!int_div_fNext_9$D_OUT[115],
|
|
int_div_fNext_9$D_OUT[115] ?
|
|
{ int_div_fNext_9$D_OUT[114:0], 1'd0 } + b__h4007 :
|
|
{ int_div_fNext_9$D_OUT[114:0], 1'd0 } - b__h4007 } ;
|
|
assign int_div_fNext_10$ENQ = CAN_FIRE_RL_int_div_work_10 ;
|
|
assign int_div_fNext_10$DEQ = CAN_FIRE_RL_int_div_work_11 ;
|
|
assign int_div_fNext_10$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_11
|
|
assign int_div_fNext_11$D_IN =
|
|
{ int_div_fNext_10$D_OUT[231:174],
|
|
int_div_fNext_10$D_OUT[172:116],
|
|
!int_div_fNext_10$D_OUT[115],
|
|
int_div_fNext_10$D_OUT[115] ?
|
|
{ int_div_fNext_10$D_OUT[114:0], 1'd0 } + b__h4331 :
|
|
{ int_div_fNext_10$D_OUT[114:0], 1'd0 } - b__h4331 } ;
|
|
assign int_div_fNext_11$ENQ = CAN_FIRE_RL_int_div_work_11 ;
|
|
assign int_div_fNext_11$DEQ = CAN_FIRE_RL_int_div_work_12 ;
|
|
assign int_div_fNext_11$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_12
|
|
assign int_div_fNext_12$D_IN =
|
|
{ int_div_fNext_11$D_OUT[231:174],
|
|
int_div_fNext_11$D_OUT[172:116],
|
|
!int_div_fNext_11$D_OUT[115],
|
|
int_div_fNext_11$D_OUT[115] ?
|
|
{ int_div_fNext_11$D_OUT[114:0], 1'd0 } + b__h4655 :
|
|
{ int_div_fNext_11$D_OUT[114:0], 1'd0 } - b__h4655 } ;
|
|
assign int_div_fNext_12$ENQ = CAN_FIRE_RL_int_div_work_12 ;
|
|
assign int_div_fNext_12$DEQ = CAN_FIRE_RL_int_div_work_13 ;
|
|
assign int_div_fNext_12$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_13
|
|
assign int_div_fNext_13$D_IN =
|
|
{ int_div_fNext_12$D_OUT[231:174],
|
|
int_div_fNext_12$D_OUT[172:116],
|
|
!int_div_fNext_12$D_OUT[115],
|
|
int_div_fNext_12$D_OUT[115] ?
|
|
{ int_div_fNext_12$D_OUT[114:0], 1'd0 } + b__h4979 :
|
|
{ int_div_fNext_12$D_OUT[114:0], 1'd0 } - b__h4979 } ;
|
|
assign int_div_fNext_13$ENQ = CAN_FIRE_RL_int_div_work_13 ;
|
|
assign int_div_fNext_13$DEQ = CAN_FIRE_RL_int_div_work_14 ;
|
|
assign int_div_fNext_13$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_14
|
|
assign int_div_fNext_14$D_IN =
|
|
{ int_div_fNext_13$D_OUT[231:174],
|
|
int_div_fNext_13$D_OUT[172:116],
|
|
!int_div_fNext_13$D_OUT[115],
|
|
int_div_fNext_13$D_OUT[115] ?
|
|
{ int_div_fNext_13$D_OUT[114:0], 1'd0 } + b__h5303 :
|
|
{ int_div_fNext_13$D_OUT[114:0], 1'd0 } - b__h5303 } ;
|
|
assign int_div_fNext_14$ENQ = CAN_FIRE_RL_int_div_work_14 ;
|
|
assign int_div_fNext_14$DEQ = CAN_FIRE_RL_int_div_work_15 ;
|
|
assign int_div_fNext_14$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_15
|
|
assign int_div_fNext_15$D_IN =
|
|
{ int_div_fNext_14$D_OUT[231:174],
|
|
int_div_fNext_14$D_OUT[172:116],
|
|
!int_div_fNext_14$D_OUT[115],
|
|
int_div_fNext_14$D_OUT[115] ?
|
|
{ int_div_fNext_14$D_OUT[114:0], 1'd0 } + b__h5627 :
|
|
{ int_div_fNext_14$D_OUT[114:0], 1'd0 } - b__h5627 } ;
|
|
assign int_div_fNext_15$ENQ = CAN_FIRE_RL_int_div_work_15 ;
|
|
assign int_div_fNext_15$DEQ = CAN_FIRE_RL_int_div_work_16 ;
|
|
assign int_div_fNext_15$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_16
|
|
assign int_div_fNext_16$D_IN =
|
|
{ int_div_fNext_15$D_OUT[231:174],
|
|
int_div_fNext_15$D_OUT[172:116],
|
|
!int_div_fNext_15$D_OUT[115],
|
|
int_div_fNext_15$D_OUT[115] ?
|
|
{ int_div_fNext_15$D_OUT[114:0], 1'd0 } + b__h5951 :
|
|
{ int_div_fNext_15$D_OUT[114:0], 1'd0 } - b__h5951 } ;
|
|
assign int_div_fNext_16$ENQ = CAN_FIRE_RL_int_div_work_16 ;
|
|
assign int_div_fNext_16$DEQ = CAN_FIRE_RL_int_div_work_17 ;
|
|
assign int_div_fNext_16$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_17
|
|
assign int_div_fNext_17$D_IN =
|
|
{ int_div_fNext_16$D_OUT[231:174],
|
|
int_div_fNext_16$D_OUT[172:116],
|
|
!int_div_fNext_16$D_OUT[115],
|
|
int_div_fNext_16$D_OUT[115] ?
|
|
{ int_div_fNext_16$D_OUT[114:0], 1'd0 } + b__h6275 :
|
|
{ int_div_fNext_16$D_OUT[114:0], 1'd0 } - b__h6275 } ;
|
|
assign int_div_fNext_17$ENQ = CAN_FIRE_RL_int_div_work_17 ;
|
|
assign int_div_fNext_17$DEQ = CAN_FIRE_RL_int_div_work_18 ;
|
|
assign int_div_fNext_17$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_18
|
|
assign int_div_fNext_18$D_IN =
|
|
{ int_div_fNext_17$D_OUT[231:174],
|
|
int_div_fNext_17$D_OUT[172:116],
|
|
!int_div_fNext_17$D_OUT[115],
|
|
int_div_fNext_17$D_OUT[115] ?
|
|
{ int_div_fNext_17$D_OUT[114:0], 1'd0 } + b__h6599 :
|
|
{ int_div_fNext_17$D_OUT[114:0], 1'd0 } - b__h6599 } ;
|
|
assign int_div_fNext_18$ENQ = CAN_FIRE_RL_int_div_work_18 ;
|
|
assign int_div_fNext_18$DEQ = CAN_FIRE_RL_int_div_work_19 ;
|
|
assign int_div_fNext_18$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_19
|
|
assign int_div_fNext_19$D_IN =
|
|
{ int_div_fNext_18$D_OUT[231:174],
|
|
int_div_fNext_18$D_OUT[172:116],
|
|
!int_div_fNext_18$D_OUT[115],
|
|
int_div_fNext_18$D_OUT[115] ?
|
|
{ int_div_fNext_18$D_OUT[114:0], 1'd0 } + b__h6923 :
|
|
{ int_div_fNext_18$D_OUT[114:0], 1'd0 } - b__h6923 } ;
|
|
assign int_div_fNext_19$ENQ = CAN_FIRE_RL_int_div_work_19 ;
|
|
assign int_div_fNext_19$DEQ = CAN_FIRE_RL_int_div_work_20 ;
|
|
assign int_div_fNext_19$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_2
|
|
assign int_div_fNext_2$D_IN =
|
|
{ int_div_fNext_1$D_OUT[231:174],
|
|
int_div_fNext_1$D_OUT[172:116],
|
|
!int_div_fNext_1$D_OUT[115],
|
|
int_div_fNext_1$D_OUT[115] ?
|
|
{ int_div_fNext_1$D_OUT[114:0], 1'd0 } + b__h1415 :
|
|
{ int_div_fNext_1$D_OUT[114:0], 1'd0 } - b__h1415 } ;
|
|
assign int_div_fNext_2$ENQ = CAN_FIRE_RL_int_div_work_2 ;
|
|
assign int_div_fNext_2$DEQ = CAN_FIRE_RL_int_div_work_3 ;
|
|
assign int_div_fNext_2$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_20
|
|
assign int_div_fNext_20$D_IN =
|
|
{ int_div_fNext_19$D_OUT[231:174],
|
|
int_div_fNext_19$D_OUT[172:116],
|
|
!int_div_fNext_19$D_OUT[115],
|
|
int_div_fNext_19$D_OUT[115] ?
|
|
{ int_div_fNext_19$D_OUT[114:0], 1'd0 } + b__h7247 :
|
|
{ int_div_fNext_19$D_OUT[114:0], 1'd0 } - b__h7247 } ;
|
|
assign int_div_fNext_20$ENQ = CAN_FIRE_RL_int_div_work_20 ;
|
|
assign int_div_fNext_20$DEQ = CAN_FIRE_RL_int_div_work_21 ;
|
|
assign int_div_fNext_20$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_21
|
|
assign int_div_fNext_21$D_IN =
|
|
{ int_div_fNext_20$D_OUT[231:174],
|
|
int_div_fNext_20$D_OUT[172:116],
|
|
!int_div_fNext_20$D_OUT[115],
|
|
int_div_fNext_20$D_OUT[115] ?
|
|
{ int_div_fNext_20$D_OUT[114:0], 1'd0 } + b__h7571 :
|
|
{ int_div_fNext_20$D_OUT[114:0], 1'd0 } - b__h7571 } ;
|
|
assign int_div_fNext_21$ENQ = CAN_FIRE_RL_int_div_work_21 ;
|
|
assign int_div_fNext_21$DEQ = CAN_FIRE_RL_int_div_work_22 ;
|
|
assign int_div_fNext_21$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_22
|
|
assign int_div_fNext_22$D_IN =
|
|
{ int_div_fNext_21$D_OUT[231:174],
|
|
int_div_fNext_21$D_OUT[172:116],
|
|
!int_div_fNext_21$D_OUT[115],
|
|
int_div_fNext_21$D_OUT[115] ?
|
|
{ int_div_fNext_21$D_OUT[114:0], 1'd0 } + b__h7895 :
|
|
{ int_div_fNext_21$D_OUT[114:0], 1'd0 } - b__h7895 } ;
|
|
assign int_div_fNext_22$ENQ = CAN_FIRE_RL_int_div_work_22 ;
|
|
assign int_div_fNext_22$DEQ = CAN_FIRE_RL_int_div_work_23 ;
|
|
assign int_div_fNext_22$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_23
|
|
assign int_div_fNext_23$D_IN =
|
|
{ int_div_fNext_22$D_OUT[231:174],
|
|
int_div_fNext_22$D_OUT[172:116],
|
|
!int_div_fNext_22$D_OUT[115],
|
|
int_div_fNext_22$D_OUT[115] ?
|
|
{ int_div_fNext_22$D_OUT[114:0], 1'd0 } + b__h8219 :
|
|
{ int_div_fNext_22$D_OUT[114:0], 1'd0 } - b__h8219 } ;
|
|
assign int_div_fNext_23$ENQ = CAN_FIRE_RL_int_div_work_23 ;
|
|
assign int_div_fNext_23$DEQ = CAN_FIRE_RL_int_div_work_24 ;
|
|
assign int_div_fNext_23$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_24
|
|
assign int_div_fNext_24$D_IN =
|
|
{ int_div_fNext_23$D_OUT[231:174],
|
|
int_div_fNext_23$D_OUT[172:116],
|
|
!int_div_fNext_23$D_OUT[115],
|
|
int_div_fNext_23$D_OUT[115] ?
|
|
{ int_div_fNext_23$D_OUT[114:0], 1'd0 } + b__h8543 :
|
|
{ int_div_fNext_23$D_OUT[114:0], 1'd0 } - b__h8543 } ;
|
|
assign int_div_fNext_24$ENQ = CAN_FIRE_RL_int_div_work_24 ;
|
|
assign int_div_fNext_24$DEQ = CAN_FIRE_RL_int_div_work_25 ;
|
|
assign int_div_fNext_24$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_25
|
|
assign int_div_fNext_25$D_IN =
|
|
{ int_div_fNext_24$D_OUT[231:174],
|
|
int_div_fNext_24$D_OUT[172:116],
|
|
!int_div_fNext_24$D_OUT[115],
|
|
int_div_fNext_24$D_OUT[115] ?
|
|
{ int_div_fNext_24$D_OUT[114:0], 1'd0 } + b__h8867 :
|
|
{ int_div_fNext_24$D_OUT[114:0], 1'd0 } - b__h8867 } ;
|
|
assign int_div_fNext_25$ENQ = CAN_FIRE_RL_int_div_work_25 ;
|
|
assign int_div_fNext_25$DEQ = CAN_FIRE_RL_int_div_work_26 ;
|
|
assign int_div_fNext_25$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_26
|
|
assign int_div_fNext_26$D_IN =
|
|
{ int_div_fNext_25$D_OUT[231:174],
|
|
int_div_fNext_25$D_OUT[172:116],
|
|
!int_div_fNext_25$D_OUT[115],
|
|
int_div_fNext_25$D_OUT[115] ?
|
|
{ int_div_fNext_25$D_OUT[114:0], 1'd0 } + b__h9191 :
|
|
{ int_div_fNext_25$D_OUT[114:0], 1'd0 } - b__h9191 } ;
|
|
assign int_div_fNext_26$ENQ = CAN_FIRE_RL_int_div_work_26 ;
|
|
assign int_div_fNext_26$DEQ = CAN_FIRE_RL_int_div_work_27 ;
|
|
assign int_div_fNext_26$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_27
|
|
assign int_div_fNext_27$D_IN =
|
|
{ int_div_fNext_26$D_OUT[231:174],
|
|
int_div_fNext_26$D_OUT[172:116],
|
|
!int_div_fNext_26$D_OUT[115],
|
|
int_div_fNext_26$D_OUT[115] ?
|
|
{ int_div_fNext_26$D_OUT[114:0], 1'd0 } + b__h9515 :
|
|
{ int_div_fNext_26$D_OUT[114:0], 1'd0 } - b__h9515 } ;
|
|
assign int_div_fNext_27$ENQ = CAN_FIRE_RL_int_div_work_27 ;
|
|
assign int_div_fNext_27$DEQ = CAN_FIRE_RL_int_div_work_28 ;
|
|
assign int_div_fNext_27$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_28
|
|
assign int_div_fNext_28$D_IN =
|
|
{ int_div_fNext_27$D_OUT[231:174],
|
|
int_div_fNext_27$D_OUT[172:116],
|
|
!int_div_fNext_27$D_OUT[115],
|
|
int_div_fNext_27$D_OUT[115] ?
|
|
{ int_div_fNext_27$D_OUT[114:0], 1'd0 } + b__h9839 :
|
|
{ int_div_fNext_27$D_OUT[114:0], 1'd0 } - b__h9839 } ;
|
|
assign int_div_fNext_28$ENQ = CAN_FIRE_RL_int_div_work_28 ;
|
|
assign int_div_fNext_28$DEQ = CAN_FIRE_RL_int_div_work_29 ;
|
|
assign int_div_fNext_28$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_29
|
|
assign int_div_fNext_29$D_IN =
|
|
{ int_div_fNext_28$D_OUT[231:174],
|
|
int_div_fNext_28$D_OUT[172:116],
|
|
!int_div_fNext_28$D_OUT[115],
|
|
int_div_fNext_28$D_OUT[115] ?
|
|
{ int_div_fNext_28$D_OUT[114:0], 1'd0 } + b__h10163 :
|
|
{ int_div_fNext_28$D_OUT[114:0], 1'd0 } - b__h10163 } ;
|
|
assign int_div_fNext_29$ENQ = CAN_FIRE_RL_int_div_work_29 ;
|
|
assign int_div_fNext_29$DEQ = CAN_FIRE_RL_int_div_work_30 ;
|
|
assign int_div_fNext_29$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_3
|
|
assign int_div_fNext_3$D_IN =
|
|
{ int_div_fNext_2$D_OUT[231:174],
|
|
int_div_fNext_2$D_OUT[172:116],
|
|
!int_div_fNext_2$D_OUT[115],
|
|
int_div_fNext_2$D_OUT[115] ?
|
|
{ int_div_fNext_2$D_OUT[114:0], 1'd0 } + b__h1739 :
|
|
{ int_div_fNext_2$D_OUT[114:0], 1'd0 } - b__h1739 } ;
|
|
assign int_div_fNext_3$ENQ = CAN_FIRE_RL_int_div_work_3 ;
|
|
assign int_div_fNext_3$DEQ = CAN_FIRE_RL_int_div_work_4 ;
|
|
assign int_div_fNext_3$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_30
|
|
assign int_div_fNext_30$D_IN =
|
|
{ int_div_fNext_29$D_OUT[231:174],
|
|
int_div_fNext_29$D_OUT[172:116],
|
|
!int_div_fNext_29$D_OUT[115],
|
|
int_div_fNext_29$D_OUT[115] ?
|
|
{ int_div_fNext_29$D_OUT[114:0], 1'd0 } + b__h10487 :
|
|
{ int_div_fNext_29$D_OUT[114:0], 1'd0 } - b__h10487 } ;
|
|
assign int_div_fNext_30$ENQ = CAN_FIRE_RL_int_div_work_30 ;
|
|
assign int_div_fNext_30$DEQ = CAN_FIRE_RL_int_div_work_31 ;
|
|
assign int_div_fNext_30$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_31
|
|
assign int_div_fNext_31$D_IN =
|
|
{ int_div_fNext_30$D_OUT[231:174],
|
|
int_div_fNext_30$D_OUT[172:116],
|
|
!int_div_fNext_30$D_OUT[115],
|
|
int_div_fNext_30$D_OUT[115] ?
|
|
{ int_div_fNext_30$D_OUT[114:0], 1'd0 } + b__h10811 :
|
|
{ int_div_fNext_30$D_OUT[114:0], 1'd0 } - b__h10811 } ;
|
|
assign int_div_fNext_31$ENQ = CAN_FIRE_RL_int_div_work_31 ;
|
|
assign int_div_fNext_31$DEQ = CAN_FIRE_RL_int_div_work_32 ;
|
|
assign int_div_fNext_31$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_32
|
|
assign int_div_fNext_32$D_IN =
|
|
{ int_div_fNext_31$D_OUT[231:174],
|
|
int_div_fNext_31$D_OUT[172:116],
|
|
!int_div_fNext_31$D_OUT[115],
|
|
int_div_fNext_31$D_OUT[115] ?
|
|
{ int_div_fNext_31$D_OUT[114:0], 1'd0 } + b__h11135 :
|
|
{ int_div_fNext_31$D_OUT[114:0], 1'd0 } - b__h11135 } ;
|
|
assign int_div_fNext_32$ENQ = CAN_FIRE_RL_int_div_work_32 ;
|
|
assign int_div_fNext_32$DEQ = CAN_FIRE_RL_int_div_work_33 ;
|
|
assign int_div_fNext_32$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_33
|
|
assign int_div_fNext_33$D_IN =
|
|
{ int_div_fNext_32$D_OUT[231:174],
|
|
int_div_fNext_32$D_OUT[172:116],
|
|
!int_div_fNext_32$D_OUT[115],
|
|
int_div_fNext_32$D_OUT[115] ?
|
|
{ int_div_fNext_32$D_OUT[114:0], 1'd0 } + b__h11459 :
|
|
{ int_div_fNext_32$D_OUT[114:0], 1'd0 } - b__h11459 } ;
|
|
assign int_div_fNext_33$ENQ = CAN_FIRE_RL_int_div_work_33 ;
|
|
assign int_div_fNext_33$DEQ = CAN_FIRE_RL_int_div_work_34 ;
|
|
assign int_div_fNext_33$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_34
|
|
assign int_div_fNext_34$D_IN =
|
|
{ int_div_fNext_33$D_OUT[231:174],
|
|
int_div_fNext_33$D_OUT[172:116],
|
|
!int_div_fNext_33$D_OUT[115],
|
|
int_div_fNext_33$D_OUT[115] ?
|
|
{ int_div_fNext_33$D_OUT[114:0], 1'd0 } + b__h11783 :
|
|
{ int_div_fNext_33$D_OUT[114:0], 1'd0 } - b__h11783 } ;
|
|
assign int_div_fNext_34$ENQ = CAN_FIRE_RL_int_div_work_34 ;
|
|
assign int_div_fNext_34$DEQ = CAN_FIRE_RL_int_div_work_35 ;
|
|
assign int_div_fNext_34$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_35
|
|
assign int_div_fNext_35$D_IN =
|
|
{ int_div_fNext_34$D_OUT[231:174],
|
|
int_div_fNext_34$D_OUT[172:116],
|
|
!int_div_fNext_34$D_OUT[115],
|
|
int_div_fNext_34$D_OUT[115] ?
|
|
{ int_div_fNext_34$D_OUT[114:0], 1'd0 } + b__h12107 :
|
|
{ int_div_fNext_34$D_OUT[114:0], 1'd0 } - b__h12107 } ;
|
|
assign int_div_fNext_35$ENQ = CAN_FIRE_RL_int_div_work_35 ;
|
|
assign int_div_fNext_35$DEQ = CAN_FIRE_RL_int_div_work_36 ;
|
|
assign int_div_fNext_35$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_36
|
|
assign int_div_fNext_36$D_IN =
|
|
{ int_div_fNext_35$D_OUT[231:174],
|
|
int_div_fNext_35$D_OUT[172:116],
|
|
!int_div_fNext_35$D_OUT[115],
|
|
int_div_fNext_35$D_OUT[115] ?
|
|
{ int_div_fNext_35$D_OUT[114:0], 1'd0 } + b__h12431 :
|
|
{ int_div_fNext_35$D_OUT[114:0], 1'd0 } - b__h12431 } ;
|
|
assign int_div_fNext_36$ENQ = CAN_FIRE_RL_int_div_work_36 ;
|
|
assign int_div_fNext_36$DEQ = CAN_FIRE_RL_int_div_work_37 ;
|
|
assign int_div_fNext_36$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_37
|
|
assign int_div_fNext_37$D_IN =
|
|
{ int_div_fNext_36$D_OUT[231:174],
|
|
int_div_fNext_36$D_OUT[172:116],
|
|
!int_div_fNext_36$D_OUT[115],
|
|
int_div_fNext_36$D_OUT[115] ?
|
|
{ int_div_fNext_36$D_OUT[114:0], 1'd0 } + b__h12755 :
|
|
{ int_div_fNext_36$D_OUT[114:0], 1'd0 } - b__h12755 } ;
|
|
assign int_div_fNext_37$ENQ = CAN_FIRE_RL_int_div_work_37 ;
|
|
assign int_div_fNext_37$DEQ = CAN_FIRE_RL_int_div_work_38 ;
|
|
assign int_div_fNext_37$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_38
|
|
assign int_div_fNext_38$D_IN =
|
|
{ int_div_fNext_37$D_OUT[231:174],
|
|
int_div_fNext_37$D_OUT[172:116],
|
|
!int_div_fNext_37$D_OUT[115],
|
|
int_div_fNext_37$D_OUT[115] ?
|
|
{ int_div_fNext_37$D_OUT[114:0], 1'd0 } + b__h13079 :
|
|
{ int_div_fNext_37$D_OUT[114:0], 1'd0 } - b__h13079 } ;
|
|
assign int_div_fNext_38$ENQ = CAN_FIRE_RL_int_div_work_38 ;
|
|
assign int_div_fNext_38$DEQ = CAN_FIRE_RL_int_div_work_39 ;
|
|
assign int_div_fNext_38$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_39
|
|
assign int_div_fNext_39$D_IN =
|
|
{ int_div_fNext_38$D_OUT[231:174],
|
|
int_div_fNext_38$D_OUT[172:116],
|
|
!int_div_fNext_38$D_OUT[115],
|
|
int_div_fNext_38$D_OUT[115] ?
|
|
{ int_div_fNext_38$D_OUT[114:0], 1'd0 } + b__h13403 :
|
|
{ int_div_fNext_38$D_OUT[114:0], 1'd0 } - b__h13403 } ;
|
|
assign int_div_fNext_39$ENQ = CAN_FIRE_RL_int_div_work_39 ;
|
|
assign int_div_fNext_39$DEQ = CAN_FIRE_RL_int_div_work_40 ;
|
|
assign int_div_fNext_39$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_4
|
|
assign int_div_fNext_4$D_IN =
|
|
{ int_div_fNext_3$D_OUT[231:174],
|
|
int_div_fNext_3$D_OUT[172:116],
|
|
!int_div_fNext_3$D_OUT[115],
|
|
int_div_fNext_3$D_OUT[115] ?
|
|
{ int_div_fNext_3$D_OUT[114:0], 1'd0 } + b__h2063 :
|
|
{ int_div_fNext_3$D_OUT[114:0], 1'd0 } - b__h2063 } ;
|
|
assign int_div_fNext_4$ENQ = CAN_FIRE_RL_int_div_work_4 ;
|
|
assign int_div_fNext_4$DEQ = CAN_FIRE_RL_int_div_work_5 ;
|
|
assign int_div_fNext_4$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_40
|
|
assign int_div_fNext_40$D_IN =
|
|
{ int_div_fNext_39$D_OUT[231:174],
|
|
int_div_fNext_39$D_OUT[172:116],
|
|
!int_div_fNext_39$D_OUT[115],
|
|
int_div_fNext_39$D_OUT[115] ?
|
|
{ int_div_fNext_39$D_OUT[114:0], 1'd0 } + b__h13727 :
|
|
{ int_div_fNext_39$D_OUT[114:0], 1'd0 } - b__h13727 } ;
|
|
assign int_div_fNext_40$ENQ = CAN_FIRE_RL_int_div_work_40 ;
|
|
assign int_div_fNext_40$DEQ = CAN_FIRE_RL_int_div_work_41 ;
|
|
assign int_div_fNext_40$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_41
|
|
assign int_div_fNext_41$D_IN =
|
|
{ int_div_fNext_40$D_OUT[231:174],
|
|
int_div_fNext_40$D_OUT[172:116],
|
|
!int_div_fNext_40$D_OUT[115],
|
|
int_div_fNext_40$D_OUT[115] ?
|
|
{ int_div_fNext_40$D_OUT[114:0], 1'd0 } + b__h14051 :
|
|
{ int_div_fNext_40$D_OUT[114:0], 1'd0 } - b__h14051 } ;
|
|
assign int_div_fNext_41$ENQ = CAN_FIRE_RL_int_div_work_41 ;
|
|
assign int_div_fNext_41$DEQ = CAN_FIRE_RL_int_div_work_42 ;
|
|
assign int_div_fNext_41$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_42
|
|
assign int_div_fNext_42$D_IN =
|
|
{ int_div_fNext_41$D_OUT[231:174],
|
|
int_div_fNext_41$D_OUT[172:116],
|
|
!int_div_fNext_41$D_OUT[115],
|
|
int_div_fNext_41$D_OUT[115] ?
|
|
{ int_div_fNext_41$D_OUT[114:0], 1'd0 } + b__h14375 :
|
|
{ int_div_fNext_41$D_OUT[114:0], 1'd0 } - b__h14375 } ;
|
|
assign int_div_fNext_42$ENQ = CAN_FIRE_RL_int_div_work_42 ;
|
|
assign int_div_fNext_42$DEQ = CAN_FIRE_RL_int_div_work_43 ;
|
|
assign int_div_fNext_42$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_43
|
|
assign int_div_fNext_43$D_IN =
|
|
{ int_div_fNext_42$D_OUT[231:174],
|
|
int_div_fNext_42$D_OUT[172:116],
|
|
!int_div_fNext_42$D_OUT[115],
|
|
int_div_fNext_42$D_OUT[115] ?
|
|
{ int_div_fNext_42$D_OUT[114:0], 1'd0 } + b__h14699 :
|
|
{ int_div_fNext_42$D_OUT[114:0], 1'd0 } - b__h14699 } ;
|
|
assign int_div_fNext_43$ENQ = CAN_FIRE_RL_int_div_work_43 ;
|
|
assign int_div_fNext_43$DEQ = CAN_FIRE_RL_int_div_work_44 ;
|
|
assign int_div_fNext_43$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_44
|
|
assign int_div_fNext_44$D_IN =
|
|
{ int_div_fNext_43$D_OUT[231:174],
|
|
int_div_fNext_43$D_OUT[172:116],
|
|
!int_div_fNext_43$D_OUT[115],
|
|
int_div_fNext_43$D_OUT[115] ?
|
|
{ int_div_fNext_43$D_OUT[114:0], 1'd0 } + b__h15023 :
|
|
{ int_div_fNext_43$D_OUT[114:0], 1'd0 } - b__h15023 } ;
|
|
assign int_div_fNext_44$ENQ = CAN_FIRE_RL_int_div_work_44 ;
|
|
assign int_div_fNext_44$DEQ = CAN_FIRE_RL_int_div_work_45 ;
|
|
assign int_div_fNext_44$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_45
|
|
assign int_div_fNext_45$D_IN =
|
|
{ int_div_fNext_44$D_OUT[231:174],
|
|
int_div_fNext_44$D_OUT[172:116],
|
|
!int_div_fNext_44$D_OUT[115],
|
|
int_div_fNext_44$D_OUT[115] ?
|
|
{ int_div_fNext_44$D_OUT[114:0], 1'd0 } + b__h15347 :
|
|
{ int_div_fNext_44$D_OUT[114:0], 1'd0 } - b__h15347 } ;
|
|
assign int_div_fNext_45$ENQ = CAN_FIRE_RL_int_div_work_45 ;
|
|
assign int_div_fNext_45$DEQ = CAN_FIRE_RL_int_div_work_46 ;
|
|
assign int_div_fNext_45$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_46
|
|
assign int_div_fNext_46$D_IN =
|
|
{ int_div_fNext_45$D_OUT[231:174],
|
|
int_div_fNext_45$D_OUT[172:116],
|
|
!int_div_fNext_45$D_OUT[115],
|
|
int_div_fNext_45$D_OUT[115] ?
|
|
{ int_div_fNext_45$D_OUT[114:0], 1'd0 } + b__h15671 :
|
|
{ int_div_fNext_45$D_OUT[114:0], 1'd0 } - b__h15671 } ;
|
|
assign int_div_fNext_46$ENQ = CAN_FIRE_RL_int_div_work_46 ;
|
|
assign int_div_fNext_46$DEQ = CAN_FIRE_RL_int_div_work_47 ;
|
|
assign int_div_fNext_46$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_47
|
|
assign int_div_fNext_47$D_IN =
|
|
{ int_div_fNext_46$D_OUT[231:174],
|
|
int_div_fNext_46$D_OUT[172:116],
|
|
!int_div_fNext_46$D_OUT[115],
|
|
int_div_fNext_46$D_OUT[115] ?
|
|
{ int_div_fNext_46$D_OUT[114:0], 1'd0 } + b__h15995 :
|
|
{ int_div_fNext_46$D_OUT[114:0], 1'd0 } - b__h15995 } ;
|
|
assign int_div_fNext_47$ENQ = CAN_FIRE_RL_int_div_work_47 ;
|
|
assign int_div_fNext_47$DEQ = CAN_FIRE_RL_int_div_work_48 ;
|
|
assign int_div_fNext_47$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_48
|
|
assign int_div_fNext_48$D_IN =
|
|
{ int_div_fNext_47$D_OUT[231:174],
|
|
int_div_fNext_47$D_OUT[172:116],
|
|
!int_div_fNext_47$D_OUT[115],
|
|
int_div_fNext_47$D_OUT[115] ?
|
|
{ int_div_fNext_47$D_OUT[114:0], 1'd0 } + b__h16319 :
|
|
{ int_div_fNext_47$D_OUT[114:0], 1'd0 } - b__h16319 } ;
|
|
assign int_div_fNext_48$ENQ = CAN_FIRE_RL_int_div_work_48 ;
|
|
assign int_div_fNext_48$DEQ = CAN_FIRE_RL_int_div_work_49 ;
|
|
assign int_div_fNext_48$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_49
|
|
assign int_div_fNext_49$D_IN =
|
|
{ int_div_fNext_48$D_OUT[231:174],
|
|
int_div_fNext_48$D_OUT[172:116],
|
|
!int_div_fNext_48$D_OUT[115],
|
|
int_div_fNext_48$D_OUT[115] ?
|
|
{ int_div_fNext_48$D_OUT[114:0], 1'd0 } + b__h16643 :
|
|
{ int_div_fNext_48$D_OUT[114:0], 1'd0 } - b__h16643 } ;
|
|
assign int_div_fNext_49$ENQ = CAN_FIRE_RL_int_div_work_49 ;
|
|
assign int_div_fNext_49$DEQ = CAN_FIRE_RL_int_div_work_50 ;
|
|
assign int_div_fNext_49$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_5
|
|
assign int_div_fNext_5$D_IN =
|
|
{ int_div_fNext_4$D_OUT[231:174],
|
|
int_div_fNext_4$D_OUT[172:116],
|
|
!int_div_fNext_4$D_OUT[115],
|
|
int_div_fNext_4$D_OUT[115] ?
|
|
{ int_div_fNext_4$D_OUT[114:0], 1'd0 } + b__h2387 :
|
|
{ int_div_fNext_4$D_OUT[114:0], 1'd0 } - b__h2387 } ;
|
|
assign int_div_fNext_5$ENQ = CAN_FIRE_RL_int_div_work_5 ;
|
|
assign int_div_fNext_5$DEQ = CAN_FIRE_RL_int_div_work_6 ;
|
|
assign int_div_fNext_5$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_50
|
|
assign int_div_fNext_50$D_IN =
|
|
{ int_div_fNext_49$D_OUT[231:174],
|
|
int_div_fNext_49$D_OUT[172:116],
|
|
!int_div_fNext_49$D_OUT[115],
|
|
int_div_fNext_49$D_OUT[115] ?
|
|
{ int_div_fNext_49$D_OUT[114:0], 1'd0 } + b__h16967 :
|
|
{ int_div_fNext_49$D_OUT[114:0], 1'd0 } - b__h16967 } ;
|
|
assign int_div_fNext_50$ENQ = CAN_FIRE_RL_int_div_work_50 ;
|
|
assign int_div_fNext_50$DEQ = CAN_FIRE_RL_int_div_work_51 ;
|
|
assign int_div_fNext_50$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_51
|
|
assign int_div_fNext_51$D_IN =
|
|
{ int_div_fNext_50$D_OUT[231:174],
|
|
int_div_fNext_50$D_OUT[172:116],
|
|
!int_div_fNext_50$D_OUT[115],
|
|
int_div_fNext_50$D_OUT[115] ?
|
|
{ int_div_fNext_50$D_OUT[114:0], 1'd0 } + b__h17291 :
|
|
{ int_div_fNext_50$D_OUT[114:0], 1'd0 } - b__h17291 } ;
|
|
assign int_div_fNext_51$ENQ = CAN_FIRE_RL_int_div_work_51 ;
|
|
assign int_div_fNext_51$DEQ = CAN_FIRE_RL_int_div_work_52 ;
|
|
assign int_div_fNext_51$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_52
|
|
assign int_div_fNext_52$D_IN =
|
|
{ int_div_fNext_51$D_OUT[231:174],
|
|
int_div_fNext_51$D_OUT[172:116],
|
|
!int_div_fNext_51$D_OUT[115],
|
|
int_div_fNext_51$D_OUT[115] ?
|
|
{ int_div_fNext_51$D_OUT[114:0], 1'd0 } + b__h17615 :
|
|
{ int_div_fNext_51$D_OUT[114:0], 1'd0 } - b__h17615 } ;
|
|
assign int_div_fNext_52$ENQ = CAN_FIRE_RL_int_div_work_52 ;
|
|
assign int_div_fNext_52$DEQ = CAN_FIRE_RL_int_div_work_53 ;
|
|
assign int_div_fNext_52$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_53
|
|
assign int_div_fNext_53$D_IN =
|
|
{ int_div_fNext_52$D_OUT[231:174],
|
|
int_div_fNext_52$D_OUT[172:116],
|
|
!int_div_fNext_52$D_OUT[115],
|
|
int_div_fNext_52$D_OUT[115] ?
|
|
{ int_div_fNext_52$D_OUT[114:0], 1'd0 } + b__h17939 :
|
|
{ int_div_fNext_52$D_OUT[114:0], 1'd0 } - b__h17939 } ;
|
|
assign int_div_fNext_53$ENQ = CAN_FIRE_RL_int_div_work_53 ;
|
|
assign int_div_fNext_53$DEQ = CAN_FIRE_RL_int_div_work_54 ;
|
|
assign int_div_fNext_53$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_54
|
|
assign int_div_fNext_54$D_IN =
|
|
{ int_div_fNext_53$D_OUT[231:174],
|
|
int_div_fNext_53$D_OUT[172:116],
|
|
!int_div_fNext_53$D_OUT[115],
|
|
int_div_fNext_53$D_OUT[115] ?
|
|
{ int_div_fNext_53$D_OUT[114:0], 1'd0 } + b__h18263 :
|
|
{ int_div_fNext_53$D_OUT[114:0], 1'd0 } - b__h18263 } ;
|
|
assign int_div_fNext_54$ENQ = CAN_FIRE_RL_int_div_work_54 ;
|
|
assign int_div_fNext_54$DEQ = CAN_FIRE_RL_int_div_work_55 ;
|
|
assign int_div_fNext_54$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_55
|
|
assign int_div_fNext_55$D_IN =
|
|
{ int_div_fNext_54$D_OUT[231:174],
|
|
int_div_fNext_54$D_OUT[172:116],
|
|
!int_div_fNext_54$D_OUT[115],
|
|
int_div_fNext_54$D_OUT[115] ?
|
|
{ int_div_fNext_54$D_OUT[114:0], 1'd0 } + b__h18587 :
|
|
{ int_div_fNext_54$D_OUT[114:0], 1'd0 } - b__h18587 } ;
|
|
assign int_div_fNext_55$ENQ = CAN_FIRE_RL_int_div_work_55 ;
|
|
assign int_div_fNext_55$DEQ = CAN_FIRE_RL_int_div_work_56 ;
|
|
assign int_div_fNext_55$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_56
|
|
assign int_div_fNext_56$D_IN =
|
|
{ int_div_fNext_55$D_OUT[231:174],
|
|
int_div_fNext_55$D_OUT[172:116],
|
|
!int_div_fNext_55$D_OUT[115],
|
|
int_div_fNext_55$D_OUT[115] ?
|
|
{ int_div_fNext_55$D_OUT[114:0], 1'd0 } + b__h18911 :
|
|
{ int_div_fNext_55$D_OUT[114:0], 1'd0 } - b__h18911 } ;
|
|
assign int_div_fNext_56$ENQ = CAN_FIRE_RL_int_div_work_56 ;
|
|
assign int_div_fNext_56$DEQ = CAN_FIRE_RL_int_div_work_57 ;
|
|
assign int_div_fNext_56$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_57
|
|
assign int_div_fNext_57$D_IN =
|
|
{ int_div_fNext_56$D_OUT[231:174],
|
|
int_div_fNext_56$D_OUT[172:116],
|
|
!int_div_fNext_56$D_OUT[115],
|
|
int_div_fNext_56$D_OUT[115] ?
|
|
{ int_div_fNext_56$D_OUT[114:0], 1'd0 } + b__h19235 :
|
|
{ int_div_fNext_56$D_OUT[114:0], 1'd0 } - b__h19235 } ;
|
|
assign int_div_fNext_57$ENQ = CAN_FIRE_RL_int_div_work_57 ;
|
|
assign int_div_fNext_57$DEQ = CAN_FIRE_RL_int_div_finish ;
|
|
assign int_div_fNext_57$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_6
|
|
assign int_div_fNext_6$D_IN =
|
|
{ int_div_fNext_5$D_OUT[231:174],
|
|
int_div_fNext_5$D_OUT[172:116],
|
|
!int_div_fNext_5$D_OUT[115],
|
|
int_div_fNext_5$D_OUT[115] ?
|
|
{ int_div_fNext_5$D_OUT[114:0], 1'd0 } + b__h2711 :
|
|
{ int_div_fNext_5$D_OUT[114:0], 1'd0 } - b__h2711 } ;
|
|
assign int_div_fNext_6$ENQ = CAN_FIRE_RL_int_div_work_6 ;
|
|
assign int_div_fNext_6$DEQ = CAN_FIRE_RL_int_div_work_7 ;
|
|
assign int_div_fNext_6$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_7
|
|
assign int_div_fNext_7$D_IN =
|
|
{ int_div_fNext_6$D_OUT[231:174],
|
|
int_div_fNext_6$D_OUT[172:116],
|
|
!int_div_fNext_6$D_OUT[115],
|
|
int_div_fNext_6$D_OUT[115] ?
|
|
{ int_div_fNext_6$D_OUT[114:0], 1'd0 } + b__h3035 :
|
|
{ int_div_fNext_6$D_OUT[114:0], 1'd0 } - b__h3035 } ;
|
|
assign int_div_fNext_7$ENQ = CAN_FIRE_RL_int_div_work_7 ;
|
|
assign int_div_fNext_7$DEQ = CAN_FIRE_RL_int_div_work_8 ;
|
|
assign int_div_fNext_7$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_8
|
|
assign int_div_fNext_8$D_IN =
|
|
{ int_div_fNext_7$D_OUT[231:174],
|
|
int_div_fNext_7$D_OUT[172:116],
|
|
!int_div_fNext_7$D_OUT[115],
|
|
int_div_fNext_7$D_OUT[115] ?
|
|
{ int_div_fNext_7$D_OUT[114:0], 1'd0 } + b__h3359 :
|
|
{ int_div_fNext_7$D_OUT[114:0], 1'd0 } - b__h3359 } ;
|
|
assign int_div_fNext_8$ENQ = CAN_FIRE_RL_int_div_work_8 ;
|
|
assign int_div_fNext_8$DEQ = CAN_FIRE_RL_int_div_work_9 ;
|
|
assign int_div_fNext_8$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fNext_9
|
|
assign int_div_fNext_9$D_IN =
|
|
{ int_div_fNext_8$D_OUT[231:174],
|
|
int_div_fNext_8$D_OUT[172:116],
|
|
!int_div_fNext_8$D_OUT[115],
|
|
int_div_fNext_8$D_OUT[115] ?
|
|
{ int_div_fNext_8$D_OUT[114:0], 1'd0 } + b__h3683 :
|
|
{ int_div_fNext_8$D_OUT[114:0], 1'd0 } - b__h3683 } ;
|
|
assign int_div_fNext_9$ENQ = CAN_FIRE_RL_int_div_work_9 ;
|
|
assign int_div_fNext_9$DEQ = CAN_FIRE_RL_int_div_work_10 ;
|
|
assign int_div_fNext_9$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fRequest
|
|
assign int_div_fRequest$D_IN = fpu_fState_S1$D_OUT[181:11] ;
|
|
assign int_div_fRequest$ENQ =
|
|
WILL_FIRE_RL_fpu_s2_stage && !fpu_fState_S1$D_OUT[318] ;
|
|
assign int_div_fRequest$DEQ = CAN_FIRE_RL_int_div_start ;
|
|
assign int_div_fRequest$CLR = 1'b0 ;
|
|
|
|
// submodule int_div_fResponse
|
|
assign int_div_fResponse$D_IN =
|
|
{ IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19[56:0],
|
|
value__h19447[114:58] } ;
|
|
assign int_div_fResponse$ENQ = CAN_FIRE_RL_int_div_finish ;
|
|
assign int_div_fResponse$DEQ =
|
|
WILL_FIRE_RL_fpu_s3_stage && !fpu_fState_S2$D_OUT[147] ;
|
|
assign int_div_fResponse$CLR = 1'b0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7 =
|
|
_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 ?
|
|
_theResult___snd__h59844 :
|
|
_theResult___snd__h59839 ;
|
|
assign IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 =
|
|
sfd__h60417[53] ?
|
|
((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ?
|
|
63'h7FF0000000000000 :
|
|
{ din_inc___2_exp__h61001, sfd__h60417[52:1] }) :
|
|
{ IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821,
|
|
sfd__h60417[51:0] } ;
|
|
assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 =
|
|
(_theResult___fst_exp__h59725 == 11'd0) ?
|
|
12'd3074 :
|
|
{ theResult___fst_exp9725_MINUS_1023__q6[10],
|
|
theResult___fst_exp9725_MINUS_1023__q6 } ;
|
|
assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 =
|
|
(sfdin__h51553[57] ?
|
|
6'd0 :
|
|
(sfdin__h51553[56] ?
|
|
6'd1 :
|
|
(sfdin__h51553[55] ?
|
|
6'd2 :
|
|
(sfdin__h51553[54] ?
|
|
6'd3 :
|
|
(sfdin__h51553[53] ?
|
|
6'd4 :
|
|
(sfdin__h51553[52] ?
|
|
6'd5 :
|
|
(sfdin__h51553[51] ?
|
|
6'd6 :
|
|
(sfdin__h51553[50] ?
|
|
6'd7 :
|
|
(sfdin__h51553[49] ?
|
|
6'd8 :
|
|
(sfdin__h51553[48] ?
|
|
6'd9 :
|
|
(sfdin__h51553[47] ?
|
|
6'd10 :
|
|
(sfdin__h51553[46] ?
|
|
6'd11 :
|
|
(sfdin__h51553[45] ?
|
|
6'd12 :
|
|
(sfdin__h51553[44] ?
|
|
6'd13 :
|
|
(sfdin__h51553[43] ?
|
|
6'd14 :
|
|
(sfdin__h51553[42] ?
|
|
6'd15 :
|
|
(sfdin__h51553[41] ?
|
|
6'd16 :
|
|
(sfdin__h51553[40] ?
|
|
6'd17 :
|
|
(sfdin__h51553[39] ?
|
|
6'd18 :
|
|
(sfdin__h51553[38] ?
|
|
6'd19 :
|
|
(sfdin__h51553[37] ?
|
|
6'd20 :
|
|
(sfdin__h51553[36] ?
|
|
6'd21 :
|
|
(sfdin__h51553[35] ?
|
|
6'd22 :
|
|
(sfdin__h51553[34] ?
|
|
6'd23 :
|
|
(sfdin__h51553[33] ?
|
|
6'd24 :
|
|
(sfdin__h51553[32] ?
|
|
6'd25 :
|
|
(sfdin__h51553[31] ?
|
|
6'd26 :
|
|
(sfdin__h51553[30] ?
|
|
6'd27 :
|
|
(sfdin__h51553[29] ?
|
|
6'd28 :
|
|
(sfdin__h51553[28] ?
|
|
6'd29 :
|
|
(sfdin__h51553[27] ?
|
|
6'd30 :
|
|
(sfdin__h51553[26] ?
|
|
6'd31 :
|
|
(sfdin__h51553[25] ?
|
|
6'd32 :
|
|
(sfdin__h51553[24] ?
|
|
6'd33 :
|
|
(sfdin__h51553[23] ?
|
|
6'd34 :
|
|
(sfdin__h51553[22] ?
|
|
6'd35 :
|
|
(sfdin__h51553[21] ?
|
|
6'd36 :
|
|
(sfdin__h51553[20] ?
|
|
6'd37 :
|
|
(sfdin__h51553[19] ?
|
|
6'd38 :
|
|
(sfdin__h51553[18] ?
|
|
6'd39 :
|
|
(sfdin__h51553[17] ?
|
|
6'd40 :
|
|
(sfdin__h51553[16] ?
|
|
6'd41 :
|
|
(sfdin__h51553[15] ?
|
|
6'd42 :
|
|
(sfdin__h51553[14] ?
|
|
6'd43 :
|
|
(sfdin__h51553[13] ?
|
|
6'd44 :
|
|
(sfdin__h51553[12] ?
|
|
6'd45 :
|
|
(sfdin__h51553[11] ?
|
|
6'd46 :
|
|
(sfdin__h51553[10] ?
|
|
6'd47 :
|
|
(sfdin__h51553[9] ?
|
|
6'd48 :
|
|
(sfdin__h51553[8] ?
|
|
6'd49 :
|
|
(sfdin__h51553[7] ?
|
|
6'd50 :
|
|
(sfdin__h51553[6] ?
|
|
6'd51 :
|
|
(sfdin__h51553[5] ?
|
|
6'd52 :
|
|
(sfdin__h51553[4] ?
|
|
6'd53 :
|
|
(sfdin__h51553[3] ?
|
|
6'd54 :
|
|
(sfdin__h51553[2] ?
|
|
6'd55 :
|
|
(sfdin__h51553[1] ?
|
|
6'd56 :
|
|
(sfdin__h51553[0] ?
|
|
6'd57 :
|
|
6'd58)))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 =
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 -
|
|
12'd3074 ;
|
|
assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1770 =
|
|
IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ?
|
|
IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 :
|
|
{ fpu_fState_S3$D_OUT[129:128],
|
|
(fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
fpu_fState_S3$D_OUT[57:56] != 2'b0 ||
|
|
fpu_fState_S3$D_OUT[127] :
|
|
fpu_fState_S3$D_OUT[127],
|
|
fpu_fState_S3$D_OUT[126],
|
|
(fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
fpu_fState_S3$D_OUT[57:56] != 2'b0 ||
|
|
fpu_fState_S3$D_OUT[125] :
|
|
fpu_fState_S3$D_OUT[125] } ;
|
|
assign IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 =
|
|
(sfdin__h51553[57] &&
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 ==
|
|
12'd1023) ?
|
|
63'h7FEFFFFFFFFFFFFF :
|
|
{ _theResult___fst_exp__h59768, sfdin__h59762[57:6] } ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 =
|
|
(((fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ?
|
|
13'd7170 :
|
|
{ {2{fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3[10]}},
|
|
fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 }) -
|
|
{ 7'd0, b__h21789 }) -
|
|
(((fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ?
|
|
13'd7170 :
|
|
{ {2{fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4[10]}},
|
|
fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 }) -
|
|
{ 7'd0, b__h29207 }) ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 =
|
|
(IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^
|
|
13'h1000) <=
|
|
13'd5120 ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 =
|
|
(IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^
|
|
13'h1000) <
|
|
13'd3020 ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 =
|
|
(IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ^
|
|
13'h1000) <
|
|
13'd3074 ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ?
|
|
!fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 :
|
|
CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0) ?
|
|
11'd2047 :
|
|
((fpu_fOperands_S0$D_OUT[129:119] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h37217) ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254) ?
|
|
52'd0 :
|
|
(IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ?
|
|
_theResult___fst_sfd__h37707 :
|
|
_theResult___fst_sfd__h37218) ;
|
|
assign IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1308 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[54]) ?
|
|
{ fpu_fOperands_S0$D_OUT[66:55], sfd__h36687 } :
|
|
((fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118]) ?
|
|
fpu_fOperands_S0$D_OUT[130:67] :
|
|
((fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54]) ?
|
|
fpu_fOperands_S0$D_OUT[66:3] :
|
|
NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305)) ;
|
|
assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 =
|
|
(fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
fpu_fState_S3$D_OUT[57:56] == 2'b0 &&
|
|
!fpu_fState_S3$D_OUT[194] :
|
|
!fpu_fState_S3$D_OUT[194] ;
|
|
assign IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1765 =
|
|
((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
{ fpu_fState_S3$D_OUT[129:128],
|
|
fpu_fState_S3$D_OUT[57:56] != 2'b0 ||
|
|
fpu_fState_S3$D_OUT[127],
|
|
fpu_fState_S3$D_OUT[126],
|
|
fpu_fState_S3$D_OUT[57:56] != 2'b0 ||
|
|
fpu_fState_S3$D_OUT[125] } :
|
|
fpu_fState_S3$D_OUT[129:125]) |
|
|
{ 2'd0,
|
|
sfdin__h51553[57] &&
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 ==
|
|
12'd1023,
|
|
_theResult___fst_exp__h59771 == 11'd0 && guard__h51381 != 2'd0,
|
|
sfdin__h51553[57] &&
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 ==
|
|
12'd1023 } ;
|
|
assign IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 =
|
|
(fpu_fState_S4$D_OUT[64:54] == 11'd0 &&
|
|
sfd__h60417[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
fpu_fState_S4$D_OUT[64:54] ;
|
|
assign IF_int_div_fNext_57D_OUT_BIT_115_THEN_int_div_ETC__q19 =
|
|
int_div_fNext_57$D_OUT[115] ?
|
|
int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 -
|
|
58'd1 :
|
|
int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 ;
|
|
assign IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8 =
|
|
sfdin__h59762[5] ? 2'd2 : 2'd0 ;
|
|
assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 =
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[65:55] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) ;
|
|
assign NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1305 =
|
|
{ NOT_fpu_fOperands_S0_first__59_BITS_129_TO_119_ETC___d1253 &&
|
|
IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1275,
|
|
IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1286,
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 ?
|
|
52'h8000000000000 :
|
|
IF_fpu_fOperands_S0_first__59_BITS_65_TO_55_69_ETC___d1303 } ;
|
|
assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1334 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 &&
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ;
|
|
assign NOT_fpu_fOperands_S0_first__59_BITS_65_TO_55_6_ETC___d1341 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[129:119] != 11'd0 ||
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0) &&
|
|
(fpu_fOperands_S0$D_OUT[65:55] != 11'd2047 ||
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0) &&
|
|
(!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ||
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208) ;
|
|
assign _0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727 =
|
|
({ 6'd0,
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ^
|
|
12'h800) <=
|
|
(IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ^
|
|
12'h800) ;
|
|
assign _theResult____h50063 =
|
|
(fpu_fState_S2$D_OUT[10:0] < 11'd58) ?
|
|
result__h50108 :
|
|
result__h50258 ;
|
|
assign _theResult___exp__h60910 =
|
|
sfd__h60417[53] ?
|
|
((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h61001) :
|
|
IF_fpu_fState_S4_first__787_BITS_64_TO_54_790__ETC___d1821 ;
|
|
assign _theResult___fst__h49072 =
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352 ?
|
|
value__h49300[10:0] :
|
|
11'd0 ;
|
|
assign _theResult___fst_exp__h59719 = fpu_fState_S3$D_OUT[120:110] - 11'd1 ;
|
|
assign _theResult___fst_exp__h59722 =
|
|
(fpu_fState_S3$D_OUT[57:56] == 2'b0) ?
|
|
_theResult___fst_exp__h59719 :
|
|
11'd2046 ;
|
|
assign _theResult___fst_exp__h59725 =
|
|
(fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
_theResult___fst_exp__h59722 :
|
|
fpu_fState_S3$D_OUT[120:110] ;
|
|
assign _theResult___fst_exp__h59768 =
|
|
sfdin__h51553[57] ?
|
|
_theResult___fst_exp__h59791 :
|
|
_theResult___fst_exp__h59855 ;
|
|
assign _theResult___fst_exp__h59771 =
|
|
(sfdin__h51553[57] &&
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 ==
|
|
12'd1023) ?
|
|
11'd2046 :
|
|
_theResult___fst_exp__h59768 ;
|
|
assign _theResult___fst_exp__h59791 =
|
|
(_theResult___fst_exp__h59725 == 11'd0) ?
|
|
11'd2 :
|
|
_theResult___fst_exp__h59725 + 11'd1 ;
|
|
assign _theResult___fst_exp__h59807 =
|
|
(_theResult___fst_exp__h59725 == 11'd0) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h59725 ;
|
|
assign _theResult___fst_exp__h59846 =
|
|
_theResult___fst_exp__h59725 -
|
|
{ 5'd0,
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 } ;
|
|
assign _theResult___fst_exp__h59852 =
|
|
(!sfdin__h51553[57] && !sfdin__h51553[56] &&
|
|
!sfdin__h51553[55] &&
|
|
!sfdin__h51553[54] &&
|
|
!sfdin__h51553[53] &&
|
|
!sfdin__h51553[52] &&
|
|
!sfdin__h51553[51] &&
|
|
!sfdin__h51553[50] &&
|
|
!sfdin__h51553[49] &&
|
|
!sfdin__h51553[48] &&
|
|
!sfdin__h51553[47] &&
|
|
!sfdin__h51553[46] &&
|
|
!sfdin__h51553[45] &&
|
|
!sfdin__h51553[44] &&
|
|
!sfdin__h51553[43] &&
|
|
!sfdin__h51553[42] &&
|
|
!sfdin__h51553[41] &&
|
|
!sfdin__h51553[40] &&
|
|
!sfdin__h51553[39] &&
|
|
!sfdin__h51553[38] &&
|
|
!sfdin__h51553[37] &&
|
|
!sfdin__h51553[36] &&
|
|
!sfdin__h51553[35] &&
|
|
!sfdin__h51553[34] &&
|
|
!sfdin__h51553[33] &&
|
|
!sfdin__h51553[32] &&
|
|
!sfdin__h51553[31] &&
|
|
!sfdin__h51553[30] &&
|
|
!sfdin__h51553[29] &&
|
|
!sfdin__h51553[28] &&
|
|
!sfdin__h51553[27] &&
|
|
!sfdin__h51553[26] &&
|
|
!sfdin__h51553[25] &&
|
|
!sfdin__h51553[24] &&
|
|
!sfdin__h51553[23] &&
|
|
!sfdin__h51553[22] &&
|
|
!sfdin__h51553[21] &&
|
|
!sfdin__h51553[20] &&
|
|
!sfdin__h51553[19] &&
|
|
!sfdin__h51553[18] &&
|
|
!sfdin__h51553[17] &&
|
|
!sfdin__h51553[16] &&
|
|
!sfdin__h51553[15] &&
|
|
!sfdin__h51553[14] &&
|
|
!sfdin__h51553[13] &&
|
|
!sfdin__h51553[12] &&
|
|
!sfdin__h51553[11] &&
|
|
!sfdin__h51553[10] &&
|
|
!sfdin__h51553[9] &&
|
|
!sfdin__h51553[8] &&
|
|
!sfdin__h51553[7] &&
|
|
!sfdin__h51553[6] &&
|
|
!sfdin__h51553[5] &&
|
|
!sfdin__h51553[4] &&
|
|
!sfdin__h51553[3] &&
|
|
!sfdin__h51553[2] &&
|
|
!sfdin__h51553[1] &&
|
|
!sfdin__h51553[0] ||
|
|
!_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BITS_1_ETC___d1727) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h59846 ;
|
|
assign _theResult___fst_exp__h59855 =
|
|
(!sfdin__h51553[57] && sfdin__h51553[56]) ?
|
|
_theResult___fst_exp__h59807 :
|
|
_theResult___fst_exp__h59852 ;
|
|
assign _theResult___fst_exp__h60991 =
|
|
(fpu_fState_S4$D_OUT[64:54] == 11'd2047) ?
|
|
fpu_fState_S4$D_OUT[64:54] :
|
|
_theResult___fst_exp__h60988 ;
|
|
assign _theResult___fst_sfd__h60992 =
|
|
(fpu_fState_S4$D_OUT[64:54] == 11'd2047) ?
|
|
fpu_fState_S4$D_OUT[53:2] :
|
|
_theResult___fst_sfd__h60989 ;
|
|
assign _theResult___sfd__h60911 =
|
|
sfd__h60417[53] ?
|
|
((fpu_fState_S4$D_OUT[64:54] == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h60417[52:1]) :
|
|
sfd__h60417[51:0] ;
|
|
assign _theResult___snd__h52150 = { fpu_fState_S3$D_OUT[56:0], 1'd0 } ;
|
|
assign _theResult___snd__h59785 = { sfdin__h51553[56:0], 1'd0 } ;
|
|
assign _theResult___snd__h59800 =
|
|
(!sfdin__h51553[57] && sfdin__h51553[56]) ?
|
|
_theResult___snd__h59802 :
|
|
_theResult___snd__h59815 ;
|
|
assign _theResult___snd__h59802 = { sfdin__h51553[55:0], 2'd0 } ;
|
|
assign _theResult___snd__h59815 =
|
|
(!sfdin__h51553[57] && !sfdin__h51553[56] &&
|
|
!sfdin__h51553[55] &&
|
|
!sfdin__h51553[54] &&
|
|
!sfdin__h51553[53] &&
|
|
!sfdin__h51553[52] &&
|
|
!sfdin__h51553[51] &&
|
|
!sfdin__h51553[50] &&
|
|
!sfdin__h51553[49] &&
|
|
!sfdin__h51553[48] &&
|
|
!sfdin__h51553[47] &&
|
|
!sfdin__h51553[46] &&
|
|
!sfdin__h51553[45] &&
|
|
!sfdin__h51553[44] &&
|
|
!sfdin__h51553[43] &&
|
|
!sfdin__h51553[42] &&
|
|
!sfdin__h51553[41] &&
|
|
!sfdin__h51553[40] &&
|
|
!sfdin__h51553[39] &&
|
|
!sfdin__h51553[38] &&
|
|
!sfdin__h51553[37] &&
|
|
!sfdin__h51553[36] &&
|
|
!sfdin__h51553[35] &&
|
|
!sfdin__h51553[34] &&
|
|
!sfdin__h51553[33] &&
|
|
!sfdin__h51553[32] &&
|
|
!sfdin__h51553[31] &&
|
|
!sfdin__h51553[30] &&
|
|
!sfdin__h51553[29] &&
|
|
!sfdin__h51553[28] &&
|
|
!sfdin__h51553[27] &&
|
|
!sfdin__h51553[26] &&
|
|
!sfdin__h51553[25] &&
|
|
!sfdin__h51553[24] &&
|
|
!sfdin__h51553[23] &&
|
|
!sfdin__h51553[22] &&
|
|
!sfdin__h51553[21] &&
|
|
!sfdin__h51553[20] &&
|
|
!sfdin__h51553[19] &&
|
|
!sfdin__h51553[18] &&
|
|
!sfdin__h51553[17] &&
|
|
!sfdin__h51553[16] &&
|
|
!sfdin__h51553[15] &&
|
|
!sfdin__h51553[14] &&
|
|
!sfdin__h51553[13] &&
|
|
!sfdin__h51553[12] &&
|
|
!sfdin__h51553[11] &&
|
|
!sfdin__h51553[10] &&
|
|
!sfdin__h51553[9] &&
|
|
!sfdin__h51553[8] &&
|
|
!sfdin__h51553[7] &&
|
|
!sfdin__h51553[6] &&
|
|
!sfdin__h51553[5] &&
|
|
!sfdin__h51553[4] &&
|
|
!sfdin__h51553[3] &&
|
|
!sfdin__h51553[2] &&
|
|
!sfdin__h51553[1] &&
|
|
!sfdin__h51553[0]) ?
|
|
sfdin__h51553 :
|
|
_theResult___snd__h59821 ;
|
|
assign _theResult___snd__h59821 =
|
|
{ IF_0_CONCAT_IF_IF_fpu_fState_S3_first__430_BIT_ETC__q7[55:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h59839 =
|
|
sfdin__h51553 <<
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1726 ;
|
|
assign _theResult___snd__h59844 =
|
|
sfdin__h51553 <<
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1724 ;
|
|
assign _theResult___snd_fst__h59874 =
|
|
{ IF_sfdin9762_BIT_5_THEN_2_ELSE_0__q8[1],
|
|
{ sfdin__h59762[4:0], 52'd0 } != 57'd0 } ;
|
|
assign _theResult___snd_fst_exp__h49084 =
|
|
(IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ||
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1352) ?
|
|
11'd0 :
|
|
value__h49124[10:0] ;
|
|
assign _theResult___snd_fst_exp__h49087 =
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ?
|
|
_theResult___snd_fst_exp__h49084 :
|
|
11'd2046 ;
|
|
assign _theResult___snd_fst_exp__h49111 =
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 ?
|
|
11'd0 :
|
|
_theResult___snd_fst_exp__h49087 ;
|
|
assign _theResult___snd_fst_sfd__h49112 =
|
|
(fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 ||
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206) ?
|
|
52'd0 :
|
|
52'hFFFFFFFFFFFFF ;
|
|
assign _theResult___snd_snd_snd__h51398 =
|
|
(fpu_fState_S3$D_OUT[57:56] == 2'b0) ?
|
|
_theResult___snd__h52150 :
|
|
fpu_fState_S3$D_OUT[57:0] ;
|
|
assign b__h10163 = { int_div_fNext_28$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h10487 = { int_div_fNext_29$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h10811 = { int_div_fNext_30$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h1091 = { int_div_fNext_0$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h11135 = { int_div_fNext_31$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h11459 = { int_div_fNext_32$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h11783 = { int_div_fNext_33$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h12107 = { int_div_fNext_34$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h12431 = { int_div_fNext_35$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h12755 = { int_div_fNext_36$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h13079 = { int_div_fNext_37$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h13403 = { int_div_fNext_38$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h13727 = { int_div_fNext_39$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h14051 = { int_div_fNext_40$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h1415 = { int_div_fNext_1$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h14375 = { int_div_fNext_41$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h14699 = { int_div_fNext_42$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h15023 = { int_div_fNext_43$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h15347 = { int_div_fNext_44$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h15671 = { int_div_fNext_45$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h15995 = { int_div_fNext_46$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h16319 = { int_div_fNext_47$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h16643 = { int_div_fNext_48$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h16967 = { int_div_fNext_49$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h17291 = { int_div_fNext_50$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h1739 = { int_div_fNext_2$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h17615 = { int_div_fNext_51$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h17939 = { int_div_fNext_52$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h18263 = { int_div_fNext_53$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h18587 = { int_div_fNext_54$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h18911 = { int_div_fNext_55$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h19235 = { int_div_fNext_56$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h19482 = { int_div_fNext_57$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h2063 = { int_div_fNext_3$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h21789 =
|
|
(fpu_fOperands_S0$D_OUT[129:119] == 11'd0) ?
|
|
(fpu_fOperands_S0$D_OUT[118] ?
|
|
6'd1 :
|
|
(fpu_fOperands_S0$D_OUT[117] ?
|
|
6'd2 :
|
|
(fpu_fOperands_S0$D_OUT[116] ?
|
|
6'd3 :
|
|
(fpu_fOperands_S0$D_OUT[115] ?
|
|
6'd4 :
|
|
(fpu_fOperands_S0$D_OUT[114] ?
|
|
6'd5 :
|
|
(fpu_fOperands_S0$D_OUT[113] ?
|
|
6'd6 :
|
|
(fpu_fOperands_S0$D_OUT[112] ?
|
|
6'd7 :
|
|
(fpu_fOperands_S0$D_OUT[111] ?
|
|
6'd8 :
|
|
(fpu_fOperands_S0$D_OUT[110] ?
|
|
6'd9 :
|
|
(fpu_fOperands_S0$D_OUT[109] ?
|
|
6'd10 :
|
|
(fpu_fOperands_S0$D_OUT[108] ?
|
|
6'd11 :
|
|
(fpu_fOperands_S0$D_OUT[107] ?
|
|
6'd12 :
|
|
(fpu_fOperands_S0$D_OUT[106] ?
|
|
6'd13 :
|
|
(fpu_fOperands_S0$D_OUT[105] ?
|
|
6'd14 :
|
|
(fpu_fOperands_S0$D_OUT[104] ?
|
|
6'd15 :
|
|
(fpu_fOperands_S0$D_OUT[103] ?
|
|
6'd16 :
|
|
(fpu_fOperands_S0$D_OUT[102] ?
|
|
6'd17 :
|
|
(fpu_fOperands_S0$D_OUT[101] ?
|
|
6'd18 :
|
|
(fpu_fOperands_S0$D_OUT[100] ?
|
|
6'd19 :
|
|
(fpu_fOperands_S0$D_OUT[99] ?
|
|
6'd20 :
|
|
(fpu_fOperands_S0$D_OUT[98] ?
|
|
6'd21 :
|
|
(fpu_fOperands_S0$D_OUT[97] ?
|
|
6'd22 :
|
|
(fpu_fOperands_S0$D_OUT[96] ?
|
|
6'd23 :
|
|
(fpu_fOperands_S0$D_OUT[95] ?
|
|
6'd24 :
|
|
(fpu_fOperands_S0$D_OUT[94] ?
|
|
6'd25 :
|
|
(fpu_fOperands_S0$D_OUT[93] ?
|
|
6'd26 :
|
|
(fpu_fOperands_S0$D_OUT[92] ?
|
|
6'd27 :
|
|
(fpu_fOperands_S0$D_OUT[91] ?
|
|
6'd28 :
|
|
(fpu_fOperands_S0$D_OUT[90] ?
|
|
6'd29 :
|
|
(fpu_fOperands_S0$D_OUT[89] ?
|
|
6'd30 :
|
|
(fpu_fOperands_S0$D_OUT[88] ?
|
|
6'd31 :
|
|
(fpu_fOperands_S0$D_OUT[87] ?
|
|
6'd32 :
|
|
(fpu_fOperands_S0$D_OUT[86] ?
|
|
6'd33 :
|
|
(fpu_fOperands_S0$D_OUT[85] ?
|
|
6'd34 :
|
|
(fpu_fOperands_S0$D_OUT[84] ?
|
|
6'd35 :
|
|
(fpu_fOperands_S0$D_OUT[83] ?
|
|
6'd36 :
|
|
(fpu_fOperands_S0$D_OUT[82] ?
|
|
6'd37 :
|
|
(fpu_fOperands_S0$D_OUT[81] ?
|
|
6'd38 :
|
|
(fpu_fOperands_S0$D_OUT[80] ?
|
|
6'd39 :
|
|
(fpu_fOperands_S0$D_OUT[79] ?
|
|
6'd40 :
|
|
(fpu_fOperands_S0$D_OUT[78] ?
|
|
6'd41 :
|
|
(fpu_fOperands_S0$D_OUT[77] ?
|
|
6'd42 :
|
|
(fpu_fOperands_S0$D_OUT[76] ?
|
|
6'd43 :
|
|
(fpu_fOperands_S0$D_OUT[75] ?
|
|
6'd44 :
|
|
(fpu_fOperands_S0$D_OUT[74] ?
|
|
6'd45 :
|
|
(fpu_fOperands_S0$D_OUT[73] ?
|
|
6'd46 :
|
|
(fpu_fOperands_S0$D_OUT[72] ?
|
|
6'd47 :
|
|
(fpu_fOperands_S0$D_OUT[71] ?
|
|
6'd48 :
|
|
(fpu_fOperands_S0$D_OUT[70] ?
|
|
6'd49 :
|
|
(fpu_fOperands_S0$D_OUT[69] ?
|
|
6'd50 :
|
|
(fpu_fOperands_S0$D_OUT[68] ?
|
|
6'd51 :
|
|
(fpu_fOperands_S0$D_OUT[67] ?
|
|
6'd52 :
|
|
6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) :
|
|
6'd0 ;
|
|
assign b__h2387 = { int_div_fNext_4$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h2711 = { int_div_fNext_5$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h29207 =
|
|
(fpu_fOperands_S0$D_OUT[65:55] == 11'd0) ?
|
|
(fpu_fOperands_S0$D_OUT[54] ?
|
|
6'd1 :
|
|
(fpu_fOperands_S0$D_OUT[53] ?
|
|
6'd2 :
|
|
(fpu_fOperands_S0$D_OUT[52] ?
|
|
6'd3 :
|
|
(fpu_fOperands_S0$D_OUT[51] ?
|
|
6'd4 :
|
|
(fpu_fOperands_S0$D_OUT[50] ?
|
|
6'd5 :
|
|
(fpu_fOperands_S0$D_OUT[49] ?
|
|
6'd6 :
|
|
(fpu_fOperands_S0$D_OUT[48] ?
|
|
6'd7 :
|
|
(fpu_fOperands_S0$D_OUT[47] ?
|
|
6'd8 :
|
|
(fpu_fOperands_S0$D_OUT[46] ?
|
|
6'd9 :
|
|
(fpu_fOperands_S0$D_OUT[45] ?
|
|
6'd10 :
|
|
(fpu_fOperands_S0$D_OUT[44] ?
|
|
6'd11 :
|
|
(fpu_fOperands_S0$D_OUT[43] ?
|
|
6'd12 :
|
|
(fpu_fOperands_S0$D_OUT[42] ?
|
|
6'd13 :
|
|
(fpu_fOperands_S0$D_OUT[41] ?
|
|
6'd14 :
|
|
(fpu_fOperands_S0$D_OUT[40] ?
|
|
6'd15 :
|
|
(fpu_fOperands_S0$D_OUT[39] ?
|
|
6'd16 :
|
|
(fpu_fOperands_S0$D_OUT[38] ?
|
|
6'd17 :
|
|
(fpu_fOperands_S0$D_OUT[37] ?
|
|
6'd18 :
|
|
(fpu_fOperands_S0$D_OUT[36] ?
|
|
6'd19 :
|
|
(fpu_fOperands_S0$D_OUT[35] ?
|
|
6'd20 :
|
|
(fpu_fOperands_S0$D_OUT[34] ?
|
|
6'd21 :
|
|
(fpu_fOperands_S0$D_OUT[33] ?
|
|
6'd22 :
|
|
(fpu_fOperands_S0$D_OUT[32] ?
|
|
6'd23 :
|
|
(fpu_fOperands_S0$D_OUT[31] ?
|
|
6'd24 :
|
|
(fpu_fOperands_S0$D_OUT[30] ?
|
|
6'd25 :
|
|
(fpu_fOperands_S0$D_OUT[29] ?
|
|
6'd26 :
|
|
(fpu_fOperands_S0$D_OUT[28] ?
|
|
6'd27 :
|
|
(fpu_fOperands_S0$D_OUT[27] ?
|
|
6'd28 :
|
|
(fpu_fOperands_S0$D_OUT[26] ?
|
|
6'd29 :
|
|
(fpu_fOperands_S0$D_OUT[25] ?
|
|
6'd30 :
|
|
(fpu_fOperands_S0$D_OUT[24] ?
|
|
6'd31 :
|
|
(fpu_fOperands_S0$D_OUT[23] ?
|
|
6'd32 :
|
|
(fpu_fOperands_S0$D_OUT[22] ?
|
|
6'd33 :
|
|
(fpu_fOperands_S0$D_OUT[21] ?
|
|
6'd34 :
|
|
(fpu_fOperands_S0$D_OUT[20] ?
|
|
6'd35 :
|
|
(fpu_fOperands_S0$D_OUT[19] ?
|
|
6'd36 :
|
|
(fpu_fOperands_S0$D_OUT[18] ?
|
|
6'd37 :
|
|
(fpu_fOperands_S0$D_OUT[17] ?
|
|
6'd38 :
|
|
(fpu_fOperands_S0$D_OUT[16] ?
|
|
6'd39 :
|
|
(fpu_fOperands_S0$D_OUT[15] ?
|
|
6'd40 :
|
|
(fpu_fOperands_S0$D_OUT[14] ?
|
|
6'd41 :
|
|
(fpu_fOperands_S0$D_OUT[13] ?
|
|
6'd42 :
|
|
(fpu_fOperands_S0$D_OUT[12] ?
|
|
6'd43 :
|
|
(fpu_fOperands_S0$D_OUT[11] ?
|
|
6'd44 :
|
|
(fpu_fOperands_S0$D_OUT[10] ?
|
|
6'd45 :
|
|
(fpu_fOperands_S0$D_OUT[9] ?
|
|
6'd46 :
|
|
(fpu_fOperands_S0$D_OUT[8] ?
|
|
6'd47 :
|
|
(fpu_fOperands_S0$D_OUT[7] ?
|
|
6'd48 :
|
|
(fpu_fOperands_S0$D_OUT[6] ?
|
|
6'd49 :
|
|
(fpu_fOperands_S0$D_OUT[5] ?
|
|
6'd50 :
|
|
(fpu_fOperands_S0$D_OUT[4] ?
|
|
6'd51 :
|
|
(fpu_fOperands_S0$D_OUT[3] ?
|
|
6'd52 :
|
|
6'd53)))))))))))))))))))))))))))))))))))))))))))))))))))) :
|
|
6'd0 ;
|
|
assign b__h3035 = { int_div_fNext_6$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h3359 = { int_div_fNext_7$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h3683 = { int_div_fNext_8$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h378 = { 1'd0, int_div_fRequest$D_OUT[56:0] } ;
|
|
assign b__h4007 = { int_div_fNext_9$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h4331 = { int_div_fNext_10$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h4655 = { int_div_fNext_11$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h4979 = { int_div_fNext_12$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h5303 = { int_div_fNext_13$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h5627 = { int_div_fNext_14$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h5951 = { int_div_fNext_15$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h6275 = { int_div_fNext_16$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h6599 = { int_div_fNext_17$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h6923 = { int_div_fNext_18$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h7247 = { int_div_fNext_19$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h7571 = { int_div_fNext_20$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h767 = { int_div_fFirst$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h7895 = { int_div_fNext_21$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h8219 = { int_div_fNext_22$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h8543 = { int_div_fNext_23$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h8867 = { int_div_fNext_24$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h9191 = { int_div_fNext_25$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h9515 = { int_div_fNext_26$D_OUT[231:174], 58'd0 } ;
|
|
assign b__h9839 = { int_div_fNext_27$D_OUT[231:174], 58'd0 } ;
|
|
assign din_inc___2_exp__h61001 = fpu_fState_S4$D_OUT[64:54] + 11'd1 ;
|
|
assign fpu_fOperands_S0D_OUT_BITS_129_TO_119_MINUS_1023__q3 =
|
|
fpu_fOperands_S0$D_OUT[129:119] - 11'd1023 ;
|
|
assign fpu_fOperands_S0D_OUT_BITS_65_TO_55_MINUS_1023__q4 =
|
|
fpu_fOperands_S0$D_OUT[65:55] - 11'd1023 ;
|
|
assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 =
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[118] ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[54] ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118] ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54] ||
|
|
fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 ;
|
|
assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 =
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ;
|
|
assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1289 =
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 &&
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 &&
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ;
|
|
assign fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1351 =
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[118] ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] != 52'd0 &&
|
|
!fpu_fOperands_S0$D_OUT[54] ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118] ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54] ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1254 ;
|
|
assign fpu_fOperands_S0_first__59_BITS_65_TO_55_69_EQ_ETC___d1212 =
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[129:119] == 11'd0 &&
|
|
fpu_fOperands_S0$D_OUT[118:67] == 52'd0 ||
|
|
fpu_fOperands_S0$D_OUT[65:55] == 11'd2047 &&
|
|
fpu_fOperands_S0$D_OUT[54:3] == 52'd0 ||
|
|
!IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1206 ||
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1208 ;
|
|
assign fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 =
|
|
fpu_fOperands_S0$D_OUT[130] == fpu_fOperands_S0$D_OUT[66] ;
|
|
assign fpu_fState_S3_first__430_BIT_121_451_CONCAT_IF_ETC___d1780 =
|
|
{ fpu_fState_S3$D_OUT[121],
|
|
IF_fpu_fState_S3_first__430_BITS_120_TO_110_43_ETC___d1441 ?
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1773 :
|
|
((fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
((fpu_fState_S3$D_OUT[57:56] == 2'b0) ?
|
|
{ _theResult___fst_exp__h59719,
|
|
fpu_fState_S3$D_OUT[109:58] } :
|
|
63'h7FEFFFFFFFFFFFFF) :
|
|
fpu_fState_S3$D_OUT[120:58]) } ;
|
|
assign guard__h51381 = x__h60140 ;
|
|
assign int_div_fNext_57_first__40_BITS_173_TO_116_42__ETC___d945 =
|
|
int_div_fNext_57$D_OUT[173:116] +
|
|
-(~int_div_fNext_57$D_OUT[173:116]) ;
|
|
assign out_exp__h60913 =
|
|
fpu_fState_S4$D_OUT[2] ?
|
|
_theResult___exp__h60910 :
|
|
fpu_fState_S4$D_OUT[64:54] ;
|
|
assign out_sfd__h60914 =
|
|
fpu_fState_S4$D_OUT[2] ?
|
|
_theResult___sfd__h60911 :
|
|
fpu_fState_S4$D_OUT[53:2] ;
|
|
assign result__h50077 = { _theResult____h50063[57:1], 1'd1 } ;
|
|
assign result__h50108 =
|
|
{ 1'd0,
|
|
value__h50121[56:1],
|
|
value__h50121[0] | sfdlsb__h50103 } ;
|
|
assign result__h50258 =
|
|
(int_div_fResponse$D_OUT[113:57] == 57'd0) ? 58'd0 : 58'd1 ;
|
|
assign sfdA__h19785 =
|
|
{ fpu_fOperands_S0$D_OUT[129:119] != 11'd0,
|
|
fpu_fOperands_S0$D_OUT[118:67] } ;
|
|
assign sfdA__h19789 = sfdA__h19785 << b__h21789 ;
|
|
assign sfdB__h19786 =
|
|
{ fpu_fOperands_S0$D_OUT[65:55] != 11'd0,
|
|
fpu_fOperands_S0$D_OUT[54:3] } ;
|
|
assign sfdB__h19791 = sfdB__h19786 << b__h29207 ;
|
|
assign sfd__h36684 = { 1'd1, fpu_fOperands_S0$D_OUT[117:67] } ;
|
|
assign sfd__h36687 = { 1'd1, fpu_fOperands_S0$D_OUT[53:3] } ;
|
|
assign sfd__h60417 =
|
|
{ 1'b0,
|
|
fpu_fState_S4$D_OUT[64:54] != 11'd0,
|
|
fpu_fState_S4$D_OUT[53:2] } +
|
|
54'd1 ;
|
|
assign sfdin__h51553 =
|
|
(fpu_fState_S3$D_OUT[120:110] == 11'd2047) ?
|
|
_theResult___snd_snd_snd__h51398 :
|
|
fpu_fState_S3$D_OUT[57:0] ;
|
|
assign sfdin__h59762 =
|
|
sfdin__h51553[57] ?
|
|
_theResult___snd__h59785 :
|
|
_theResult___snd__h59800 ;
|
|
assign sfdlsb__h50103 = x__h50197 != 58'd0 ;
|
|
assign theResult___fst_exp9725_MINUS_1023__q6 =
|
|
_theResult___fst_exp__h59725 - 11'd1023 ;
|
|
assign value__h19447 =
|
|
int_div_fNext_57$D_OUT[115] ?
|
|
int_div_fNext_57$D_OUT[115:0] + b__h19482 :
|
|
int_div_fNext_57$D_OUT[115:0] ;
|
|
assign value__h49124 =
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 +
|
|
13'd1023 ;
|
|
assign value__h49179 = { 1'b0, sfdA__h19789 } ;
|
|
assign value__h49300 =
|
|
13'd7170 -
|
|
IF_fpu_fOperands_S0_first__59_BITS_129_TO_119__ETC___d1205 ;
|
|
assign value__h50121 =
|
|
int_div_fResponse$D_OUT[113:57] >> fpu_fState_S2$D_OUT[10:0] ;
|
|
assign x__h49176 = { value__h49179, 60'd0 } ;
|
|
assign x__h49237 = { sfdB__h19791, 4'b0 } ;
|
|
assign x__h49291 =
|
|
fpu_fOperands_S0_first__59_BITS_129_TO_119_60__ETC___d1216 ?
|
|
11'd0 :
|
|
_theResult___fst__h49072 ;
|
|
assign x__h50197 = { 1'd0, int_div_fResponse$D_OUT[113:57] } << x__h50204 ;
|
|
assign x__h50204 = 11'd58 - fpu_fState_S2$D_OUT[10:0] ;
|
|
assign x__h50487 =
|
|
(int_div_fResponse$D_OUT[56:0] == 57'd0) ?
|
|
_theResult____h50063 :
|
|
result__h50077 ;
|
|
assign x__h60140 =
|
|
(sfdin__h51553[57] &&
|
|
IF_IF_fpu_fState_S3_first__430_BITS_120_TO_110_ETC___d1487 ==
|
|
12'd1023) ?
|
|
2'd3 :
|
|
_theResult___snd_fst__h59874 ;
|
|
always@(fpu_fState_S4$D_OUT or out_sfd__h60914 or _theResult___sfd__h60911)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 =
|
|
fpu_fState_S4$D_OUT[53:2];
|
|
2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 =
|
|
out_sfd__h60914;
|
|
2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 =
|
|
_theResult___sfd__h60911;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or _theResult___sfd__h60911)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 =
|
|
fpu_fState_S4$D_OUT[53:2];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 =
|
|
_theResult___sfd__h60911;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2 or
|
|
_theResult___sfd__h60911)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd0:
|
|
_theResult___fst_sfd__h60989 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q1;
|
|
3'd1:
|
|
_theResult___fst_sfd__h60989 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q2;
|
|
3'd2:
|
|
_theResult___fst_sfd__h60989 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ?
|
|
fpu_fState_S4$D_OUT[53:2] :
|
|
_theResult___sfd__h60911;
|
|
3'd3:
|
|
_theResult___fst_sfd__h60989 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[53:2] :
|
|
(fpu_fState_S4$D_OUT[65] ?
|
|
_theResult___sfd__h60911 :
|
|
fpu_fState_S4$D_OUT[53:2]);
|
|
3'd4: _theResult___fst_sfd__h60989 = fpu_fState_S4$D_OUT[53:2];
|
|
default: _theResult___fst_sfd__h60989 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fOperands_S0$D_OUT or
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258)
|
|
begin
|
|
case (fpu_fOperands_S0$D_OUT[2:0])
|
|
3'd0, 3'd1: _theResult___fst_exp__h37217 = 11'd2047;
|
|
3'd2:
|
|
_theResult___fst_exp__h37217 =
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ?
|
|
11'd2047 :
|
|
11'd2046;
|
|
3'd3:
|
|
_theResult___fst_exp__h37217 =
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ?
|
|
11'd2046 :
|
|
11'd2047;
|
|
3'd4: _theResult___fst_exp__h37217 = 11'd2046;
|
|
default: _theResult___fst_exp__h37217 = 11'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fOperands_S0$D_OUT or
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258)
|
|
begin
|
|
case (fpu_fOperands_S0$D_OUT[2:0])
|
|
3'd0, 3'd1: _theResult___fst_sfd__h37218 = 52'd0;
|
|
3'd2:
|
|
_theResult___fst_sfd__h37218 =
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ?
|
|
52'd0 :
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd3:
|
|
_theResult___fst_sfd__h37218 =
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ?
|
|
52'hFFFFFFFFFFFFF :
|
|
52'd0;
|
|
3'd4: _theResult___fst_sfd__h37218 = 52'hFFFFFFFFFFFFF;
|
|
default: _theResult___fst_sfd__h37218 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fOperands_S0$D_OUT or
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258)
|
|
begin
|
|
case (fpu_fOperands_S0$D_OUT[2:0])
|
|
3'd0: _theResult___fst_sfd__h37707 = 52'd0;
|
|
3'd1: _theResult___fst_sfd__h37707 = 52'd1;
|
|
3'd2:
|
|
_theResult___fst_sfd__h37707 =
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ?
|
|
52'd1 :
|
|
52'd0;
|
|
3'd3:
|
|
_theResult___fst_sfd__h37707 =
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258 ?
|
|
52'd0 :
|
|
52'd1;
|
|
default: _theResult___fst_sfd__h37707 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fOperands_S0$D_OUT or
|
|
fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258)
|
|
begin
|
|
case (fpu_fOperands_S0$D_OUT[2:0])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 =
|
|
!fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258;
|
|
default: CASE_fpu_fOperands_S0D_OUT_BITS_2_TO_0_0_NOT__ETC__q5 =
|
|
fpu_fOperands_S0$D_OUT[2:0] == 3'd4 &&
|
|
!fpu_fOperands_S0_first__59_BIT_130_256_EQ_fpu__ETC___d1258;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or out_exp__h60913 or _theResult___exp__h60910)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 =
|
|
fpu_fState_S4$D_OUT[64:54];
|
|
2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 =
|
|
out_exp__h60913;
|
|
2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 =
|
|
_theResult___exp__h60910;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or _theResult___exp__h60910)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 =
|
|
fpu_fState_S4$D_OUT[64:54];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 =
|
|
_theResult___exp__h60910;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10 or
|
|
_theResult___exp__h60910)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd0:
|
|
_theResult___fst_exp__h60988 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q9;
|
|
3'd1:
|
|
_theResult___fst_exp__h60988 =
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q10;
|
|
3'd2:
|
|
_theResult___fst_exp__h60988 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ?
|
|
fpu_fState_S4$D_OUT[64:54] :
|
|
_theResult___exp__h60910;
|
|
3'd3:
|
|
_theResult___fst_exp__h60988 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[64:54] :
|
|
(fpu_fState_S4$D_OUT[65] ?
|
|
_theResult___exp__h60910 :
|
|
fpu_fState_S4$D_OUT[64:54]);
|
|
3'd4: _theResult___fst_exp__h60988 = fpu_fState_S4$D_OUT[64:54];
|
|
default: _theResult___fst_exp__h60988 = 11'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd2, 3'd3:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 =
|
|
fpu_fState_S4$D_OUT[65];
|
|
default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 =
|
|
fpu_fState_S4$D_OUT[68:66] == 3'd4 &&
|
|
fpu_fState_S4$D_OUT[65];
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd2:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0 || fpu_fState_S4$D_OUT[65]) ?
|
|
fpu_fState_S4$D_OUT[64:2] :
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824;
|
|
3'd3:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[64:2] :
|
|
(fpu_fState_S4$D_OUT[65] ?
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 :
|
|
fpu_fState_S4$D_OUT[64:2]);
|
|
3'd4:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 =
|
|
fpu_fState_S4$D_OUT[64:2];
|
|
default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 = 63'd0;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 =
|
|
fpu_fState_S4$D_OUT[65];
|
|
2'd3:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 =
|
|
fpu_fState_S4$D_OUT[1:0] == 2'b11 && fpu_fState_S4$D_OUT[65];
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'b0, 2'b01:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 =
|
|
fpu_fState_S4$D_OUT[64:2];
|
|
2'b10:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 =
|
|
fpu_fState_S4$D_OUT[2] ?
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824 :
|
|
fpu_fState_S4$D_OUT[64:2];
|
|
2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 =
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[1:0])
|
|
2'd0: CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 = 63'd0;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 =
|
|
IF_0b0_CONCAT_NOT_fpu_fState_S4_first__787_BIT_ETC___d1824;
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S4$D_OUT or
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 or
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15)
|
|
begin
|
|
case (fpu_fState_S4$D_OUT[68:66])
|
|
3'd0:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 =
|
|
{ CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q13,
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0b0_fpu_f_ETC__q14 };
|
|
3'd1:
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 =
|
|
(fpu_fState_S4$D_OUT[1:0] == 2'b0) ?
|
|
fpu_fState_S4$D_OUT[65:2] :
|
|
{ (fpu_fState_S4$D_OUT[1:0] == 2'b01 ||
|
|
fpu_fState_S4$D_OUT[1:0] == 2'b10 ||
|
|
fpu_fState_S4$D_OUT[1:0] == 2'b11) &&
|
|
fpu_fState_S4$D_OUT[65],
|
|
CASE_fpu_fState_S4D_OUT_BITS_1_TO_0_0_0_0b1_I_ETC__q15 };
|
|
default: CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_0_CASE__ETC__q16 =
|
|
{ CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_fpu_f_ETC__q11,
|
|
CASE_fpu_fState_S4D_OUT_BITS_68_TO_66_2_IF_fp_ETC__q12 };
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S3$D_OUT)
|
|
begin
|
|
case (fpu_fState_S3$D_OUT[124:122])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 =
|
|
fpu_fState_S3$D_OUT[121];
|
|
default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_fpu_ETC__q17 =
|
|
fpu_fState_S3$D_OUT[124:122] == 3'd4 &&
|
|
fpu_fState_S3$D_OUT[121];
|
|
endcase
|
|
end
|
|
always@(fpu_fState_S3$D_OUT)
|
|
begin
|
|
case (fpu_fState_S3$D_OUT[124:122])
|
|
3'd0, 3'd1:
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 =
|
|
63'h7FF0000000000000;
|
|
3'd2:
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 =
|
|
fpu_fState_S3$D_OUT[121] ?
|
|
63'h7FEFFFFFFFFFFFFF :
|
|
63'h7FF0000000000000;
|
|
3'd3:
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 =
|
|
fpu_fState_S3$D_OUT[121] ?
|
|
63'h7FF0000000000000 :
|
|
63'h7FEFFFFFFFFFFFFF;
|
|
3'd4:
|
|
CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 =
|
|
63'h7FEFFFFFFFFFFFFF;
|
|
default: CASE_fpu_fState_S3D_OUT_BITS_124_TO_122_0_921_ETC__q18 = 63'd0;
|
|
endcase
|
|
end
|
|
endmodule // mkDoubleDiv
|
|
|