2140 lines
76 KiB
Verilog
2140 lines
76 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Mon Jul 13 18:28:48 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_write_enq O 1 const
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// read_deq O 370
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// RDY_read_deq O 1 const
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// RDY_setLSQAtCommitNotified O 1 const
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// RDY_setExecuted_deqLSQ O 1 const
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// RDY_setExecuted_doFinishAlu_0_set O 1 const
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// RDY_setExecuted_doFinishAlu_1_set O 1 const
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// RDY_setExecuted_doFinishFpuMulDiv_0_set O 1 const
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// RDY_setExecuted_doFinishMem O 1 const
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// getOrigPC O 129 reg
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// RDY_getOrigPC O 1 const
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// getOrigPredPC O 129
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// RDY_getOrigPredPC O 1 const
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// getOrig_Inst O 32 reg
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// RDY_getOrig_Inst O 1 const
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// dependsOn_wrongSpec O 1 reg
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// RDY_dependsOn_wrongSpec O 1 const
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// RDY_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// write_enq_x I 370
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// setExecuted_deqLSQ_cause I 14
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// setExecuted_deqLSQ_ld_killed I 3
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// setExecuted_doFinishAlu_0_set_csrData I 131
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// setExecuted_doFinishAlu_0_set_cause I 12
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// setExecuted_doFinishAlu_1_set_csrData I 131
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// setExecuted_doFinishAlu_1_set_cause I 12
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// setExecuted_doFinishFpuMulDiv_0_set_fflags I 5
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// setExecuted_doFinishFpuMulDiv_0_set_cause I 6
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// setExecuted_doFinishMem_vaddr I 129
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// setExecuted_doFinishMem_store_data I 64 unused
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// setExecuted_doFinishMem_store_data_BE I 8 unused
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// setExecuted_doFinishMem_access_at_commit I 1
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// setExecuted_doFinishMem_non_mmio_st_done I 1
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// dependsOn_wrongSpec_tag I 4
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// correctSpeculation_mask I 12
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// EN_write_enq I 1
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// EN_setLSQAtCommitNotified I 1
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// EN_setExecuted_deqLSQ I 1
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// EN_setExecuted_doFinishAlu_0_set I 1
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// EN_setExecuted_doFinishAlu_1_set I 1
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// EN_setExecuted_doFinishFpuMulDiv_0_set I 1
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// EN_setExecuted_doFinishMem I 1
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// EN_correctSpeculation I 1
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//
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// Combinational paths from inputs to outputs:
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// dependsOn_wrongSpec_tag -> dependsOn_wrongSpec
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkRobRowSynth(CLK,
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RST_N,
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write_enq_x,
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EN_write_enq,
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RDY_write_enq,
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read_deq,
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RDY_read_deq,
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EN_setLSQAtCommitNotified,
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RDY_setLSQAtCommitNotified,
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setExecuted_deqLSQ_cause,
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setExecuted_deqLSQ_ld_killed,
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EN_setExecuted_deqLSQ,
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RDY_setExecuted_deqLSQ,
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setExecuted_doFinishAlu_0_set_csrData,
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setExecuted_doFinishAlu_0_set_cause,
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EN_setExecuted_doFinishAlu_0_set,
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RDY_setExecuted_doFinishAlu_0_set,
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setExecuted_doFinishAlu_1_set_csrData,
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setExecuted_doFinishAlu_1_set_cause,
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EN_setExecuted_doFinishAlu_1_set,
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RDY_setExecuted_doFinishAlu_1_set,
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setExecuted_doFinishFpuMulDiv_0_set_fflags,
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setExecuted_doFinishFpuMulDiv_0_set_cause,
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EN_setExecuted_doFinishFpuMulDiv_0_set,
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RDY_setExecuted_doFinishFpuMulDiv_0_set,
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setExecuted_doFinishMem_vaddr,
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setExecuted_doFinishMem_store_data,
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setExecuted_doFinishMem_store_data_BE,
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setExecuted_doFinishMem_access_at_commit,
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setExecuted_doFinishMem_non_mmio_st_done,
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EN_setExecuted_doFinishMem,
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RDY_setExecuted_doFinishMem,
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getOrigPC,
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RDY_getOrigPC,
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getOrigPredPC,
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RDY_getOrigPredPC,
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getOrig_Inst,
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RDY_getOrig_Inst,
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dependsOn_wrongSpec_tag,
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dependsOn_wrongSpec,
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RDY_dependsOn_wrongSpec,
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correctSpeculation_mask,
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EN_correctSpeculation,
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RDY_correctSpeculation);
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input CLK;
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input RST_N;
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// action method write_enq
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input [369 : 0] write_enq_x;
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input EN_write_enq;
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output RDY_write_enq;
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// value method read_deq
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output [369 : 0] read_deq;
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output RDY_read_deq;
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// action method setLSQAtCommitNotified
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input EN_setLSQAtCommitNotified;
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output RDY_setLSQAtCommitNotified;
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// action method setExecuted_deqLSQ
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input [13 : 0] setExecuted_deqLSQ_cause;
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input [2 : 0] setExecuted_deqLSQ_ld_killed;
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input EN_setExecuted_deqLSQ;
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output RDY_setExecuted_deqLSQ;
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// action method setExecuted_doFinishAlu_0_set
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input [130 : 0] setExecuted_doFinishAlu_0_set_csrData;
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input [11 : 0] setExecuted_doFinishAlu_0_set_cause;
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input EN_setExecuted_doFinishAlu_0_set;
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output RDY_setExecuted_doFinishAlu_0_set;
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// action method setExecuted_doFinishAlu_1_set
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input [130 : 0] setExecuted_doFinishAlu_1_set_csrData;
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input [11 : 0] setExecuted_doFinishAlu_1_set_cause;
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input EN_setExecuted_doFinishAlu_1_set;
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output RDY_setExecuted_doFinishAlu_1_set;
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// action method setExecuted_doFinishFpuMulDiv_0_set
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input [4 : 0] setExecuted_doFinishFpuMulDiv_0_set_fflags;
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input [5 : 0] setExecuted_doFinishFpuMulDiv_0_set_cause;
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input EN_setExecuted_doFinishFpuMulDiv_0_set;
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output RDY_setExecuted_doFinishFpuMulDiv_0_set;
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// action method setExecuted_doFinishMem
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input [128 : 0] setExecuted_doFinishMem_vaddr;
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input [63 : 0] setExecuted_doFinishMem_store_data;
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input [7 : 0] setExecuted_doFinishMem_store_data_BE;
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input setExecuted_doFinishMem_access_at_commit;
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input setExecuted_doFinishMem_non_mmio_st_done;
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input EN_setExecuted_doFinishMem;
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output RDY_setExecuted_doFinishMem;
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// value method getOrigPC
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output [128 : 0] getOrigPC;
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output RDY_getOrigPC;
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// value method getOrigPredPC
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output [128 : 0] getOrigPredPC;
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output RDY_getOrigPredPC;
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// value method getOrig_Inst
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output [31 : 0] getOrig_Inst;
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output RDY_getOrig_Inst;
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// value method dependsOn_wrongSpec
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input [3 : 0] dependsOn_wrongSpec_tag;
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output dependsOn_wrongSpec;
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output RDY_dependsOn_wrongSpec;
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// action method correctSpeculation
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input [11 : 0] correctSpeculation_mask;
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input EN_correctSpeculation;
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output RDY_correctSpeculation;
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// signals for module outputs
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wire [369 : 0] read_deq;
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wire [128 : 0] getOrigPC, getOrigPredPC;
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wire [31 : 0] getOrig_Inst;
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wire RDY_correctSpeculation,
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RDY_dependsOn_wrongSpec,
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RDY_getOrigPC,
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RDY_getOrigPredPC,
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RDY_getOrig_Inst,
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RDY_read_deq,
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RDY_setExecuted_deqLSQ,
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RDY_setExecuted_doFinishAlu_0_set,
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RDY_setExecuted_doFinishAlu_1_set,
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RDY_setExecuted_doFinishFpuMulDiv_0_set,
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RDY_setExecuted_doFinishMem,
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RDY_setLSQAtCommitNotified,
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RDY_write_enq,
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dependsOn_wrongSpec;
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// inlined wires
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wire [130 : 0] m_ppc_vaddr_csrData_lat_0$wget,
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m_ppc_vaddr_csrData_lat_1$wget,
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m_ppc_vaddr_csrData_lat_2$wget,
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m_ppc_vaddr_csrData_lat_3$wget;
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wire [13 : 0] m_trap_lat_0$wget,
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m_trap_lat_1$wget,
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m_trap_lat_2$wget,
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m_trap_lat_3$wget;
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wire m_rob_inst_state_lat_4$whas,
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m_trap_lat_0$whas,
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m_trap_lat_1$whas,
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m_trap_lat_2$whas;
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// register m_claimed_phy_reg
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reg m_claimed_phy_reg;
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wire m_claimed_phy_reg$D_IN, m_claimed_phy_reg$EN;
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// register m_csr
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reg [12 : 0] m_csr;
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wire [12 : 0] m_csr$D_IN;
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wire m_csr$EN;
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// register m_epochIncremented
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reg m_epochIncremented;
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wire m_epochIncremented$D_IN, m_epochIncremented$EN;
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// register m_fflags_rl
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reg [4 : 0] m_fflags_rl;
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wire [4 : 0] m_fflags_rl$D_IN;
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wire m_fflags_rl$EN;
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// register m_iType
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reg [4 : 0] m_iType;
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wire [4 : 0] m_iType$D_IN;
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wire m_iType$EN;
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// register m_ldKilled_rl
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reg [2 : 0] m_ldKilled_rl;
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wire [2 : 0] m_ldKilled_rl$D_IN;
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wire m_ldKilled_rl$EN;
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// register m_lsqAtCommitNotified_rl
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reg m_lsqAtCommitNotified_rl;
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wire m_lsqAtCommitNotified_rl$D_IN, m_lsqAtCommitNotified_rl$EN;
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// register m_lsqTag
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reg [5 : 0] m_lsqTag;
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wire [5 : 0] m_lsqTag$D_IN;
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wire m_lsqTag$EN;
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// register m_memAccessAtCommit_rl
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reg m_memAccessAtCommit_rl;
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wire m_memAccessAtCommit_rl$D_IN, m_memAccessAtCommit_rl$EN;
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// register m_nonMMIOStDone_rl
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reg m_nonMMIOStDone_rl;
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wire m_nonMMIOStDone_rl$D_IN, m_nonMMIOStDone_rl$EN;
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// register m_orig_inst
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reg [31 : 0] m_orig_inst;
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wire [31 : 0] m_orig_inst$D_IN;
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wire m_orig_inst$EN;
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// register m_pc_rl
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reg [128 : 0] m_pc_rl;
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wire [128 : 0] m_pc_rl$D_IN;
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wire m_pc_rl$EN;
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// register m_ppc_vaddr_csrData_rl
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reg [130 : 0] m_ppc_vaddr_csrData_rl;
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wire [130 : 0] m_ppc_vaddr_csrData_rl$D_IN;
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wire m_ppc_vaddr_csrData_rl$EN;
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// register m_rg_dst_reg
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reg [6 : 0] m_rg_dst_reg;
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wire [6 : 0] m_rg_dst_reg$D_IN;
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wire m_rg_dst_reg$EN;
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// register m_rob_inst_state_rl
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reg m_rob_inst_state_rl;
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wire m_rob_inst_state_rl$D_IN, m_rob_inst_state_rl$EN;
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// register m_scr
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reg [5 : 0] m_scr;
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wire [5 : 0] m_scr$D_IN;
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wire m_scr$EN;
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// register m_spec_bits_rl
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reg [11 : 0] m_spec_bits_rl;
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wire [11 : 0] m_spec_bits_rl$D_IN;
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wire m_spec_bits_rl$EN;
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// register m_trap_rl
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reg [13 : 0] m_trap_rl;
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wire [13 : 0] m_trap_rl$D_IN;
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wire m_trap_rl$EN;
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// register m_will_dirty_fpu_state
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reg m_will_dirty_fpu_state;
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wire m_will_dirty_fpu_state$D_IN, m_will_dirty_fpu_state$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_fflags_canon,
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CAN_FIRE_RL_m_ldKilled_canon,
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CAN_FIRE_RL_m_lsqAtCommitNotified_canon,
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CAN_FIRE_RL_m_memAccessAtCommit_canon,
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CAN_FIRE_RL_m_nonMMIOStDone_canon,
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CAN_FIRE_RL_m_pc_canon,
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CAN_FIRE_RL_m_ppc_vaddr_csrData_canon,
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CAN_FIRE_RL_m_rob_inst_state_canon,
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CAN_FIRE_RL_m_setPcWires,
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CAN_FIRE_RL_m_spec_bits_canon,
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CAN_FIRE_RL_m_trap_canon,
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CAN_FIRE_correctSpeculation,
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CAN_FIRE_setExecuted_deqLSQ,
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CAN_FIRE_setExecuted_doFinishAlu_0_set,
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CAN_FIRE_setExecuted_doFinishAlu_1_set,
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CAN_FIRE_setExecuted_doFinishFpuMulDiv_0_set,
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CAN_FIRE_setExecuted_doFinishMem,
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CAN_FIRE_setLSQAtCommitNotified,
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CAN_FIRE_write_enq,
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WILL_FIRE_RL_m_fflags_canon,
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WILL_FIRE_RL_m_ldKilled_canon,
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WILL_FIRE_RL_m_lsqAtCommitNotified_canon,
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WILL_FIRE_RL_m_memAccessAtCommit_canon,
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WILL_FIRE_RL_m_nonMMIOStDone_canon,
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WILL_FIRE_RL_m_pc_canon,
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WILL_FIRE_RL_m_ppc_vaddr_csrData_canon,
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WILL_FIRE_RL_m_rob_inst_state_canon,
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WILL_FIRE_RL_m_setPcWires,
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WILL_FIRE_RL_m_spec_bits_canon,
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WILL_FIRE_RL_m_trap_canon,
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WILL_FIRE_correctSpeculation,
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WILL_FIRE_setExecuted_deqLSQ,
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WILL_FIRE_setExecuted_doFinishAlu_0_set,
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WILL_FIRE_setExecuted_doFinishAlu_1_set,
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WILL_FIRE_setExecuted_doFinishFpuMulDiv_0_set,
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WILL_FIRE_setExecuted_doFinishMem,
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WILL_FIRE_setLSQAtCommitNotified,
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WILL_FIRE_write_enq;
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// inputs to muxes for submodule ports
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wire [13 : 0] MUX_m_trap_lat_2$wset_1__VAL_1,
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MUX_m_trap_lat_2$wset_1__VAL_2;
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wire MUX_m_trap_lat_2$wset_1__SEL_1;
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// remaining internal signals
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reg [12 : 0] CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7,
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CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q11,
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CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18;
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reg [11 : 0] CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
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CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22;
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reg [4 : 0] CASE_m_scr_BITS_4_TO_0_0_m_scr_BITS_4_TO_0_1_m_ETC__q2,
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CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q5,
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CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q6,
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CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q10,
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CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q9,
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CASE_setExecuted_doFinishAlu_0_set_cause_BITS__ETC__q13,
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CASE_setExecuted_doFinishAlu_1_set_cause_BITS__ETC__q14,
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CASE_setExecuted_doFinishFpuMulDiv_0_set_cause_ETC__q12,
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CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16,
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CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17,
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CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23;
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reg [3 : 0] CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q4,
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CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q8,
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CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15;
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reg [1 : 0] CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
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CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19,
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CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20,
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CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21;
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wire [196 : 0] m_scr_26_BIT_5_27_CONCAT_IF_m_scr_26_BIT_5_27__ETC___d1115;
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wire [162 : 0] IF_m_ppc_vaddr_csrData_rl_64_BITS_130_TO_129_6_ETC___d1113;
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wire [128 : 0] IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d588,
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IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d590;
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wire [12 : 0] IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d544,
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IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d545;
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wire [11 : 0] sb__h18415, upd__h9919;
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wire [5 : 0] IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d71,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d73;
|
|
wire [4 : 0] IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d336,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d338,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d340,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d342,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d344,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d346,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d348,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d350,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d352,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d354,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d356,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d404,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d406,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d408,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d410,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d412,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d414;
|
|
wire [3 : 0] IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d535,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d537,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d539,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d541;
|
|
wire [1 : 0] IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d637;
|
|
wire IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d627,
|
|
IF_m_memAccessAtCommit_lat_1_whas__42_THEN_m_m_ETC___d648,
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d568,
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d577,
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d570,
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d579,
|
|
IF_m_rob_inst_state_lat_3_whas__03_THEN_m_rob__ETC___d615,
|
|
IF_m_trap_lat_0_whas__6_THEN_NOT_m_trap_lat_0__ETC___d42,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d110,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d121,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d132,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d143,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d154,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d165,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d176,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d187,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d198,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d209,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d220,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d231,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d242,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d253,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d264,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d275,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d286,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d297,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d308,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d319,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d32,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d330,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d365,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d376,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d387,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d398,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d430,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d441,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d452,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d463,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d474,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d485,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d496,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d507,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d518,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d529,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d60,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d88,
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d99,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d101,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d112,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d123,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d134,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d145,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d156,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d167,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d178,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d189,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d200,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d211,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d222,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d233,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d244,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d255,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d266,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d277,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d288,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d299,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d310,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d321,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d332,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d34,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d367,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d378,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d389,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d400,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d432,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d443,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d454,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d465,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d476,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d487,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d498,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d509,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d520,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d531,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d62,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d90,
|
|
setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1345;
|
|
|
|
// action method write_enq
|
|
assign RDY_write_enq = 1'd1 ;
|
|
assign CAN_FIRE_write_enq = 1'd1 ;
|
|
assign WILL_FIRE_write_enq = EN_write_enq ;
|
|
|
|
// value method read_deq
|
|
assign read_deq =
|
|
{ m_pc_rl,
|
|
m_orig_inst,
|
|
m_iType,
|
|
m_rg_dst_reg,
|
|
m_scr_26_BIT_5_27_CONCAT_IF_m_scr_26_BIT_5_27__ETC___d1115 } ;
|
|
assign RDY_read_deq = 1'd1 ;
|
|
|
|
// action method setLSQAtCommitNotified
|
|
assign RDY_setLSQAtCommitNotified = 1'd1 ;
|
|
assign CAN_FIRE_setLSQAtCommitNotified = 1'd1 ;
|
|
assign WILL_FIRE_setLSQAtCommitNotified = EN_setLSQAtCommitNotified ;
|
|
|
|
// action method setExecuted_deqLSQ
|
|
assign RDY_setExecuted_deqLSQ = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_deqLSQ = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_deqLSQ = EN_setExecuted_deqLSQ ;
|
|
|
|
// action method setExecuted_doFinishAlu_0_set
|
|
assign RDY_setExecuted_doFinishAlu_0_set = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishAlu_0_set = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishAlu_0_set =
|
|
EN_setExecuted_doFinishAlu_0_set ;
|
|
|
|
// action method setExecuted_doFinishAlu_1_set
|
|
assign RDY_setExecuted_doFinishAlu_1_set = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishAlu_1_set = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishAlu_1_set =
|
|
EN_setExecuted_doFinishAlu_1_set ;
|
|
|
|
// action method setExecuted_doFinishFpuMulDiv_0_set
|
|
assign RDY_setExecuted_doFinishFpuMulDiv_0_set = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishFpuMulDiv_0_set = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishFpuMulDiv_0_set =
|
|
EN_setExecuted_doFinishFpuMulDiv_0_set ;
|
|
|
|
// action method setExecuted_doFinishMem
|
|
assign RDY_setExecuted_doFinishMem = 1'd1 ;
|
|
assign CAN_FIRE_setExecuted_doFinishMem = 1'd1 ;
|
|
assign WILL_FIRE_setExecuted_doFinishMem = EN_setExecuted_doFinishMem ;
|
|
|
|
// value method getOrigPC
|
|
assign getOrigPC = m_pc_rl ;
|
|
assign RDY_getOrigPC = 1'd1 ;
|
|
|
|
// value method getOrigPredPC
|
|
assign getOrigPredPC =
|
|
(m_ppc_vaddr_csrData_rl[130:129] == 2'd0) ?
|
|
m_ppc_vaddr_csrData_rl[128:0] :
|
|
129'h000001FFFFC0180040000000000000000 ;
|
|
assign RDY_getOrigPredPC = 1'd1 ;
|
|
|
|
// value method getOrig_Inst
|
|
assign getOrig_Inst = m_orig_inst ;
|
|
assign RDY_getOrig_Inst = 1'd1 ;
|
|
|
|
// value method dependsOn_wrongSpec
|
|
assign dependsOn_wrongSpec = m_spec_bits_rl[dependsOn_wrongSpec_tag] ;
|
|
assign RDY_dependsOn_wrongSpec = 1'd1 ;
|
|
|
|
// action method correctSpeculation
|
|
assign RDY_correctSpeculation = 1'd1 ;
|
|
assign CAN_FIRE_correctSpeculation = 1'd1 ;
|
|
assign WILL_FIRE_correctSpeculation = EN_correctSpeculation ;
|
|
|
|
// rule RL_m_setPcWires
|
|
assign CAN_FIRE_RL_m_setPcWires = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_setPcWires = 1'd1 ;
|
|
|
|
// rule RL_m_pc_canon
|
|
assign CAN_FIRE_RL_m_pc_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_pc_canon = 1'd1 ;
|
|
|
|
// rule RL_m_trap_canon
|
|
assign CAN_FIRE_RL_m_trap_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_trap_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ppc_vaddr_csrData_canon
|
|
assign CAN_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
|
|
|
|
// rule RL_m_fflags_canon
|
|
assign CAN_FIRE_RL_m_fflags_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_fflags_canon = 1'd1 ;
|
|
|
|
// rule RL_m_rob_inst_state_canon
|
|
assign CAN_FIRE_RL_m_rob_inst_state_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_rob_inst_state_canon = 1'd1 ;
|
|
|
|
// rule RL_m_ldKilled_canon
|
|
assign CAN_FIRE_RL_m_ldKilled_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_ldKilled_canon = 1'd1 ;
|
|
|
|
// rule RL_m_memAccessAtCommit_canon
|
|
assign CAN_FIRE_RL_m_memAccessAtCommit_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_memAccessAtCommit_canon = 1'd1 ;
|
|
|
|
// rule RL_m_lsqAtCommitNotified_canon
|
|
assign CAN_FIRE_RL_m_lsqAtCommitNotified_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_lsqAtCommitNotified_canon = 1'd1 ;
|
|
|
|
// rule RL_m_nonMMIOStDone_canon
|
|
assign CAN_FIRE_RL_m_nonMMIOStDone_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_nonMMIOStDone_canon = 1'd1 ;
|
|
|
|
// rule RL_m_spec_bits_canon
|
|
assign CAN_FIRE_RL_m_spec_bits_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_spec_bits_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_m_trap_lat_2$wset_1__SEL_1 =
|
|
EN_setExecuted_deqLSQ && setExecuted_deqLSQ_cause[13] ;
|
|
assign MUX_m_trap_lat_2$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q11 } ;
|
|
assign MUX_m_trap_lat_2$wset_1__VAL_2 =
|
|
{ 9'd362,
|
|
CASE_setExecuted_doFinishFpuMulDiv_0_set_cause_ETC__q12 } ;
|
|
|
|
// inlined wires
|
|
assign m_trap_lat_0$wget =
|
|
{ 3'd4,
|
|
setExecuted_doFinishAlu_0_set_cause[10:5],
|
|
CASE_setExecuted_doFinishAlu_0_set_cause_BITS__ETC__q13 } ;
|
|
assign m_trap_lat_0$whas =
|
|
EN_setExecuted_doFinishAlu_0_set &&
|
|
setExecuted_doFinishAlu_0_set_cause[11] &&
|
|
!m_trap_rl[13] ;
|
|
assign m_trap_lat_1$wget =
|
|
{ 3'd4,
|
|
setExecuted_doFinishAlu_1_set_cause[10:5],
|
|
CASE_setExecuted_doFinishAlu_1_set_cause_BITS__ETC__q14 } ;
|
|
assign m_trap_lat_1$whas =
|
|
EN_setExecuted_doFinishAlu_1_set &&
|
|
setExecuted_doFinishAlu_1_set_cause[11] &&
|
|
IF_m_trap_lat_0_whas__6_THEN_NOT_m_trap_lat_0__ETC___d42 ;
|
|
assign m_trap_lat_2$wget =
|
|
MUX_m_trap_lat_2$wset_1__SEL_1 ?
|
|
MUX_m_trap_lat_2$wset_1__VAL_1 :
|
|
MUX_m_trap_lat_2$wset_1__VAL_2 ;
|
|
assign m_trap_lat_2$whas =
|
|
EN_setExecuted_deqLSQ && setExecuted_deqLSQ_cause[13] ||
|
|
EN_setExecuted_doFinishFpuMulDiv_0_set &&
|
|
setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1345 ;
|
|
assign m_trap_lat_3$wget =
|
|
{ write_enq_x[176],
|
|
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 } ;
|
|
assign m_ppc_vaddr_csrData_lat_0$wget =
|
|
{ CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19,
|
|
setExecuted_doFinishAlu_0_set_csrData[128:0] } ;
|
|
assign m_ppc_vaddr_csrData_lat_1$wget =
|
|
{ CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20,
|
|
setExecuted_doFinishAlu_1_set_csrData[128:0] } ;
|
|
assign m_ppc_vaddr_csrData_lat_2$wget =
|
|
{ 2'd1, setExecuted_doFinishMem_vaddr } ;
|
|
assign m_ppc_vaddr_csrData_lat_3$wget =
|
|
{ CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21,
|
|
write_enq_x[160:32] } ;
|
|
assign m_rob_inst_state_lat_4$whas =
|
|
EN_setExecuted_doFinishMem &&
|
|
setExecuted_doFinishMem_non_mmio_st_done ;
|
|
|
|
// register m_claimed_phy_reg
|
|
assign m_claimed_phy_reg$D_IN = write_enq_x[177] ;
|
|
assign m_claimed_phy_reg$EN = EN_write_enq ;
|
|
|
|
// register m_csr
|
|
assign m_csr$D_IN =
|
|
{ write_enq_x[190],
|
|
CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22 } ;
|
|
assign m_csr$EN = EN_write_enq ;
|
|
|
|
// register m_epochIncremented
|
|
assign m_epochIncremented$D_IN = write_enq_x[12] ;
|
|
assign m_epochIncremented$EN = EN_write_enq ;
|
|
|
|
// register m_fflags_rl
|
|
assign m_fflags_rl$D_IN =
|
|
EN_write_enq ?
|
|
write_enq_x[31:27] :
|
|
(EN_setExecuted_doFinishFpuMulDiv_0_set ?
|
|
setExecuted_doFinishFpuMulDiv_0_set_fflags :
|
|
m_fflags_rl) ;
|
|
assign m_fflags_rl$EN = 1'd1 ;
|
|
|
|
// register m_iType
|
|
assign m_iType$D_IN = write_enq_x[208:204] ;
|
|
assign m_iType$EN = EN_write_enq ;
|
|
|
|
// register m_ldKilled_rl
|
|
assign m_ldKilled_rl$D_IN =
|
|
{ IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d627,
|
|
IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d637 } ;
|
|
assign m_ldKilled_rl$EN = 1'd1 ;
|
|
|
|
// register m_lsqAtCommitNotified_rl
|
|
assign m_lsqAtCommitNotified_rl$D_IN =
|
|
!EN_write_enq &&
|
|
(EN_setLSQAtCommitNotified || m_lsqAtCommitNotified_rl) ;
|
|
assign m_lsqAtCommitNotified_rl$EN = 1'd1 ;
|
|
|
|
// register m_lsqTag
|
|
assign m_lsqTag$D_IN = write_enq_x[24:19] ;
|
|
assign m_lsqTag$EN = EN_write_enq ;
|
|
|
|
// register m_memAccessAtCommit_rl
|
|
assign m_memAccessAtCommit_rl$D_IN =
|
|
IF_m_memAccessAtCommit_lat_1_whas__42_THEN_m_m_ETC___d648 ;
|
|
assign m_memAccessAtCommit_rl$EN = 1'd1 ;
|
|
|
|
// register m_nonMMIOStDone_rl
|
|
assign m_nonMMIOStDone_rl$D_IN =
|
|
!EN_write_enq &&
|
|
(EN_setExecuted_doFinishMem ?
|
|
setExecuted_doFinishMem_non_mmio_st_done :
|
|
m_nonMMIOStDone_rl) ;
|
|
assign m_nonMMIOStDone_rl$EN = 1'd1 ;
|
|
|
|
// register m_orig_inst
|
|
assign m_orig_inst$D_IN = write_enq_x[240:209] ;
|
|
assign m_orig_inst$EN = EN_write_enq ;
|
|
|
|
// register m_pc_rl
|
|
assign m_pc_rl$D_IN = EN_write_enq ? write_enq_x[369:241] : m_pc_rl ;
|
|
assign m_pc_rl$EN = 1'd1 ;
|
|
|
|
// register m_ppc_vaddr_csrData_rl
|
|
assign m_ppc_vaddr_csrData_rl$D_IN =
|
|
{ IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d570 ?
|
|
2'd0 :
|
|
(IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d579 ?
|
|
2'd1 :
|
|
2'd2),
|
|
IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d590 } ;
|
|
assign m_ppc_vaddr_csrData_rl$EN = 1'd1 ;
|
|
|
|
// register m_rg_dst_reg
|
|
assign m_rg_dst_reg$D_IN = write_enq_x[203:197] ;
|
|
assign m_rg_dst_reg$EN = EN_write_enq ;
|
|
|
|
// register m_rob_inst_state_rl
|
|
assign m_rob_inst_state_rl$D_IN =
|
|
EN_write_enq ?
|
|
write_enq_x[25] :
|
|
m_rob_inst_state_lat_4$whas ||
|
|
IF_m_rob_inst_state_lat_3_whas__03_THEN_m_rob__ETC___d615 ;
|
|
assign m_rob_inst_state_rl$EN = 1'd1 ;
|
|
|
|
// register m_scr
|
|
assign m_scr$D_IN =
|
|
{ write_enq_x[196],
|
|
CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23 } ;
|
|
assign m_scr$EN = EN_write_enq ;
|
|
|
|
// register m_spec_bits_rl
|
|
assign m_spec_bits_rl$D_IN =
|
|
EN_correctSpeculation ? upd__h9919 : sb__h18415 ;
|
|
assign m_spec_bits_rl$EN = 1'd1 ;
|
|
|
|
// register m_trap_rl
|
|
assign m_trap_rl$D_IN =
|
|
{ IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d34,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d545 } ;
|
|
assign m_trap_rl$EN = 1'd1 ;
|
|
|
|
// register m_will_dirty_fpu_state
|
|
assign m_will_dirty_fpu_state$D_IN = write_enq_x[26] ;
|
|
assign m_will_dirty_fpu_state$EN = EN_write_enq ;
|
|
|
|
// remaining internal signals
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d336 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d310 ?
|
|
5'd24 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d321 ?
|
|
5'd25 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d332 ?
|
|
5'd26 :
|
|
5'd27)) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d338 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d288 ?
|
|
5'd22 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d299 ?
|
|
5'd23 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d336) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d340 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d266 ?
|
|
5'd20 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d277 ?
|
|
5'd21 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d338) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d342 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d244 ?
|
|
5'd18 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d255 ?
|
|
5'd19 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d340) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d344 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d222 ?
|
|
5'd16 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d233 ?
|
|
5'd17 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d342) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d346 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d200 ?
|
|
5'd10 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d211 ?
|
|
5'd11 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d344) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d348 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d178 ?
|
|
5'd8 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d189 ?
|
|
5'd9 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d346) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d350 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d156 ?
|
|
5'd6 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d167 ?
|
|
5'd7 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d348) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d352 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d134 ?
|
|
5'd4 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d145 ?
|
|
5'd5 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d350) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d354 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d112 ?
|
|
5'd2 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d123 ?
|
|
5'd3 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d352) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d356 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d90 ?
|
|
5'd0 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d101 ?
|
|
5'd1 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d354) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d404 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d378 ?
|
|
5'd12 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d389 ?
|
|
5'd13 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d400 ?
|
|
5'd15 :
|
|
5'd28)) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d406 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d189 ?
|
|
5'd9 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d211 ?
|
|
5'd11 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d404) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d408 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d167 ?
|
|
5'd7 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d178 ?
|
|
5'd8 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d406) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d410 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d145 ?
|
|
5'd5 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d156 ?
|
|
5'd6 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d408) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d412 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d123 ?
|
|
5'd3 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d134 ?
|
|
5'd4 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d410) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d414 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d101 ?
|
|
5'd1 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d112 ?
|
|
5'd2 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d412) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d535 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d509 ?
|
|
4'd9 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d520 ?
|
|
4'd11 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d531 ?
|
|
4'd14 :
|
|
4'd15)) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d537 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d487 ?
|
|
4'd7 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d498 ?
|
|
4'd8 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d535) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d539 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d465 ?
|
|
4'd4 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d476 ?
|
|
4'd5 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d537) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d541 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d443 ?
|
|
4'd1 :
|
|
(IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d454 ?
|
|
4'd3 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d539) ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d544 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d367 ?
|
|
{ 8'd106,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d90 ?
|
|
5'd0 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d414 } :
|
|
{ 9'd298,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d432 ?
|
|
4'd0 :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d541 } ;
|
|
assign IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d545 =
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d62 ?
|
|
{ 2'd0,
|
|
IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d73,
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d356 } :
|
|
IF_IF_m_trap_lat_4_whas__4_THEN_m_trap_lat_4_w_ETC___d544 ;
|
|
assign IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d627 =
|
|
!EN_write_enq &&
|
|
(EN_setExecuted_deqLSQ ?
|
|
setExecuted_deqLSQ_ld_killed[2] :
|
|
m_ldKilled_rl[2]) ;
|
|
assign IF_m_ldKilled_lat_1_whas__18_THEN_m_ldKilled_l_ETC___d637 =
|
|
EN_write_enq ?
|
|
2'b10 :
|
|
(EN_setExecuted_deqLSQ ?
|
|
setExecuted_deqLSQ_ld_killed[1:0] :
|
|
m_ldKilled_rl[1:0]) ;
|
|
assign IF_m_memAccessAtCommit_lat_1_whas__42_THEN_m_m_ETC___d648 =
|
|
EN_write_enq ?
|
|
write_enq_x[208:204] == 5'd19 :
|
|
(EN_setExecuted_doFinishMem ?
|
|
setExecuted_doFinishMem_access_at_commit :
|
|
m_memAccessAtCommit_rl) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d568 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[130:129] == 2'd0 :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[130:129] == 2'd0 :
|
|
m_ppc_vaddr_csrData_rl[130:129] == 2'd0) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d577 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[130:129] == 2'd1 :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[130:129] == 2'd1 :
|
|
m_ppc_vaddr_csrData_rl[130:129] == 2'd1) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d588 =
|
|
EN_setExecuted_doFinishAlu_1_set ?
|
|
m_ppc_vaddr_csrData_lat_1$wget[128:0] :
|
|
(EN_setExecuted_doFinishAlu_0_set ?
|
|
m_ppc_vaddr_csrData_lat_0$wget[128:0] :
|
|
m_ppc_vaddr_csrData_rl[128:0]) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d570 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[130:129] == 2'd0 :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[130:129] == 2'd0 :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d568) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d579 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[130:129] == 2'd1 :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[130:129] == 2'd1 :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d577) ;
|
|
assign IF_m_ppc_vaddr_csrData_lat_3_whas__48_THEN_m_p_ETC___d590 =
|
|
EN_write_enq ?
|
|
m_ppc_vaddr_csrData_lat_3$wget[128:0] :
|
|
(EN_setExecuted_doFinishMem ?
|
|
m_ppc_vaddr_csrData_lat_2$wget[128:0] :
|
|
IF_m_ppc_vaddr_csrData_lat_1_whas__56_THEN_m_p_ETC___d588) ;
|
|
assign IF_m_ppc_vaddr_csrData_rl_64_BITS_130_TO_129_6_ETC___d1113 =
|
|
{ CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1,
|
|
m_ppc_vaddr_csrData_rl[128:0],
|
|
m_fflags_rl,
|
|
m_will_dirty_fpu_state,
|
|
m_rob_inst_state_rl,
|
|
m_lsqTag,
|
|
m_ldKilled_rl,
|
|
m_memAccessAtCommit_rl,
|
|
m_lsqAtCommitNotified_rl,
|
|
m_nonMMIOStDone_rl,
|
|
m_epochIncremented,
|
|
m_spec_bits_rl } ;
|
|
assign IF_m_rob_inst_state_lat_3_whas__03_THEN_m_rob__ETC___d615 =
|
|
EN_setExecuted_deqLSQ ||
|
|
EN_setExecuted_doFinishFpuMulDiv_0_set ||
|
|
EN_setExecuted_doFinishAlu_1_set ||
|
|
EN_setExecuted_doFinishAlu_0_set ||
|
|
m_rob_inst_state_rl ;
|
|
assign IF_m_trap_lat_0_whas__6_THEN_NOT_m_trap_lat_0__ETC___d42 =
|
|
m_trap_lat_0$whas ? !m_trap_lat_0$wget[13] : !m_trap_rl[13] ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d110 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd2 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd2 :
|
|
m_trap_rl[4:0] == 5'd2) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d121 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd3 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd3 :
|
|
m_trap_rl[4:0] == 5'd3) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d132 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd4 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd4 :
|
|
m_trap_rl[4:0] == 5'd4) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d143 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd5 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd5 :
|
|
m_trap_rl[4:0] == 5'd5) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d154 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd6 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd6 :
|
|
m_trap_rl[4:0] == 5'd6) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d165 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd7 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd7 :
|
|
m_trap_rl[4:0] == 5'd7) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d176 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd8 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd8 :
|
|
m_trap_rl[4:0] == 5'd8) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d187 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd9 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd9 :
|
|
m_trap_rl[4:0] == 5'd9) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d198 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd10 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd10 :
|
|
m_trap_rl[4:0] == 5'd10) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d209 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd11 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd11 :
|
|
m_trap_rl[4:0] == 5'd11) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d220 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd16 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd16 :
|
|
m_trap_rl[4:0] == 5'd16) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d231 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd17 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd17 :
|
|
m_trap_rl[4:0] == 5'd17) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d242 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd18 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd18 :
|
|
m_trap_rl[4:0] == 5'd18) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d253 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd19 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd19 :
|
|
m_trap_rl[4:0] == 5'd19) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d264 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd20 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd20 :
|
|
m_trap_rl[4:0] == 5'd20) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d275 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd21 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd21 :
|
|
m_trap_rl[4:0] == 5'd21) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d286 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd22 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd22 :
|
|
m_trap_rl[4:0] == 5'd22) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d297 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd23 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd23 :
|
|
m_trap_rl[4:0] == 5'd23) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d308 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd24 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd24 :
|
|
m_trap_rl[4:0] == 5'd24) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d319 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd25 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd25 :
|
|
m_trap_rl[4:0] == 5'd25) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d32 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[13] :
|
|
(m_trap_lat_0$whas ? m_trap_lat_0$wget[13] : m_trap_rl[13]) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d330 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd26 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd26 :
|
|
m_trap_rl[4:0] == 5'd26) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d365 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[12:11] == 2'd1 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[12:11] == 2'd1 :
|
|
m_trap_rl[12:11] == 2'd1) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d376 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd12 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd12 :
|
|
m_trap_rl[4:0] == 5'd12) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d387 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd13 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd13 :
|
|
m_trap_rl[4:0] == 5'd13) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d398 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd15 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd15 :
|
|
m_trap_rl[4:0] == 5'd15) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d430 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd0 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd0 :
|
|
m_trap_rl[3:0] == 4'd0) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d441 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd1 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd1 :
|
|
m_trap_rl[3:0] == 4'd1) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d452 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd3 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd3 :
|
|
m_trap_rl[3:0] == 4'd3) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d463 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd4 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd4 :
|
|
m_trap_rl[3:0] == 4'd4) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d474 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd5 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd5 :
|
|
m_trap_rl[3:0] == 4'd5) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d485 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd7 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd7 :
|
|
m_trap_rl[3:0] == 4'd7) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d496 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd8 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd8 :
|
|
m_trap_rl[3:0] == 4'd8) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d507 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd9 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd9 :
|
|
m_trap_rl[3:0] == 4'd9) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d518 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd11 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd11 :
|
|
m_trap_rl[3:0] == 4'd11) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d529 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[3:0] == 4'd14 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[3:0] == 4'd14 :
|
|
m_trap_rl[3:0] == 4'd14) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d60 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[12:11] == 2'd0 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[12:11] == 2'd0 :
|
|
m_trap_rl[12:11] == 2'd0) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d71 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[10:5] :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[10:5] :
|
|
m_trap_rl[10:5]) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d88 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd0 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd0 :
|
|
m_trap_rl[4:0] == 5'd0) ;
|
|
assign IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d99 =
|
|
m_trap_lat_1$whas ?
|
|
m_trap_lat_1$wget[4:0] == 5'd1 :
|
|
(m_trap_lat_0$whas ?
|
|
m_trap_lat_0$wget[4:0] == 5'd1 :
|
|
m_trap_rl[4:0] == 5'd1) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d101 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd1 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd1 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d99) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d112 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd2 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd2 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d110) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d123 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd3 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd3 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d121) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d134 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd4 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd4 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d132) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d145 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd5 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd5 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d143) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d156 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd6 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd6 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d154) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d167 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd7 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd7 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d165) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d178 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd8 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd8 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d176) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d189 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd9 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd9 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d187) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d200 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd10 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd10 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d198) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d211 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd11 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd11 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d209) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d222 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd16 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd16 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d220) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d233 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd17 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd17 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d231) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d244 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd18 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd18 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d242) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d255 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd19 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd19 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d253) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d266 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd20 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd20 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d264) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d277 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd21 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd21 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d275) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d288 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd22 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd22 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d286) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d299 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd23 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd23 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d297) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d310 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd24 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd24 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d308) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d321 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd25 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd25 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d319) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d332 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd26 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd26 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d330) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d34 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[13] :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[13] :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d32) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d367 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[12:11] == 2'd1 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[12:11] == 2'd1 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d365) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d378 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd12 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd12 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d376) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d389 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd13 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd13 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d387) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d400 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd15 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd15 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d398) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d432 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd0 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd0 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d430) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d443 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd1 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd1 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d441) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d454 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd3 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd3 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d452) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d465 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd4 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd4 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d463) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d476 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd5 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd5 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d474) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d487 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd7 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd7 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d485) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d498 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd8 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd8 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d496) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d509 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd9 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd9 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d507) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d520 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd11 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd11 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d518) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d531 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[3:0] == 4'd14 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[3:0] == 4'd14 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d529) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d62 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[12:11] == 2'd0 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[12:11] == 2'd0 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d60) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d73 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[10:5] :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[10:5] :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d71) ;
|
|
assign IF_m_trap_lat_3_whas__7_THEN_m_trap_lat_3_wget_ETC___d90 =
|
|
EN_write_enq ?
|
|
m_trap_lat_3$wget[4:0] == 5'd0 :
|
|
(m_trap_lat_2$whas ?
|
|
m_trap_lat_2$wget[4:0] == 5'd0 :
|
|
IF_m_trap_lat_1_whas__3_THEN_m_trap_lat_1_wget_ETC___d88) ;
|
|
assign m_scr_26_BIT_5_27_CONCAT_IF_m_scr_26_BIT_5_27__ETC___d1115 =
|
|
{ m_scr[5],
|
|
CASE_m_scr_BITS_4_TO_0_0_m_scr_BITS_4_TO_0_1_m_ETC__q2,
|
|
m_csr[12],
|
|
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
|
|
m_claimed_phy_reg,
|
|
m_trap_rl[13],
|
|
CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7,
|
|
IF_m_ppc_vaddr_csrData_rl_64_BITS_130_TO_129_6_ETC___d1113 } ;
|
|
assign sb__h18415 = EN_write_enq ? write_enq_x[11:0] : m_spec_bits_rl ;
|
|
assign setExecuted_doFinishFpuMulDiv_0_set_cause_BIT__ETC___d1345 =
|
|
setExecuted_doFinishFpuMulDiv_0_set_cause[5] &&
|
|
(m_trap_lat_1$whas ?
|
|
!m_trap_lat_1$wget[13] :
|
|
IF_m_trap_lat_0_whas__6_THEN_NOT_m_trap_lat_0__ETC___d42) ;
|
|
assign upd__h9919 = sb__h18415 & correctSpeculation_mask ;
|
|
always@(m_ppc_vaddr_csrData_rl)
|
|
begin
|
|
case (m_ppc_vaddr_csrData_rl[130:129])
|
|
2'd0, 2'd1:
|
|
CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1 =
|
|
m_ppc_vaddr_csrData_rl[130:129];
|
|
default: CASE_m_ppc_vaddr_csrData_rl_BITS_130_TO_129_0__ETC__q1 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(m_scr)
|
|
begin
|
|
case (m_scr[4:0])
|
|
5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31:
|
|
CASE_m_scr_BITS_4_TO_0_0_m_scr_BITS_4_TO_0_1_m_ETC__q2 = m_scr[4:0];
|
|
default: CASE_m_scr_BITS_4_TO_0_0_m_scr_BITS_4_TO_0_1_m_ETC__q2 = 5'd10;
|
|
endcase
|
|
end
|
|
always@(m_csr)
|
|
begin
|
|
case (m_csr[11:0])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd1952,
|
|
12'd1953,
|
|
12'd1954,
|
|
12'd1955,
|
|
12'd1968,
|
|
12'd1969,
|
|
12'd1970,
|
|
12'd1971,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2496,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3008,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3 =
|
|
m_csr[11:0];
|
|
default: CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(m_trap_rl)
|
|
begin
|
|
case (m_trap_rl[3:0])
|
|
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
|
|
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q4 =
|
|
m_trap_rl[3:0];
|
|
default: CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q4 = 4'd15;
|
|
endcase
|
|
end
|
|
always@(m_trap_rl)
|
|
begin
|
|
case (m_trap_rl[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q5 =
|
|
m_trap_rl[4:0];
|
|
default: CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q5 = 5'd27;
|
|
endcase
|
|
end
|
|
always@(m_trap_rl)
|
|
begin
|
|
case (m_trap_rl[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd11,
|
|
5'd12,
|
|
5'd13,
|
|
5'd15:
|
|
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q6 =
|
|
m_trap_rl[4:0];
|
|
default: CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q6 = 5'd28;
|
|
endcase
|
|
end
|
|
always@(m_trap_rl or
|
|
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q4 or
|
|
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q5 or
|
|
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q6)
|
|
begin
|
|
case (m_trap_rl[12:11])
|
|
2'd0:
|
|
CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7 =
|
|
{ 2'd0,
|
|
m_trap_rl[10:5],
|
|
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q5 };
|
|
2'd1:
|
|
CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7 =
|
|
{ m_trap_rl[12:11],
|
|
6'h2A,
|
|
CASE_m_trap_rl_BITS_4_TO_0_0_m_trap_rl_BITS_4__ETC__q6 };
|
|
default: CASE_m_trap_rl_BITS_12_TO_11_0_0_CONCAT_m_trap_ETC__q7 =
|
|
{ 9'd298,
|
|
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q4 };
|
|
endcase
|
|
end
|
|
always@(setExecuted_deqLSQ_cause)
|
|
begin
|
|
case (setExecuted_deqLSQ_cause[3:0])
|
|
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
|
|
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q8 =
|
|
setExecuted_deqLSQ_cause[3:0];
|
|
default: CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q8 = 4'd15;
|
|
endcase
|
|
end
|
|
always@(setExecuted_deqLSQ_cause)
|
|
begin
|
|
case (setExecuted_deqLSQ_cause[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q9 =
|
|
setExecuted_deqLSQ_cause[4:0];
|
|
default: CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q9 = 5'd27;
|
|
endcase
|
|
end
|
|
always@(setExecuted_deqLSQ_cause)
|
|
begin
|
|
case (setExecuted_deqLSQ_cause[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd11,
|
|
5'd12,
|
|
5'd13,
|
|
5'd15:
|
|
CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q10 =
|
|
setExecuted_deqLSQ_cause[4:0];
|
|
default: CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q10 =
|
|
5'd28;
|
|
endcase
|
|
end
|
|
always@(setExecuted_deqLSQ_cause or
|
|
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q8 or
|
|
CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q9 or
|
|
CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q10)
|
|
begin
|
|
case (setExecuted_deqLSQ_cause[12:11])
|
|
2'd0:
|
|
CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q11 =
|
|
{ 2'd0,
|
|
setExecuted_deqLSQ_cause[10:5],
|
|
CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q9 };
|
|
2'd1:
|
|
CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q11 =
|
|
{ setExecuted_deqLSQ_cause[12:11],
|
|
6'h2A,
|
|
CASE_setExecuted_deqLSQ_cause_BITS_4_TO_0_0_se_ETC__q10 };
|
|
default: CASE_setExecuted_deqLSQ_cause_BITS_12_TO_11_0__ETC__q11 =
|
|
{ 9'd298,
|
|
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q8 };
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishFpuMulDiv_0_set_cause)
|
|
begin
|
|
case (setExecuted_doFinishFpuMulDiv_0_set_cause[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd11,
|
|
5'd12,
|
|
5'd13,
|
|
5'd15:
|
|
CASE_setExecuted_doFinishFpuMulDiv_0_set_cause_ETC__q12 =
|
|
setExecuted_doFinishFpuMulDiv_0_set_cause[4:0];
|
|
default: CASE_setExecuted_doFinishFpuMulDiv_0_set_cause_ETC__q12 =
|
|
5'd28;
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishAlu_0_set_cause)
|
|
begin
|
|
case (setExecuted_doFinishAlu_0_set_cause[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_setExecuted_doFinishAlu_0_set_cause_BITS__ETC__q13 =
|
|
setExecuted_doFinishAlu_0_set_cause[4:0];
|
|
default: CASE_setExecuted_doFinishAlu_0_set_cause_BITS__ETC__q13 =
|
|
5'd27;
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishAlu_1_set_cause)
|
|
begin
|
|
case (setExecuted_doFinishAlu_1_set_cause[4:0])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_setExecuted_doFinishAlu_1_set_cause_BITS__ETC__q14 =
|
|
setExecuted_doFinishAlu_1_set_cause[4:0];
|
|
default: CASE_setExecuted_doFinishAlu_1_set_cause_BITS__ETC__q14 =
|
|
5'd27;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[166:163])
|
|
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
|
|
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 =
|
|
write_enq_x[166:163];
|
|
default: CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 =
|
|
4'd15;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[167:163])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd10,
|
|
5'd11,
|
|
5'd16,
|
|
5'd17,
|
|
5'd18,
|
|
5'd19,
|
|
5'd20,
|
|
5'd21,
|
|
5'd22,
|
|
5'd23,
|
|
5'd24,
|
|
5'd25,
|
|
5'd26:
|
|
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 =
|
|
write_enq_x[167:163];
|
|
default: CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 =
|
|
5'd27;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[167:163])
|
|
5'd0,
|
|
5'd1,
|
|
5'd2,
|
|
5'd3,
|
|
5'd4,
|
|
5'd5,
|
|
5'd6,
|
|
5'd7,
|
|
5'd8,
|
|
5'd9,
|
|
5'd11,
|
|
5'd12,
|
|
5'd13,
|
|
5'd15:
|
|
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17 =
|
|
write_enq_x[167:163];
|
|
default: CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17 =
|
|
5'd28;
|
|
endcase
|
|
end
|
|
always@(write_enq_x or
|
|
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 or
|
|
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 or
|
|
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17)
|
|
begin
|
|
case (write_enq_x[175:174])
|
|
2'd0:
|
|
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 =
|
|
{ 2'd0,
|
|
write_enq_x[173:168],
|
|
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q16 };
|
|
2'd1:
|
|
CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 =
|
|
{ write_enq_x[175:174],
|
|
6'h2A,
|
|
CASE_write_enq_x_BITS_167_TO_163_0_write_enq_x_ETC__q17 };
|
|
default: CASE_write_enq_x_BITS_175_TO_174_0_0_CONCAT_wr_ETC__q18 =
|
|
{ 9'd298,
|
|
CASE_write_enq_x_BITS_166_TO_163_0_write_enq_x_ETC__q15 };
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishAlu_0_set_csrData)
|
|
begin
|
|
case (setExecuted_doFinishAlu_0_set_csrData[130:129])
|
|
2'd0, 2'd1:
|
|
CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19 =
|
|
setExecuted_doFinishAlu_0_set_csrData[130:129];
|
|
default: CASE_setExecuted_doFinishAlu_0_set_csrData_BIT_ETC__q19 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(setExecuted_doFinishAlu_1_set_csrData)
|
|
begin
|
|
case (setExecuted_doFinishAlu_1_set_csrData[130:129])
|
|
2'd0, 2'd1:
|
|
CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20 =
|
|
setExecuted_doFinishAlu_1_set_csrData[130:129];
|
|
default: CASE_setExecuted_doFinishAlu_1_set_csrData_BIT_ETC__q20 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[162:161])
|
|
2'd0, 2'd1:
|
|
CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21 =
|
|
write_enq_x[162:161];
|
|
default: CASE_write_enq_x_BITS_162_TO_161_0_write_enq_x_ETC__q21 = 2'd2;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[189:178])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd1952,
|
|
12'd1953,
|
|
12'd1954,
|
|
12'd1955,
|
|
12'd1968,
|
|
12'd1969,
|
|
12'd1970,
|
|
12'd1971,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2496,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3008,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22 =
|
|
write_enq_x[189:178];
|
|
default: CASE_write_enq_x_BITS_189_TO_178_1_write_enq_x_ETC__q22 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(write_enq_x)
|
|
begin
|
|
case (write_enq_x[195:191])
|
|
5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31:
|
|
CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23 =
|
|
write_enq_x[195:191];
|
|
default: CASE_write_enq_x_BITS_195_TO_191_0_write_enq_x_ETC__q23 =
|
|
5'd10;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_fflags_rl <= `BSV_ASSIGNMENT_DELAY 5'h0A;
|
|
m_ldKilled_rl <= `BSV_ASSIGNMENT_DELAY 3'h2;
|
|
m_lsqAtCommitNotified_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
|
|
m_memAccessAtCommit_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
|
|
m_nonMMIOStDone_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
|
|
m_pc_rl <= `BSV_ASSIGNMENT_DELAY
|
|
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_ppc_vaddr_csrData_rl <= `BSV_ASSIGNMENT_DELAY
|
|
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
|
|
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_trap_rl <= `BSV_ASSIGNMENT_DELAY 14'h2AAA;
|
|
end
|
|
else
|
|
begin
|
|
if (m_fflags_rl$EN)
|
|
m_fflags_rl <= `BSV_ASSIGNMENT_DELAY m_fflags_rl$D_IN;
|
|
if (m_ldKilled_rl$EN)
|
|
m_ldKilled_rl <= `BSV_ASSIGNMENT_DELAY m_ldKilled_rl$D_IN;
|
|
if (m_lsqAtCommitNotified_rl$EN)
|
|
m_lsqAtCommitNotified_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_lsqAtCommitNotified_rl$D_IN;
|
|
if (m_memAccessAtCommit_rl$EN)
|
|
m_memAccessAtCommit_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_memAccessAtCommit_rl$D_IN;
|
|
if (m_nonMMIOStDone_rl$EN)
|
|
m_nonMMIOStDone_rl <= `BSV_ASSIGNMENT_DELAY m_nonMMIOStDone_rl$D_IN;
|
|
if (m_pc_rl$EN) m_pc_rl <= `BSV_ASSIGNMENT_DELAY m_pc_rl$D_IN;
|
|
if (m_ppc_vaddr_csrData_rl$EN)
|
|
m_ppc_vaddr_csrData_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_ppc_vaddr_csrData_rl$D_IN;
|
|
if (m_rob_inst_state_rl$EN)
|
|
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY
|
|
m_rob_inst_state_rl$D_IN;
|
|
if (m_spec_bits_rl$EN)
|
|
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_rl$D_IN;
|
|
if (m_trap_rl$EN) m_trap_rl <= `BSV_ASSIGNMENT_DELAY m_trap_rl$D_IN;
|
|
end
|
|
if (m_claimed_phy_reg$EN)
|
|
m_claimed_phy_reg <= `BSV_ASSIGNMENT_DELAY m_claimed_phy_reg$D_IN;
|
|
if (m_csr$EN) m_csr <= `BSV_ASSIGNMENT_DELAY m_csr$D_IN;
|
|
if (m_epochIncremented$EN)
|
|
m_epochIncremented <= `BSV_ASSIGNMENT_DELAY m_epochIncremented$D_IN;
|
|
if (m_iType$EN) m_iType <= `BSV_ASSIGNMENT_DELAY m_iType$D_IN;
|
|
if (m_lsqTag$EN) m_lsqTag <= `BSV_ASSIGNMENT_DELAY m_lsqTag$D_IN;
|
|
if (m_orig_inst$EN) m_orig_inst <= `BSV_ASSIGNMENT_DELAY m_orig_inst$D_IN;
|
|
if (m_rg_dst_reg$EN)
|
|
m_rg_dst_reg <= `BSV_ASSIGNMENT_DELAY m_rg_dst_reg$D_IN;
|
|
if (m_scr$EN) m_scr <= `BSV_ASSIGNMENT_DELAY m_scr$D_IN;
|
|
if (m_will_dirty_fpu_state$EN)
|
|
m_will_dirty_fpu_state <= `BSV_ASSIGNMENT_DELAY
|
|
m_will_dirty_fpu_state$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_claimed_phy_reg = 1'h0;
|
|
m_csr = 13'h0AAA;
|
|
m_epochIncremented = 1'h0;
|
|
m_fflags_rl = 5'h0A;
|
|
m_iType = 5'h0A;
|
|
m_ldKilled_rl = 3'h2;
|
|
m_lsqAtCommitNotified_rl = 1'h0;
|
|
m_lsqTag = 6'h2A;
|
|
m_memAccessAtCommit_rl = 1'h0;
|
|
m_nonMMIOStDone_rl = 1'h0;
|
|
m_orig_inst = 32'hAAAAAAAA;
|
|
m_pc_rl = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_ppc_vaddr_csrData_rl = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
m_rg_dst_reg = 7'h2A;
|
|
m_rob_inst_state_rl = 1'h0;
|
|
m_scr = 6'h2A;
|
|
m_spec_bits_rl = 12'hAAA;
|
|
m_trap_rl = 14'h2AAA;
|
|
m_will_dirty_fpu_state = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishAlu_0_set &&
|
|
setExecuted_doFinishAlu_0_set_csrData[130:129] != 2'd0 &&
|
|
setExecuted_doFinishAlu_0_set_csrData[130:129] != 2'd1 &&
|
|
!m_csr[12] &&
|
|
!m_scr[5])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishAlu_1_set &&
|
|
setExecuted_doFinishAlu_1_set_csrData[130:129] != 2'd0 &&
|
|
setExecuted_doFinishAlu_1_set_csrData[130:129] != 2'd1 &&
|
|
!m_csr[12] &&
|
|
!m_scr[5])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishMem &&
|
|
setExecuted_doFinishMem_access_at_commit &&
|
|
setExecuted_doFinishMem_non_mmio_st_done)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_setExecuted_doFinishMem &&
|
|
setExecuted_doFinishMem_non_mmio_st_done &&
|
|
m_iType != 5'd5)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[18])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[15])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[14])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write_enq && write_enq_x[13])
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkRobRowSynth
|
|
|