192 lines
7.1 KiB
Verilog
192 lines
7.1 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Mon Jul 13 18:29:36 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// decodeBrPred O 130
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// decodeBrPred_pc I 129
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// decodeBrPred_dInst I 145
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// decodeBrPred_histTaken I 1
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// decodeBrPred_is_32b_inst I 1
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//
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// Combinational paths from inputs to outputs:
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// (decodeBrPred_pc,
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// decodeBrPred_dInst,
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// decodeBrPred_histTaken,
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// decodeBrPred_is_32b_inst) -> decodeBrPred
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_decodeBrPred(decodeBrPred_pc,
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decodeBrPred_dInst,
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decodeBrPred_histTaken,
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decodeBrPred_is_32b_inst,
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decodeBrPred);
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// value method decodeBrPred
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input [128 : 0] decodeBrPred_pc;
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input [144 : 0] decodeBrPred_dInst;
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input decodeBrPred_histTaken;
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input decodeBrPred_is_32b_inst;
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output [129 : 0] decodeBrPred;
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// signals for module outputs
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wire [129 : 0] decodeBrPred;
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// remaining internal signals
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reg [128 : 0] CASE_decodeBrPred_dInst_BITS_144_TO_140_8_jTar_ETC__q4;
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wire [128 : 0] jTarget__h28, pcPlusN__h24;
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wire [65 : 0] cr_address__h336, pointer__h157;
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wire [63 : 0] IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23,
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address__h1139,
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x__h635,
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x__h702;
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wire [49 : 0] highBitsfilter__h165,
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highOffsetBits__h166,
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signBits__h163,
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x__h193;
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wire [31 : 0] decodeBrPred_dInst_BITS_31_TO_0__q2;
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wire [25 : 0] IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86;
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wire [18 : 0] INV_decodeBrPred_pc_BITS_108_TO_90__q1;
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wire [13 : 0] b_base__h680,
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cr_addrBits__h337,
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repBoundBits__h172,
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toBoundsM1__h176,
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toBounds__h175,
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x__h673;
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wire [11 : 0] IF_INV_decodeBrPred_pc_BITS_108_TO_90_BIT_0_TH_ETC__q3,
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b_top__h679,
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inc__h1103;
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wire [5 : 0] IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40;
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wire [2 : 0] b_expBotHalf__h571, b_expTopHalf__h569, repBound__h666;
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wire IF_IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_de_ETC___d67,
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IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d73;
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// value method decodeBrPred
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assign decodeBrPred =
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{ decodeBrPred_dInst[144:140] != 5'd9 &&
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decodeBrPred_dInst[144:140] != 5'd11 &&
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decodeBrPred_dInst[144:140] != 5'd12,
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CASE_decodeBrPred_dInst_BITS_144_TO_140_8_jTar_ETC__q4 } ;
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// remaining internal signals
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assign IF_IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_de_ETC___d67 =
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IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23[63] ?
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x__h635[13:0] >= toBounds__h175 &&
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repBoundBits__h172 != cr_addrBits__h337 :
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x__h635[13:0] < toBoundsM1__h176 ;
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assign IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40 =
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INV_decodeBrPred_pc_BITS_108_TO_90__q1[0] ?
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{ b_expTopHalf__h569, b_expBotHalf__h571 } :
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6'd0 ;
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assign IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86 =
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INV_decodeBrPred_pc_BITS_108_TO_90__q1[0] ?
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{ IF_INV_decodeBrPred_pc_BITS_108_TO_90_BIT_0_TH_ETC__q3[11:3],
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40[5:3],
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x__h673[13:3],
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40[2:0] } :
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{ b_top__h679, b_base__h680 } ;
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assign IF_INV_decodeBrPred_pc_BITS_108_TO_90_BIT_0_TH_ETC__q3 =
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INV_decodeBrPred_pc_BITS_108_TO_90__q1[0] ?
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{ decodeBrPred_pc[89:81], 3'd0 } :
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b_top__h679 ;
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assign IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23 =
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{ {32{decodeBrPred_dInst_BITS_31_TO_0__q2[31]}},
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decodeBrPred_dInst_BITS_31_TO_0__q2 } ;
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assign IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d73 =
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(highOffsetBits__h166 == 50'd0 &&
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IF_IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_de_ETC___d67 ||
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40 >=
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6'd50) &&
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decodeBrPred_pc[128] ;
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assign INV_decodeBrPred_pc_BITS_108_TO_90__q1 = ~decodeBrPred_pc[108:90] ;
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assign address__h1139 =
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decodeBrPred_pc[63:0] + { {52{inc__h1103[11]}}, inc__h1103 } ;
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assign b_base__h680 =
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{ decodeBrPred_pc[77:67],
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~decodeBrPred_pc[66],
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decodeBrPred_pc[65:64] } ;
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assign b_expBotHalf__h571 =
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{ ~decodeBrPred_pc[66], decodeBrPred_pc[65:64] } ;
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assign b_expTopHalf__h569 =
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{ ~decodeBrPred_pc[80:79], decodeBrPred_pc[78] } ;
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assign b_top__h679 =
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{ decodeBrPred_pc[89:81],
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~decodeBrPred_pc[80:79],
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decodeBrPred_pc[78] } ;
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assign cr_addrBits__h337 =
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INV_decodeBrPred_pc_BITS_108_TO_90__q1[0] ?
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x__h702[13:0] :
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decodeBrPred_pc[13:0] ;
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assign cr_address__h336 = { 2'd0, decodeBrPred_pc[63:0] } ;
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assign decodeBrPred_dInst_BITS_31_TO_0__q2 = decodeBrPred_dInst[31:0] ;
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assign highBitsfilter__h165 =
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50'h3FFFFFFFFFFFF <<
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40 ;
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assign highOffsetBits__h166 = x__h193 & highBitsfilter__h165 ;
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assign inc__h1103 = decodeBrPred_is_32b_inst ? 12'd4 : 12'd2 ;
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assign jTarget__h28 =
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{ IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d73,
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decodeBrPred_pc[127:90],
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86[25:17],
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~IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86[16:15],
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86[14:3],
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~IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86[2],
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d86[1:0],
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pointer__h157[63:0] } ;
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assign pcPlusN__h24 = { decodeBrPred_pc[128:64], address__h1139 } ;
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assign pointer__h157 =
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cr_address__h336 +
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{ 2'd0,
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IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23 } ;
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assign repBoundBits__h172 = { repBound__h666, 11'd0 } ;
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assign repBound__h666 = x__h673[13:11] - 3'b001 ;
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assign signBits__h163 =
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{50{IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23[63]}} ;
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assign toBoundsM1__h176 = repBoundBits__h172 + ~cr_addrBits__h337 ;
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assign toBounds__h175 = repBoundBits__h172 - cr_addrBits__h337 ;
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assign x__h193 =
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IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23[63:14] ^
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signBits__h163 ;
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assign x__h635 =
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IF_decodeBrPred_dInst_BIT_32_0_THEN_SEXT_decod_ETC___d23 >>
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IF_INV_decodeBrPred_pc_BITS_108_TO_90_8_9_BIT__ETC___d40 ;
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assign x__h673 =
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INV_decodeBrPred_pc_BITS_108_TO_90__q1[0] ?
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{ decodeBrPred_pc[77:67], 3'd0 } :
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b_base__h680 ;
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assign x__h702 =
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decodeBrPred_pc[63:0] >>
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{ b_expTopHalf__h569, b_expBotHalf__h571 } ;
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always@(decodeBrPred_dInst or
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pcPlusN__h24 or jTarget__h28 or decodeBrPred_histTaken)
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begin
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case (decodeBrPred_dInst[144:140])
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5'd8:
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CASE_decodeBrPred_dInst_BITS_144_TO_140_8_jTar_ETC__q4 =
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jTarget__h28;
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5'd10:
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CASE_decodeBrPred_dInst_BITS_144_TO_140_8_jTar_ETC__q4 =
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decodeBrPred_histTaken ? jTarget__h28 : pcPlusN__h24;
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default: CASE_decodeBrPred_dInst_BITS_144_TO_140_8_jTar_ETC__q4 =
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pcPlusN__h24;
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endcase
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end
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endmodule // module_decodeBrPred
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