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e89f7a8130c7bfbcbc7e00a68b24ad53f56020ec
Toooba/src_SSITH_P3/xilinx_ip/hdl
History
Jessica Clarke e89f7a8130 Regenerate verilog
2020-07-13 18:54:53 +01:00
..
ASSIGN1.v
Fixes for synthesis
2020-06-05 17:40:28 +01:00
BRAM2.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
FIFO1.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO2.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO10.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
FIFO20.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFOL1.v
Add missing module (FIFOL1) to Xilinx import.
2019-04-24 21:34:52 -04:00
MakeClock.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
MakeReset0.v
Fixes for synthesis
2020-06-05 17:40:28 +01:00
MakeResetA.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
mkAluDispToRegFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkAluExeToFinFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkAluRegToExeFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkBht.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkCore.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkCoreW.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDCRqMshrWrapper.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDebug_Module.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDirPredictor.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDivExecQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDM_Abstract_Commands.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDM_CSR_Tap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_GPR_Tap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_Mem_Tap.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkDM_Run_Control.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDM_System_Bus.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDoubleDiv.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDoubleFMA.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDoubleSqrt.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDPipeline.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDPRqMshrWrapper.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDTlbSynth.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkDummyStoreBuffer.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkEpochManager.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkFabric_2x3.v
Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D
2020-03-09 14:47:20 -04:00
mkFetchStage.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkFmaExecQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkFpuMulDivDispToRegFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkFpuMulDivRegToExeFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkGSelectGHistReg.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkGSelectPred.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkGShareGHistReg.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkGSharePred.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkIBankWrapper.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkICoCache.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkICRqMshrWrapper.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkIPipeline.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkIPRqMshrWrapper.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkITlb.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkJtagTap.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkL2Tlb.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkLastLvCRqMshr.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkLLCache.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkLLPipeline.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkLSQIssueLdQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkMemDispToRegFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkMemLoader.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkMemRegToExeFifo.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkMinimumExecQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkMMIOInst.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkMulExecQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkNullTransCache.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkP3_Core.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkPLIC_16_2_7.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkPowerOnReset.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkProc.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkRas.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkRegRenamingTable.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkReorderBufferSynth.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkReservationStationAlu.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkReservationStationFpuMulDiv.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkReservationStationMem.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkRFileSynth.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkRobRowSynth.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkScoreboardAggr.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkScoreboardCons.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSimpleRespQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSoC_Map.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSpecTagManager.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSplitLSQ.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSplitTransCache.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkStoreBufferEhr.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSyncBramFifo_w36_d512.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkSyncFifo_w32_d16.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkTagController.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkTourGHistReg.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkTourPred.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkTourPredSecure.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkTrace_Data2_to_Trace_Data.v
Regenerate verilog
2020-06-05 17:49:32 +01:00
mkTV_Encode.v
Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.
2020-03-08 21:29:30 -04:00
mkTV_Xactor.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
mkXilinxFpDiv.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpDivIP.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpDivSim.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpFma.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpFmaIP.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpFmaSim.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpSqrt.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpSqrtIP.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
mkXilinxFpSqrtSim.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_alu.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_aluBr.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_amoExec.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_basicExec.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_brAddrCalc.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_capChecks.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_capInspect.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_capModify.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_checkForException.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_decode.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_decodeBrPred.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_execFpuSimple.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_getControlFlow.v
Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point.
2020-02-12 10:44:30 -05:00
module_prepareBoundsCheck.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_setBoundsALU.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
module_specialRWALU.v
Regenerate verilog
2020-07-13 18:54:53 +01:00
RegFile.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
RegUNInit.v
Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)
2020-03-13 16:38:54 -04:00
reset_guard.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
ResetEither.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
RevertReg.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
SizedFIFO0.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SizedFIFO.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
SyncFIFOLevel.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncHandshake.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncReset0.v
Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)
2020-03-13 16:38:54 -04:00
SyncResetA.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncWire.v
Fixes for synthesis
2020-06-05 17:40:28 +01:00