359 lines
10 KiB
Plaintext
359 lines
10 KiB
Plaintext
package Proc;
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// Copyright (c) 2018 Massachusetts Institute of Technology
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//
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// Permission is hereby granted, free of charge, to any person
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// obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without
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// restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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// Portions Copyright (c) 2019 Bluespec, Inc.
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// ================================================================
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// BSV lib imports
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import Vector::*;
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import GetPut::*;
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import ClientServer::*;
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import Connectable::*;
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import FIFOF :: *;
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import ConfigReg :: *;
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// ----------------
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// BSV additional libs
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import GetPut_Aux :: *;
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// ================================================================
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// Project imports
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// ----------------
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// From MIT RISCY-OOO
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import Types::*;
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import ProcTypes::*;
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import L1CoCache::*;
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import L2Tlb::*;
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import CCTypes::*;
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import CacheUtils::*;
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import LLCache::*;
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import MemLoader::*;
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import L1LLConnect::*;
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import LLCDmaConnect::*;
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import MMIOAddrs::*;
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import MMIOCore::*;
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import DramCommon::*;
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import Performance::*;
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// ----------------
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// From McStriiv
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import AXI4_Types :: *;
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import Fabric_Defs :: *;
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import Core :: *;
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import Proc_IFC :: *;
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import MMIOPlatform :: *;
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import LLC_AXI4_Adapter :: *;
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import MMIO_AXI4_Adapter :: *;
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// ================================================================
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(* synthesize *)
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module mkProc (Proc_IFC);
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// cores
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Vector#(CoreNum, Core) core = ?;
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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core[i] <- mkCore(fromInteger(i));
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end
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// ----------------
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// Verbosity control for debugging
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// Verbosity: 0=quiet; 1=instruction trace; 2=more detail
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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// ----------------
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// Reset requests and responses (TODO: to be implemented)
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FIFOF #(Bit #(0)) f_reset_reqs <- mkFIFOF;
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FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
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// ----------------
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// Communication to/from External debug module (TODO: to be implemented)
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`ifdef INCLUDE_GDB_CONTROL
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// Debugger run-control
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FIFOF #(Bool) f_run_halt_reqs <- mkFIFOF;
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FIFOF #(Bool) f_run_halt_rsps <- mkFIFOF;
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// Stop-request from debugger (e.g., GDB ^C or Dsharp 'stop')
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Reg #(Bool) rg_stop_req <- mkReg (False);
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// Count instrs after step-request from debugger (via dcsr.step)
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Reg #(Bit #(1)) rg_step_count <- mkReg (0);
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// Debugger GPR read/write request/response
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FIFOF #(MemoryRequest #(5, XLEN)) f_gpr_reqs <- mkFIFOF1;
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FIFOF #(MemoryResponse #( XLEN)) f_gpr_rsps <- mkFIFOF1;
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`ifdef ISA_F
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// Debugger FPR read/write request/response
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FIFOF #(MemoryRequest #(5, FLEN)) f_fpr_reqs <- mkFIFOF1;
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FIFOF #(MemoryResponse #( FLEN)) f_fpr_rsps <- mkFIFOF1;
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`endif
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// Debugger CSR read/write request/response
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FIFOF #(MemoryRequest #(12, XLEN)) f_csr_reqs <- mkFIFOF1;
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FIFOF #(MemoryResponse #( XLEN)) f_csr_rsps <- mkFIFOF1;
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`endif
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// ----------------
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// Tandem Verification (TODO: to be implemented)
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`ifdef INCLUDE_TANDEM_VERIF
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FIFOF #(Trace_Data) f_trace_data <- mkFIFOF;
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`endif
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// ----------------
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// MMIO
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MMIO_AXI4_Adapter_IFC mmio_axi4_adapter <- mkMMIO_AXI4_Adapter;
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// MMIO platform
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Vector#(CoreNum, MMIOCoreToPlatform) mmioToP;
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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mmioToP[i] = core[i].mmioToPlatform;
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end
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MMIOPlatform mmioPlatform <- mkMMIOPlatform (mmioToP,
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mmio_axi4_adapter.core_side);
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// last level cache
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LLCache llc <- mkLLCache;
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// connect LLC to L1 caches
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Vector#(L1Num, ChildCacheToParent#(L1Way, void)) l1 = ?;
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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l1[i] = core[i].dCacheToParent;
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l1[i + valueof(CoreNum)] = core[i].iCacheToParent;
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end
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mkL1LLConnect(llc.to_child, l1);
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// ================================================================
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// LLC's DMA connections
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// Core's tlbToMem
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Vector#(CoreNum, TlbMemClient) tlbToMem = ?;
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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tlbToMem[i] = core[i].tlbToMem;
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end
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// Stub out memLoader (TODO: can be Debug Module's access)
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let memLoaderStub = interface MemLoaderMemClient;
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interface memReq = nullFifoDeq;
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interface respSt = nullFifoEnq;
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endinterface;
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mkLLCDmaConnect(llc.dma, memLoaderStub, tlbToMem);
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// ================================================================
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// interface LLC to AXI4
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LLC_AXI4_Adapter_IFC llc_axi4_adapter <- mkLLC_AXi4_Adapter (llc.to_mem);
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// ================================================================
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// Connect stats
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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rule broadcastStats;
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Bool doStats <- core[i].sendDoStats;
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for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin
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core[j].recvDoStats(doStats);
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end
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llc.perf.setStatus(doStats);
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endrule
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end
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// ================================================================
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// Stub out deadlock and renameDebug interfaces
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for(Integer j = 0; j < valueof(CoreNum); j = j+1) begin
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rule rl_dummy1;
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let x <- core[j].deadlock.dCacheCRqStuck.get;
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endrule
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rule rl_dummy2;
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let x <- core[j].deadlock.dCachePRqStuck.get;
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endrule
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rule rl_dummy3;
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let x <- core[j].deadlock.iCacheCRqStuck.get;
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endrule
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rule rl_dummy4;
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let x <- core[j].deadlock.iCachePRqStuck.get;
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endrule
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rule rl_dummy5;
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let x <- core[j].deadlock.renameInstStuck.get;
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endrule
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rule rl_dummy6;
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let x <- core[j].deadlock.renameCorrectPathStuck.get;
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endrule
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rule rl_dummy7;
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let x <- core[j].deadlock.commitInstStuck.get;
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endrule
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rule rl_dummy8;
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let x <- core[j].deadlock.commitUserInstStuck.get;
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endrule
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rule rl_dummy9;
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let x <- core[j].deadlock.checkStarted.get;
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endrule
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rule rl_dummy20;
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let x <- core[j].renameDebug.renameErr.get;
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endrule
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end
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// ================================================================
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// Reset
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rule rl_reset;
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let x <- pop (f_reset_reqs);
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llc_axi4_adapter.reset;
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mmio_axi4_adapter.reset;
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f_reset_rsps.enq (?);
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endrule
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// ----------------
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// Termination detection
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for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
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rule rl_terminate;
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let x <- core[i].coreIndInv.terminate;
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$display ("Core %d terminated", i);
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endrule
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end
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// Print out values written 'tohost'
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rule rl_tohost;
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let x <- mmioPlatform.to_host;
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$display ("mmioPlatform.rl_tohost: 0x%0x (= %0d)", x, x);
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if (x != 0) begin
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// Standard RISC-V ISA tests finish by writing a value tohost with x[0]==1.
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// Further when x[63:1]==0, all tests within the program pass,
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// otherwise x[63:1] = the test within the program that failed.
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let failed_testnum = (x >> 1);
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if (failed_testnum == 0)
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$display ("PASS");
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else
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$display ("FAIL %0d", failed_testnum);
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$finish (0);
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end
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endrule
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// ================================================================
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// ================================================================
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// ================================================================
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// INTERFACE
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// Reset
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interface Server hart0_server_reset = toGPServer (f_reset_reqs, f_reset_rsps);
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// ----------------
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// Start the cores running
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method Action start (Addr startpc, Addr tohostAddr, Addr fromhostAddr);
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action
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for(Integer i = 0; i < valueof(CoreNum); i = i+1)
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core[i].coreReq.start (startpc, tohostAddr, fromhostAddr);
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endaction
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mmioPlatform.start (tohostAddr, fromhostAddr);
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$display ("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h",
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startpc, tohostAddr, fromhostAddr);
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endmethod
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// ----------------
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// SoC fabric connections
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// Fabric master interface for memory (from LLC)
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interface master0 = llc_axi4_adapter.mem_master;
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// Fabric master interface for IO (from MMIOPlatform)
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interface master1 = mmio_axi4_adapter.mmio_master;
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// ----------------
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// External interrupts
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method Action m_external_interrupt_req (x);
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core[0].setMEIP (pack (x));
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endmethod
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method Action s_external_interrupt_req (x);
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core[0].setSEIP (pack (x));
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endmethod
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// ----------------
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// Non-maskable interrupt
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// TODO: fixup: NMIs should send CPU to an NMI vector (TBD in SoC_Map)
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method Action non_maskable_interrupt_req (Bool set_not_clear) = noAction;
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// ----------------
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// For tracing
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method Action set_verbosity (Bit #(4) verbosity);
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cfg_verbosity <= verbosity;
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endmethod
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// ----------------
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// Optional interface to Tandem Verifier
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`ifdef INCLUDE_TANDEM_VERIF
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interface Get trace_data_out = toGet (f_trace_data);
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`endif
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// ----------------
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// Optional interface to Debug Module
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`ifdef INCLUDE_GDB_CONTROL
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// run-control, other
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interface Server hart0_server_run_halt = toGPServer (f_run_halt_reqs, f_run_halt_rsps);
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interface Put hart0_put_other_req;
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method Action put (Bit #(4) req);
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cfg_verbosity <= req;
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endmethod
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endinterface
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// GPR access
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interface MemoryServer hart0_gpr_mem_server = toGPServer (f_gpr_reqs, f_gpr_rsps);
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`ifdef ISA_F
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// FPR access
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interface MemoryServer hart0_fpr_mem_server = toGPServer (f_fpr_reqs, f_fpr_rsps);
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`endif
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// CSR access
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interface MemoryServer hart0_csr_mem_server = toGPServer (f_csr_reqs, f_csr_rsps);
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`endif
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endmodule
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endpackage
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