288 lines
8.6 KiB
Plaintext
288 lines
8.6 KiB
Plaintext
// Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
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package Debug_Module;
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// ================================================================
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// This is the top-level package of a collection that implements the
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// "Debug Module" specified in:
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//
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// "RISC-V External Debug Support"
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// Version 0.13
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// 7c760b0151e43523ab3d2180e7852cd6f27d942c
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// Mon Jul 3 17:04:59 2017 -0700
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// Note: the spec actually represents three (almost) completely
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// independent functionalities:
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// Run Control: to start/stop harts, query their start/stop status, etc.
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// Abstract Commands: to read/write RISC-V registers and RISC-V CSRs
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// System Bus Access: to read/write RISC-V memory/devices
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// The only exception to complete independence is that the Run Control
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// part has a 'reset' for the Debug Module itself, which includes all
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// three parts.
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// Unfortunately the spec is not written to make this three-part
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// organization clear--aspects of the three parts are completely
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// intermingled. Even the address map mixes registers from the three
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// parts.
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// Here, this top-level package is merely a wrapper that dispatches
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// DMI requests to the three packages that implement the three parts:
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// DM_Run_Control
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// DM_Abstract_Commands
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// DM_System_Bus
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// DM_Common contains common spec-level (implementation-independent) definitions.
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// ================================================================
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// Our Debug Module (DM) has a two sides:
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// - GDB/Host-facing
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// - CPU/Platform-facing
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// The GDB/Host-facing side is called DMI (Debug Module Interface) in
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// the spec, and is a simple memory-like read/write interface, into a
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// debug module address space (unrelated to the RISC-V memory address
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// space).
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// The CPU/Platform-facing side has request/response interfaces for
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// CPU run-control, CPU register/CSR access and RISC-V system memory
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// access.
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// ================================================================
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// BSV library imports
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import Memory :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import SpecialFIFOs :: *;
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// ----------------
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// Other library imports
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import Semi_FIFOF :: *;
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import Cur_Cycle :: *;
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// ================================================================
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// Project imports
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import ISA_Decls :: *;
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import AXI4_Types :: *;
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import Fabric_Defs :: *;
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import DM_Common :: *;
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import DM_Run_Control :: *;
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import DM_Abstract_Commands :: *;
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import DM_System_Bus :: *;
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// ================================================================
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export DM_Common :: *;
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export Debug_Module_IFC (..);
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export mkDebug_Module;
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// ================================================================
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// Interface to the Debug Module
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interface Debug_Module_IFC;
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// ----------------
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// DMI (Debug Module Interface) facing remote debugger
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interface DMI dmi;
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// ----------------
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// Facing CPU
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// This section replicated for additional harts.
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// Reset and run-control
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interface Get #(Token) hart0_get_reset_req;
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interface Client #(Bool, Bool) hart0_client_run_halt;
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interface Get #(Bit #(4)) hart0_get_other_req;
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// GPR access
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interface MemoryClient #(5, XLEN) hart0_gpr_mem_client;
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// CSR access
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interface MemoryClient #(12, XLEN) hart0_csr_mem_client;
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Get #(Token) get_ndm_reset_req;
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// Read/Write RISC-V memory
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interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master;
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endinterface
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// ================================================================
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(* synthesize *)
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module mkDebug_Module (Debug_Module_IFC);
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// The three parts
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DM_Run_Control_IFC dm_run_control <- mkDM_Run_Control;
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DM_Abstract_Commands_IFC dm_abstract_commands <- mkDM_Abstract_Commands;
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DM_System_Bus_IFC dm_system_bus <- mkDM_System_Bus;
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FIFOF#(DM_Addr) f_read_addr <- mkBypassFIFOF;
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// ================================================================
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// Reset all three parts when dm_run_control.dmactive is low
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rule rl_reset (! dm_run_control.dmactive);
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$display ("%0d: Debug_Module reset", cur_cycle);
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dm_run_control.reset;
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dm_abstract_commands.reset;
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dm_system_bus.reset;
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endrule
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// ================================================================
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// INTERFACE
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// ----------------
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// Facing GDB/DMI (Debug Module Interface)
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interface DMI dmi;
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method Action read_addr (DM_Addr dm_addr);
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f_read_addr.enq(dm_addr);
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endmethod
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method ActionValue #(DM_Word) read_data;
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let dm_addr = f_read_addr.first;
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f_read_addr.deq;
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DM_Word dm_word = ?;
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_dmstatus)
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|| (dm_addr == dm_addr_hartinfo)
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|| (dm_addr == dm_addr_haltsum)
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|| (dm_addr == dm_addr_hawindowsel)
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|| (dm_addr == dm_addr_hawindow)
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|| (dm_addr == dm_addr_devtreeaddr0)
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|| (dm_addr == dm_addr_authdata)
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|| (dm_addr == dm_addr_haltregion0)
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|| (dm_addr == dm_addr_haltregion31)
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|| (dm_addr == dm_addr_verbosity))
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dm_word <- dm_run_control.av_read (dm_addr);
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else if ( (dm_addr == dm_addr_abstractcs)
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|| (dm_addr == dm_addr_command)
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|| (dm_addr == dm_addr_data0)
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|| (dm_addr == dm_addr_data1)
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|| (dm_addr == dm_addr_data2)
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|| (dm_addr == dm_addr_data3)
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|| (dm_addr == dm_addr_data4)
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|| (dm_addr == dm_addr_data5)
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|| (dm_addr == dm_addr_data6)
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|| (dm_addr == dm_addr_data7)
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|| (dm_addr == dm_addr_data8)
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|| (dm_addr == dm_addr_data9)
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|| (dm_addr == dm_addr_data10)
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|| (dm_addr == dm_addr_data11)
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|| (dm_addr == dm_addr_abstractauto)
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|| (dm_addr == dm_addr_progbuf0))
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dm_word <- dm_abstract_commands.av_read (dm_addr);
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else if ( (dm_addr == dm_addr_sbcs)
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|| (dm_addr == dm_addr_sbaddress0)
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|| (dm_addr == dm_addr_sbaddress1)
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|| (dm_addr == dm_addr_sbaddress2)
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|| (dm_addr == dm_addr_sbdata0)
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|| (dm_addr == dm_addr_sbdata1)
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|| (dm_addr == dm_addr_sbdata2)
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|| (dm_addr == dm_addr_sbdata3))
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dm_word <- dm_system_bus.av_read (dm_addr);
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else begin
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// TODO: set error status?
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dm_word = 0;
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end
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return dm_word;
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endmethod
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method Action write (DM_Addr dm_addr, DM_Word dm_word);
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_dmstatus)
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|| (dm_addr == dm_addr_hartinfo)
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|| (dm_addr == dm_addr_haltsum)
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|| (dm_addr == dm_addr_hawindowsel)
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|| (dm_addr == dm_addr_hawindow)
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|| (dm_addr == dm_addr_devtreeaddr0)
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|| (dm_addr == dm_addr_authdata)
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|| (dm_addr == dm_addr_haltregion0)
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|| (dm_addr == dm_addr_haltregion31)
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|| (dm_addr == dm_addr_verbosity))
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dm_run_control.write (dm_addr, dm_word);
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else if ( (dm_addr == dm_addr_abstractcs)
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|| (dm_addr == dm_addr_command)
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|| (dm_addr == dm_addr_data0)
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|| (dm_addr == dm_addr_data1)
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|| (dm_addr == dm_addr_data2)
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|| (dm_addr == dm_addr_data3)
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|| (dm_addr == dm_addr_data4)
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|| (dm_addr == dm_addr_data5)
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|| (dm_addr == dm_addr_data6)
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|| (dm_addr == dm_addr_data7)
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|| (dm_addr == dm_addr_data8)
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|| (dm_addr == dm_addr_data9)
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|| (dm_addr == dm_addr_data10)
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|| (dm_addr == dm_addr_data11)
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|| (dm_addr == dm_addr_abstractauto)
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|| (dm_addr == dm_addr_progbuf0))
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dm_abstract_commands.write (dm_addr, dm_word);
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else if ( (dm_addr == dm_addr_sbcs)
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|| (dm_addr == dm_addr_sbaddress0)
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|| (dm_addr == dm_addr_sbaddress1)
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|| (dm_addr == dm_addr_sbaddress2)
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|| (dm_addr == dm_addr_sbdata0)
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|| (dm_addr == dm_addr_sbdata1)
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|| (dm_addr == dm_addr_sbdata2)
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|| (dm_addr == dm_addr_sbdata3))
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dm_system_bus.write (dm_addr, dm_word);
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else begin
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// TODO: set error status?
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noAction;
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end
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endmethod
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endinterface
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// ----------------
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// Facing CPU/hart0
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// Reset and run-control
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interface Get hart0_get_reset_req = dm_run_control.hart0_get_reset_req;
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interface Client hart0_client_run_halt = dm_run_control.hart0_client_run_halt;
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interface Get hart0_get_other_req = dm_run_control.hart0_get_other_req;
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// GPR access
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interface MemoryClient hart0_gpr_mem_client = dm_abstract_commands.hart0_gpr_mem_client;
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// CSR access
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interface MemoryClient hart0_csr_mem_client = dm_abstract_commands.hart0_csr_mem_client;
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Get get_ndm_reset_req = dm_run_control.get_ndm_reset_req;
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// Read/Write RISC-V memory
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interface AXI4_Master_IFC master = dm_system_bus.master;
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endmodule
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// ================================================================
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endpackage
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