Toooba

Files

rsnikhil f280287589 Bug fixes; now passing rv64mi-p-csr ISA test

Modified:
    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        Bug fixes in 'getTrap' function:
	- Trap if Fpu regs are accessed but mstatus_fs is "Off" (2'b00)
	- Trap if r/w or privilege denies access to CSR in CSRRW/C/S instruction
    src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
        Bug fix: add support for 'u' bit in function 'getExtensionBits'

2019-04-10 23:06:27 -04:00

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Add support for external debug module.

2019-04-09 14:08:36 -04:00

CPU

Bug fixes; now passing rv64mi-p-access ISA test

2019-04-10 12:42:23 -04:00

Debug_Module

Ensure that halt asserted after ndm reset is not ignored.