Robert Norton ff0221f6bc Fix CHERI Exception numbering to match spec. ...

It looks like PermitUnsealViolation and PermitSetCIDViolation were accidentally renumbered to fill in the gap left by the retired CCallAcessIDCViolation.

2021-08-02 12:15:05 +01:00

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BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Move to Flute standard placement for Tag Cache events, which is just the

2021-06-01 15:17:25 +01:00

CPU

Check in Rename stage for nextPcs of Traps

2021-07-26 07:02:21 +01:00

Debug_Module

Multicore debug cleanups

2021-01-21 20:51:02 +00:00

ISA

Fix CHERI Exception numbering to match spec.

2021-08-02 12:15:05 +01:00

PLIC

Adapt the PLIC instantiation and wiring to support multiple cores

2021-01-31 17:54:43 +00:00

RISCY_OOO

Check in Rename stage for nextPcs of Traps

2021-07-26 07:02:21 +01:00