Add capability size to name of modules and files
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@@ -104,16 +104,24 @@ class BlarneyGenerator(Generator):
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# a typedef of cheri_cap_dec_t which is a decompressed capability
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# generates a _mod.sv file containing a module which combinationally takes an "opaque"
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# capability as the input and gives a decompressed capability as the output
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# In the filename, "cheri" is appended with the in-memory capability width
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# (i.e. the filename will be "cheri64_pkg.sv") so that differently sized capabilities
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# can exist
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class SystemVerilogGenerator(Generator):
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def emit(self):
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cap_type_name = "cheri_cap_t" # the name of the opaque cap type
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cap_dec_type_name = "cheri_cap_dec_t" # the name of the expanded cap type
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cap_dec_mod_name = "cheri_cap_expander" # the name of the expanding module
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cap_in_signal_name = "cap_i" # the name of the input signal to the expanding module
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cap_out_signal_name = "cap_o" # the name of the output signal to the expanding module
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cap_search_string = "cap" # the string required for inferring capability width
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# get the size of in-memory capability by assuming that the name of the
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# modules matches "module_wrap$SIZE_..." and taking just the size part
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in_mem_cap_size = self.modules[0].verilogModuleName()[11:]
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in_mem_cap_size = in_mem_cap_size[:in_mem_cap_size.find("_")]
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pkg_file_name = "cheri_pkg.sv"
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cap_type_name = "cheri_cap_t" # the name of the opaque cap type
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cap_dec_type_name = "cheri_cap_dec_t" # the name of the expanded cap type
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cap_dec_mod_name = "cheri{:s}_cap_expander".format(in_mem_cap_size) # the name of the expanding module
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cap_in_signal_name = "cap_i" # the name of the input signal to the expanding module
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cap_out_signal_name = "cap_o" # the name of the output signal to the expanding module
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cap_search_string = "cap" # the string required for inferring capability width
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pkg_file_name = "cheri{:s}_pkg.sv".format(in_mem_cap_size)
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module_file_name = "{:s}.sv".format(cap_dec_mod_name)
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# prepend namehint if non-empty
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