Default to CAP64 and RISCV architecture

This commit is contained in:
Ivan Ribeiro
2019-07-18 14:52:05 +01:00
parent fdc1cbee2e
commit f948e576d9

View File

@@ -1,11 +1,15 @@
CAP ?= 64
CAP ?= 128
ifeq ($(CAP), 128) ifeq ($(CAP), 128)
BSCFLAGS = -D CAP128 BSCFLAGS = -D CAP128
else else
BSCFLAGS = -D CAP64 BSCFLAGS = -D CAP64
endif endif
ARCH ?= RISCV
ifeq ($(ARCH), RISCV)
BSCFLAGS += -D RISCV
endif
verilog-wrappers: CHERICapWrap.bsv CHERICap.bsv CHERICC_Fat.bsv verilog-wrappers: CHERICapWrap.bsv CHERICap.bsv CHERICC_Fat.bsv
bsc $(BSCFLAGS) -verilog -u $< bsc $(BSCFLAGS) -verilog -u $<