From fd1f7c12a297c0f50f4533578b1261c3de05eb6c Mon Sep 17 00:00:00 2001
From: Ivan Ribeiro <ivanmgribeiro@gmail.com>
Date: Sat, 30 Sep 2023 18:01:28 +0100
Subject: [PATCH] Add SystemVerilog wrappers to generator

---
 fusesoc/fusesoc-script.py | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/fusesoc/fusesoc-script.py b/fusesoc/fusesoc-script.py
index 72b80fa..a3b066a 100644
--- a/fusesoc/fusesoc-script.py
+++ b/fusesoc/fusesoc-script.py
@@ -67,6 +67,21 @@ vfiles = glob.glob(os.path.join(os.getcwd(), "*.v"))
 print("verilog files:")
 print(vfiles)
 
+# generate systemverilog files
+subprocess.call(["python3", bsv_src_root + "/CHERICapWrap.py", "--generator", "sv"] + vfiles, cwd=workdir)
+
+# collect systemverilog files and package files
+pkgfiles = glob.glob(os.path.join(os.getcwd(), "*_pkg.sv"))
+svfiles = glob.glob(os.path.join(os.getcwd(), "*.sv"))
+#
+# remove package files from systemverilog files
+for pkgfile in pkgfiles:
+  svfiles.remove(pkgfile)
+
+print("svfiles and pkgfiles:")
+print(svfiles)
+print(pkgfiles)
+
 # write core file
 with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as f:
   txt = 'CAPI=2:\n'
@@ -74,12 +89,24 @@ with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as
   txt += 'description: "Autogenerated Verilog & SystemVerilog versions of the cheri-cap-lib functions"\n\n'
 
   txt += 'filesets:\n'
+  txt += '  files_pkg:\n'
+  txt += '    files:\n'
+  txt += '      - '
+  txt += '\n      - '.join([os.path.basename(file) for file in pkgfiles])
+  txt += '\n'
+  txt += '    file_type: systemVerilogSource\n'
   txt += '  files_v:\n'
   txt += '    files:\n'
   txt += '      - '
   txt += '\n      - '.join([os.path.basename(file) for file in vfiles])
   txt += '\n'
   txt += '    file_type: verilogSource\n'
+  txt += '  files_sv:\n'
+  txt += '    files:\n'
+  txt += '      - '
+  txt += '\n      - '.join([os.path.basename(file) for file in svfiles])
+  txt += '\n'
+  txt += '    file_type: systemVerilogSource\n'
   txt += '\n'
 
   txt += 'targets:\n'
@@ -87,6 +114,9 @@ with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as
   txt += '    description: "Default target that contains the Verilog files"\n'
   txt += '    filesets:\n'
   txt += '      - files_v\n'
+  txt += '      - files_pkg\n'
+  txt += '      - files_sv\n'
 
   f.write(txt)
 
+