//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name                         I/O  size props
// wrap128_getBase                O    32
// wrap128_getBase_cap            I   115
//
// Combinational paths from inputs to outputs:
//   wrap128_getBase_cap -> wrap128_getBase
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module module_wrap128_getBase(wrap128_getBase_cap,
			      wrap128_getBase);
  // value method wrap128_getBase
  input  [114 : 0] wrap128_getBase_cap;
  output [31 : 0] wrap128_getBase;

  // signals for module outputs
  wire [31 : 0] wrap128_getBase;

  // remaining internal signals
  wire [31 : 0] addBase__h64;
  wire [23 : 0] mask__h65;
  wire [9 : 0] x__h167;

  // value method wrap128_getBase
  assign wrap128_getBase =
	     { wrap128_getBase_cap[113:90] & mask__h65, 8'd0 } +
	     addBase__h64 ;

  // remaining internal signals
  assign addBase__h64 =
	     { {22{x__h167[9]}}, x__h167 } << wrap128_getBase_cap[31:26] ;
  assign mask__h65 = 24'd16777215 << wrap128_getBase_cap[31:26] ;
  assign x__h167 = { wrap128_getBase_cap[1:0], wrap128_getBase_cap[17:10] } ;
endmodule  // module_wrap128_getBase