// // Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87) // // On Tue Feb 17 13:06:25 GMT 2026 // // // Ports: // Name I/O size props // wrap64_modifyOffset O 116 // wrap64_modifyOffset_cap I 115 // wrap64_modifyOffset_offset I 32 // wrap64_modifyOffset_doInc I 1 // // Combinational paths from inputs to outputs: // (wrap64_modifyOffset_cap, // wrap64_modifyOffset_offset, // wrap64_modifyOffset_doInc) -> wrap64_modifyOffset // // `ifdef BSV_ASSIGNMENT_DELAY `else `define BSV_ASSIGNMENT_DELAY `endif `ifdef BSV_POSITIVE_RESET `define BSV_RESET_VALUE 1'b1 `define BSV_RESET_EDGE posedge `else `define BSV_RESET_VALUE 1'b0 `define BSV_RESET_EDGE negedge `endif module module_wrap64_modifyOffset(wrap64_modifyOffset_cap, wrap64_modifyOffset_offset, wrap64_modifyOffset_doInc, wrap64_modifyOffset); // value method wrap64_modifyOffset input [114 : 0] wrap64_modifyOffset_cap; input [31 : 0] wrap64_modifyOffset_offset; input wrap64_modifyOffset_doInc; output [115 : 0] wrap64_modifyOffset; // signals for module outputs wire [115 : 0] wrap64_modifyOffset; // remaining internal signals reg [1 : 0] mask__h585; wire [31 : 0] addBase__h631, pointer__h74, result_d_address__h600, ret___1_address__h611, x__h491, x__h741; wire [23 : 0] highOffsetBits__h81, mask__h632, signBits__h78, x__h108; wire [9 : 0] x__h682; wire [7 : 0] newAddrBits__h584, repBoundBits__h87, result_d_addrBits__h601, toBoundsM1_A__h86, toBoundsM1_B__h89, toBoundsM1__h91, toBounds_A__h85, toBounds_B__h88, toBounds__h90; wire [3 : 0] IF_wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_ETC___d83; wire [2 : 0] repBound__h881; wire IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73, IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34, NOT_wrap64_modifyOffset_offset_SRL_wrap64_modi_ETC___d25, wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71, wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70; // value method wrap64_modifyOffset assign wrap64_modifyOffset = { highOffsetBits__h81 == 24'd0 && IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34 || wrap64_modifyOffset_cap[31:26] >= 6'd24, (highOffsetBits__h81 == 24'd0 && IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34 || wrap64_modifyOffset_cap[31:26] >= 6'd24) && wrap64_modifyOffset_cap[114], result_d_address__h600, result_d_addrBits__h601, wrap64_modifyOffset_cap[73:10], repBound__h881, wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70, wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71, IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73, IF_wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_ETC___d83 } ; // remaining internal signals assign IF_wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_ETC___d83 = { (wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70 == IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ? 2'd0 : ((wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70 && !IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ? 2'd1 : 2'd3), (wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71 == IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ? 2'd0 : ((wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71 && !IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ? 2'd1 : 2'd3) } ; assign IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73 = result_d_addrBits__h601[7:5] < repBound__h881 ; assign IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34 = wrap64_modifyOffset_offset[31] ? NOT_wrap64_modifyOffset_offset_SRL_wrap64_modi_ETC___d25 : (wrap64_modifyOffset_doInc ? x__h491[7:0] < toBoundsM1__h91 : x__h491[7:0] <= toBoundsM1__h91) ; assign NOT_wrap64_modifyOffset_offset_SRL_wrap64_modi_ETC___d25 = x__h491[7:0] >= toBounds__h90 && (!wrap64_modifyOffset_doInc || repBoundBits__h87 != wrap64_modifyOffset_cap[81:74]) ; assign addBase__h631 = { {22{x__h682[9]}}, x__h682 } << wrap64_modifyOffset_cap[31:26] ; assign highOffsetBits__h81 = x__h108 & mask__h632 ; assign mask__h632 = 24'd16777215 << wrap64_modifyOffset_cap[31:26] ; assign newAddrBits__h584 = wrap64_modifyOffset_cap[17:10] + x__h491[7:0] ; assign pointer__h74 = wrap64_modifyOffset_cap[113:82] + wrap64_modifyOffset_offset ; assign repBoundBits__h87 = { wrap64_modifyOffset_cap[9:7], 5'd0 } ; assign repBound__h881 = wrap64_modifyOffset_cap[17:15] - 3'b001 ; assign result_d_addrBits__h601 = wrap64_modifyOffset_doInc ? x__h741[7:0] : { mask__h585, 6'd63 } & newAddrBits__h584 ; assign result_d_address__h600 = wrap64_modifyOffset_doInc ? pointer__h74 : ret___1_address__h611 ; assign ret___1_address__h611 = { wrap64_modifyOffset_cap[113:90] & mask__h632, 8'd0 } + addBase__h631 + wrap64_modifyOffset_offset ; assign signBits__h78 = {24{wrap64_modifyOffset_offset[31]}} ; assign toBoundsM1_A__h86 = { 3'b110, ~wrap64_modifyOffset_cap[14:10] } ; assign toBoundsM1_B__h89 = repBoundBits__h87 + ~wrap64_modifyOffset_cap[81:74] ; assign toBoundsM1__h91 = wrap64_modifyOffset_doInc ? toBoundsM1_B__h89 : toBoundsM1_A__h86 ; assign toBounds_A__h85 = 8'd224 - { 3'b0, wrap64_modifyOffset_cap[14:10] } ; assign toBounds_B__h88 = repBoundBits__h87 - wrap64_modifyOffset_cap[81:74] ; assign toBounds__h90 = wrap64_modifyOffset_doInc ? toBounds_B__h88 : toBounds_A__h85 ; assign wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71 = wrap64_modifyOffset_cap[17:15] < repBound__h881 ; assign wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70 = wrap64_modifyOffset_cap[25:23] < repBound__h881 ; assign x__h108 = wrap64_modifyOffset_offset[31:8] ^ signBits__h78 ; assign x__h491 = wrap64_modifyOffset_offset >> wrap64_modifyOffset_cap[31:26] ; assign x__h682 = { wrap64_modifyOffset_cap[1:0], wrap64_modifyOffset_cap[17:10] } ; assign x__h741 = pointer__h74 >> wrap64_modifyOffset_cap[31:26] ; always@(wrap64_modifyOffset_cap) begin case (wrap64_modifyOffset_cap[31:26]) 6'd25: mask__h585 = 2'b01; 6'd26: mask__h585 = 2'b0; default: mask__h585 = 2'b11; endcase end endmodule // module_wrap64_modifyOffset