//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name                         I/O  size props
// wrap64_setAddr                 O   116
// wrap64_setAddr_cap             I   115
// wrap64_setAddr_addr            I    32
//
// Combinational paths from inputs to outputs:
//   (wrap64_setAddr_cap, wrap64_setAddr_addr) -> wrap64_setAddr
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module module_wrap64_setAddr(wrap64_setAddr_cap,
			     wrap64_setAddr_addr,
			     wrap64_setAddr);
  // value method wrap64_setAddr
  input  [114 : 0] wrap64_setAddr_cap;
  input  [31 : 0] wrap64_setAddr_addr;
  output [115 : 0] wrap64_setAddr;

  // signals for module outputs
  wire [115 : 0] wrap64_setAddr;

  // remaining internal signals
  wire [31 : 0] x__h102;
  wire [23 : 0] deltaAddrHi__h76, deltaAddrUpper__h78, mask__h77;
  wire [3 : 0] IF_wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap_ETC___d40;
  wire [2 : 0] repBound__h430;
  wire [1 : 0] x__h84;
  wire SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18,
       wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30,
       wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29,
       wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28;

  // value method wrap64_setAddr
  assign wrap64_setAddr =
	     { SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18,
	       SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18 &&
	       wrap64_setAddr_cap[114],
	       wrap64_setAddr_addr,
	       x__h102[7:0],
	       wrap64_setAddr_cap[73:10],
	       repBound__h430,
	       wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28,
	       wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29,
	       wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30,
	       IF_wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap_ETC___d40 } ;

  // remaining internal signals
  assign IF_wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap_ETC___d40 =
	     { (wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28 ==
		wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
		 2'd0 :
		 ((wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28 &&
		   !wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
		    2'd1 :
		    2'd3),
	       (wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29 ==
		wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
		 2'd0 :
		 ((wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29 &&
		   !wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
		    2'd1 :
		    2'd3) } ;
  assign SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18 =
	     deltaAddrHi__h76 == deltaAddrUpper__h78 ;
  assign deltaAddrHi__h76 =
	     { {22{x__h84[1]}}, x__h84 } << wrap64_setAddr_cap[31:26] ;
  assign deltaAddrUpper__h78 =
	     (wrap64_setAddr_addr[31:8] & mask__h77) -
	     (wrap64_setAddr_cap[113:90] & mask__h77) ;
  assign mask__h77 = 24'd16777215 << wrap64_setAddr_cap[31:26] ;
  assign repBound__h430 = wrap64_setAddr_cap[17:15] - 3'b001 ;
  assign wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30 =
	     x__h102[7:5] < repBound__h430 ;
  assign wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29 =
	     wrap64_setAddr_cap[17:15] < repBound__h430 ;
  assign wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28 =
	     wrap64_setAddr_cap[25:23] < repBound__h430 ;
  assign x__h102 = wrap64_setAddr_addr >> wrap64_setAddr_cap[31:26] ;
  assign x__h84 =
	     { 1'b0, x__h102[7:5] < wrap64_setAddr_cap[9:7] } -
	     { 1'b0, wrap64_setAddr_cap[4] } ;
endmodule  // module_wrap64_setAddr