//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name                         I/O  size props
// wrap64_setKind                 O   115
// wrap64_setKind_cap             I   115
// wrap64_setKind_kind            I     7
//
// Combinational paths from inputs to outputs:
//   (wrap64_setKind_cap, wrap64_setKind_kind) -> wrap64_setKind
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module module_wrap64_setKind(wrap64_setKind_cap,
			     wrap64_setKind_kind,
			     wrap64_setKind);
  // value method wrap64_setKind
  input  [114 : 0] wrap64_setKind_cap;
  input  [6 : 0] wrap64_setKind_kind;
  output [114 : 0] wrap64_setKind;

  // signals for module outputs
  wire [114 : 0] wrap64_setKind;

  // remaining internal signals
  reg [3 : 0] CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1;

  // value method wrap64_setKind
  assign wrap64_setKind =
	     { wrap64_setKind_cap[114:61],
	       CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1,
	       wrap64_setKind_cap[56:0] } ;

  // remaining internal signals
  always@(wrap64_setKind_kind)
  begin
    case (wrap64_setKind_kind[6:4])
      3'd0: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd15;
      3'd1: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd14;
      3'd2: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd13;
      3'd3: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd12;
      default: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 =
		   wrap64_setKind_kind[3:0];
    endcase
  end
endmodule  // module_wrap64_setKind