//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name                         I/O  size props
// wrap64_setOffset               O   116
// wrap64_setOffset_cap           I   115
// wrap64_setOffset_offset        I    32
//
// Combinational paths from inputs to outputs:
//   (wrap64_setOffset_cap, wrap64_setOffset_offset) -> wrap64_setOffset
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module module_wrap64_setOffset(wrap64_setOffset_cap,
			       wrap64_setOffset_offset,
			       wrap64_setOffset);
  // value method wrap64_setOffset
  input  [114 : 0] wrap64_setOffset_cap;
  input  [31 : 0] wrap64_setOffset_offset;
  output [115 : 0] wrap64_setOffset;

  // signals for module outputs
  wire [115 : 0] wrap64_setOffset;

  // remaining internal signals
  reg [1 : 0] mask__h560;
  wire [31 : 0] addBase__h594, result_d_address__h572, x__h488;
  wire [23 : 0] highOffsetBits__h80, mask__h595, signBits__h77, x__h107;
  wire [9 : 0] x__h645;
  wire [7 : 0] newAddrBits__h559,
	       result_d_addrBits__h573,
	       toBoundsM1__h90,
	       toBounds__h89;
  wire [3 : 0] IF_wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wr_ETC___d62;
  wire [2 : 0] repBound__h826;
  wire IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52,
       IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19,
       wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50,
       wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49;

  // value method wrap64_setOffset
  assign wrap64_setOffset =
	     { highOffsetBits__h80 == 24'd0 &&
	       IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19 ||
	       wrap64_setOffset_cap[31:26] >= 6'd24,
	       (highOffsetBits__h80 == 24'd0 &&
		IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19 ||
		wrap64_setOffset_cap[31:26] >= 6'd24) &&
	       wrap64_setOffset_cap[114],
	       result_d_address__h572,
	       result_d_addrBits__h573,
	       wrap64_setOffset_cap[73:10],
	       repBound__h826,
	       wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49,
	       wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50,
	       IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52,
	       IF_wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wr_ETC___d62 } ;

  // remaining internal signals
  assign IF_wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wr_ETC___d62 =
	     { (wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49 ==
		IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
		 2'd0 :
		 ((wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49 &&
		   !IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
		    2'd1 :
		    2'd3),
	       (wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50 ==
		IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
		 2'd0 :
		 ((wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50 &&
		   !IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
		    2'd1 :
		    2'd3) } ;
  assign IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52 =
	     result_d_addrBits__h573[7:5] < repBound__h826 ;
  assign IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19 =
	     wrap64_setOffset_offset[31] ?
	       x__h488[7:0] >= toBounds__h89 :
	       x__h488[7:0] <= toBoundsM1__h90 ;
  assign addBase__h594 =
	     { {22{x__h645[9]}}, x__h645 } << wrap64_setOffset_cap[31:26] ;
  assign highOffsetBits__h80 = x__h107 & mask__h595 ;
  assign mask__h595 = 24'd16777215 << wrap64_setOffset_cap[31:26] ;
  assign newAddrBits__h559 = wrap64_setOffset_cap[17:10] + x__h488[7:0] ;
  assign repBound__h826 = wrap64_setOffset_cap[17:15] - 3'b001 ;
  assign result_d_addrBits__h573 = { mask__h560, 6'd63 } & newAddrBits__h559 ;
  assign result_d_address__h572 =
	     { wrap64_setOffset_cap[113:90] & mask__h595, 8'd0 } +
	     addBase__h594 +
	     wrap64_setOffset_offset ;
  assign signBits__h77 = {24{wrap64_setOffset_offset[31]}} ;
  assign toBoundsM1__h90 = { 3'b110, ~wrap64_setOffset_cap[14:10] } ;
  assign toBounds__h89 = 8'd224 - { 3'b0, wrap64_setOffset_cap[14:10] } ;
  assign wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50 =
	     wrap64_setOffset_cap[17:15] < repBound__h826 ;
  assign wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49 =
	     wrap64_setOffset_cap[25:23] < repBound__h826 ;
  assign x__h107 = wrap64_setOffset_offset[31:8] ^ signBits__h77 ;
  assign x__h488 = wrap64_setOffset_offset >> wrap64_setOffset_cap[31:26] ;
  assign x__h645 =
	     { wrap64_setOffset_cap[1:0], wrap64_setOffset_cap[17:10] } ;
  always@(wrap64_setOffset_cap)
  begin
    case (wrap64_setOffset_cap[31:26])
      6'd25: mask__h560 = 2'b01;
      6'd26: mask__h560 = 2'b0;
      default: mask__h560 = 2'b11;
    endcase
  end
endmodule  // module_wrap64_setOffset