06eff948d9
files_root is actually the directory where the fusesoc command was executed, but what we want here is the location of the python file being executed so we can find the bluespec sources
125 lines
3.2 KiB
Python
125 lines
3.2 KiB
Python
import yaml
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import subprocess
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import argparse
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import shutil
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import os
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import glob
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# get yaml file location from single argument
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argparser = argparse.ArgumentParser()
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argparser.add_argument('yaml_file')
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args = argparser.parse_args()
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# load yaml file
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with open(args.yaml_file, "r") as yamlfile:
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try:
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print(yamlfile)
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yamlcfg = yaml.safe_load(yamlfile)
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except yaml.YAMLError as exc:
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print(exc)
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# TODO debug
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print(yamlcfg)
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print(yamlcfg['parameters']['capwidth'])
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# use capwidth if provided, or default to CAP64
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cfgwidth = yamlcfg["parameters"]["capwidth"]
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capwidth = "CAP64" if cfgwidth in [None, ""] else cfgwidth
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# TODO debug
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print("capwidth:")
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print(capwidth)
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# get current working directory for file generation
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workdir = os.getcwd()
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# location of source files is actually one level above the location of the core file
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bsv_src_root = os.path.join(os.path.dirname(__file__), "..")
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print("bsv_src_root")
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print(bsv_src_root)
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# set up bluespec command + arguments
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bscargs = list()
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bscargs.extend(["bsc"])
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bscargs.extend(["-vdir", workdir])
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bscargs.extend(["-bdir", workdir])
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bscargs.extend(["-simdir", workdir])
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bscargs.extend(["-D", "{}".format(capwidth)])
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bscargs.extend(["-D", "RISCV"])
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bscargs.extend(["-verilog"])
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bscargs.extend(["-u"])
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bscargs.extend(["CHERICapWrap.bsv"])
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# TODO debug
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print(bscargs)
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# blocking call to bsc to generate verilog files
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subprocess.call(bscargs, cwd=bsv_src_root)
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print("CCL AUTOGEN NAME:")
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print("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]))
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# collect verilog files
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vfiles = glob.glob(os.path.join(os.getcwd(), "*.v"))
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print("verilog files:")
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print(vfiles)
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# generate systemverilog files
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subprocess.call(["python3", bsv_src_root + "/CHERICapWrap.py", "--generator", "sv"] + vfiles, cwd=workdir)
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# collect systemverilog files and package files
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pkgfiles = glob.glob(os.path.join(os.getcwd(), "*_pkg.sv"))
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svfiles = glob.glob(os.path.join(os.getcwd(), "*.sv"))
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#
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# remove package files from systemverilog files
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for pkgfile in pkgfiles:
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svfiles.remove(pkgfile)
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print("svfiles and pkgfiles:")
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print(svfiles)
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print(pkgfiles)
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# write core file
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with open("cheri-cap-lib-verilog-autogen-{}.core".format(capwidth[3:]), 'w') as f:
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txt = 'CAPI=2:\n'
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txt += 'name: "ucam:cheri:cheri-cap-lib-verilog-autogen-{}"\n'.format(capwidth[3:])
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txt += 'description: "Autogenerated Verilog & SystemVerilog versions of the cheri-cap-lib functions"\n\n'
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txt += 'filesets:\n'
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txt += ' files_pkg:\n'
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txt += ' files:\n'
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txt += ' - '
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txt += '\n - '.join([os.path.basename(file) for file in pkgfiles])
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txt += '\n'
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txt += ' file_type: systemVerilogSource\n'
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txt += ' files_v:\n'
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txt += ' files:\n'
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txt += ' - '
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txt += '\n - '.join([os.path.basename(file) for file in vfiles])
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txt += '\n'
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txt += ' file_type: verilogSource\n'
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txt += ' files_sv:\n'
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txt += ' files:\n'
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txt += ' - '
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txt += '\n - '.join([os.path.basename(file) for file in svfiles])
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txt += '\n'
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txt += ' file_type: systemVerilogSource\n'
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txt += '\n'
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txt += 'targets:\n'
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txt += ' default:\n'
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txt += ' description: "Default target that contains the Verilog files"\n'
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txt += ' filesets:\n'
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txt += ' - files_v\n'
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txt += ' - files_pkg\n'
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txt += ' - files_sv\n'
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f.write(txt)
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