bea5e463c6
Various minor changes to Blarney wrapper script: * Blarney.BV -> Blarney.Core.BV * Custom now needs input widths as well as output widths * Custom now takes additional argument (netlist generator -> Nothing) * makePrim1 now takes 2 params, not 3
94 lines
3.3 KiB
Python
Executable File
94 lines
3.3 KiB
Python
Executable File
#! /usr/bin/env python3
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import argparse
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import re
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parser = argparse.ArgumentParser(description=
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'''Generates a Blarney wrapper for the given Bluespec generated verilog file
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containing a module definition of a purely combinational CHERI function.
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''')
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parser.add_argument('verilog_files', metavar='VERILOG_FILE', type=str, nargs='+',
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help='The file(s) to process')
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parser.add_argument('--output', '-o', metavar='OUTPUT_FILE', type=str, nargs='?',
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default="CHERIBlarneyWrappers",
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help='The output Blarney Haskell module to generate')
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args = parser.parse_args()
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class BlarneyWrapper:
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def __init__(self, size, name, ins, out):
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self.size = size
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self.name = name
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self.ins = ins
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self.out = out
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def verilogModuleName(self):
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return "module_wrap{:d}_{:s}".format(self.size, self.name)
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def verilogInputNames(self):
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return ["wrap{:d}_{:s}_{:s}".format(self.size, self.name, nm)
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for nm in [x[0] for x in self.ins]]
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def verilogOutputName(self):
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return "wrap{:d}_{:s}".format(self.size, self.name)
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def emitBlarney(self):
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ins_names = [x[0] for x in self.ins]
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ins_wdths = [x[1] for x in self.ins]
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str_type = "{:s} :: {:s}{:s}{:s}".format(
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self.name,
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" -> ".join(["Bit {:d}".format(n) for n in ins_wdths]),
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" -> " if self.ins else "",
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"Bit {:d}".format(self.out[1]))
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str_decl = "{:s} {:s} = FromBV $\n makePrim1 (Custom \"{:s}\" [{:s}] [{:s}] [] False Nothing) [{:s}]".format(
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self.name, " ".join(ins_names),
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self.verilogModuleName(),
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", ".join(["(\"{:s}\", {:d})".format(n, w)
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for (n, w) in zip(self.verilogInputNames(),
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ins_wdths)]),
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"(\"{:s}\", {:d})".format(self.verilogOutputName(), self.out[1]),
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", ".join(["toBV {:s}".format(nm) for nm in ins_names]))
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return "{:s}\n{:s}".format(str_type, str_decl)
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def main():
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# define module regexp
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modDecl = re.compile("^module\s+module_wrap(\d+)_(\w+)\(")
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# TODO handle size 1
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#
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wrappers = []
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for fname in args.verilog_files:
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size = 0
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name = None
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ins = []
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out = ("",0)
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with open(fname, "r") as f:
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for ln in f:
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modM = modDecl.match(ln)
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if modM:
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size = int(modM.group(1))
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name = modM.group(2)
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break
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if not name:
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print("Couldn't find a valid Verilog module definition")
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exit(-1)
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# define input/output regexp
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inDecl = re.compile("^\s*input(\s+\[(\d+)\s+:\s+0\])?\s+wrap(\d+)_"+name+"_(\w+);")
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outDecl = re.compile("^\s*output(\s+\[(\d+)\s+:\s+0\])?\s+wrap(\d+)_"+name+";")
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for ln in f:
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inM = inDecl.match(ln)
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outM = outDecl.match(ln)
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if inM:
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ins.append((inM.group(4), (int(inM.group(2)) + 1) if inM.group(1) else 1))
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elif outM:
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out = (name, (int(outM.group(2)) + 1) if outM.group(1) else 1)
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#else:
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# print("===>> no match for line: {:s}".format(ln))
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wrappers.append(BlarneyWrapper(size, name, ins, out))
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with open(args.output+".hs", "w") as f:
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#print("module CHERI{:d} where\n".format(size))
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f.write("module "+args.output+" where\n\n")
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f.write("import Blarney\n")
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f.write("import Blarney.Core.BV\n")
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for w in wrappers:
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f.write("\n{:s}\n".format(w.emitBlarney()))
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if __name__ == "__main__":
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main()
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