116 lines
4.2 KiB
Verilog
116 lines
4.2 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_fromMem O 115
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// wrap128_fromMem_mem_cap I 89
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//
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// Combinational paths from inputs to outputs:
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// wrap128_fromMem_mem_cap -> wrap128_fromMem
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_fromMem(wrap128_fromMem_mem_cap,
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wrap128_fromMem);
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// value method wrap128_fromMem
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input [88 : 0] wrap128_fromMem_mem_cap;
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output [114 : 0] wrap128_fromMem;
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// signals for module outputs
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wire [114 : 0] wrap128_fromMem;
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// remaining internal signals
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wire [88 : 0] thin__h113;
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wire [31 : 0] x__h428;
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wire [21 : 0] IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d33;
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wire [7 : 0] bounds_topBits__h585,
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res_addrBits__h131,
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x__h618,
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x__h638,
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x__h653;
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wire [5 : 0] x__h462;
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wire [4 : 0] IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d52;
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wire [2 : 0] repBound__h698, tb__h695;
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wire [1 : 0] carry_out__h553,
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impliedTopBits__h555,
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len_correction__h554,
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x__h635;
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wire IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39,
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40,
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42;
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// value method wrap128_fromMem
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assign wrap128_fromMem =
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{ thin__h113[88],
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thin__h113[31:0],
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res_addrBits__h131,
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thin__h113[87:46],
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d33,
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repBound__h698,
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39,
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40,
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d52 } ;
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// remaining internal signals
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assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d33 =
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{ thin__h113[46] ? x__h462 : 6'd0, x__h618, x__h638 } ;
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assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39 =
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tb__h695 < repBound__h698 ;
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assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40 =
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x__h638[7:5] < repBound__h698 ;
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assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42 =
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res_addrBits__h131[7:5] < repBound__h698 ;
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assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d52 =
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{ IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42,
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(IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39 ==
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
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2'd0 :
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((IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39 &&
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!IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
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2'd1 :
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2'd3),
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(IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40 ==
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IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
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2'd0 :
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((IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40 &&
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!IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
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2'd1 :
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2'd3) } ;
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assign bounds_topBits__h585 = { 2'h2, thin__h113[45:43], 3'd0 } ;
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assign carry_out__h553 = (x__h653[5:0] < x__h638[5:0]) ? 2'b01 : 2'b0 ;
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assign impliedTopBits__h555 = x__h635 + len_correction__h554 ;
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assign len_correction__h554 = thin__h113[46] ? 2'b01 : 2'b0 ;
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assign repBound__h698 = x__h638[7:5] - 3'b001 ;
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assign res_addrBits__h131 =
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thin__h113[46] ? x__h428[7:0] : thin__h113[7:0] ;
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assign tb__h695 = { impliedTopBits__h555, x__h653[5] } ;
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assign thin__h113 = wrap128_fromMem_mem_cap ^ 89'h00007D55555430200000000 ;
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assign x__h428 = thin__h113[31:0] >> x__h462 ;
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assign x__h462 = { thin__h113[42:40], thin__h113[34:32] } ;
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assign x__h618 = { impliedTopBits__h555, x__h653[5:0] } ;
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assign x__h635 = x__h638[7:6] + carry_out__h553 ;
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assign x__h638 =
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thin__h113[46] ?
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{ thin__h113[39:35], 3'd0 } :
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thin__h113[39:32] ;
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assign x__h653 = thin__h113[46] ? bounds_topBits__h585 : thin__h113[47:40] ;
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endmodule // module_wrap128_fromMem
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