57 lines
1.6 KiB
Verilog
57 lines
1.6 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_getOffset O 32
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// wrap128_getOffset_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap128_getOffset_cap -> wrap128_getOffset
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_getOffset(wrap128_getOffset_cap,
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wrap128_getOffset);
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// value method wrap128_getOffset
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input [114 : 0] wrap128_getOffset_cap;
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output [31 : 0] wrap128_getOffset;
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// signals for module outputs
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wire [31 : 0] wrap128_getOffset;
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// remaining internal signals
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wire [31 : 0] addrLSB__h68, x__h204, x__h79, x__h81, y__h203;
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wire [9 : 0] base__h66, offset__h67;
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// value method wrap128_getOffset
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assign wrap128_getOffset = x__h79 | addrLSB__h68 ;
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// remaining internal signals
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assign addrLSB__h68 = wrap128_getOffset_cap[113:82] & y__h203 ;
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assign base__h66 =
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{ wrap128_getOffset_cap[1:0], wrap128_getOffset_cap[17:10] } ;
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assign offset__h67 = { 2'b0, wrap128_getOffset_cap[81:74] } - base__h66 ;
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assign x__h204 = 32'hFFFFFFFF << wrap128_getOffset_cap[31:26] ;
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assign x__h79 = x__h81 << wrap128_getOffset_cap[31:26] ;
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assign x__h81 = { {22{offset__h67[9]}}, offset__h67 } ;
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assign y__h203 = ~x__h204 ;
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endmodule // module_wrap128_getOffset
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