42 lines
980 B
Verilog
42 lines
980 B
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
|
|
//
|
|
// On Tue Feb 17 13:11:39 GMT 2026
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// wrap128_getSoftPerms O 16 const
|
|
// wrap128_getSoftPerms_cap I 115 unused
|
|
//
|
|
// No combinational paths from inputs to outputs
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module module_wrap128_getSoftPerms(wrap128_getSoftPerms_cap,
|
|
wrap128_getSoftPerms);
|
|
// value method wrap128_getSoftPerms
|
|
input [114 : 0] wrap128_getSoftPerms_cap;
|
|
output [15 : 0] wrap128_getSoftPerms;
|
|
|
|
// signals for module outputs
|
|
wire [15 : 0] wrap128_getSoftPerms;
|
|
|
|
// value method wrap128_getSoftPerms
|
|
assign wrap128_getSoftPerms = 16'd0 ;
|
|
endmodule // module_wrap128_getSoftPerms
|
|
|