115 lines
4.4 KiB
Verilog
115 lines
4.4 KiB
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
|
|
//
|
|
// On Tue Feb 17 13:11:39 GMT 2026
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// wrap128_incOffset O 116
|
|
// wrap128_incOffset_cap I 115
|
|
// wrap128_incOffset_inc I 32
|
|
//
|
|
// Combinational paths from inputs to outputs:
|
|
// (wrap128_incOffset_cap, wrap128_incOffset_inc) -> wrap128_incOffset
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module module_wrap128_incOffset(wrap128_incOffset_cap,
|
|
wrap128_incOffset_inc,
|
|
wrap128_incOffset);
|
|
// value method wrap128_incOffset
|
|
input [114 : 0] wrap128_incOffset_cap;
|
|
input [31 : 0] wrap128_incOffset_inc;
|
|
output [115 : 0] wrap128_incOffset;
|
|
|
|
// signals for module outputs
|
|
wire [115 : 0] wrap128_incOffset;
|
|
|
|
// remaining internal signals
|
|
wire [31 : 0] result_d_address__h574, x__h488, x__h597;
|
|
wire [23 : 0] highBitsfilter__h79,
|
|
highOffsetBits__h80,
|
|
signBits__h77,
|
|
x__h107;
|
|
wire [7 : 0] repBoundBits__h86, toBoundsM1__h90, toBounds__h89;
|
|
wire [3 : 0] IF_wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d53;
|
|
wire [2 : 0] repBound__h738;
|
|
wire IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23,
|
|
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43,
|
|
wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41,
|
|
wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40;
|
|
|
|
// value method wrap128_incOffset
|
|
assign wrap128_incOffset =
|
|
{ highOffsetBits__h80 == 24'd0 &&
|
|
IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23 ||
|
|
wrap128_incOffset_cap[31:26] >= 6'd24,
|
|
(highOffsetBits__h80 == 24'd0 &&
|
|
IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23 ||
|
|
wrap128_incOffset_cap[31:26] >= 6'd24) &&
|
|
wrap128_incOffset_cap[114],
|
|
result_d_address__h574,
|
|
x__h597[7:0],
|
|
wrap128_incOffset_cap[73:10],
|
|
repBound__h738,
|
|
wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40,
|
|
wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41,
|
|
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43,
|
|
IF_wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d53 } ;
|
|
|
|
// remaining internal signals
|
|
assign IF_wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d53 =
|
|
{ (wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40 ==
|
|
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
|
|
2'd0 :
|
|
((wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40 &&
|
|
!wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
|
|
2'd1 :
|
|
2'd3),
|
|
(wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41 ==
|
|
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
|
|
2'd0 :
|
|
((wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41 &&
|
|
!wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
|
|
2'd1 :
|
|
2'd3) } ;
|
|
assign IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23 =
|
|
wrap128_incOffset_inc[31] ?
|
|
x__h488[7:0] >= toBounds__h89 &&
|
|
repBoundBits__h86 != wrap128_incOffset_cap[81:74] :
|
|
x__h488[7:0] < toBoundsM1__h90 ;
|
|
assign highBitsfilter__h79 = 24'd16777215 << wrap128_incOffset_cap[31:26] ;
|
|
assign highOffsetBits__h80 = x__h107 & highBitsfilter__h79 ;
|
|
assign repBoundBits__h86 = { wrap128_incOffset_cap[9:7], 5'd0 } ;
|
|
assign repBound__h738 = wrap128_incOffset_cap[17:15] - 3'b001 ;
|
|
assign result_d_address__h574 =
|
|
wrap128_incOffset_cap[113:82] + wrap128_incOffset_inc ;
|
|
assign signBits__h77 = {24{wrap128_incOffset_inc[31]}} ;
|
|
assign toBoundsM1__h90 = repBoundBits__h86 + ~wrap128_incOffset_cap[81:74] ;
|
|
assign toBounds__h89 = repBoundBits__h86 - wrap128_incOffset_cap[81:74] ;
|
|
assign wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43 =
|
|
x__h597[7:5] < repBound__h738 ;
|
|
assign wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41 =
|
|
wrap128_incOffset_cap[17:15] < repBound__h738 ;
|
|
assign wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40 =
|
|
wrap128_incOffset_cap[25:23] < repBound__h738 ;
|
|
assign x__h107 = wrap128_incOffset_inc[31:8] ^ signBits__h77 ;
|
|
assign x__h488 = wrap128_incOffset_inc >> wrap128_incOffset_cap[31:26] ;
|
|
assign x__h597 = result_d_address__h574 >> wrap128_incOffset_cap[31:26] ;
|
|
endmodule // module_wrap128_incOffset
|
|
|