43 lines
997 B
Verilog
43 lines
997 B
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_isValidCap O 1
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// wrap128_isValidCap_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap128_isValidCap_cap -> wrap128_isValidCap
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_isValidCap(wrap128_isValidCap_cap,
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wrap128_isValidCap);
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// value method wrap128_isValidCap
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input [114 : 0] wrap128_isValidCap_cap;
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output wrap128_isValidCap;
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// signals for module outputs
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wire wrap128_isValidCap;
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// value method wrap128_isValidCap
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assign wrap128_isValidCap = wrap128_isValidCap_cap[114] ;
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endmodule // module_wrap128_isValidCap
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