177 lines
6.6 KiB
Verilog
177 lines
6.6 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_modifyOffset O 116
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// wrap128_modifyOffset_cap I 115
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// wrap128_modifyOffset_offset I 32
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// wrap128_modifyOffset_doInc I 1
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//
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// Combinational paths from inputs to outputs:
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// (wrap128_modifyOffset_cap,
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// wrap128_modifyOffset_offset,
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// wrap128_modifyOffset_doInc) -> wrap128_modifyOffset
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_modifyOffset(wrap128_modifyOffset_cap,
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wrap128_modifyOffset_offset,
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wrap128_modifyOffset_doInc,
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wrap128_modifyOffset);
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// value method wrap128_modifyOffset
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input [114 : 0] wrap128_modifyOffset_cap;
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input [31 : 0] wrap128_modifyOffset_offset;
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input wrap128_modifyOffset_doInc;
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output [115 : 0] wrap128_modifyOffset;
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// signals for module outputs
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wire [115 : 0] wrap128_modifyOffset;
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// remaining internal signals
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reg [1 : 0] mask__h585;
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wire [31 : 0] addBase__h631,
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pointer__h74,
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result_d_address__h600,
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ret___1_address__h611,
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x__h491,
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x__h741;
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wire [23 : 0] highOffsetBits__h81, mask__h632, signBits__h78, x__h108;
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wire [9 : 0] x__h682;
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wire [7 : 0] newAddrBits__h584,
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repBoundBits__h87,
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result_d_addrBits__h601,
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toBoundsM1_A__h86,
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toBoundsM1_B__h89,
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toBoundsM1__h91,
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toBounds_A__h85,
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toBounds_B__h88,
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toBounds__h90;
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wire [3 : 0] IF_wrap128_modifyOffset_cap_BITS_25_TO_23_9_UL_ETC___d83;
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wire [2 : 0] repBound__h881;
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wire IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73,
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IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34,
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NOT_wrap128_modifyOffset_offset_SRL_wrap128_mo_ETC___d25,
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wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71,
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wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70;
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// value method wrap128_modifyOffset
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assign wrap128_modifyOffset =
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{ highOffsetBits__h81 == 24'd0 &&
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IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34 ||
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wrap128_modifyOffset_cap[31:26] >= 6'd24,
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(highOffsetBits__h81 == 24'd0 &&
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IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34 ||
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wrap128_modifyOffset_cap[31:26] >= 6'd24) &&
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wrap128_modifyOffset_cap[114],
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result_d_address__h600,
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result_d_addrBits__h601,
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wrap128_modifyOffset_cap[73:10],
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repBound__h881,
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wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70,
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wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71,
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IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73,
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IF_wrap128_modifyOffset_cap_BITS_25_TO_23_9_UL_ETC___d83 } ;
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// remaining internal signals
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assign IF_wrap128_modifyOffset_cap_BITS_25_TO_23_9_UL_ETC___d83 =
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{ (wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70 ==
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IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
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2'd0 :
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((wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70 &&
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!IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
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2'd1 :
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2'd3),
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(wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71 ==
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IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
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2'd0 :
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((wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71 &&
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!IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
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2'd1 :
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2'd3) } ;
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assign IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73 =
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result_d_addrBits__h601[7:5] < repBound__h881 ;
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assign IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34 =
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wrap128_modifyOffset_offset[31] ?
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NOT_wrap128_modifyOffset_offset_SRL_wrap128_mo_ETC___d25 :
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(wrap128_modifyOffset_doInc ?
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x__h491[7:0] < toBoundsM1__h91 :
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x__h491[7:0] <= toBoundsM1__h91) ;
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assign NOT_wrap128_modifyOffset_offset_SRL_wrap128_mo_ETC___d25 =
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x__h491[7:0] >= toBounds__h90 &&
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(!wrap128_modifyOffset_doInc ||
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repBoundBits__h87 != wrap128_modifyOffset_cap[81:74]) ;
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assign addBase__h631 =
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{ {22{x__h682[9]}}, x__h682 } <<
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wrap128_modifyOffset_cap[31:26] ;
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assign highOffsetBits__h81 = x__h108 & mask__h632 ;
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assign mask__h632 = 24'd16777215 << wrap128_modifyOffset_cap[31:26] ;
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assign newAddrBits__h584 = wrap128_modifyOffset_cap[17:10] + x__h491[7:0] ;
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assign pointer__h74 =
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wrap128_modifyOffset_cap[113:82] + wrap128_modifyOffset_offset ;
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assign repBoundBits__h87 = { wrap128_modifyOffset_cap[9:7], 5'd0 } ;
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assign repBound__h881 = wrap128_modifyOffset_cap[17:15] - 3'b001 ;
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assign result_d_addrBits__h601 =
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wrap128_modifyOffset_doInc ?
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x__h741[7:0] :
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{ mask__h585, 6'd63 } & newAddrBits__h584 ;
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assign result_d_address__h600 =
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wrap128_modifyOffset_doInc ?
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pointer__h74 :
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ret___1_address__h611 ;
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assign ret___1_address__h611 =
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{ wrap128_modifyOffset_cap[113:90] & mask__h632, 8'd0 } +
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addBase__h631 +
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wrap128_modifyOffset_offset ;
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assign signBits__h78 = {24{wrap128_modifyOffset_offset[31]}} ;
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assign toBoundsM1_A__h86 = { 3'b110, ~wrap128_modifyOffset_cap[14:10] } ;
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assign toBoundsM1_B__h89 =
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repBoundBits__h87 + ~wrap128_modifyOffset_cap[81:74] ;
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assign toBoundsM1__h91 =
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wrap128_modifyOffset_doInc ?
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toBoundsM1_B__h89 :
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toBoundsM1_A__h86 ;
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assign toBounds_A__h85 =
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8'd224 - { 3'b0, wrap128_modifyOffset_cap[14:10] } ;
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assign toBounds_B__h88 =
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repBoundBits__h87 - wrap128_modifyOffset_cap[81:74] ;
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assign toBounds__h90 =
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wrap128_modifyOffset_doInc ? toBounds_B__h88 : toBounds_A__h85 ;
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assign wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71 =
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wrap128_modifyOffset_cap[17:15] < repBound__h881 ;
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assign wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70 =
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wrap128_modifyOffset_cap[25:23] < repBound__h881 ;
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assign x__h108 = wrap128_modifyOffset_offset[31:8] ^ signBits__h78 ;
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assign x__h491 =
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wrap128_modifyOffset_offset >> wrap128_modifyOffset_cap[31:26] ;
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assign x__h682 =
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{ wrap128_modifyOffset_cap[1:0],
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wrap128_modifyOffset_cap[17:10] } ;
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assign x__h741 = pointer__h74 >> wrap128_modifyOffset_cap[31:26] ;
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always@(wrap128_modifyOffset_cap)
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begin
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case (wrap128_modifyOffset_cap[31:26])
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6'd25: mask__h585 = 2'b01;
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6'd26: mask__h585 = 2'b0;
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default: mask__h585 = 2'b11;
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endcase
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end
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endmodule // module_wrap128_modifyOffset
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