53 lines
1.3 KiB
Verilog
53 lines
1.3 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_nullWithAddr O 115
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// wrap128_nullWithAddr_addr I 32
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//
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// Combinational paths from inputs to outputs:
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// wrap128_nullWithAddr_addr -> wrap128_nullWithAddr
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_nullWithAddr(wrap128_nullWithAddr_addr,
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wrap128_nullWithAddr);
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// value method wrap128_nullWithAddr
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input [31 : 0] wrap128_nullWithAddr_addr;
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output [114 : 0] wrap128_nullWithAddr;
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// signals for module outputs
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wire [114 : 0] wrap128_nullWithAddr;
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// remaining internal signals
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wire [7 : 0] res_addrBits__h116;
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// value method wrap128_nullWithAddr
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assign wrap128_nullWithAddr =
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{ 1'd0,
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wrap128_nullWithAddr_addr,
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res_addrBits__h116,
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74'h0001F555555690003F0 } ;
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// remaining internal signals
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assign res_addrBits__h116 = { 2'd0, wrap128_nullWithAddr_addr[31:26] } ;
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endmodule // module_wrap128_nullWithAddr
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