130 lines
4.9 KiB
Verilog
130 lines
4.9 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_setOffset O 116
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// wrap128_setOffset_cap I 115
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// wrap128_setOffset_offset I 32
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//
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// Combinational paths from inputs to outputs:
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// (wrap128_setOffset_cap, wrap128_setOffset_offset) -> wrap128_setOffset
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_setOffset(wrap128_setOffset_cap,
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wrap128_setOffset_offset,
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wrap128_setOffset);
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// value method wrap128_setOffset
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input [114 : 0] wrap128_setOffset_cap;
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input [31 : 0] wrap128_setOffset_offset;
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output [115 : 0] wrap128_setOffset;
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// signals for module outputs
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wire [115 : 0] wrap128_setOffset;
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// remaining internal signals
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reg [1 : 0] mask__h560;
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wire [31 : 0] addBase__h594, result_d_address__h572, x__h488;
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wire [23 : 0] highOffsetBits__h80, mask__h595, signBits__h77, x__h107;
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wire [9 : 0] x__h645;
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wire [7 : 0] newAddrBits__h559,
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result_d_addrBits__h573,
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toBoundsM1__h90,
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toBounds__h89;
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wire [3 : 0] IF_wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_w_ETC___d62;
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wire [2 : 0] repBound__h826;
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wire IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52,
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IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19,
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wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50,
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wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49;
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// value method wrap128_setOffset
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assign wrap128_setOffset =
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{ highOffsetBits__h80 == 24'd0 &&
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IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19 ||
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wrap128_setOffset_cap[31:26] >= 6'd24,
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(highOffsetBits__h80 == 24'd0 &&
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IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19 ||
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wrap128_setOffset_cap[31:26] >= 6'd24) &&
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wrap128_setOffset_cap[114],
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result_d_address__h572,
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result_d_addrBits__h573,
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wrap128_setOffset_cap[73:10],
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repBound__h826,
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wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49,
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wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50,
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IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52,
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IF_wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_w_ETC___d62 } ;
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// remaining internal signals
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assign IF_wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_w_ETC___d62 =
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{ (wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49 ==
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IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
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2'd0 :
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((wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49 &&
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!IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
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2'd1 :
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2'd3),
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(wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50 ==
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IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
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2'd0 :
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((wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50 &&
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!IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
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2'd1 :
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2'd3) } ;
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assign IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52 =
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result_d_addrBits__h573[7:5] < repBound__h826 ;
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assign IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19 =
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wrap128_setOffset_offset[31] ?
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x__h488[7:0] >= toBounds__h89 :
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x__h488[7:0] <= toBoundsM1__h90 ;
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assign addBase__h594 =
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{ {22{x__h645[9]}}, x__h645 } << wrap128_setOffset_cap[31:26] ;
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assign highOffsetBits__h80 = x__h107 & mask__h595 ;
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assign mask__h595 = 24'd16777215 << wrap128_setOffset_cap[31:26] ;
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assign newAddrBits__h559 = wrap128_setOffset_cap[17:10] + x__h488[7:0] ;
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assign repBound__h826 = wrap128_setOffset_cap[17:15] - 3'b001 ;
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assign result_d_addrBits__h573 = { mask__h560, 6'd63 } & newAddrBits__h559 ;
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assign result_d_address__h572 =
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{ wrap128_setOffset_cap[113:90] & mask__h595, 8'd0 } +
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addBase__h594 +
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wrap128_setOffset_offset ;
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assign signBits__h77 = {24{wrap128_setOffset_offset[31]}} ;
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assign toBoundsM1__h90 = { 3'b110, ~wrap128_setOffset_cap[14:10] } ;
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assign toBounds__h89 = 8'd224 - { 3'b0, wrap128_setOffset_cap[14:10] } ;
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assign wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50 =
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wrap128_setOffset_cap[17:15] < repBound__h826 ;
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assign wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49 =
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wrap128_setOffset_cap[25:23] < repBound__h826 ;
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assign x__h107 = wrap128_setOffset_offset[31:8] ^ signBits__h77 ;
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assign x__h488 = wrap128_setOffset_offset >> wrap128_setOffset_cap[31:26] ;
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assign x__h645 =
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{ wrap128_setOffset_cap[1:0], wrap128_setOffset_cap[17:10] } ;
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always@(wrap128_setOffset_cap)
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begin
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case (wrap128_setOffset_cap[31:26])
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6'd25: mask__h560 = 2'b01;
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6'd26: mask__h560 = 2'b0;
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default: mask__h560 = 2'b11;
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endcase
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end
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endmodule // module_wrap128_setOffset
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