67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
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//
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// On Tue Feb 17 13:11:39 GMT 2026
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//
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//
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// Ports:
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// Name I/O size props
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// wrap128_toMem O 89
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// wrap128_toMem_cap I 115
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//
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// Combinational paths from inputs to outputs:
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// wrap128_toMem_cap -> wrap128_toMem
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_wrap128_toMem(wrap128_toMem_cap,
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wrap128_toMem);
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// value method wrap128_toMem
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input [114 : 0] wrap128_toMem_cap;
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output [88 : 0] wrap128_toMem;
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// signals for module outputs
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wire [88 : 0] wrap128_toMem;
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// remaining internal signals
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wire [87 : 0] x__h467;
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wire [13 : 0] IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15;
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// value method wrap128_toMem
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assign wrap128_toMem = { wrap128_toMem_cap[114], x__h467 } ;
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// remaining internal signals
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assign IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15 =
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wrap128_toMem_cap[32] ?
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{ wrap128_toMem_cap[23:21],
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wrap128_toMem_cap[31:29],
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wrap128_toMem_cap[17:13],
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wrap128_toMem_cap[28:26] } :
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wrap128_toMem_cap[23:10] ;
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assign x__h467 =
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{ wrap128_toMem_cap[73:61],
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~wrap128_toMem_cap[60:57],
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24'hAAAAAA ^ 24'hAAAAAA,
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~wrap128_toMem_cap[32],
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IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[13:10],
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~IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[9:8],
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IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[7:2],
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~IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[1],
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IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[0],
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wrap128_toMem_cap[113:82] } ;
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endmodule // module_wrap128_toMem
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