39 lines
868 B
Verilog
39 lines
868 B
Verilog
//
|
|
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
|
|
//
|
|
// On Tue Feb 17 13:06:26 GMT 2026
|
|
//
|
|
//
|
|
// Ports:
|
|
// Name I/O size props
|
|
// wrap64_almightyCap O 115 const
|
|
//
|
|
// No combinational paths from inputs to outputs
|
|
//
|
|
//
|
|
|
|
`ifdef BSV_ASSIGNMENT_DELAY
|
|
`else
|
|
`define BSV_ASSIGNMENT_DELAY
|
|
`endif
|
|
|
|
`ifdef BSV_POSITIVE_RESET
|
|
`define BSV_RESET_VALUE 1'b1
|
|
`define BSV_RESET_EDGE posedge
|
|
`else
|
|
`define BSV_RESET_VALUE 1'b0
|
|
`define BSV_RESET_EDGE negedge
|
|
`endif
|
|
|
|
module module_wrap64_almightyCap(wrap64_almightyCap);
|
|
// value method wrap64_almightyCap
|
|
output [114 : 0] wrap64_almightyCap;
|
|
|
|
// signals for module outputs
|
|
wire [114 : 0] wrap64_almightyCap;
|
|
|
|
// value method wrap64_almightyCap
|
|
assign wrap64_almightyCap = 115'h40000000003FFDF555555690003F0 ;
|
|
endmodule // module_wrap64_almightyCap
|
|
|